1/* -*- linux-c -*- * 2 * 3 * ALSA driver for the digigram lx6464es interface 4 * low-level interface 5 * 6 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; see the file COPYING. If not, write to 20 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330, 21 * Boston, MA 02111-1307, USA. 22 * 23 */ 24 25/* #define RMH_DEBUG 1 */ 26 27#include <linux/module.h> 28#include <linux/pci.h> 29#include <linux/delay.h> 30 31#include "lx6464es.h" 32#include "lx_core.h" 33 34/* low-level register access */ 35 36static const unsigned long dsp_port_offsets[] = { 37 0, 38 0x400, 39 0x401, 40 0x402, 41 0x403, 42 0x404, 43 0x405, 44 0x406, 45 0x407, 46 0x408, 47 0x409, 48 0x40a, 49 0x40b, 50 0x40c, 51 52 0x410, 53 0x411, 54 0x412, 55 0x413, 56 0x414, 57 0x415, 58 0x416, 59 60 0x420, 61 0x430, 62 0x431, 63 0x432, 64 0x433, 65 0x434, 66 0x440 67}; 68 69static void __iomem *lx_dsp_register(struct lx6464es *chip, int port) 70{ 71 void __iomem *base_address = chip->port_dsp_bar; 72 return base_address + dsp_port_offsets[port]*4; 73} 74 75unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port) 76{ 77 void __iomem *address = lx_dsp_register(chip, port); 78 return ioread32(address); 79} 80 81void lx_dsp_reg_readbuf(struct lx6464es *chip, int port, u32 *data, u32 len) 82{ 83 void __iomem *address = lx_dsp_register(chip, port); 84 memcpy_fromio(data, address, len*sizeof(u32)); 85} 86 87 88void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data) 89{ 90 void __iomem *address = lx_dsp_register(chip, port); 91 iowrite32(data, address); 92} 93 94void lx_dsp_reg_writebuf(struct lx6464es *chip, int port, const u32 *data, 95 u32 len) 96{ 97 void __iomem *address = lx_dsp_register(chip, port); 98 memcpy_toio(address, data, len*sizeof(u32)); 99} 100 101 102static const unsigned long plx_port_offsets[] = { 103 0x04, 104 0x40, 105 0x44, 106 0x48, 107 0x4c, 108 0x50, 109 0x54, 110 0x58, 111 0x5c, 112 0x64, 113 0x68, 114 0x6C 115}; 116 117static void __iomem *lx_plx_register(struct lx6464es *chip, int port) 118{ 119 void __iomem *base_address = chip->port_plx_remapped; 120 return base_address + plx_port_offsets[port]; 121} 122 123unsigned long lx_plx_reg_read(struct lx6464es *chip, int port) 124{ 125 void __iomem *address = lx_plx_register(chip, port); 126 return ioread32(address); 127} 128 129void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data) 130{ 131 void __iomem *address = lx_plx_register(chip, port); 132 iowrite32(data, address); 133} 134 135u32 lx_plx_mbox_read(struct lx6464es *chip, int mbox_nr) 136{ 137 int index; 138 139 switch (mbox_nr) { 140 case 1: 141 index = ePLX_MBOX1; break; 142 case 2: 143 index = ePLX_MBOX2; break; 144 case 3: 145 index = ePLX_MBOX3; break; 146 case 4: 147 index = ePLX_MBOX4; break; 148 case 5: 149 index = ePLX_MBOX5; break; 150 case 6: 151 index = ePLX_MBOX6; break; 152 case 7: 153 index = ePLX_MBOX7; break; 154 case 0: /* reserved for HF flags */ 155 snd_BUG(); 156 default: 157 return 0xdeadbeef; 158 } 159 160 return lx_plx_reg_read(chip, index); 161} 162 163int lx_plx_mbox_write(struct lx6464es *chip, int mbox_nr, u32 value) 164{ 165 int index = -1; 166 167 switch (mbox_nr) { 168 case 1: 169 index = ePLX_MBOX1; break; 170 case 3: 171 index = ePLX_MBOX3; break; 172 case 4: 173 index = ePLX_MBOX4; break; 174 case 5: 175 index = ePLX_MBOX5; break; 176 case 6: 177 index = ePLX_MBOX6; break; 178 case 7: 179 index = ePLX_MBOX7; break; 180 case 0: /* reserved for HF flags */ 181 case 2: /* reserved for Pipe States 182 * the DSP keeps an image of it */ 183 snd_BUG(); 184 return -EBADRQC; 185 } 186 187 lx_plx_reg_write(chip, index, value); 188 return 0; 189} 190 191 192/* rmh */ 193 194#ifdef CONFIG_SND_DEBUG 195#define CMD_NAME(a) a 196#else 197#define CMD_NAME(a) NULL 198#endif 199 200#define Reg_CSM_MR 0x00000002 201#define Reg_CSM_MC 0x00000001 202 203struct dsp_cmd_info { 204 u32 dcCodeOp; /* Op Code of the command (usually 1st 24-bits 205 * word).*/ 206 u16 dcCmdLength; /* Command length in words of 24 bits.*/ 207 u16 dcStatusType; /* Status type: 0 for fixed length, 1 for 208 * random. */ 209 u16 dcStatusLength; /* Status length (if fixed).*/ 210 char *dcOpName; 211}; 212 213/* 214 Initialization and control data for the Microblaze interface 215 - OpCode: 216 the opcode field of the command set at the proper offset 217 - CmdLength 218 the number of command words 219 - StatusType 220 offset in the status registers: 0 means that the return value may be 221 different from 0, and must be read 222 - StatusLength 223 the number of status words (in addition to the return value) 224*/ 225 226static struct dsp_cmd_info dsp_commands[] = 227{ 228 { (CMD_00_INFO_DEBUG << OPCODE_OFFSET) , 1 /*custom*/ 229 , 1 , 0 /**/ , CMD_NAME("INFO_DEBUG") }, 230 { (CMD_01_GET_SYS_CFG << OPCODE_OFFSET) , 1 /**/ 231 , 1 , 2 /**/ , CMD_NAME("GET_SYS_CFG") }, 232 { (CMD_02_SET_GRANULARITY << OPCODE_OFFSET) , 1 /**/ 233 , 1 , 0 /**/ , CMD_NAME("SET_GRANULARITY") }, 234 { (CMD_03_SET_TIMER_IRQ << OPCODE_OFFSET) , 1 /**/ 235 , 1 , 0 /**/ , CMD_NAME("SET_TIMER_IRQ") }, 236 { (CMD_04_GET_EVENT << OPCODE_OFFSET) , 1 /**/ 237 , 1 , 0 /*up to 10*/ , CMD_NAME("GET_EVENT") }, 238 { (CMD_05_GET_PIPES << OPCODE_OFFSET) , 1 /**/ 239 , 1 , 2 /*up to 4*/ , CMD_NAME("GET_PIPES") }, 240 { (CMD_06_ALLOCATE_PIPE << OPCODE_OFFSET) , 1 /**/ 241 , 0 , 0 /**/ , CMD_NAME("ALLOCATE_PIPE") }, 242 { (CMD_07_RELEASE_PIPE << OPCODE_OFFSET) , 1 /**/ 243 , 0 , 0 /**/ , CMD_NAME("RELEASE_PIPE") }, 244 { (CMD_08_ASK_BUFFERS << OPCODE_OFFSET) , 1 /**/ 245 , 1 , MAX_STREAM_BUFFER , CMD_NAME("ASK_BUFFERS") }, 246 { (CMD_09_STOP_PIPE << OPCODE_OFFSET) , 1 /**/ 247 , 0 , 0 /*up to 2*/ , CMD_NAME("STOP_PIPE") }, 248 { (CMD_0A_GET_PIPE_SPL_COUNT << OPCODE_OFFSET) , 1 /**/ 249 , 1 , 1 /*up to 2*/ , CMD_NAME("GET_PIPE_SPL_COUNT") }, 250 { (CMD_0B_TOGGLE_PIPE_STATE << OPCODE_OFFSET) , 1 /*up to 5*/ 251 , 1 , 0 /**/ , CMD_NAME("TOGGLE_PIPE_STATE") }, 252 { (CMD_0C_DEF_STREAM << OPCODE_OFFSET) , 1 /*up to 4*/ 253 , 1 , 0 /**/ , CMD_NAME("DEF_STREAM") }, 254 { (CMD_0D_SET_MUTE << OPCODE_OFFSET) , 3 /**/ 255 , 1 , 0 /**/ , CMD_NAME("SET_MUTE") }, 256 { (CMD_0E_GET_STREAM_SPL_COUNT << OPCODE_OFFSET) , 1/**/ 257 , 1 , 2 /**/ , CMD_NAME("GET_STREAM_SPL_COUNT") }, 258 { (CMD_0F_UPDATE_BUFFER << OPCODE_OFFSET) , 3 /*up to 4*/ 259 , 0 , 1 /**/ , CMD_NAME("UPDATE_BUFFER") }, 260 { (CMD_10_GET_BUFFER << OPCODE_OFFSET) , 1 /**/ 261 , 1 , 4 /**/ , CMD_NAME("GET_BUFFER") }, 262 { (CMD_11_CANCEL_BUFFER << OPCODE_OFFSET) , 1 /**/ 263 , 1 , 1 /*up to 4*/ , CMD_NAME("CANCEL_BUFFER") }, 264 { (CMD_12_GET_PEAK << OPCODE_OFFSET) , 1 /**/ 265 , 1 , 1 /**/ , CMD_NAME("GET_PEAK") }, 266 { (CMD_13_SET_STREAM_STATE << OPCODE_OFFSET) , 1 /**/ 267 , 1 , 0 /**/ , CMD_NAME("SET_STREAM_STATE") }, 268}; 269 270static void lx_message_init(struct lx_rmh *rmh, enum cmd_mb_opcodes cmd) 271{ 272 snd_BUG_ON(cmd >= CMD_14_INVALID); 273 274 rmh->cmd[0] = dsp_commands[cmd].dcCodeOp; 275 rmh->cmd_len = dsp_commands[cmd].dcCmdLength; 276 rmh->stat_len = dsp_commands[cmd].dcStatusLength; 277 rmh->dsp_stat = dsp_commands[cmd].dcStatusType; 278 rmh->cmd_idx = cmd; 279 memset(&rmh->cmd[1], 0, (REG_CRM_NUMBER - 1) * sizeof(u32)); 280 281#ifdef CONFIG_SND_DEBUG 282 memset(rmh->stat, 0, REG_CRM_NUMBER * sizeof(u32)); 283#endif 284#ifdef RMH_DEBUG 285 rmh->cmd_idx = cmd; 286#endif 287} 288 289#ifdef RMH_DEBUG 290#define LXRMH "lx6464es rmh: " 291static void lx_message_dump(struct lx_rmh *rmh) 292{ 293 u8 idx = rmh->cmd_idx; 294 int i; 295 296 snd_printk(LXRMH "command %s\n", dsp_commands[idx].dcOpName); 297 298 for (i = 0; i != rmh->cmd_len; ++i) 299 snd_printk(LXRMH "\tcmd[%d] %08x\n", i, rmh->cmd[i]); 300 301 for (i = 0; i != rmh->stat_len; ++i) 302 snd_printk(LXRMH "\tstat[%d]: %08x\n", i, rmh->stat[i]); 303 snd_printk("\n"); 304} 305#else 306static inline void lx_message_dump(struct lx_rmh *rmh) 307{} 308#endif 309 310 311 312/* sleep 500 - 100 = 400 times 100us -> the timeout is >= 40 ms */ 313#define XILINX_TIMEOUT_MS 40 314#define XILINX_POLL_NO_SLEEP 100 315#define XILINX_POLL_ITERATIONS 150 316 317 318static int lx_message_send_atomic(struct lx6464es *chip, struct lx_rmh *rmh) 319{ 320 u32 reg = ED_DSP_TIMED_OUT; 321 int dwloop; 322 323 if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) { 324 snd_printk(KERN_ERR LXP "PIOSendMessage eReg_CSM %x\n", reg); 325 return -EBUSY; 326 } 327 328 /* write command */ 329 lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len); 330 331 /* MicoBlaze gogogo */ 332 lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC); 333 334 /* wait for device to answer */ 335 for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS * 1000; ++dwloop) { 336 if (lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR) { 337 if (rmh->dsp_stat == 0) 338 reg = lx_dsp_reg_read(chip, eReg_CRM1); 339 else 340 reg = 0; 341 goto polling_successful; 342 } else 343 udelay(1); 344 } 345 snd_printk(KERN_WARNING LXP "TIMEOUT lx_message_send_atomic! " 346 "polling failed\n"); 347 348polling_successful: 349 if ((reg & ERROR_VALUE) == 0) { 350 /* read response */ 351 if (rmh->stat_len) { 352 snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1)); 353 lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat, 354 rmh->stat_len); 355 } 356 } else 357 snd_printk(LXP "rmh error: %08x\n", reg); 358 359 /* clear Reg_CSM_MR */ 360 lx_dsp_reg_write(chip, eReg_CSM, 0); 361 362 switch (reg) { 363 case ED_DSP_TIMED_OUT: 364 snd_printk(KERN_WARNING LXP "lx_message_send: dsp timeout\n"); 365 return -ETIMEDOUT; 366 367 case ED_DSP_CRASHED: 368 snd_printk(KERN_WARNING LXP "lx_message_send: dsp crashed\n"); 369 return -EAGAIN; 370 } 371 372 lx_message_dump(rmh); 373 374 return reg; 375} 376 377 378/* low-level dsp access */ 379int __devinit lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version) 380{ 381 u16 ret; 382 unsigned long flags; 383 384 spin_lock_irqsave(&chip->msg_lock, flags); 385 386 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG); 387 ret = lx_message_send_atomic(chip, &chip->rmh); 388 389 *rdsp_version = chip->rmh.stat[1]; 390 spin_unlock_irqrestore(&chip->msg_lock, flags); 391 return ret; 392} 393 394int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq) 395{ 396 u16 ret = 0; 397 unsigned long flags; 398 u32 freq_raw = 0; 399 u32 freq = 0; 400 u32 frequency = 0; 401 402 spin_lock_irqsave(&chip->msg_lock, flags); 403 404 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG); 405 ret = lx_message_send_atomic(chip, &chip->rmh); 406 407 if (ret == 0) { 408 freq_raw = chip->rmh.stat[0] >> FREQ_FIELD_OFFSET; 409 freq = freq_raw & XES_FREQ_COUNT8_MASK; 410 411 if ((freq < XES_FREQ_COUNT8_48_MAX) || 412 (freq > XES_FREQ_COUNT8_44_MIN)) 413 frequency = 0; /* unknown */ 414 else if (freq >= XES_FREQ_COUNT8_44_MAX) 415 frequency = 44100; 416 else 417 frequency = 48000; 418 } 419 420 spin_unlock_irqrestore(&chip->msg_lock, flags); 421 422 *rfreq = frequency * chip->freq_ratio; 423 424 return ret; 425} 426 427int lx_dsp_get_mac(struct lx6464es *chip, u8 *mac_address) 428{ 429 u32 macmsb, maclsb; 430 431 macmsb = lx_dsp_reg_read(chip, eReg_ADMACESMSB) & 0x00FFFFFF; 432 maclsb = lx_dsp_reg_read(chip, eReg_ADMACESLSB) & 0x00FFFFFF; 433 434 /* todo: endianess handling */ 435 mac_address[5] = ((u8 *)(&maclsb))[0]; 436 mac_address[4] = ((u8 *)(&maclsb))[1]; 437 mac_address[3] = ((u8 *)(&maclsb))[2]; 438 mac_address[2] = ((u8 *)(&macmsb))[0]; 439 mac_address[1] = ((u8 *)(&macmsb))[1]; 440 mac_address[0] = ((u8 *)(&macmsb))[2]; 441 442 return 0; 443} 444 445 446int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran) 447{ 448 unsigned long flags; 449 int ret; 450 451 spin_lock_irqsave(&chip->msg_lock, flags); 452 453 lx_message_init(&chip->rmh, CMD_02_SET_GRANULARITY); 454 chip->rmh.cmd[0] |= gran; 455 456 ret = lx_message_send_atomic(chip, &chip->rmh); 457 spin_unlock_irqrestore(&chip->msg_lock, flags); 458 return ret; 459} 460 461int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data) 462{ 463 unsigned long flags; 464 int ret; 465 466 spin_lock_irqsave(&chip->msg_lock, flags); 467 468 lx_message_init(&chip->rmh, CMD_04_GET_EVENT); 469 chip->rmh.stat_len = 9; /* we don't necessarily need the full length */ 470 471 ret = lx_message_send_atomic(chip, &chip->rmh); 472 473 if (!ret) 474 memcpy(data, chip->rmh.stat, chip->rmh.stat_len * sizeof(u32)); 475 476 spin_unlock_irqrestore(&chip->msg_lock, flags); 477 return ret; 478} 479 480#define CSES_TIMEOUT 100 /* microseconds */ 481#define CSES_CE 0x0001 482#define CSES_BROADCAST 0x0002 483#define CSES_UPDATE_LDSV 0x0004 484 485int lx_dsp_es_check_pipeline(struct lx6464es *chip) 486{ 487 int i; 488 489 for (i = 0; i != CSES_TIMEOUT; ++i) { 490 /* 491 * le bit CSES_UPDATE_LDSV est ���� 1 d����s que le macprog 492 * est pret. il re-passe ���� 0 lorsque le premier read a 493 * ����t���� fait. pour l'instant on retire le test car ce bit 494 * passe a 1 environ 200 ���� 400 ms apr����s que le registre 495 * confES ���� ����t���� ����crit (kick du xilinx ES). 496 * 497 * On ne teste que le bit CE. 498 * */ 499 500 u32 cses = lx_dsp_reg_read(chip, eReg_CSES); 501 502 if ((cses & CSES_CE) == 0) 503 return 0; 504 505 udelay(1); 506 } 507 508 return -ETIMEDOUT; 509} 510 511 512#define PIPE_INFO_TO_CMD(capture, pipe) \ 513 ((u32)((u32)(pipe) | ((capture) ? ID_IS_CAPTURE : 0L)) << ID_OFFSET) 514 515 516 517/* low-level pipe handling */ 518int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture, 519 int channels) 520{ 521 int err; 522 unsigned long flags; 523 524 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 525 526 spin_lock_irqsave(&chip->msg_lock, flags); 527 lx_message_init(&chip->rmh, CMD_06_ALLOCATE_PIPE); 528 529 chip->rmh.cmd[0] |= pipe_cmd; 530 chip->rmh.cmd[0] |= channels; 531 532 err = lx_message_send_atomic(chip, &chip->rmh); 533 spin_unlock_irqrestore(&chip->msg_lock, flags); 534 535 if (err != 0) 536 snd_printk(KERN_ERR "lx6464es: could not allocate pipe\n"); 537 538 return err; 539} 540 541int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture) 542{ 543 int err; 544 unsigned long flags; 545 546 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 547 548 spin_lock_irqsave(&chip->msg_lock, flags); 549 lx_message_init(&chip->rmh, CMD_07_RELEASE_PIPE); 550 551 chip->rmh.cmd[0] |= pipe_cmd; 552 553 err = lx_message_send_atomic(chip, &chip->rmh); 554 spin_unlock_irqrestore(&chip->msg_lock, flags); 555 556 return err; 557} 558 559int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture, 560 u32 *r_needed, u32 *r_freed, u32 *size_array) 561{ 562 int err; 563 unsigned long flags; 564 565 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 566 567#ifdef CONFIG_SND_DEBUG 568 if (size_array) 569 memset(size_array, 0, sizeof(u32)*MAX_STREAM_BUFFER); 570#endif 571 572 *r_needed = 0; 573 *r_freed = 0; 574 575 spin_lock_irqsave(&chip->msg_lock, flags); 576 lx_message_init(&chip->rmh, CMD_08_ASK_BUFFERS); 577 578 chip->rmh.cmd[0] |= pipe_cmd; 579 580 err = lx_message_send_atomic(chip, &chip->rmh); 581 582 if (!err) { 583 int i; 584 for (i = 0; i < MAX_STREAM_BUFFER; ++i) { 585 u32 stat = chip->rmh.stat[i]; 586 if (stat & (BF_EOB << BUFF_FLAGS_OFFSET)) { 587 /* finished */ 588 *r_freed += 1; 589 if (size_array) 590 size_array[i] = stat & MASK_DATA_SIZE; 591 } else if ((stat & (BF_VALID << BUFF_FLAGS_OFFSET)) 592 == 0) 593 /* free */ 594 *r_needed += 1; 595 } 596 597 } 598 599 spin_unlock_irqrestore(&chip->msg_lock, flags); 600 return err; 601} 602 603 604int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture) 605{ 606 int err; 607 unsigned long flags; 608 609 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 610 611 spin_lock_irqsave(&chip->msg_lock, flags); 612 lx_message_init(&chip->rmh, CMD_09_STOP_PIPE); 613 614 chip->rmh.cmd[0] |= pipe_cmd; 615 616 err = lx_message_send_atomic(chip, &chip->rmh); 617 618 spin_unlock_irqrestore(&chip->msg_lock, flags); 619 return err; 620} 621 622static int lx_pipe_toggle_state(struct lx6464es *chip, u32 pipe, int is_capture) 623{ 624 int err; 625 unsigned long flags; 626 627 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 628 629 spin_lock_irqsave(&chip->msg_lock, flags); 630 lx_message_init(&chip->rmh, CMD_0B_TOGGLE_PIPE_STATE); 631 632 chip->rmh.cmd[0] |= pipe_cmd; 633 634 err = lx_message_send_atomic(chip, &chip->rmh); 635 636 spin_unlock_irqrestore(&chip->msg_lock, flags); 637 return err; 638} 639 640 641int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture) 642{ 643 int err; 644 645 err = lx_pipe_wait_for_idle(chip, pipe, is_capture); 646 if (err < 0) 647 return err; 648 649 err = lx_pipe_toggle_state(chip, pipe, is_capture); 650 651 return err; 652} 653 654int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture) 655{ 656 int err = 0; 657 658 err = lx_pipe_wait_for_start(chip, pipe, is_capture); 659 if (err < 0) 660 return err; 661 662 err = lx_pipe_toggle_state(chip, pipe, is_capture); 663 664 return err; 665} 666 667 668int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture, 669 u64 *rsample_count) 670{ 671 int err; 672 unsigned long flags; 673 674 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 675 676 spin_lock_irqsave(&chip->msg_lock, flags); 677 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT); 678 679 chip->rmh.cmd[0] |= pipe_cmd; 680 chip->rmh.stat_len = 2; /* need all words here! */ 681 682 err = lx_message_send_atomic(chip, &chip->rmh); /* don't sleep! */ 683 684 if (err != 0) 685 snd_printk(KERN_ERR 686 "lx6464es: could not query pipe's sample count\n"); 687 else { 688 *rsample_count = ((u64)(chip->rmh.stat[0] & MASK_SPL_COUNT_HI) 689 << 24) /* hi part */ 690 + chip->rmh.stat[1]; /* lo part */ 691 } 692 693 spin_unlock_irqrestore(&chip->msg_lock, flags); 694 return err; 695} 696 697int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate) 698{ 699 int err; 700 unsigned long flags; 701 702 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 703 704 spin_lock_irqsave(&chip->msg_lock, flags); 705 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT); 706 707 chip->rmh.cmd[0] |= pipe_cmd; 708 709 err = lx_message_send_atomic(chip, &chip->rmh); 710 711 if (err != 0) 712 snd_printk(KERN_ERR "lx6464es: could not query pipe's state\n"); 713 else 714 *rstate = (chip->rmh.stat[0] >> PSTATE_OFFSET) & 0x0F; 715 716 spin_unlock_irqrestore(&chip->msg_lock, flags); 717 return err; 718} 719 720static int lx_pipe_wait_for_state(struct lx6464es *chip, u32 pipe, 721 int is_capture, u16 state) 722{ 723 int i; 724 725 /* max 2*PCMOnlyGranularity = 2*1024 at 44100 = < 50 ms: 726 * timeout 50 ms */ 727 for (i = 0; i != 50; ++i) { 728 u16 current_state; 729 int err = lx_pipe_state(chip, pipe, is_capture, ¤t_state); 730 731 if (err < 0) 732 return err; 733 734 if (current_state == state) 735 return 0; 736 737 mdelay(1); 738 } 739 740 return -ETIMEDOUT; 741} 742 743int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture) 744{ 745 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_RUN); 746} 747 748int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture) 749{ 750 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_IDLE); 751} 752 753/* low-level stream handling */ 754int lx_stream_set_state(struct lx6464es *chip, u32 pipe, 755 int is_capture, enum stream_state_t state) 756{ 757 int err; 758 unsigned long flags; 759 760 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 761 762 spin_lock_irqsave(&chip->msg_lock, flags); 763 lx_message_init(&chip->rmh, CMD_13_SET_STREAM_STATE); 764 765 chip->rmh.cmd[0] |= pipe_cmd; 766 chip->rmh.cmd[0] |= state; 767 768 err = lx_message_send_atomic(chip, &chip->rmh); 769 spin_unlock_irqrestore(&chip->msg_lock, flags); 770 771 return err; 772} 773 774int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime, 775 u32 pipe, int is_capture) 776{ 777 int err; 778 unsigned long flags; 779 780 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 781 782 u32 channels = runtime->channels; 783 784 if (runtime->channels != channels) 785 snd_printk(KERN_ERR LXP "channel count mismatch: %d vs %d", 786 runtime->channels, channels); 787 788 spin_lock_irqsave(&chip->msg_lock, flags); 789 lx_message_init(&chip->rmh, CMD_0C_DEF_STREAM); 790 791 chip->rmh.cmd[0] |= pipe_cmd; 792 793 if (runtime->sample_bits == 16) 794 /* 16 bit format */ 795 chip->rmh.cmd[0] |= (STREAM_FMT_16b << STREAM_FMT_OFFSET); 796 797 if (snd_pcm_format_little_endian(runtime->format)) 798 /* little endian/intel format */ 799 chip->rmh.cmd[0] |= (STREAM_FMT_intel << STREAM_FMT_OFFSET); 800 801 chip->rmh.cmd[0] |= channels-1; 802 803 err = lx_message_send_atomic(chip, &chip->rmh); 804 spin_unlock_irqrestore(&chip->msg_lock, flags); 805 806 return err; 807} 808 809int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture, 810 int *rstate) 811{ 812 int err; 813 unsigned long flags; 814 815 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 816 817 spin_lock_irqsave(&chip->msg_lock, flags); 818 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT); 819 820 chip->rmh.cmd[0] |= pipe_cmd; 821 822 err = lx_message_send_atomic(chip, &chip->rmh); 823 824 *rstate = (chip->rmh.stat[0] & SF_START) ? START_STATE : PAUSE_STATE; 825 826 spin_unlock_irqrestore(&chip->msg_lock, flags); 827 return err; 828} 829 830int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture, 831 u64 *r_bytepos) 832{ 833 int err; 834 unsigned long flags; 835 836 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 837 838 spin_lock_irqsave(&chip->msg_lock, flags); 839 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT); 840 841 chip->rmh.cmd[0] |= pipe_cmd; 842 843 err = lx_message_send_atomic(chip, &chip->rmh); 844 845 *r_bytepos = ((u64) (chip->rmh.stat[0] & MASK_SPL_COUNT_HI) 846 << 32) /* hi part */ 847 + chip->rmh.stat[1]; /* lo part */ 848 849 spin_unlock_irqrestore(&chip->msg_lock, flags); 850 return err; 851} 852 853/* low-level buffer handling */ 854int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture, 855 u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi, 856 u32 *r_buffer_index) 857{ 858 int err; 859 unsigned long flags; 860 861 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 862 863 spin_lock_irqsave(&chip->msg_lock, flags); 864 lx_message_init(&chip->rmh, CMD_0F_UPDATE_BUFFER); 865 866 chip->rmh.cmd[0] |= pipe_cmd; 867 chip->rmh.cmd[0] |= BF_NOTIFY_EOB; /* request interrupt notification */ 868 869 /* todo: pause request, circular buffer */ 870 871 chip->rmh.cmd[1] = buffer_size & MASK_DATA_SIZE; 872 chip->rmh.cmd[2] = buf_address_lo; 873 874 if (buf_address_hi) { 875 chip->rmh.cmd_len = 4; 876 chip->rmh.cmd[3] = buf_address_hi; 877 chip->rmh.cmd[0] |= BF_64BITS_ADR; 878 } 879 880 err = lx_message_send_atomic(chip, &chip->rmh); 881 882 if (err == 0) { 883 *r_buffer_index = chip->rmh.stat[0]; 884 goto done; 885 } 886 887 if (err == EB_RBUFFERS_TABLE_OVERFLOW) 888 snd_printk(LXP "lx_buffer_give EB_RBUFFERS_TABLE_OVERFLOW\n"); 889 890 if (err == EB_INVALID_STREAM) 891 snd_printk(LXP "lx_buffer_give EB_INVALID_STREAM\n"); 892 893 if (err == EB_CMD_REFUSED) 894 snd_printk(LXP "lx_buffer_give EB_CMD_REFUSED\n"); 895 896 done: 897 spin_unlock_irqrestore(&chip->msg_lock, flags); 898 return err; 899} 900 901int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture, 902 u32 *r_buffer_size) 903{ 904 int err; 905 unsigned long flags; 906 907 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 908 909 spin_lock_irqsave(&chip->msg_lock, flags); 910 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER); 911 912 chip->rmh.cmd[0] |= pipe_cmd; 913 chip->rmh.cmd[0] |= MASK_BUFFER_ID; /* ask for the current buffer: the 914 * microblaze will seek for it */ 915 916 err = lx_message_send_atomic(chip, &chip->rmh); 917 918 if (err == 0) 919 *r_buffer_size = chip->rmh.stat[0] & MASK_DATA_SIZE; 920 921 spin_unlock_irqrestore(&chip->msg_lock, flags); 922 return err; 923} 924 925int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture, 926 u32 buffer_index) 927{ 928 int err; 929 unsigned long flags; 930 931 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 932 933 spin_lock_irqsave(&chip->msg_lock, flags); 934 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER); 935 936 chip->rmh.cmd[0] |= pipe_cmd; 937 chip->rmh.cmd[0] |= buffer_index; 938 939 err = lx_message_send_atomic(chip, &chip->rmh); 940 941 spin_unlock_irqrestore(&chip->msg_lock, flags); 942 return err; 943} 944 945 946/* low-level gain/peak handling 947 * 948 * \todo: can we unmute capture/playback channels independently? 949 * 950 * */ 951int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute) 952{ 953 int err; 954 unsigned long flags; 955 956 /* bit set to 1: channel muted */ 957 u64 mute_mask = unmute ? 0 : 0xFFFFFFFFFFFFFFFFLLU; 958 959 spin_lock_irqsave(&chip->msg_lock, flags); 960 lx_message_init(&chip->rmh, CMD_0D_SET_MUTE); 961 962 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, 0); 963 964 chip->rmh.cmd[1] = (u32)(mute_mask >> (u64)32); /* hi part */ 965 chip->rmh.cmd[2] = (u32)(mute_mask & (u64)0xFFFFFFFF); /* lo part */ 966 967 snd_printk("mute %x %x %x\n", chip->rmh.cmd[0], chip->rmh.cmd[1], 968 chip->rmh.cmd[2]); 969 970 err = lx_message_send_atomic(chip, &chip->rmh); 971 972 spin_unlock_irqrestore(&chip->msg_lock, flags); 973 return err; 974} 975 976static u32 peak_map[] = { 977 0x00000109, /* -90.308dB */ 978 0x0000083B, /* -72.247dB */ 979 0x000020C4, /* -60.205dB */ 980 0x00008273, /* -48.030dB */ 981 0x00020756, /* -36.005dB */ 982 0x00040C37, /* -30.001dB */ 983 0x00081385, /* -24.002dB */ 984 0x00101D3F, /* -18.000dB */ 985 0x0016C310, /* -15.000dB */ 986 0x002026F2, /* -12.001dB */ 987 0x002D6A86, /* -9.000dB */ 988 0x004026E6, /* -6.004dB */ 989 0x005A9DF6, /* -3.000dB */ 990 0x0065AC8B, /* -2.000dB */ 991 0x00721481, /* -1.000dB */ 992 0x007FFFFF, /* FS */ 993}; 994 995int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels, 996 u32 *r_levels) 997{ 998 int err = 0; 999 unsigned long flags; 1000 int i; 1001 spin_lock_irqsave(&chip->msg_lock, flags); 1002 1003 for (i = 0; i < channels; i += 4) { 1004 u32 s0, s1, s2, s3; 1005 1006 lx_message_init(&chip->rmh, CMD_12_GET_PEAK); 1007 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, i); 1008 1009 err = lx_message_send_atomic(chip, &chip->rmh); 1010 1011 if (err == 0) { 1012 s0 = peak_map[chip->rmh.stat[0] & 0x0F]; 1013 s1 = peak_map[(chip->rmh.stat[0] >> 4) & 0xf]; 1014 s2 = peak_map[(chip->rmh.stat[0] >> 8) & 0xf]; 1015 s3 = peak_map[(chip->rmh.stat[0] >> 12) & 0xf]; 1016 } else 1017 s0 = s1 = s2 = s3 = 0; 1018 1019 r_levels[0] = s0; 1020 r_levels[1] = s1; 1021 r_levels[2] = s2; 1022 r_levels[3] = s3; 1023 1024 r_levels += 4; 1025 } 1026 1027 spin_unlock_irqrestore(&chip->msg_lock, flags); 1028 return err; 1029} 1030 1031/* interrupt handling */ 1032#define PCX_IRQ_NONE 0 1033#define IRQCS_ACTIVE_PCIDB 0x00002000L /* Bit n�������� 13 */ 1034#define IRQCS_ENABLE_PCIIRQ 0x00000100L /* Bit n�������� 08 */ 1035#define IRQCS_ENABLE_PCIDB 0x00000200L /* Bit n�������� 09 */ 1036 1037static u32 lx_interrupt_test_ack(struct lx6464es *chip) 1038{ 1039 u32 irqcs = lx_plx_reg_read(chip, ePLX_IRQCS); 1040 1041 /* Test if PCI Doorbell interrupt is active */ 1042 if (irqcs & IRQCS_ACTIVE_PCIDB) { 1043 u32 temp; 1044 irqcs = PCX_IRQ_NONE; 1045 1046 while ((temp = lx_plx_reg_read(chip, ePLX_L2PCIDB))) { 1047 /* RAZ interrupt */ 1048 irqcs |= temp; 1049 lx_plx_reg_write(chip, ePLX_L2PCIDB, temp); 1050 } 1051 1052 return irqcs; 1053 } 1054 return PCX_IRQ_NONE; 1055} 1056 1057static int lx_interrupt_ack(struct lx6464es *chip, u32 *r_irqsrc, 1058 int *r_async_pending, int *r_async_escmd) 1059{ 1060 u32 irq_async; 1061 u32 irqsrc = lx_interrupt_test_ack(chip); 1062 1063 if (irqsrc == PCX_IRQ_NONE) 1064 return 0; 1065 1066 *r_irqsrc = irqsrc; 1067 1068 irq_async = irqsrc & MASK_SYS_ASYNC_EVENTS; /* + EtherSound response 1069 * (set by xilinx) + EOB */ 1070 1071 if (irq_async & MASK_SYS_STATUS_ESA) { 1072 irq_async &= ~MASK_SYS_STATUS_ESA; 1073 *r_async_escmd = 1; 1074 } 1075 1076 if (irq_async) { 1077 /* snd_printd("interrupt: async event pending\n"); */ 1078 *r_async_pending = 1; 1079 } 1080 1081 return 1; 1082} 1083 1084static int lx_interrupt_handle_async_events(struct lx6464es *chip, u32 irqsrc, 1085 int *r_freq_changed, 1086 u64 *r_notified_in_pipe_mask, 1087 u64 *r_notified_out_pipe_mask) 1088{ 1089 int err; 1090 u32 stat[9]; /* answer from CMD_04_GET_EVENT */ 1091 1092 /* On peut optimiser pour ne pas lire les evenements vides 1093 * les mots de r��������ponse sont dans l'ordre suivant : 1094 * Stat[0] mot de status g��������n��������ral 1095 * Stat[1] fin de buffer OUT pF 1096 * Stat[2] fin de buffer OUT pf 1097 * Stat[3] fin de buffer IN pF 1098 * Stat[4] fin de buffer IN pf 1099 * Stat[5] underrun poid fort 1100 * Stat[6] underrun poid faible 1101 * Stat[7] overrun poid fort 1102 * Stat[8] overrun poid faible 1103 * */ 1104 1105 u64 orun_mask; 1106 u64 urun_mask; 1107 int eb_pending_out = (irqsrc & MASK_SYS_STATUS_EOBO) ? 1 : 0; 1108 int eb_pending_in = (irqsrc & MASK_SYS_STATUS_EOBI) ? 1 : 0; 1109 1110 *r_freq_changed = (irqsrc & MASK_SYS_STATUS_FREQ) ? 1 : 0; 1111 1112 err = lx_dsp_read_async_events(chip, stat); 1113 if (err < 0) 1114 return err; 1115 1116 if (eb_pending_in) { 1117 *r_notified_in_pipe_mask = ((u64)stat[3] << 32) 1118 + stat[4]; 1119 snd_printdd(LXP "interrupt: EOBI pending %llx\n", 1120 *r_notified_in_pipe_mask); 1121 } 1122 if (eb_pending_out) { 1123 *r_notified_out_pipe_mask = ((u64)stat[1] << 32) 1124 + stat[2]; 1125 snd_printdd(LXP "interrupt: EOBO pending %llx\n", 1126 *r_notified_out_pipe_mask); 1127 } 1128 1129 orun_mask = ((u64)stat[7] << 32) + stat[8]; 1130 urun_mask = ((u64)stat[5] << 32) + stat[6]; 1131 1132 /* todo: handle xrun notification */ 1133 1134 return err; 1135} 1136 1137static int lx_interrupt_request_new_buffer(struct lx6464es *chip, 1138 struct lx_stream *lx_stream) 1139{ 1140 struct snd_pcm_substream *substream = lx_stream->stream; 1141 int is_capture = lx_stream->is_capture; 1142 int err; 1143 unsigned long flags; 1144 1145 const u32 channels = substream->runtime->channels; 1146 const u32 bytes_per_frame = channels * 3; 1147 const u32 period_size = substream->runtime->period_size; 1148 const u32 period_bytes = period_size * bytes_per_frame; 1149 const u32 pos = lx_stream->frame_pos; 1150 const u32 next_pos = ((pos+1) == substream->runtime->periods) ? 1151 0 : pos + 1; 1152 1153 dma_addr_t buf = substream->dma_buffer.addr + pos * period_bytes; 1154 u32 buf_hi = 0; 1155 u32 buf_lo = 0; 1156 u32 buffer_index = 0; 1157 1158 u32 needed, freed; 1159 u32 size_array[MAX_STREAM_BUFFER]; 1160 1161 snd_printdd("->lx_interrupt_request_new_buffer\n"); 1162 1163 spin_lock_irqsave(&chip->lock, flags); 1164 1165 err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, size_array); 1166 snd_printdd(LXP "interrupt: needed %d, freed %d\n", needed, freed); 1167 1168 unpack_pointer(buf, &buf_lo, &buf_hi); 1169 err = lx_buffer_give(chip, 0, is_capture, period_bytes, buf_lo, buf_hi, 1170 &buffer_index); 1171 snd_printdd(LXP "interrupt: gave buffer index %x on %p (%d bytes)\n", 1172 buffer_index, (void *)buf, period_bytes); 1173 1174 lx_stream->frame_pos = next_pos; 1175 spin_unlock_irqrestore(&chip->lock, flags); 1176 1177 return err; 1178} 1179 1180void lx_tasklet_playback(unsigned long data) 1181{ 1182 struct lx6464es *chip = (struct lx6464es *)data; 1183 struct lx_stream *lx_stream = &chip->playback_stream; 1184 int err; 1185 1186 snd_printdd("->lx_tasklet_playback\n"); 1187 1188 err = lx_interrupt_request_new_buffer(chip, lx_stream); 1189 if (err < 0) 1190 snd_printk(KERN_ERR LXP 1191 "cannot request new buffer for playback\n"); 1192 1193 snd_pcm_period_elapsed(lx_stream->stream); 1194} 1195 1196void lx_tasklet_capture(unsigned long data) 1197{ 1198 struct lx6464es *chip = (struct lx6464es *)data; 1199 struct lx_stream *lx_stream = &chip->capture_stream; 1200 int err; 1201 1202 snd_printdd("->lx_tasklet_capture\n"); 1203 err = lx_interrupt_request_new_buffer(chip, lx_stream); 1204 if (err < 0) 1205 snd_printk(KERN_ERR LXP 1206 "cannot request new buffer for capture\n"); 1207 1208 snd_pcm_period_elapsed(lx_stream->stream); 1209} 1210 1211 1212 1213static int lx_interrupt_handle_audio_transfer(struct lx6464es *chip, 1214 u64 notified_in_pipe_mask, 1215 u64 notified_out_pipe_mask) 1216{ 1217 int err = 0; 1218 1219 if (notified_in_pipe_mask) { 1220 snd_printdd(LXP "requesting audio transfer for capture\n"); 1221 tasklet_hi_schedule(&chip->tasklet_capture); 1222 } 1223 1224 if (notified_out_pipe_mask) { 1225 snd_printdd(LXP "requesting audio transfer for playback\n"); 1226 tasklet_hi_schedule(&chip->tasklet_playback); 1227 } 1228 1229 return err; 1230} 1231 1232 1233irqreturn_t lx_interrupt(int irq, void *dev_id) 1234{ 1235 struct lx6464es *chip = dev_id; 1236 int async_pending, async_escmd; 1237 u32 irqsrc; 1238 1239 spin_lock(&chip->lock); 1240 1241 snd_printdd("**************************************************\n"); 1242 1243 if (!lx_interrupt_ack(chip, &irqsrc, &async_pending, &async_escmd)) { 1244 spin_unlock(&chip->lock); 1245 snd_printdd("IRQ_NONE\n"); 1246 return IRQ_NONE; /* this device did not cause the interrupt */ 1247 } 1248 1249 if (irqsrc & MASK_SYS_STATUS_CMD_DONE) 1250 goto exit; 1251 1252 1253 if (async_pending) { 1254 u64 notified_in_pipe_mask = 0; 1255 u64 notified_out_pipe_mask = 0; 1256 int freq_changed; 1257 int err; 1258 1259 /* handle async events */ 1260 err = lx_interrupt_handle_async_events(chip, irqsrc, 1261 &freq_changed, 1262 ¬ified_in_pipe_mask, 1263 ¬ified_out_pipe_mask); 1264 if (err) 1265 snd_printk(KERN_ERR LXP 1266 "error handling async events\n"); 1267 1268 err = lx_interrupt_handle_audio_transfer(chip, 1269 notified_in_pipe_mask, 1270 notified_out_pipe_mask 1271 ); 1272 if (err) 1273 snd_printk(KERN_ERR LXP 1274 "error during audio transfer\n"); 1275 } 1276 1277 if (async_escmd) { 1278 } 1279 1280exit: 1281 spin_unlock(&chip->lock); 1282 return IRQ_HANDLED; /* this device caused the interrupt */ 1283} 1284 1285 1286static void lx_irq_set(struct lx6464es *chip, int enable) 1287{ 1288 u32 reg = lx_plx_reg_read(chip, ePLX_IRQCS); 1289 1290 /* enable/disable interrupts 1291 * 1292 * Set the Doorbell and PCI interrupt enable bits 1293 * 1294 * */ 1295 if (enable) 1296 reg |= (IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB); 1297 else 1298 reg &= ~(IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB); 1299 lx_plx_reg_write(chip, ePLX_IRQCS, reg); 1300} 1301 1302void lx_irq_enable(struct lx6464es *chip) 1303{ 1304 snd_printdd("->lx_irq_enable\n"); 1305 lx_irq_set(chip, 1); 1306} 1307 1308void lx_irq_disable(struct lx6464es *chip) 1309{ 1310 snd_printdd("->lx_irq_disable\n"); 1311 lx_irq_set(chip, 0); 1312} 1313