1/* 2 * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99) 3 * Copyright (c) by Matze Braun <MatzeBraun@gmx.de>. 4 * Takashi Iwai <tiwai@suse.de> 5 * 6 * Most of the driver code comes from Zach Brown(zab@redhat.com) 7 * Alan Cox OSS Driver 8 * Rewritted from card-es1938.c source. 9 * 10 * TODO: 11 * Perhaps Synth 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 26 * 27 * 28 * Notes from Zach Brown about the driver code 29 * 30 * Hardware Description 31 * 32 * A working Maestro setup contains the Maestro chip wired to a 33 * codec or 2. In the Maestro we have the APUs, the ASSP, and the 34 * Wavecache. The APUs can be though of as virtual audio routing 35 * channels. They can take data from a number of sources and perform 36 * basic encodings of the data. The wavecache is a storehouse for 37 * PCM data. Typically it deals with PCI and interracts with the 38 * APUs. The ASSP is a wacky DSP like device that ESS is loth 39 * to release docs on. Thankfully it isn't required on the Maestro 40 * until you start doing insane things like FM emulation and surround 41 * encoding. The codecs are almost always AC-97 compliant codecs, 42 * but it appears that early Maestros may have had PT101 (an ESS 43 * part?) wired to them. The only real difference in the Maestro 44 * families is external goop like docking capability, memory for 45 * the ASSP, and initialization differences. 46 * 47 * Driver Operation 48 * 49 * We only drive the APU/Wavecache as typical DACs and drive the 50 * mixers in the codecs. There are 64 APUs. We assign 6 to each 51 * /dev/dsp? device. 2 channels for output, and 4 channels for 52 * input. 53 * 54 * Each APU can do a number of things, but we only really use 55 * 3 basic functions. For playback we use them to convert PCM 56 * data fetched over PCI by the wavecahche into analog data that 57 * is handed to the codec. One APU for mono, and a pair for stereo. 58 * When in stereo, the combination of smarts in the APU and Wavecache 59 * decide which wavecache gets the left or right channel. 60 * 61 * For record we still use the old overly mono system. For each in 62 * coming channel the data comes in from the codec, through a 'input' 63 * APU, through another rate converter APU, and then into memory via 64 * the wavecache and PCI. If its stereo, we mash it back into LRLR in 65 * software. The pass between the 2 APUs is supposedly what requires us 66 * to have a 512 byte buffer sitting around in wavecache/memory. 67 * 68 * The wavecache makes our life even more fun. First off, it can 69 * only address the first 28 bits of PCI address space, making it 70 * useless on quite a few architectures. Secondly, its insane. 71 * It claims to fetch from 4 regions of PCI space, each 4 meg in length. 72 * But that doesn't really work. You can only use 1 region. So all our 73 * allocations have to be in 4meg of each other. Booo. Hiss. 74 * So we have a module parameter, dsps_order, that is the order of 75 * the number of dsps to provide. All their buffer space is allocated 76 * on open time. The sonicvibes OSS routines we inherited really want 77 * power of 2 buffers, so we have all those next to each other, then 78 * 512 byte regions for the recording wavecaches. This ends up 79 * wasting quite a bit of memory. The only fixes I can see would be 80 * getting a kernel allocator that could work in zones, or figuring out 81 * just how to coerce the WP into doing what we want. 82 * 83 * The indirection of the various registers means we have to spinlock 84 * nearly all register accesses. We have the main register indirection 85 * like the wave cache, maestro registers, etc. Then we have beasts 86 * like the APU interface that is indirect registers gotten at through 87 * the main maestro indirection. Ouch. We spinlock around the actual 88 * ports on a per card basis. This means spinlock activity at each IO 89 * operation, but the only IO operation clusters are in non critical 90 * paths and it makes the code far easier to follow. Interrupts are 91 * blocked while holding the locks because the int handler has to 92 * get at some of them :(. The mixer interface doesn't, however. 93 * We also have an OSS state lock that is thrown around in a few 94 * places. 95 */ 96 97#include <asm/io.h> 98#include <linux/delay.h> 99#include <linux/interrupt.h> 100#include <linux/init.h> 101#include <linux/pci.h> 102#include <linux/dma-mapping.h> 103#include <linux/slab.h> 104#include <linux/gameport.h> 105#include <linux/moduleparam.h> 106#include <linux/mutex.h> 107#include <linux/input.h> 108 109#include <sound/core.h> 110#include <sound/pcm.h> 111#include <sound/mpu401.h> 112#include <sound/ac97_codec.h> 113#include <sound/initval.h> 114 115#define CARD_NAME "ESS Maestro1/2" 116#define DRIVER_NAME "ES1968" 117 118MODULE_DESCRIPTION("ESS Maestro"); 119MODULE_LICENSE("GPL"); 120MODULE_SUPPORTED_DEVICE("{{ESS,Maestro 2e}," 121 "{ESS,Maestro 2}," 122 "{ESS,Maestro 1}," 123 "{TerraTec,DMX}}"); 124 125#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 126#define SUPPORT_JOYSTICK 1 127#endif 128 129static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */ 130static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 131static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 132static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 }; 133static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 }; 134static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 }; 135static int clock[SNDRV_CARDS]; 136static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2}; 137static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2}; 138#ifdef SUPPORT_JOYSTICK 139static int joystick[SNDRV_CARDS]; 140#endif 141 142module_param_array(index, int, NULL, 0444); 143MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard."); 144module_param_array(id, charp, NULL, 0444); 145MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard."); 146module_param_array(enable, bool, NULL, 0444); 147MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard."); 148module_param_array(total_bufsize, int, NULL, 0444); 149MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB."); 150module_param_array(pcm_substreams_p, int, NULL, 0444); 151MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard."); 152module_param_array(pcm_substreams_c, int, NULL, 0444); 153MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard."); 154module_param_array(clock, int, NULL, 0444); 155MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)"); 156module_param_array(use_pm, int, NULL, 0444); 157MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)"); 158module_param_array(enable_mpu, int, NULL, 0444); 159MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)"); 160#ifdef SUPPORT_JOYSTICK 161module_param_array(joystick, bool, NULL, 0444); 162MODULE_PARM_DESC(joystick, "Enable joystick."); 163#endif 164 165 166#define NR_APUS 64 167#define NR_APU_REGS 16 168 169/* NEC Versas ? */ 170#define NEC_VERSA_SUBID1 0x80581033 171#define NEC_VERSA_SUBID2 0x803c1033 172 173/* Mode Flags */ 174#define ESS_FMT_STEREO 0x01 175#define ESS_FMT_16BIT 0x02 176 177#define DAC_RUNNING 1 178#define ADC_RUNNING 2 179 180/* Values for the ESM_LEGACY_AUDIO_CONTROL */ 181 182#define ESS_DISABLE_AUDIO 0x8000 183#define ESS_ENABLE_SERIAL_IRQ 0x4000 184#define IO_ADRESS_ALIAS 0x0020 185#define MPU401_IRQ_ENABLE 0x0010 186#define MPU401_IO_ENABLE 0x0008 187#define GAME_IO_ENABLE 0x0004 188#define FM_IO_ENABLE 0x0002 189#define SB_IO_ENABLE 0x0001 190 191/* Values for the ESM_CONFIG_A */ 192 193#define PIC_SNOOP1 0x4000 194#define PIC_SNOOP2 0x2000 195#define SAFEGUARD 0x0800 196#define DMA_CLEAR 0x0700 197#define DMA_DDMA 0x0000 198#define DMA_TDMA 0x0100 199#define DMA_PCPCI 0x0200 200#define POST_WRITE 0x0080 201#define PCI_TIMING 0x0040 202#define SWAP_LR 0x0020 203#define SUBTR_DECODE 0x0002 204 205/* Values for the ESM_CONFIG_B */ 206 207#define SPDIF_CONFB 0x0100 208#define HWV_CONFB 0x0080 209#define DEBOUNCE 0x0040 210#define GPIO_CONFB 0x0020 211#define CHI_CONFB 0x0010 212#define IDMA_CONFB 0x0008 /*undoc */ 213#define MIDI_FIX 0x0004 /*undoc */ 214#define IRQ_TO_ISA 0x0001 /*undoc */ 215 216/* Values for Ring Bus Control B */ 217#define RINGB_2CODEC_ID_MASK 0x0003 218#define RINGB_DIS_VALIDATION 0x0008 219#define RINGB_EN_SPDIF 0x0010 220#define RINGB_EN_2CODEC 0x0020 221#define RINGB_SING_BIT_DUAL 0x0040 222 223/* ****Port Adresses**** */ 224 225/* Write & Read */ 226#define ESM_INDEX 0x02 227#define ESM_DATA 0x00 228 229/* AC97 + RingBus */ 230#define ESM_AC97_INDEX 0x30 231#define ESM_AC97_DATA 0x32 232#define ESM_RING_BUS_DEST 0x34 233#define ESM_RING_BUS_CONTR_A 0x36 234#define ESM_RING_BUS_CONTR_B 0x38 235#define ESM_RING_BUS_SDO 0x3A 236 237/* WaveCache*/ 238#define WC_INDEX 0x10 239#define WC_DATA 0x12 240#define WC_CONTROL 0x14 241 242/* ASSP*/ 243#define ASSP_INDEX 0x80 244#define ASSP_MEMORY 0x82 245#define ASSP_DATA 0x84 246#define ASSP_CONTROL_A 0xA2 247#define ASSP_CONTROL_B 0xA4 248#define ASSP_CONTROL_C 0xA6 249#define ASSP_HOSTW_INDEX 0xA8 250#define ASSP_HOSTW_DATA 0xAA 251#define ASSP_HOSTW_IRQ 0xAC 252/* Midi */ 253#define ESM_MPU401_PORT 0x98 254/* Others */ 255#define ESM_PORT_HOST_IRQ 0x18 256 257#define IDR0_DATA_PORT 0x00 258#define IDR1_CRAM_POINTER 0x01 259#define IDR2_CRAM_DATA 0x02 260#define IDR3_WAVE_DATA 0x03 261#define IDR4_WAVE_PTR_LOW 0x04 262#define IDR5_WAVE_PTR_HI 0x05 263#define IDR6_TIMER_CTRL 0x06 264#define IDR7_WAVE_ROMRAM 0x07 265 266#define WRITEABLE_MAP 0xEFFFFF 267#define READABLE_MAP 0x64003F 268 269/* PCI Register */ 270 271#define ESM_LEGACY_AUDIO_CONTROL 0x40 272#define ESM_ACPI_COMMAND 0x54 273#define ESM_CONFIG_A 0x50 274#define ESM_CONFIG_B 0x52 275#define ESM_DDMA 0x60 276 277/* Bob Bits */ 278#define ESM_BOB_ENABLE 0x0001 279#define ESM_BOB_START 0x0001 280 281/* Host IRQ Control Bits */ 282#define ESM_RESET_MAESTRO 0x8000 283#define ESM_RESET_DIRECTSOUND 0x4000 284#define ESM_HIRQ_ClkRun 0x0100 285#define ESM_HIRQ_HW_VOLUME 0x0040 286#define ESM_HIRQ_HARPO 0x0030 /* What's that? */ 287#define ESM_HIRQ_ASSP 0x0010 288#define ESM_HIRQ_DSIE 0x0004 289#define ESM_HIRQ_MPU401 0x0002 290#define ESM_HIRQ_SB 0x0001 291 292/* Host IRQ Status Bits */ 293#define ESM_MPU401_IRQ 0x02 294#define ESM_SB_IRQ 0x01 295#define ESM_SOUND_IRQ 0x04 296#define ESM_ASSP_IRQ 0x10 297#define ESM_HWVOL_IRQ 0x40 298 299#define ESS_SYSCLK 50000000 300#define ESM_BOB_FREQ 200 301#define ESM_BOB_FREQ_MAX 800 302 303#define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */ 304#define ESM_FREQ_ESM2 (50000000L / 1024L) 305 306/* APU Modes: reg 0x00, bit 4-7 */ 307#define ESM_APU_MODE_SHIFT 4 308#define ESM_APU_MODE_MASK (0xf << 4) 309#define ESM_APU_OFF 0x00 310#define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */ 311#define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */ 312#define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */ 313#define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */ 314#define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */ 315#define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */ 316#define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */ 317#define ESM_APU_CORRELATOR 0x08 /* Correlator */ 318#define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */ 319#define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */ 320#define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */ 321#define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */ 322#define ESM_APU_RESERVED1 0x0D /* Reserved 1 */ 323#define ESM_APU_RESERVED2 0x0E /* Reserved 2 */ 324#define ESM_APU_RESERVED3 0x0F /* Reserved 3 */ 325 326/* reg 0x00 */ 327#define ESM_APU_FILTER_Q_SHIFT 0 328#define ESM_APU_FILTER_Q_MASK (3 << 0) 329/* APU Filtey Q Control */ 330#define ESM_APU_FILTER_LESSQ 0x00 331#define ESM_APU_FILTER_MOREQ 0x03 332 333#define ESM_APU_FILTER_TYPE_SHIFT 2 334#define ESM_APU_FILTER_TYPE_MASK (3 << 2) 335#define ESM_APU_ENV_TYPE_SHIFT 8 336#define ESM_APU_ENV_TYPE_MASK (3 << 8) 337#define ESM_APU_ENV_STATE_SHIFT 10 338#define ESM_APU_ENV_STATE_MASK (3 << 10) 339#define ESM_APU_END_CURVE (1 << 12) 340#define ESM_APU_INT_ON_LOOP (1 << 13) 341#define ESM_APU_DMA_ENABLE (1 << 14) 342 343/* reg 0x02 */ 344#define ESM_APU_SUBMIX_GROUP_SHIRT 0 345#define ESM_APU_SUBMIX_GROUP_MASK (7 << 0) 346#define ESM_APU_SUBMIX_MODE (1 << 3) 347#define ESM_APU_6dB (1 << 4) 348#define ESM_APU_DUAL_EFFECT (1 << 5) 349#define ESM_APU_EFFECT_CHANNELS_SHIFT 6 350#define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6) 351 352/* reg 0x03 */ 353#define ESM_APU_STEP_SIZE_MASK 0x0fff 354 355/* reg 0x04 */ 356#define ESM_APU_PHASE_SHIFT 0 357#define ESM_APU_PHASE_MASK (0xff << 0) 358#define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */ 359#define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8) 360 361/* reg 0x05 - wave start offset */ 362/* reg 0x06 - wave end offset */ 363/* reg 0x07 - wave loop length */ 364 365/* reg 0x08 */ 366#define ESM_APU_EFFECT_GAIN_SHIFT 0 367#define ESM_APU_EFFECT_GAIN_MASK (0xff << 0) 368#define ESM_APU_TREMOLO_DEPTH_SHIFT 8 369#define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8) 370#define ESM_APU_TREMOLO_RATE_SHIFT 12 371#define ESM_APU_TREMOLO_RATE_MASK (0xf << 12) 372 373/* reg 0x09 */ 374/* bit 0-7 amplitude dest? */ 375#define ESM_APU_AMPLITUDE_NOW_SHIFT 8 376#define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8) 377 378/* reg 0x0a */ 379#define ESM_APU_POLAR_PAN_SHIFT 0 380#define ESM_APU_POLAR_PAN_MASK (0x3f << 0) 381/* Polar Pan Control */ 382#define ESM_APU_PAN_CENTER_CIRCLE 0x00 383#define ESM_APU_PAN_MIDDLE_RADIUS 0x01 384#define ESM_APU_PAN_OUTSIDE_RADIUS 0x02 385 386#define ESM_APU_FILTER_TUNING_SHIFT 8 387#define ESM_APU_FILTER_TUNING_MASK (0xff << 8) 388 389/* reg 0x0b */ 390#define ESM_APU_DATA_SRC_A_SHIFT 0 391#define ESM_APU_DATA_SRC_A_MASK (0x7f << 0) 392#define ESM_APU_INV_POL_A (1 << 7) 393#define ESM_APU_DATA_SRC_B_SHIFT 8 394#define ESM_APU_DATA_SRC_B_MASK (0x7f << 8) 395#define ESM_APU_INV_POL_B (1 << 15) 396 397#define ESM_APU_VIBRATO_RATE_SHIFT 0 398#define ESM_APU_VIBRATO_RATE_MASK (0xf << 0) 399#define ESM_APU_VIBRATO_DEPTH_SHIFT 4 400#define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4) 401#define ESM_APU_VIBRATO_PHASE_SHIFT 8 402#define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8) 403 404/* reg 0x0c */ 405#define ESM_APU_RADIUS_SELECT (1 << 6) 406 407/* APU Filter Control */ 408#define ESM_APU_FILTER_2POLE_LOPASS 0x00 409#define ESM_APU_FILTER_2POLE_BANDPASS 0x01 410#define ESM_APU_FILTER_2POLE_HIPASS 0x02 411#define ESM_APU_FILTER_1POLE_LOPASS 0x03 412#define ESM_APU_FILTER_1POLE_HIPASS 0x04 413#define ESM_APU_FILTER_OFF 0x05 414 415/* APU ATFP Type */ 416#define ESM_APU_ATFP_AMPLITUDE 0x00 417#define ESM_APU_ATFP_TREMELO 0x01 418#define ESM_APU_ATFP_FILTER 0x02 419#define ESM_APU_ATFP_PAN 0x03 420 421/* APU ATFP Flags */ 422#define ESM_APU_ATFP_FLG_OFF 0x00 423#define ESM_APU_ATFP_FLG_WAIT 0x01 424#define ESM_APU_ATFP_FLG_DONE 0x02 425#define ESM_APU_ATFP_FLG_INPROCESS 0x03 426 427 428/* capture mixing buffer size */ 429#define ESM_MEM_ALIGN 0x1000 430#define ESM_MIXBUF_SIZE 0x400 431 432#define ESM_MODE_PLAY 0 433#define ESM_MODE_CAPTURE 1 434 435 436/* APU use in the driver */ 437enum snd_enum_apu_type { 438 ESM_APU_PCM_PLAY, 439 ESM_APU_PCM_CAPTURE, 440 ESM_APU_PCM_RATECONV, 441 ESM_APU_FREE 442}; 443 444/* chip type */ 445enum { 446 TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E 447}; 448 449/* DMA Hack! */ 450struct esm_memory { 451 struct snd_dma_buffer buf; 452 int empty; /* status */ 453 struct list_head list; 454}; 455 456/* Playback Channel */ 457struct esschan { 458 int running; 459 460 u8 apu[4]; 461 u8 apu_mode[4]; 462 463 /* playback/capture pcm buffer */ 464 struct esm_memory *memory; 465 /* capture mixer buffer */ 466 struct esm_memory *mixbuf; 467 468 unsigned int hwptr; /* current hw pointer in bytes */ 469 unsigned int count; /* sample counter in bytes */ 470 unsigned int dma_size; /* total buffer size in bytes */ 471 unsigned int frag_size; /* period size in bytes */ 472 unsigned int wav_shift; 473 u16 base[4]; /* offset for ptr */ 474 475 /* stereo/16bit flag */ 476 unsigned char fmt; 477 int mode; /* playback / capture */ 478 479 int bob_freq; /* required timer frequency */ 480 481 struct snd_pcm_substream *substream; 482 483 /* linked list */ 484 struct list_head list; 485 486#ifdef CONFIG_PM 487 u16 wc_map[4]; 488#endif 489}; 490 491struct es1968 { 492 /* Module Config */ 493 int total_bufsize; /* in bytes */ 494 495 int playback_streams, capture_streams; 496 497 unsigned int clock; /* clock */ 498 /* for clock measurement */ 499 unsigned int in_measurement: 1; 500 unsigned int measure_apu; 501 unsigned int measure_lastpos; 502 unsigned int measure_count; 503 504 /* buffer */ 505 struct snd_dma_buffer dma; 506 507 /* Resources... */ 508 int irq; 509 unsigned long io_port; 510 int type; 511 struct pci_dev *pci; 512 struct snd_card *card; 513 struct snd_pcm *pcm; 514 int do_pm; /* power-management enabled */ 515 516 /* DMA memory block */ 517 struct list_head buf_list; 518 519 /* ALSA Stuff */ 520 struct snd_ac97 *ac97; 521 struct snd_rawmidi *rmidi; 522 523 spinlock_t reg_lock; 524 unsigned int in_suspend; 525 526 /* Maestro Stuff */ 527 u16 maestro_map[32]; 528 int bobclient; /* active timer instancs */ 529 int bob_freq; /* timer frequency */ 530 struct mutex memory_mutex; /* memory lock */ 531 532 /* APU states */ 533 unsigned char apu[NR_APUS]; 534 535 /* active substreams */ 536 struct list_head substream_list; 537 spinlock_t substream_lock; 538 539#ifdef CONFIG_PM 540 u16 apu_map[NR_APUS][NR_APU_REGS]; 541#endif 542 543#ifdef SUPPORT_JOYSTICK 544 struct gameport *gameport; 545#endif 546 547#ifdef CONFIG_SND_ES1968_INPUT 548 struct input_dev *input_dev; 549 char phys[64]; /* physical device path */ 550#else 551 struct snd_kcontrol *master_switch; /* for h/w volume control */ 552 struct snd_kcontrol *master_volume; 553 spinlock_t ac97_lock; 554 struct tasklet_struct hwvol_tq; 555#endif 556}; 557 558static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id); 559 560static DEFINE_PCI_DEVICE_TABLE(snd_es1968_ids) = { 561 /* Maestro 1 */ 562 { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO }, 563 /* Maestro 2 */ 564 { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 }, 565 /* Maestro 2E */ 566 { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E }, 567 { 0, } 568}; 569 570MODULE_DEVICE_TABLE(pci, snd_es1968_ids); 571 572/* ********************* 573 * Low Level Funcs! * 574 *********************/ 575 576/* no spinlock */ 577static void __maestro_write(struct es1968 *chip, u16 reg, u16 data) 578{ 579 outw(reg, chip->io_port + ESM_INDEX); 580 outw(data, chip->io_port + ESM_DATA); 581 chip->maestro_map[reg] = data; 582} 583 584static inline void maestro_write(struct es1968 *chip, u16 reg, u16 data) 585{ 586 unsigned long flags; 587 spin_lock_irqsave(&chip->reg_lock, flags); 588 __maestro_write(chip, reg, data); 589 spin_unlock_irqrestore(&chip->reg_lock, flags); 590} 591 592/* no spinlock */ 593static u16 __maestro_read(struct es1968 *chip, u16 reg) 594{ 595 if (READABLE_MAP & (1 << reg)) { 596 outw(reg, chip->io_port + ESM_INDEX); 597 chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA); 598 } 599 return chip->maestro_map[reg]; 600} 601 602static inline u16 maestro_read(struct es1968 *chip, u16 reg) 603{ 604 unsigned long flags; 605 u16 result; 606 spin_lock_irqsave(&chip->reg_lock, flags); 607 result = __maestro_read(chip, reg); 608 spin_unlock_irqrestore(&chip->reg_lock, flags); 609 return result; 610} 611 612/* Wait for the codec bus to be free */ 613static int snd_es1968_ac97_wait(struct es1968 *chip) 614{ 615 int timeout = 100000; 616 617 while (timeout-- > 0) { 618 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1)) 619 return 0; 620 cond_resched(); 621 } 622 snd_printd("es1968: ac97 timeout\n"); 623 return 1; /* timeout */ 624} 625 626static int snd_es1968_ac97_wait_poll(struct es1968 *chip) 627{ 628 int timeout = 100000; 629 630 while (timeout-- > 0) { 631 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1)) 632 return 0; 633 } 634 snd_printd("es1968: ac97 timeout\n"); 635 return 1; /* timeout */ 636} 637 638static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) 639{ 640 struct es1968 *chip = ac97->private_data; 641#ifndef CONFIG_SND_ES1968_INPUT 642 unsigned long flags; 643#endif 644 645 snd_es1968_ac97_wait(chip); 646 647 /* Write the bus */ 648#ifndef CONFIG_SND_ES1968_INPUT 649 spin_lock_irqsave(&chip->ac97_lock, flags); 650#endif 651 outw(val, chip->io_port + ESM_AC97_DATA); 652 /*msleep(1);*/ 653 outb(reg, chip->io_port + ESM_AC97_INDEX); 654 /*msleep(1);*/ 655#ifndef CONFIG_SND_ES1968_INPUT 656 spin_unlock_irqrestore(&chip->ac97_lock, flags); 657#endif 658} 659 660static unsigned short snd_es1968_ac97_read(struct snd_ac97 *ac97, unsigned short reg) 661{ 662 u16 data = 0; 663 struct es1968 *chip = ac97->private_data; 664#ifndef CONFIG_SND_ES1968_INPUT 665 unsigned long flags; 666#endif 667 668 snd_es1968_ac97_wait(chip); 669 670#ifndef CONFIG_SND_ES1968_INPUT 671 spin_lock_irqsave(&chip->ac97_lock, flags); 672#endif 673 outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX); 674 /*msleep(1);*/ 675 676 if (!snd_es1968_ac97_wait_poll(chip)) { 677 data = inw(chip->io_port + ESM_AC97_DATA); 678 /*msleep(1);*/ 679 } 680#ifndef CONFIG_SND_ES1968_INPUT 681 spin_unlock_irqrestore(&chip->ac97_lock, flags); 682#endif 683 684 return data; 685} 686 687/* no spinlock */ 688static void apu_index_set(struct es1968 *chip, u16 index) 689{ 690 int i; 691 __maestro_write(chip, IDR1_CRAM_POINTER, index); 692 for (i = 0; i < 1000; i++) 693 if (__maestro_read(chip, IDR1_CRAM_POINTER) == index) 694 return; 695 snd_printd("es1968: APU register select failed. (Timeout)\n"); 696} 697 698/* no spinlock */ 699static void apu_data_set(struct es1968 *chip, u16 data) 700{ 701 int i; 702 for (i = 0; i < 1000; i++) { 703 if (__maestro_read(chip, IDR0_DATA_PORT) == data) 704 return; 705 __maestro_write(chip, IDR0_DATA_PORT, data); 706 } 707 snd_printd("es1968: APU register set probably failed (Timeout)!\n"); 708} 709 710/* no spinlock */ 711static void __apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data) 712{ 713 if (snd_BUG_ON(channel >= NR_APUS)) 714 return; 715#ifdef CONFIG_PM 716 chip->apu_map[channel][reg] = data; 717#endif 718 reg |= (channel << 4); 719 apu_index_set(chip, reg); 720 apu_data_set(chip, data); 721} 722 723static void apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data) 724{ 725 unsigned long flags; 726 spin_lock_irqsave(&chip->reg_lock, flags); 727 __apu_set_register(chip, channel, reg, data); 728 spin_unlock_irqrestore(&chip->reg_lock, flags); 729} 730 731static u16 __apu_get_register(struct es1968 *chip, u16 channel, u8 reg) 732{ 733 if (snd_BUG_ON(channel >= NR_APUS)) 734 return 0; 735 reg |= (channel << 4); 736 apu_index_set(chip, reg); 737 return __maestro_read(chip, IDR0_DATA_PORT); 738} 739 740static u16 apu_get_register(struct es1968 *chip, u16 channel, u8 reg) 741{ 742 unsigned long flags; 743 u16 v; 744 spin_lock_irqsave(&chip->reg_lock, flags); 745 v = __apu_get_register(chip, channel, reg); 746 spin_unlock_irqrestore(&chip->reg_lock, flags); 747 return v; 748} 749 750 751static void wave_set_register(struct es1968 *chip, u16 reg, u16 value) 752{ 753 unsigned long flags; 754 755 spin_lock_irqsave(&chip->reg_lock, flags); 756 outw(reg, chip->io_port + WC_INDEX); 757 outw(value, chip->io_port + WC_DATA); 758 spin_unlock_irqrestore(&chip->reg_lock, flags); 759} 760 761static u16 wave_get_register(struct es1968 *chip, u16 reg) 762{ 763 unsigned long flags; 764 u16 value; 765 766 spin_lock_irqsave(&chip->reg_lock, flags); 767 outw(reg, chip->io_port + WC_INDEX); 768 value = inw(chip->io_port + WC_DATA); 769 spin_unlock_irqrestore(&chip->reg_lock, flags); 770 771 return value; 772} 773 774/* ******************* 775 * Bob the Timer! * 776 *******************/ 777 778static void snd_es1968_bob_stop(struct es1968 *chip) 779{ 780 u16 reg; 781 782 reg = __maestro_read(chip, 0x11); 783 reg &= ~ESM_BOB_ENABLE; 784 __maestro_write(chip, 0x11, reg); 785 reg = __maestro_read(chip, 0x17); 786 reg &= ~ESM_BOB_START; 787 __maestro_write(chip, 0x17, reg); 788} 789 790static void snd_es1968_bob_start(struct es1968 *chip) 791{ 792 int prescale; 793 int divide; 794 795 /* compute ideal interrupt frequency for buffer size & play rate */ 796 /* first, find best prescaler value to match freq */ 797 for (prescale = 5; prescale < 12; prescale++) 798 if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9))) 799 break; 800 801 /* next, back off prescaler whilst getting divider into optimum range */ 802 divide = 1; 803 while ((prescale > 5) && (divide < 32)) { 804 prescale--; 805 divide <<= 1; 806 } 807 divide >>= 1; 808 809 /* now fine-tune the divider for best match */ 810 for (; divide < 31; divide++) 811 if (chip->bob_freq > 812 ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break; 813 814 /* divide = 0 is illegal, but don't let prescale = 4! */ 815 if (divide == 0) { 816 divide++; 817 if (prescale > 5) 818 prescale--; 819 } else if (divide > 1) 820 divide--; 821 822 __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */ 823 824 /* Now set IDR 11/17 */ 825 __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1); 826 __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1); 827} 828 829/* call with substream spinlock */ 830static void snd_es1968_bob_inc(struct es1968 *chip, int freq) 831{ 832 chip->bobclient++; 833 if (chip->bobclient == 1) { 834 chip->bob_freq = freq; 835 snd_es1968_bob_start(chip); 836 } else if (chip->bob_freq < freq) { 837 snd_es1968_bob_stop(chip); 838 chip->bob_freq = freq; 839 snd_es1968_bob_start(chip); 840 } 841} 842 843/* call with substream spinlock */ 844static void snd_es1968_bob_dec(struct es1968 *chip) 845{ 846 chip->bobclient--; 847 if (chip->bobclient <= 0) 848 snd_es1968_bob_stop(chip); 849 else if (chip->bob_freq > ESM_BOB_FREQ) { 850 /* check reduction of timer frequency */ 851 int max_freq = ESM_BOB_FREQ; 852 struct esschan *es; 853 list_for_each_entry(es, &chip->substream_list, list) { 854 if (max_freq < es->bob_freq) 855 max_freq = es->bob_freq; 856 } 857 if (max_freq != chip->bob_freq) { 858 snd_es1968_bob_stop(chip); 859 chip->bob_freq = max_freq; 860 snd_es1968_bob_start(chip); 861 } 862 } 863} 864 865static int 866snd_es1968_calc_bob_rate(struct es1968 *chip, struct esschan *es, 867 struct snd_pcm_runtime *runtime) 868{ 869 /* we acquire 4 interrupts per period for precise control.. */ 870 int freq = runtime->rate * 4; 871 if (es->fmt & ESS_FMT_STEREO) 872 freq <<= 1; 873 if (es->fmt & ESS_FMT_16BIT) 874 freq <<= 1; 875 freq /= es->frag_size; 876 if (freq < ESM_BOB_FREQ) 877 freq = ESM_BOB_FREQ; 878 else if (freq > ESM_BOB_FREQ_MAX) 879 freq = ESM_BOB_FREQ_MAX; 880 return freq; 881} 882 883 884/************* 885 * PCM Part * 886 *************/ 887 888static u32 snd_es1968_compute_rate(struct es1968 *chip, u32 freq) 889{ 890 u32 rate = (freq << 16) / chip->clock; 891 return rate; 892} 893 894/* get current pointer */ 895static inline unsigned int 896snd_es1968_get_dma_ptr(struct es1968 *chip, struct esschan *es) 897{ 898 unsigned int offset; 899 900 offset = apu_get_register(chip, es->apu[0], 5); 901 902 offset -= es->base[0]; 903 904 return (offset & 0xFFFE); /* hardware is in words */ 905} 906 907static void snd_es1968_apu_set_freq(struct es1968 *chip, int apu, int freq) 908{ 909 apu_set_register(chip, apu, 2, 910 (apu_get_register(chip, apu, 2) & 0x00FF) | 911 ((freq & 0xff) << 8) | 0x10); 912 apu_set_register(chip, apu, 3, freq >> 8); 913} 914 915/* spin lock held */ 916static inline void snd_es1968_trigger_apu(struct es1968 *esm, int apu, int mode) 917{ 918 /* set the APU mode */ 919 __apu_set_register(esm, apu, 0, 920 (__apu_get_register(esm, apu, 0) & 0xff0f) | 921 (mode << 4)); 922} 923 924static void snd_es1968_pcm_start(struct es1968 *chip, struct esschan *es) 925{ 926 spin_lock(&chip->reg_lock); 927 __apu_set_register(chip, es->apu[0], 5, es->base[0]); 928 snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]); 929 if (es->mode == ESM_MODE_CAPTURE) { 930 __apu_set_register(chip, es->apu[2], 5, es->base[2]); 931 snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]); 932 } 933 if (es->fmt & ESS_FMT_STEREO) { 934 __apu_set_register(chip, es->apu[1], 5, es->base[1]); 935 snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]); 936 if (es->mode == ESM_MODE_CAPTURE) { 937 __apu_set_register(chip, es->apu[3], 5, es->base[3]); 938 snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]); 939 } 940 } 941 spin_unlock(&chip->reg_lock); 942} 943 944static void snd_es1968_pcm_stop(struct es1968 *chip, struct esschan *es) 945{ 946 spin_lock(&chip->reg_lock); 947 snd_es1968_trigger_apu(chip, es->apu[0], 0); 948 snd_es1968_trigger_apu(chip, es->apu[1], 0); 949 if (es->mode == ESM_MODE_CAPTURE) { 950 snd_es1968_trigger_apu(chip, es->apu[2], 0); 951 snd_es1968_trigger_apu(chip, es->apu[3], 0); 952 } 953 spin_unlock(&chip->reg_lock); 954} 955 956/* set the wavecache control reg */ 957static void snd_es1968_program_wavecache(struct es1968 *chip, struct esschan *es, 958 int channel, u32 addr, int capture) 959{ 960 u32 tmpval = (addr - 0x10) & 0xFFF8; 961 962 if (! capture) { 963 if (!(es->fmt & ESS_FMT_16BIT)) 964 tmpval |= 4; /* 8bit */ 965 if (es->fmt & ESS_FMT_STEREO) 966 tmpval |= 2; /* stereo */ 967 } 968 969 /* set the wavecache control reg */ 970 wave_set_register(chip, es->apu[channel] << 3, tmpval); 971 972#ifdef CONFIG_PM 973 es->wc_map[channel] = tmpval; 974#endif 975} 976 977 978static void snd_es1968_playback_setup(struct es1968 *chip, struct esschan *es, 979 struct snd_pcm_runtime *runtime) 980{ 981 u32 pa; 982 int high_apu = 0; 983 int channel, apu; 984 int i, size; 985 unsigned long flags; 986 u32 freq; 987 988 size = es->dma_size >> es->wav_shift; 989 990 if (es->fmt & ESS_FMT_STEREO) 991 high_apu++; 992 993 for (channel = 0; channel <= high_apu; channel++) { 994 apu = es->apu[channel]; 995 996 snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0); 997 998 /* Offset to PCMBAR */ 999 pa = es->memory->buf.addr; 1000 pa -= chip->dma.addr; 1001 pa >>= 1; /* words */ 1002 1003 pa |= 0x00400000; /* System RAM (Bit 22) */ 1004 1005 if (es->fmt & ESS_FMT_STEREO) { 1006 /* Enable stereo */ 1007 if (channel) 1008 pa |= 0x00800000; /* (Bit 23) */ 1009 if (es->fmt & ESS_FMT_16BIT) 1010 pa >>= 1; 1011 } 1012 1013 /* base offset of dma calcs when reading the pointer 1014 on this left one */ 1015 es->base[channel] = pa & 0xFFFF; 1016 1017 for (i = 0; i < 16; i++) 1018 apu_set_register(chip, apu, i, 0x0000); 1019 1020 /* Load the buffer into the wave engine */ 1021 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8); 1022 apu_set_register(chip, apu, 5, pa & 0xFFFF); 1023 apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF); 1024 /* setting loop == sample len */ 1025 apu_set_register(chip, apu, 7, size); 1026 1027 /* clear effects/env.. */ 1028 apu_set_register(chip, apu, 8, 0x0000); 1029 /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */ 1030 apu_set_register(chip, apu, 9, 0xD000); 1031 1032 /* clear routing stuff */ 1033 apu_set_register(chip, apu, 11, 0x0000); 1034 /* dma on, no envelopes, filter to all 1s) */ 1035 apu_set_register(chip, apu, 0, 0x400F); 1036 1037 if (es->fmt & ESS_FMT_16BIT) 1038 es->apu_mode[channel] = ESM_APU_16BITLINEAR; 1039 else 1040 es->apu_mode[channel] = ESM_APU_8BITLINEAR; 1041 1042 if (es->fmt & ESS_FMT_STEREO) { 1043 /* set panning: left or right */ 1044 /* Check: different panning. On my Canyon 3D Chipset the 1045 Channels are swapped. I don't know, about the output 1046 to the SPDif Link. Perhaps you have to change this 1047 and not the APU Regs 4-5. */ 1048 apu_set_register(chip, apu, 10, 1049 0x8F00 | (channel ? 0 : 0x10)); 1050 es->apu_mode[channel] += 1; /* stereo */ 1051 } else 1052 apu_set_register(chip, apu, 10, 0x8F08); 1053 } 1054 1055 spin_lock_irqsave(&chip->reg_lock, flags); 1056 /* clear WP interrupts */ 1057 outw(1, chip->io_port + 0x04); 1058 /* enable WP ints */ 1059 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); 1060 spin_unlock_irqrestore(&chip->reg_lock, flags); 1061 1062 freq = runtime->rate; 1063 /* set frequency */ 1064 if (freq > 48000) 1065 freq = 48000; 1066 if (freq < 4000) 1067 freq = 4000; 1068 1069 /* hmmm.. */ 1070 if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO)) 1071 freq >>= 1; 1072 1073 freq = snd_es1968_compute_rate(chip, freq); 1074 1075 /* Load the frequency, turn on 6dB */ 1076 snd_es1968_apu_set_freq(chip, es->apu[0], freq); 1077 snd_es1968_apu_set_freq(chip, es->apu[1], freq); 1078} 1079 1080 1081static void init_capture_apu(struct es1968 *chip, struct esschan *es, int channel, 1082 unsigned int pa, unsigned int bsize, 1083 int mode, int route) 1084{ 1085 int i, apu = es->apu[channel]; 1086 1087 es->apu_mode[channel] = mode; 1088 1089 /* set the wavecache control reg */ 1090 snd_es1968_program_wavecache(chip, es, channel, pa, 1); 1091 1092 /* Offset to PCMBAR */ 1093 pa -= chip->dma.addr; 1094 pa >>= 1; /* words */ 1095 1096 /* base offset of dma calcs when reading the pointer 1097 on this left one */ 1098 es->base[channel] = pa & 0xFFFF; 1099 pa |= 0x00400000; /* bit 22 -> System RAM */ 1100 1101 /* Begin loading the APU */ 1102 for (i = 0; i < 16; i++) 1103 apu_set_register(chip, apu, i, 0x0000); 1104 1105 /* need to enable subgroups.. and we should probably 1106 have different groups for different /dev/dsps.. */ 1107 apu_set_register(chip, apu, 2, 0x8); 1108 1109 /* Load the buffer into the wave engine */ 1110 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8); 1111 apu_set_register(chip, apu, 5, pa & 0xFFFF); 1112 apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF); 1113 apu_set_register(chip, apu, 7, bsize); 1114 /* clear effects/env.. */ 1115 apu_set_register(chip, apu, 8, 0x00F0); 1116 /* amplitude now? sure. why not. */ 1117 apu_set_register(chip, apu, 9, 0x0000); 1118 /* set filter tune, radius, polar pan */ 1119 apu_set_register(chip, apu, 10, 0x8F08); 1120 /* route input */ 1121 apu_set_register(chip, apu, 11, route); 1122 /* dma on, no envelopes, filter to all 1s) */ 1123 apu_set_register(chip, apu, 0, 0x400F); 1124} 1125 1126static void snd_es1968_capture_setup(struct es1968 *chip, struct esschan *es, 1127 struct snd_pcm_runtime *runtime) 1128{ 1129 int size; 1130 u32 freq; 1131 unsigned long flags; 1132 1133 size = es->dma_size >> es->wav_shift; 1134 1135 /* APU assignments: 1136 0 = mono/left SRC 1137 1 = right SRC 1138 2 = mono/left Input Mixer 1139 3 = right Input Mixer 1140 */ 1141 /* data seems to flow from the codec, through an apu into 1142 the 'mixbuf' bit of page, then through the SRC apu 1143 and out to the real 'buffer'. ok. sure. */ 1144 1145 /* input mixer (left/mono) */ 1146 /* parallel in crap, see maestro reg 0xC [8-11] */ 1147 init_capture_apu(chip, es, 2, 1148 es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */ 1149 ESM_APU_INPUTMIXER, 0x14); 1150 /* SRC (left/mono); get input from inputing apu */ 1151 init_capture_apu(chip, es, 0, es->memory->buf.addr, size, 1152 ESM_APU_SRCONVERTOR, es->apu[2]); 1153 if (es->fmt & ESS_FMT_STEREO) { 1154 /* input mixer (right) */ 1155 init_capture_apu(chip, es, 3, 1156 es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2, 1157 ESM_MIXBUF_SIZE/4, /* in words */ 1158 ESM_APU_INPUTMIXER, 0x15); 1159 /* SRC (right) */ 1160 init_capture_apu(chip, es, 1, 1161 es->memory->buf.addr + size*2, size, 1162 ESM_APU_SRCONVERTOR, es->apu[3]); 1163 } 1164 1165 freq = runtime->rate; 1166 /* Sample Rate conversion APUs don't like 0x10000 for their rate */ 1167 if (freq > 47999) 1168 freq = 47999; 1169 if (freq < 4000) 1170 freq = 4000; 1171 1172 freq = snd_es1968_compute_rate(chip, freq); 1173 1174 /* Load the frequency, turn on 6dB */ 1175 snd_es1968_apu_set_freq(chip, es->apu[0], freq); 1176 snd_es1968_apu_set_freq(chip, es->apu[1], freq); 1177 1178 /* fix mixer rate at 48khz. and its _must_ be 0x10000. */ 1179 freq = 0x10000; 1180 snd_es1968_apu_set_freq(chip, es->apu[2], freq); 1181 snd_es1968_apu_set_freq(chip, es->apu[3], freq); 1182 1183 spin_lock_irqsave(&chip->reg_lock, flags); 1184 /* clear WP interrupts */ 1185 outw(1, chip->io_port + 0x04); 1186 /* enable WP ints */ 1187 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); 1188 spin_unlock_irqrestore(&chip->reg_lock, flags); 1189} 1190 1191/******************* 1192 * ALSA Interface * 1193 *******************/ 1194 1195static int snd_es1968_pcm_prepare(struct snd_pcm_substream *substream) 1196{ 1197 struct es1968 *chip = snd_pcm_substream_chip(substream); 1198 struct snd_pcm_runtime *runtime = substream->runtime; 1199 struct esschan *es = runtime->private_data; 1200 1201 es->dma_size = snd_pcm_lib_buffer_bytes(substream); 1202 es->frag_size = snd_pcm_lib_period_bytes(substream); 1203 1204 es->wav_shift = 1; /* maestro handles always 16bit */ 1205 es->fmt = 0; 1206 if (snd_pcm_format_width(runtime->format) == 16) 1207 es->fmt |= ESS_FMT_16BIT; 1208 if (runtime->channels > 1) { 1209 es->fmt |= ESS_FMT_STEREO; 1210 if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */ 1211 es->wav_shift++; 1212 } 1213 es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime); 1214 1215 switch (es->mode) { 1216 case ESM_MODE_PLAY: 1217 snd_es1968_playback_setup(chip, es, runtime); 1218 break; 1219 case ESM_MODE_CAPTURE: 1220 snd_es1968_capture_setup(chip, es, runtime); 1221 break; 1222 } 1223 1224 return 0; 1225} 1226 1227static int snd_es1968_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1228{ 1229 struct es1968 *chip = snd_pcm_substream_chip(substream); 1230 struct esschan *es = substream->runtime->private_data; 1231 1232 spin_lock(&chip->substream_lock); 1233 switch (cmd) { 1234 case SNDRV_PCM_TRIGGER_START: 1235 case SNDRV_PCM_TRIGGER_RESUME: 1236 if (es->running) 1237 break; 1238 snd_es1968_bob_inc(chip, es->bob_freq); 1239 es->count = 0; 1240 es->hwptr = 0; 1241 snd_es1968_pcm_start(chip, es); 1242 es->running = 1; 1243 break; 1244 case SNDRV_PCM_TRIGGER_STOP: 1245 case SNDRV_PCM_TRIGGER_SUSPEND: 1246 if (! es->running) 1247 break; 1248 snd_es1968_pcm_stop(chip, es); 1249 es->running = 0; 1250 snd_es1968_bob_dec(chip); 1251 break; 1252 } 1253 spin_unlock(&chip->substream_lock); 1254 return 0; 1255} 1256 1257static snd_pcm_uframes_t snd_es1968_pcm_pointer(struct snd_pcm_substream *substream) 1258{ 1259 struct es1968 *chip = snd_pcm_substream_chip(substream); 1260 struct esschan *es = substream->runtime->private_data; 1261 unsigned int ptr; 1262 1263 ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift; 1264 1265 return bytes_to_frames(substream->runtime, ptr % es->dma_size); 1266} 1267 1268static struct snd_pcm_hardware snd_es1968_playback = { 1269 .info = (SNDRV_PCM_INFO_MMAP | 1270 SNDRV_PCM_INFO_MMAP_VALID | 1271 SNDRV_PCM_INFO_INTERLEAVED | 1272 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1273 /*SNDRV_PCM_INFO_PAUSE |*/ 1274 SNDRV_PCM_INFO_RESUME), 1275 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1276 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1277 .rate_min = 4000, 1278 .rate_max = 48000, 1279 .channels_min = 1, 1280 .channels_max = 2, 1281 .buffer_bytes_max = 65536, 1282 .period_bytes_min = 256, 1283 .period_bytes_max = 65536, 1284 .periods_min = 1, 1285 .periods_max = 1024, 1286 .fifo_size = 0, 1287}; 1288 1289static struct snd_pcm_hardware snd_es1968_capture = { 1290 .info = (SNDRV_PCM_INFO_NONINTERLEAVED | 1291 SNDRV_PCM_INFO_MMAP | 1292 SNDRV_PCM_INFO_MMAP_VALID | 1293 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1294 /*SNDRV_PCM_INFO_PAUSE |*/ 1295 SNDRV_PCM_INFO_RESUME), 1296 .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE, 1297 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1298 .rate_min = 4000, 1299 .rate_max = 48000, 1300 .channels_min = 1, 1301 .channels_max = 2, 1302 .buffer_bytes_max = 65536, 1303 .period_bytes_min = 256, 1304 .period_bytes_max = 65536, 1305 .periods_min = 1, 1306 .periods_max = 1024, 1307 .fifo_size = 0, 1308}; 1309 1310/* ************************* 1311 * DMA memory management * 1312 *************************/ 1313 1314/* Because the Maestro can only take addresses relative to the PCM base address 1315 register :( */ 1316 1317static int calc_available_memory_size(struct es1968 *chip) 1318{ 1319 int max_size = 0; 1320 struct esm_memory *buf; 1321 1322 mutex_lock(&chip->memory_mutex); 1323 list_for_each_entry(buf, &chip->buf_list, list) { 1324 if (buf->empty && buf->buf.bytes > max_size) 1325 max_size = buf->buf.bytes; 1326 } 1327 mutex_unlock(&chip->memory_mutex); 1328 if (max_size >= 128*1024) 1329 max_size = 127*1024; 1330 return max_size; 1331} 1332 1333/* allocate a new memory chunk with the specified size */ 1334static struct esm_memory *snd_es1968_new_memory(struct es1968 *chip, int size) 1335{ 1336 struct esm_memory *buf; 1337 1338 size = ALIGN(size, ESM_MEM_ALIGN); 1339 mutex_lock(&chip->memory_mutex); 1340 list_for_each_entry(buf, &chip->buf_list, list) { 1341 if (buf->empty && buf->buf.bytes >= size) 1342 goto __found; 1343 } 1344 mutex_unlock(&chip->memory_mutex); 1345 return NULL; 1346 1347__found: 1348 if (buf->buf.bytes > size) { 1349 struct esm_memory *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL); 1350 if (chunk == NULL) { 1351 mutex_unlock(&chip->memory_mutex); 1352 return NULL; 1353 } 1354 chunk->buf = buf->buf; 1355 chunk->buf.bytes -= size; 1356 chunk->buf.area += size; 1357 chunk->buf.addr += size; 1358 chunk->empty = 1; 1359 buf->buf.bytes = size; 1360 list_add(&chunk->list, &buf->list); 1361 } 1362 buf->empty = 0; 1363 mutex_unlock(&chip->memory_mutex); 1364 return buf; 1365} 1366 1367/* free a memory chunk */ 1368static void snd_es1968_free_memory(struct es1968 *chip, struct esm_memory *buf) 1369{ 1370 struct esm_memory *chunk; 1371 1372 mutex_lock(&chip->memory_mutex); 1373 buf->empty = 1; 1374 if (buf->list.prev != &chip->buf_list) { 1375 chunk = list_entry(buf->list.prev, struct esm_memory, list); 1376 if (chunk->empty) { 1377 chunk->buf.bytes += buf->buf.bytes; 1378 list_del(&buf->list); 1379 kfree(buf); 1380 buf = chunk; 1381 } 1382 } 1383 if (buf->list.next != &chip->buf_list) { 1384 chunk = list_entry(buf->list.next, struct esm_memory, list); 1385 if (chunk->empty) { 1386 buf->buf.bytes += chunk->buf.bytes; 1387 list_del(&chunk->list); 1388 kfree(chunk); 1389 } 1390 } 1391 mutex_unlock(&chip->memory_mutex); 1392} 1393 1394static void snd_es1968_free_dmabuf(struct es1968 *chip) 1395{ 1396 struct list_head *p; 1397 1398 if (! chip->dma.area) 1399 return; 1400 snd_dma_reserve_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci)); 1401 while ((p = chip->buf_list.next) != &chip->buf_list) { 1402 struct esm_memory *chunk = list_entry(p, struct esm_memory, list); 1403 list_del(p); 1404 kfree(chunk); 1405 } 1406} 1407 1408static int __devinit 1409snd_es1968_init_dmabuf(struct es1968 *chip) 1410{ 1411 int err; 1412 struct esm_memory *chunk; 1413 1414 chip->dma.dev.type = SNDRV_DMA_TYPE_DEV; 1415 chip->dma.dev.dev = snd_dma_pci_data(chip->pci); 1416 if (! snd_dma_get_reserved_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci))) { 1417 err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV, 1418 snd_dma_pci_data(chip->pci), 1419 chip->total_bufsize, &chip->dma); 1420 if (err < 0 || ! chip->dma.area) { 1421 snd_printk(KERN_ERR "es1968: can't allocate dma pages for size %d\n", 1422 chip->total_bufsize); 1423 return -ENOMEM; 1424 } 1425 if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) { 1426 snd_dma_free_pages(&chip->dma); 1427 snd_printk(KERN_ERR "es1968: DMA buffer beyond 256MB.\n"); 1428 return -ENOMEM; 1429 } 1430 } 1431 1432 INIT_LIST_HEAD(&chip->buf_list); 1433 /* allocate an empty chunk */ 1434 chunk = kmalloc(sizeof(*chunk), GFP_KERNEL); 1435 if (chunk == NULL) { 1436 snd_es1968_free_dmabuf(chip); 1437 return -ENOMEM; 1438 } 1439 memset(chip->dma.area, 0, ESM_MEM_ALIGN); 1440 chunk->buf = chip->dma; 1441 chunk->buf.area += ESM_MEM_ALIGN; 1442 chunk->buf.addr += ESM_MEM_ALIGN; 1443 chunk->buf.bytes -= ESM_MEM_ALIGN; 1444 chunk->empty = 1; 1445 list_add(&chunk->list, &chip->buf_list); 1446 1447 return 0; 1448} 1449 1450/* setup the dma_areas */ 1451/* buffer is extracted from the pre-allocated memory chunk */ 1452static int snd_es1968_hw_params(struct snd_pcm_substream *substream, 1453 struct snd_pcm_hw_params *hw_params) 1454{ 1455 struct es1968 *chip = snd_pcm_substream_chip(substream); 1456 struct snd_pcm_runtime *runtime = substream->runtime; 1457 struct esschan *chan = runtime->private_data; 1458 int size = params_buffer_bytes(hw_params); 1459 1460 if (chan->memory) { 1461 if (chan->memory->buf.bytes >= size) { 1462 runtime->dma_bytes = size; 1463 return 0; 1464 } 1465 snd_es1968_free_memory(chip, chan->memory); 1466 } 1467 chan->memory = snd_es1968_new_memory(chip, size); 1468 if (chan->memory == NULL) { 1469 // snd_printd("cannot allocate dma buffer: size = %d\n", size); 1470 return -ENOMEM; 1471 } 1472 snd_pcm_set_runtime_buffer(substream, &chan->memory->buf); 1473 return 1; /* area was changed */ 1474} 1475 1476/* remove dma areas if allocated */ 1477static int snd_es1968_hw_free(struct snd_pcm_substream *substream) 1478{ 1479 struct es1968 *chip = snd_pcm_substream_chip(substream); 1480 struct snd_pcm_runtime *runtime = substream->runtime; 1481 struct esschan *chan; 1482 1483 if (runtime->private_data == NULL) 1484 return 0; 1485 chan = runtime->private_data; 1486 if (chan->memory) { 1487 snd_es1968_free_memory(chip, chan->memory); 1488 chan->memory = NULL; 1489 } 1490 return 0; 1491} 1492 1493 1494/* 1495 * allocate APU pair 1496 */ 1497static int snd_es1968_alloc_apu_pair(struct es1968 *chip, int type) 1498{ 1499 int apu; 1500 1501 for (apu = 0; apu < NR_APUS; apu += 2) { 1502 if (chip->apu[apu] == ESM_APU_FREE && 1503 chip->apu[apu + 1] == ESM_APU_FREE) { 1504 chip->apu[apu] = chip->apu[apu + 1] = type; 1505 return apu; 1506 } 1507 } 1508 return -EBUSY; 1509} 1510 1511/* 1512 * release APU pair 1513 */ 1514static void snd_es1968_free_apu_pair(struct es1968 *chip, int apu) 1515{ 1516 chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE; 1517} 1518 1519 1520/****************** 1521 * PCM open/close * 1522 ******************/ 1523 1524static int snd_es1968_playback_open(struct snd_pcm_substream *substream) 1525{ 1526 struct es1968 *chip = snd_pcm_substream_chip(substream); 1527 struct snd_pcm_runtime *runtime = substream->runtime; 1528 struct esschan *es; 1529 int apu1; 1530 1531 /* search 2 APUs */ 1532 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY); 1533 if (apu1 < 0) 1534 return apu1; 1535 1536 es = kzalloc(sizeof(*es), GFP_KERNEL); 1537 if (!es) { 1538 snd_es1968_free_apu_pair(chip, apu1); 1539 return -ENOMEM; 1540 } 1541 1542 es->apu[0] = apu1; 1543 es->apu[1] = apu1 + 1; 1544 es->apu_mode[0] = 0; 1545 es->apu_mode[1] = 0; 1546 es->running = 0; 1547 es->substream = substream; 1548 es->mode = ESM_MODE_PLAY; 1549 1550 runtime->private_data = es; 1551 runtime->hw = snd_es1968_playback; 1552 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max = 1553 calc_available_memory_size(chip); 1554 1555 spin_lock_irq(&chip->substream_lock); 1556 list_add(&es->list, &chip->substream_list); 1557 spin_unlock_irq(&chip->substream_lock); 1558 1559 return 0; 1560} 1561 1562static int snd_es1968_capture_open(struct snd_pcm_substream *substream) 1563{ 1564 struct snd_pcm_runtime *runtime = substream->runtime; 1565 struct es1968 *chip = snd_pcm_substream_chip(substream); 1566 struct esschan *es; 1567 int apu1, apu2; 1568 1569 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE); 1570 if (apu1 < 0) 1571 return apu1; 1572 apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV); 1573 if (apu2 < 0) { 1574 snd_es1968_free_apu_pair(chip, apu1); 1575 return apu2; 1576 } 1577 1578 es = kzalloc(sizeof(*es), GFP_KERNEL); 1579 if (!es) { 1580 snd_es1968_free_apu_pair(chip, apu1); 1581 snd_es1968_free_apu_pair(chip, apu2); 1582 return -ENOMEM; 1583 } 1584 1585 es->apu[0] = apu1; 1586 es->apu[1] = apu1 + 1; 1587 es->apu[2] = apu2; 1588 es->apu[3] = apu2 + 1; 1589 es->apu_mode[0] = 0; 1590 es->apu_mode[1] = 0; 1591 es->apu_mode[2] = 0; 1592 es->apu_mode[3] = 0; 1593 es->running = 0; 1594 es->substream = substream; 1595 es->mode = ESM_MODE_CAPTURE; 1596 1597 /* get mixbuffer */ 1598 if ((es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE)) == NULL) { 1599 snd_es1968_free_apu_pair(chip, apu1); 1600 snd_es1968_free_apu_pair(chip, apu2); 1601 kfree(es); 1602 return -ENOMEM; 1603 } 1604 memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE); 1605 1606 runtime->private_data = es; 1607 runtime->hw = snd_es1968_capture; 1608 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max = 1609 calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */ 1610 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES); 1611 1612 spin_lock_irq(&chip->substream_lock); 1613 list_add(&es->list, &chip->substream_list); 1614 spin_unlock_irq(&chip->substream_lock); 1615 1616 return 0; 1617} 1618 1619static int snd_es1968_playback_close(struct snd_pcm_substream *substream) 1620{ 1621 struct es1968 *chip = snd_pcm_substream_chip(substream); 1622 struct esschan *es; 1623 1624 if (substream->runtime->private_data == NULL) 1625 return 0; 1626 es = substream->runtime->private_data; 1627 spin_lock_irq(&chip->substream_lock); 1628 list_del(&es->list); 1629 spin_unlock_irq(&chip->substream_lock); 1630 snd_es1968_free_apu_pair(chip, es->apu[0]); 1631 kfree(es); 1632 1633 return 0; 1634} 1635 1636static int snd_es1968_capture_close(struct snd_pcm_substream *substream) 1637{ 1638 struct es1968 *chip = snd_pcm_substream_chip(substream); 1639 struct esschan *es; 1640 1641 if (substream->runtime->private_data == NULL) 1642 return 0; 1643 es = substream->runtime->private_data; 1644 spin_lock_irq(&chip->substream_lock); 1645 list_del(&es->list); 1646 spin_unlock_irq(&chip->substream_lock); 1647 snd_es1968_free_memory(chip, es->mixbuf); 1648 snd_es1968_free_apu_pair(chip, es->apu[0]); 1649 snd_es1968_free_apu_pair(chip, es->apu[2]); 1650 kfree(es); 1651 1652 return 0; 1653} 1654 1655static struct snd_pcm_ops snd_es1968_playback_ops = { 1656 .open = snd_es1968_playback_open, 1657 .close = snd_es1968_playback_close, 1658 .ioctl = snd_pcm_lib_ioctl, 1659 .hw_params = snd_es1968_hw_params, 1660 .hw_free = snd_es1968_hw_free, 1661 .prepare = snd_es1968_pcm_prepare, 1662 .trigger = snd_es1968_pcm_trigger, 1663 .pointer = snd_es1968_pcm_pointer, 1664}; 1665 1666static struct snd_pcm_ops snd_es1968_capture_ops = { 1667 .open = snd_es1968_capture_open, 1668 .close = snd_es1968_capture_close, 1669 .ioctl = snd_pcm_lib_ioctl, 1670 .hw_params = snd_es1968_hw_params, 1671 .hw_free = snd_es1968_hw_free, 1672 .prepare = snd_es1968_pcm_prepare, 1673 .trigger = snd_es1968_pcm_trigger, 1674 .pointer = snd_es1968_pcm_pointer, 1675}; 1676 1677 1678/* 1679 * measure clock 1680 */ 1681#define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */ 1682 1683static void __devinit es1968_measure_clock(struct es1968 *chip) 1684{ 1685 int i, apu; 1686 unsigned int pa, offset, t; 1687 struct esm_memory *memory; 1688 struct timeval start_time, stop_time; 1689 1690 if (chip->clock == 0) 1691 chip->clock = 48000; /* default clock value */ 1692 1693 /* search 2 APUs (although one apu is enough) */ 1694 if ((apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY)) < 0) { 1695 snd_printk(KERN_ERR "Hmm, cannot find empty APU pair!?\n"); 1696 return; 1697 } 1698 if ((memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE)) == NULL) { 1699 snd_printk(KERN_ERR "cannot allocate dma buffer - using default clock %d\n", chip->clock); 1700 snd_es1968_free_apu_pair(chip, apu); 1701 return; 1702 } 1703 1704 memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE); 1705 1706 wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8); 1707 1708 pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1); 1709 pa |= 0x00400000; /* System RAM (Bit 22) */ 1710 1711 /* initialize apu */ 1712 for (i = 0; i < 16; i++) 1713 apu_set_register(chip, apu, i, 0x0000); 1714 1715 apu_set_register(chip, apu, 0, 0x400f); 1716 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8); 1717 apu_set_register(chip, apu, 5, pa & 0xffff); 1718 apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff); 1719 apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2); 1720 apu_set_register(chip, apu, 8, 0x0000); 1721 apu_set_register(chip, apu, 9, 0xD000); 1722 apu_set_register(chip, apu, 10, 0x8F08); 1723 apu_set_register(chip, apu, 11, 0x0000); 1724 spin_lock_irq(&chip->reg_lock); 1725 outw(1, chip->io_port + 0x04); /* clear WP interrupts */ 1726 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */ 1727 spin_unlock_irq(&chip->reg_lock); 1728 1729 snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */ 1730 1731 chip->in_measurement = 1; 1732 chip->measure_apu = apu; 1733 spin_lock_irq(&chip->reg_lock); 1734 snd_es1968_bob_inc(chip, ESM_BOB_FREQ); 1735 __apu_set_register(chip, apu, 5, pa & 0xffff); 1736 snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR); 1737 do_gettimeofday(&start_time); 1738 spin_unlock_irq(&chip->reg_lock); 1739 msleep(50); 1740 spin_lock_irq(&chip->reg_lock); 1741 offset = __apu_get_register(chip, apu, 5); 1742 do_gettimeofday(&stop_time); 1743 snd_es1968_trigger_apu(chip, apu, 0); /* stop */ 1744 snd_es1968_bob_dec(chip); 1745 chip->in_measurement = 0; 1746 spin_unlock_irq(&chip->reg_lock); 1747 1748 /* check the current position */ 1749 offset -= (pa & 0xffff); 1750 offset &= 0xfffe; 1751 offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2); 1752 1753 t = stop_time.tv_sec - start_time.tv_sec; 1754 t *= 1000000; 1755 if (stop_time.tv_usec < start_time.tv_usec) 1756 t -= start_time.tv_usec - stop_time.tv_usec; 1757 else 1758 t += stop_time.tv_usec - start_time.tv_usec; 1759 if (t == 0) { 1760 snd_printk(KERN_ERR "?? calculation error..\n"); 1761 } else { 1762 offset *= 1000; 1763 offset = (offset / t) * 1000 + ((offset % t) * 1000) / t; 1764 if (offset < 47500 || offset > 48500) { 1765 if (offset >= 40000 && offset <= 50000) 1766 chip->clock = (chip->clock * offset) / 48000; 1767 } 1768 printk(KERN_INFO "es1968: clocking to %d\n", chip->clock); 1769 } 1770 snd_es1968_free_memory(chip, memory); 1771 snd_es1968_free_apu_pair(chip, apu); 1772} 1773 1774 1775/* 1776 */ 1777 1778static void snd_es1968_pcm_free(struct snd_pcm *pcm) 1779{ 1780 struct es1968 *esm = pcm->private_data; 1781 snd_es1968_free_dmabuf(esm); 1782 esm->pcm = NULL; 1783} 1784 1785static int __devinit 1786snd_es1968_pcm(struct es1968 *chip, int device) 1787{ 1788 struct snd_pcm *pcm; 1789 int err; 1790 1791 /* get DMA buffer */ 1792 if ((err = snd_es1968_init_dmabuf(chip)) < 0) 1793 return err; 1794 1795 /* set PCMBAR */ 1796 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12); 1797 wave_set_register(chip, 0x01FD, chip->dma.addr >> 12); 1798 wave_set_register(chip, 0x01FE, chip->dma.addr >> 12); 1799 wave_set_register(chip, 0x01FF, chip->dma.addr >> 12); 1800 1801 if ((err = snd_pcm_new(chip->card, "ESS Maestro", device, 1802 chip->playback_streams, 1803 chip->capture_streams, &pcm)) < 0) 1804 return err; 1805 1806 pcm->private_data = chip; 1807 pcm->private_free = snd_es1968_pcm_free; 1808 1809 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops); 1810 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops); 1811 1812 pcm->info_flags = 0; 1813 1814 strcpy(pcm->name, "ESS Maestro"); 1815 1816 chip->pcm = pcm; 1817 1818 return 0; 1819} 1820/* 1821 * suppress jitter on some maestros when playing stereo 1822 */ 1823static void snd_es1968_suppress_jitter(struct es1968 *chip, struct esschan *es) 1824{ 1825 unsigned int cp1; 1826 unsigned int cp2; 1827 unsigned int diff; 1828 1829 cp1 = __apu_get_register(chip, 0, 5); 1830 cp2 = __apu_get_register(chip, 1, 5); 1831 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1); 1832 1833 if (diff > 1) 1834 __maestro_write(chip, IDR0_DATA_PORT, cp1); 1835} 1836 1837/* 1838 * update pointer 1839 */ 1840static void snd_es1968_update_pcm(struct es1968 *chip, struct esschan *es) 1841{ 1842 unsigned int hwptr; 1843 unsigned int diff; 1844 struct snd_pcm_substream *subs = es->substream; 1845 1846 if (subs == NULL || !es->running) 1847 return; 1848 1849 hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift; 1850 hwptr %= es->dma_size; 1851 1852 diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size; 1853 1854 es->hwptr = hwptr; 1855 es->count += diff; 1856 1857 if (es->count > es->frag_size) { 1858 spin_unlock(&chip->substream_lock); 1859 snd_pcm_period_elapsed(subs); 1860 spin_lock(&chip->substream_lock); 1861 es->count %= es->frag_size; 1862 } 1863} 1864 1865/* The hardware volume works by incrementing / decrementing 2 counters 1866 (without wrap around) in response to volume button presses and then 1867 generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7 1868 of a byte wide register. The meaning of bits 0 and 4 is unknown. */ 1869static void es1968_update_hw_volume(unsigned long private_data) 1870{ 1871 struct es1968 *chip = (struct es1968 *) private_data; 1872 int x, val; 1873#ifndef CONFIG_SND_ES1968_INPUT 1874 unsigned long flags; 1875#endif 1876 1877 /* Figure out which volume control button was pushed, 1878 based on differences from the default register 1879 values. */ 1880 x = inb(chip->io_port + 0x1c) & 0xee; 1881 /* Reset the volume control registers. */ 1882 outb(0x88, chip->io_port + 0x1c); 1883 outb(0x88, chip->io_port + 0x1d); 1884 outb(0x88, chip->io_port + 0x1e); 1885 outb(0x88, chip->io_port + 0x1f); 1886 1887 if (chip->in_suspend) 1888 return; 1889 1890#ifndef CONFIG_SND_ES1968_INPUT 1891 if (! chip->master_switch || ! chip->master_volume) 1892 return; 1893 1894 spin_lock_irqsave(&chip->ac97_lock, flags); 1895 val = chip->ac97->regs[AC97_MASTER]; 1896 switch (x) { 1897 case 0x88: 1898 /* mute */ 1899 val ^= 0x8000; 1900 chip->ac97->regs[AC97_MASTER] = val; 1901 outw(val, chip->io_port + ESM_AC97_DATA); 1902 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX); 1903 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1904 &chip->master_switch->id); 1905 break; 1906 case 0xaa: 1907 /* volume up */ 1908 if ((val & 0x7f) > 0) 1909 val--; 1910 if ((val & 0x7f00) > 0) 1911 val -= 0x0100; 1912 chip->ac97->regs[AC97_MASTER] = val; 1913 outw(val, chip->io_port + ESM_AC97_DATA); 1914 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX); 1915 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1916 &chip->master_volume->id); 1917 break; 1918 case 0x66: 1919 /* volume down */ 1920 if ((val & 0x7f) < 0x1f) 1921 val++; 1922 if ((val & 0x7f00) < 0x1f00) 1923 val += 0x0100; 1924 chip->ac97->regs[AC97_MASTER] = val; 1925 outw(val, chip->io_port + ESM_AC97_DATA); 1926 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX); 1927 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1928 &chip->master_volume->id); 1929 break; 1930 } 1931 spin_unlock_irqrestore(&chip->ac97_lock, flags); 1932#else 1933 if (!chip->input_dev) 1934 return; 1935 1936 val = 0; 1937 switch (x) { 1938 case 0x88: 1939 /* The counters have not changed, yet we've received a HV 1940 interrupt. According to tests run by various people this 1941 happens when pressing the mute button. */ 1942 val = KEY_MUTE; 1943 break; 1944 case 0xaa: 1945 /* counters increased by 1 -> volume up */ 1946 val = KEY_VOLUMEUP; 1947 break; 1948 case 0x66: 1949 /* counters decreased by 1 -> volume down */ 1950 val = KEY_VOLUMEDOWN; 1951 break; 1952 } 1953 1954 if (val) { 1955 input_report_key(chip->input_dev, val, 1); 1956 input_sync(chip->input_dev); 1957 input_report_key(chip->input_dev, val, 0); 1958 input_sync(chip->input_dev); 1959 } 1960#endif 1961} 1962 1963/* 1964 * interrupt handler 1965 */ 1966static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id) 1967{ 1968 struct es1968 *chip = dev_id; 1969 u32 event; 1970 1971 if (!(event = inb(chip->io_port + 0x1A))) 1972 return IRQ_NONE; 1973 1974 outw(inw(chip->io_port + 4) & 1, chip->io_port + 4); 1975 1976 if (event & ESM_HWVOL_IRQ) 1977#ifdef CONFIG_SND_ES1968_INPUT 1978 es1968_update_hw_volume((unsigned long)chip); 1979#else 1980 tasklet_schedule(&chip->hwvol_tq); /* we'll do this later */ 1981#endif 1982 1983 /* else ack 'em all, i imagine */ 1984 outb(0xFF, chip->io_port + 0x1A); 1985 1986 if ((event & ESM_MPU401_IRQ) && chip->rmidi) { 1987 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data); 1988 } 1989 1990 if (event & ESM_SOUND_IRQ) { 1991 struct esschan *es; 1992 spin_lock(&chip->substream_lock); 1993 list_for_each_entry(es, &chip->substream_list, list) { 1994 if (es->running) { 1995 snd_es1968_update_pcm(chip, es); 1996 if (es->fmt & ESS_FMT_STEREO) 1997 snd_es1968_suppress_jitter(chip, es); 1998 } 1999 } 2000 spin_unlock(&chip->substream_lock); 2001 if (chip->in_measurement) { 2002 unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5); 2003 if (curp < chip->measure_lastpos) 2004 chip->measure_count++; 2005 chip->measure_lastpos = curp; 2006 } 2007 } 2008 2009 return IRQ_HANDLED; 2010} 2011 2012/* 2013 * Mixer stuff 2014 */ 2015 2016static int __devinit 2017snd_es1968_mixer(struct es1968 *chip) 2018{ 2019 struct snd_ac97_bus *pbus; 2020 struct snd_ac97_template ac97; 2021#ifndef CONFIG_SND_ES1968_INPUT 2022 struct snd_ctl_elem_id elem_id; 2023#endif 2024 int err; 2025 static struct snd_ac97_bus_ops ops = { 2026 .write = snd_es1968_ac97_write, 2027 .read = snd_es1968_ac97_read, 2028 }; 2029 2030 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0) 2031 return err; 2032 pbus->no_vra = 1; /* ES1968 doesn't need VRA */ 2033 2034 memset(&ac97, 0, sizeof(ac97)); 2035 ac97.private_data = chip; 2036 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0) 2037 return err; 2038 2039#ifndef CONFIG_SND_ES1968_INPUT 2040 /* attach master switch / volumes for h/w volume control */ 2041 memset(&elem_id, 0, sizeof(elem_id)); 2042 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2043 strcpy(elem_id.name, "Master Playback Switch"); 2044 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id); 2045 memset(&elem_id, 0, sizeof(elem_id)); 2046 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2047 strcpy(elem_id.name, "Master Playback Volume"); 2048 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id); 2049#endif 2050 2051 return 0; 2052} 2053 2054/* 2055 * reset ac97 codec 2056 */ 2057 2058static void snd_es1968_ac97_reset(struct es1968 *chip) 2059{ 2060 unsigned long ioaddr = chip->io_port; 2061 2062 unsigned short save_ringbus_a; 2063 unsigned short save_68; 2064 unsigned short w; 2065 unsigned int vend; 2066 2067 /* save configuration */ 2068 save_ringbus_a = inw(ioaddr + 0x36); 2069 2070 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */ 2071 /* set command/status address i/o to 1st codec */ 2072 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a); 2073 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c); 2074 2075 /* disable ac link */ 2076 outw(0x0000, ioaddr + 0x36); 2077 save_68 = inw(ioaddr + 0x68); 2078 pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */ 2079 pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend); 2080 if (w & 1) 2081 save_68 |= 0x10; 2082 outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */ 2083 outw(0x0001, ioaddr + 0x68); /* gpio write */ 2084 outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */ 2085 udelay(20); 2086 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */ 2087 msleep(20); 2088 2089 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */ 2090 outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38); 2091 outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a); 2092 outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c); 2093 2094 /* now the second codec */ 2095 /* disable ac link */ 2096 outw(0x0000, ioaddr + 0x36); 2097 outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */ 2098 save_68 = inw(ioaddr + 0x68); 2099 outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */ 2100 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */ 2101 udelay(20); 2102 outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */ 2103 msleep(500); 2104 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); 2105 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a); 2106 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c); 2107 2108 if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) { 2109 /* turn on external amp? */ 2110 outw(0xf9ff, ioaddr + 0x64); 2111 outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68); 2112 outw(0x0209, ioaddr + 0x60); 2113 } 2114 2115 /* restore.. */ 2116 outw(save_ringbus_a, ioaddr + 0x36); 2117 2118 /* Turn on the 978 docking chip. 2119 First frob the "master output enable" bit, 2120 then set most of the playback volume control registers to max. */ 2121 outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0); 2122 outb(0xff, ioaddr+0xc3); 2123 outb(0xff, ioaddr+0xc4); 2124 outb(0xff, ioaddr+0xc6); 2125 outb(0xff, ioaddr+0xc8); 2126 outb(0x3f, ioaddr+0xcf); 2127 outb(0x3f, ioaddr+0xd0); 2128} 2129 2130static void snd_es1968_reset(struct es1968 *chip) 2131{ 2132 /* Reset */ 2133 outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND, 2134 chip->io_port + ESM_PORT_HOST_IRQ); 2135 udelay(10); 2136 outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ); 2137 udelay(10); 2138} 2139 2140/* 2141 * initialize maestro chip 2142 */ 2143static void snd_es1968_chip_init(struct es1968 *chip) 2144{ 2145 struct pci_dev *pci = chip->pci; 2146 int i; 2147 unsigned long iobase = chip->io_port; 2148 u16 w; 2149 u32 n; 2150 2151 /* We used to muck around with pci config space that 2152 * we had no business messing with. We don't know enough 2153 * about the machine to know which DMA mode is appropriate, 2154 * etc. We were guessing wrong on some machines and making 2155 * them unhappy. We now trust in the BIOS to do things right, 2156 * which almost certainly means a new host of problems will 2157 * arise with broken BIOS implementations. screw 'em. 2158 * We're already intolerant of machines that don't assign 2159 * IRQs. 2160 */ 2161 2162 /* Config Reg A */ 2163 pci_read_config_word(pci, ESM_CONFIG_A, &w); 2164 2165 w &= ~DMA_CLEAR; /* Clear DMA bits */ 2166 w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */ 2167 w &= ~SAFEGUARD; /* Safeguard off */ 2168 w |= POST_WRITE; /* Posted write */ 2169 w |= PCI_TIMING; /* PCI timing on */ 2170 w &= ~SWAP_LR; /* swap left/right 2171 seems to only have effect on SB 2172 Emulation */ 2173 w &= ~SUBTR_DECODE; /* Subtractive decode off */ 2174 2175 pci_write_config_word(pci, ESM_CONFIG_A, w); 2176 2177 /* Config Reg B */ 2178 2179 pci_read_config_word(pci, ESM_CONFIG_B, &w); 2180 2181 w &= ~(1 << 15); /* Turn off internal clock multiplier */ 2182 w &= ~(1 << 14); /* External clock */ 2183 2184 w &= ~SPDIF_CONFB; /* disable S/PDIF output */ 2185 w |= HWV_CONFB; /* HWV on */ 2186 w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */ 2187 w &= ~GPIO_CONFB; /* GPIO 4:5 */ 2188 w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */ 2189 w &= ~IDMA_CONFB; /* IDMA off (undocumented) */ 2190 w &= ~MIDI_FIX; /* MIDI fix off (undoc) */ 2191 w &= ~(1 << 1); /* reserved, always write 0 */ 2192 w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */ 2193 2194 pci_write_config_word(pci, ESM_CONFIG_B, w); 2195 2196 /* DDMA off */ 2197 2198 pci_read_config_word(pci, ESM_DDMA, &w); 2199 w &= ~(1 << 0); 2200 pci_write_config_word(pci, ESM_DDMA, w); 2201 2202 /* 2203 * Legacy mode 2204 */ 2205 2206 pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w); 2207 2208 w |= ESS_DISABLE_AUDIO; /* Disable Legacy Audio */ 2209 w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */ 2210 w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */ 2211 2212 pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w); 2213 2214 /* Set up 978 docking control chip. */ 2215 pci_read_config_word(pci, 0x58, &w); 2216 w|=1<<2; /* Enable 978. */ 2217 w|=1<<3; /* Turn on 978 hardware volume control. */ 2218 w&=~(1<<11); /* Turn on 978 mixer volume control. */ 2219 pci_write_config_word(pci, 0x58, w); 2220 2221 /* Sound Reset */ 2222 2223 snd_es1968_reset(chip); 2224 2225 /* 2226 * Ring Bus Setup 2227 */ 2228 2229 /* setup usual 0x34 stuff.. 0x36 may be chip specific */ 2230 outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */ 2231 udelay(20); 2232 outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */ 2233 udelay(20); 2234 2235 /* 2236 * Reset the CODEC 2237 */ 2238 2239 snd_es1968_ac97_reset(chip); 2240 2241 /* Ring Bus Control B */ 2242 2243 n = inl(iobase + ESM_RING_BUS_CONTR_B); 2244 n &= ~RINGB_EN_SPDIF; /* SPDIF off */ 2245 //w |= RINGB_EN_2CODEC; /* enable 2nd codec */ 2246 outl(n, iobase + ESM_RING_BUS_CONTR_B); 2247 2248 /* Set hardware volume control registers to midpoints. 2249 We can tell which button was pushed based on how they change. */ 2250 outb(0x88, iobase+0x1c); 2251 outb(0x88, iobase+0x1d); 2252 outb(0x88, iobase+0x1e); 2253 outb(0x88, iobase+0x1f); 2254 2255 /* it appears some maestros (dell 7500) only work if these are set, 2256 regardless of wether we use the assp or not. */ 2257 2258 outb(0, iobase + ASSP_CONTROL_B); 2259 outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */ 2260 outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */ 2261 2262 /* 2263 * set up wavecache 2264 */ 2265 for (i = 0; i < 16; i++) { 2266 /* Write 0 into the buffer area 0x1E0->1EF */ 2267 outw(0x01E0 + i, iobase + WC_INDEX); 2268 outw(0x0000, iobase + WC_DATA); 2269 2270 /* The 1.10 test program seem to write 0 into the buffer area 2271 * 0x1D0-0x1DF too.*/ 2272 outw(0x01D0 + i, iobase + WC_INDEX); 2273 outw(0x0000, iobase + WC_DATA); 2274 } 2275 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2276 (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00)); 2277 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2278 wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100); 2279 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2280 wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200); 2281 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2282 wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400); 2283 2284 2285 maestro_write(chip, IDR2_CRAM_DATA, 0x0000); 2286 /* Now back to the DirectSound stuff */ 2287 /* audio serial configuration.. ? */ 2288 maestro_write(chip, 0x08, 0xB004); 2289 maestro_write(chip, 0x09, 0x001B); 2290 maestro_write(chip, 0x0A, 0x8000); 2291 maestro_write(chip, 0x0B, 0x3F37); 2292 maestro_write(chip, 0x0C, 0x0098); 2293 2294 /* parallel in, has something to do with recording :) */ 2295 maestro_write(chip, 0x0C, 2296 (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000); 2297 /* parallel out */ 2298 maestro_write(chip, 0x0C, 2299 (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500); 2300 2301 maestro_write(chip, 0x0D, 0x7632); 2302 2303 /* Wave cache control on - test off, sg off, 2304 enable, enable extra chans 1Mb */ 2305 2306 w = inw(iobase + WC_CONTROL); 2307 2308 w &= ~0xFA00; /* Seems to be reserved? I don't know */ 2309 w |= 0xA000; /* reserved... I don't know */ 2310 w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable 2311 Seems to crash the Computer if enabled... */ 2312 w |= 0x0100; /* Wave Cache Operation Enabled */ 2313 w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */ 2314 w &= ~0x0060; /* Clear Wavtable Size */ 2315 w |= 0x0020; /* Wavetable Size : 1MB */ 2316 /* Bit 4 is reserved */ 2317 w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */ 2318 /* Bit 1 is reserved */ 2319 w &= ~0x0001; /* Test Mode off */ 2320 2321 outw(w, iobase + WC_CONTROL); 2322 2323 /* Now clear the APU control ram */ 2324 for (i = 0; i < NR_APUS; i++) { 2325 for (w = 0; w < NR_APU_REGS; w++) 2326 apu_set_register(chip, i, w, 0); 2327 2328 } 2329} 2330 2331/* Enable IRQ's */ 2332static void snd_es1968_start_irq(struct es1968 *chip) 2333{ 2334 unsigned short w; 2335 w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME; 2336 if (chip->rmidi) 2337 w |= ESM_HIRQ_MPU401; 2338 outb(w, chip->io_port + 0x1A); 2339 outw(w, chip->io_port + ESM_PORT_HOST_IRQ); 2340} 2341 2342#ifdef CONFIG_PM 2343/* 2344 * PM support 2345 */ 2346static int es1968_suspend(struct pci_dev *pci, pm_message_t state) 2347{ 2348 struct snd_card *card = pci_get_drvdata(pci); 2349 struct es1968 *chip = card->private_data; 2350 2351 if (! chip->do_pm) 2352 return 0; 2353 2354 chip->in_suspend = 1; 2355 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2356 snd_pcm_suspend_all(chip->pcm); 2357 snd_ac97_suspend(chip->ac97); 2358 snd_es1968_bob_stop(chip); 2359 2360 pci_disable_device(pci); 2361 pci_save_state(pci); 2362 pci_set_power_state(pci, pci_choose_state(pci, state)); 2363 return 0; 2364} 2365 2366static int es1968_resume(struct pci_dev *pci) 2367{ 2368 struct snd_card *card = pci_get_drvdata(pci); 2369 struct es1968 *chip = card->private_data; 2370 struct esschan *es; 2371 2372 if (! chip->do_pm) 2373 return 0; 2374 2375 /* restore all our config */ 2376 pci_set_power_state(pci, PCI_D0); 2377 pci_restore_state(pci); 2378 if (pci_enable_device(pci) < 0) { 2379 printk(KERN_ERR "es1968: pci_enable_device failed, " 2380 "disabling device\n"); 2381 snd_card_disconnect(card); 2382 return -EIO; 2383 } 2384 pci_set_master(pci); 2385 2386 snd_es1968_chip_init(chip); 2387 2388 /* need to restore the base pointers.. */ 2389 if (chip->dma.addr) { 2390 /* set PCMBAR */ 2391 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12); 2392 } 2393 2394 snd_es1968_start_irq(chip); 2395 2396 /* restore ac97 state */ 2397 snd_ac97_resume(chip->ac97); 2398 2399 list_for_each_entry(es, &chip->substream_list, list) { 2400 switch (es->mode) { 2401 case ESM_MODE_PLAY: 2402 snd_es1968_playback_setup(chip, es, es->substream->runtime); 2403 break; 2404 case ESM_MODE_CAPTURE: 2405 snd_es1968_capture_setup(chip, es, es->substream->runtime); 2406 break; 2407 } 2408 } 2409 2410 /* start timer again */ 2411 if (chip->bobclient) 2412 snd_es1968_bob_start(chip); 2413 2414 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2415 chip->in_suspend = 0; 2416 return 0; 2417} 2418#endif /* CONFIG_PM */ 2419 2420#ifdef SUPPORT_JOYSTICK 2421#define JOYSTICK_ADDR 0x200 2422static int __devinit snd_es1968_create_gameport(struct es1968 *chip, int dev) 2423{ 2424 struct gameport *gp; 2425 struct resource *r; 2426 u16 val; 2427 2428 if (!joystick[dev]) 2429 return -ENODEV; 2430 2431 r = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport"); 2432 if (!r) 2433 return -EBUSY; 2434 2435 chip->gameport = gp = gameport_allocate_port(); 2436 if (!gp) { 2437 printk(KERN_ERR "es1968: cannot allocate memory for gameport\n"); 2438 release_and_free_resource(r); 2439 return -ENOMEM; 2440 } 2441 2442 pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val); 2443 pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04); 2444 2445 gameport_set_name(gp, "ES1968 Gameport"); 2446 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 2447 gameport_set_dev_parent(gp, &chip->pci->dev); 2448 gp->io = JOYSTICK_ADDR; 2449 gameport_set_port_data(gp, r); 2450 2451 gameport_register_port(gp); 2452 2453 return 0; 2454} 2455 2456static void snd_es1968_free_gameport(struct es1968 *chip) 2457{ 2458 if (chip->gameport) { 2459 struct resource *r = gameport_get_port_data(chip->gameport); 2460 2461 gameport_unregister_port(chip->gameport); 2462 chip->gameport = NULL; 2463 2464 release_and_free_resource(r); 2465 } 2466} 2467#else 2468static inline int snd_es1968_create_gameport(struct es1968 *chip, int dev) { return -ENOSYS; } 2469static inline void snd_es1968_free_gameport(struct es1968 *chip) { } 2470#endif 2471 2472#ifdef CONFIG_SND_ES1968_INPUT 2473static int __devinit snd_es1968_input_register(struct es1968 *chip) 2474{ 2475 struct input_dev *input_dev; 2476 int err; 2477 2478 input_dev = input_allocate_device(); 2479 if (!input_dev) 2480 return -ENOMEM; 2481 2482 snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0", 2483 pci_name(chip->pci)); 2484 2485 input_dev->name = chip->card->driver; 2486 input_dev->phys = chip->phys; 2487 input_dev->id.bustype = BUS_PCI; 2488 input_dev->id.vendor = chip->pci->vendor; 2489 input_dev->id.product = chip->pci->device; 2490 input_dev->dev.parent = &chip->pci->dev; 2491 2492 __set_bit(EV_KEY, input_dev->evbit); 2493 __set_bit(KEY_MUTE, input_dev->keybit); 2494 __set_bit(KEY_VOLUMEDOWN, input_dev->keybit); 2495 __set_bit(KEY_VOLUMEUP, input_dev->keybit); 2496 2497 err = input_register_device(input_dev); 2498 if (err) { 2499 input_free_device(input_dev); 2500 return err; 2501 } 2502 2503 chip->input_dev = input_dev; 2504 return 0; 2505} 2506#endif /* CONFIG_SND_ES1968_INPUT */ 2507 2508static int snd_es1968_free(struct es1968 *chip) 2509{ 2510#ifdef CONFIG_SND_ES1968_INPUT 2511 if (chip->input_dev) 2512 input_unregister_device(chip->input_dev); 2513#endif 2514 2515 if (chip->io_port) { 2516 if (chip->irq >= 0) 2517 synchronize_irq(chip->irq); 2518 outw(1, chip->io_port + 0x04); /* clear WP interrupts */ 2519 outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */ 2520 } 2521 2522 if (chip->irq >= 0) 2523 free_irq(chip->irq, chip); 2524 snd_es1968_free_gameport(chip); 2525 pci_release_regions(chip->pci); 2526 pci_disable_device(chip->pci); 2527 kfree(chip); 2528 return 0; 2529} 2530 2531static int snd_es1968_dev_free(struct snd_device *device) 2532{ 2533 struct es1968 *chip = device->device_data; 2534 return snd_es1968_free(chip); 2535} 2536 2537struct ess_device_list { 2538 unsigned short type; /* chip type */ 2539 unsigned short vendor; /* subsystem vendor id */ 2540}; 2541 2542static struct ess_device_list pm_whitelist[] __devinitdata = { 2543 { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */ 2544 { TYPE_MAESTRO2E, 0x1028 }, 2545 { TYPE_MAESTRO2E, 0x103c }, 2546 { TYPE_MAESTRO2E, 0x1179 }, 2547 { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */ 2548 { TYPE_MAESTRO2E, 0x1558 }, 2549}; 2550 2551static struct ess_device_list mpu_blacklist[] __devinitdata = { 2552 { TYPE_MAESTRO2, 0x125d }, 2553}; 2554 2555static int __devinit snd_es1968_create(struct snd_card *card, 2556 struct pci_dev *pci, 2557 int total_bufsize, 2558 int play_streams, 2559 int capt_streams, 2560 int chip_type, 2561 int do_pm, 2562 struct es1968 **chip_ret) 2563{ 2564 static struct snd_device_ops ops = { 2565 .dev_free = snd_es1968_dev_free, 2566 }; 2567 struct es1968 *chip; 2568 int i, err; 2569 2570 *chip_ret = NULL; 2571 2572 /* enable PCI device */ 2573 if ((err = pci_enable_device(pci)) < 0) 2574 return err; 2575 /* check, if we can restrict PCI DMA transfers to 28 bits */ 2576 if (pci_set_dma_mask(pci, DMA_BIT_MASK(28)) < 0 || 2577 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(28)) < 0) { 2578 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n"); 2579 pci_disable_device(pci); 2580 return -ENXIO; 2581 } 2582 2583 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 2584 if (! chip) { 2585 pci_disable_device(pci); 2586 return -ENOMEM; 2587 } 2588 2589 /* Set Vars */ 2590 chip->type = chip_type; 2591 spin_lock_init(&chip->reg_lock); 2592 spin_lock_init(&chip->substream_lock); 2593 INIT_LIST_HEAD(&chip->buf_list); 2594 INIT_LIST_HEAD(&chip->substream_list); 2595 mutex_init(&chip->memory_mutex); 2596#ifndef CONFIG_SND_ES1968_INPUT 2597 spin_lock_init(&chip->ac97_lock); 2598 tasklet_init(&chip->hwvol_tq, es1968_update_hw_volume, (unsigned long)chip); 2599#endif 2600 chip->card = card; 2601 chip->pci = pci; 2602 chip->irq = -1; 2603 chip->total_bufsize = total_bufsize; /* in bytes */ 2604 chip->playback_streams = play_streams; 2605 chip->capture_streams = capt_streams; 2606 2607 if ((err = pci_request_regions(pci, "ESS Maestro")) < 0) { 2608 kfree(chip); 2609 pci_disable_device(pci); 2610 return err; 2611 } 2612 chip->io_port = pci_resource_start(pci, 0); 2613 if (request_irq(pci->irq, snd_es1968_interrupt, IRQF_SHARED, 2614 "ESS Maestro", chip)) { 2615 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 2616 snd_es1968_free(chip); 2617 return -EBUSY; 2618 } 2619 chip->irq = pci->irq; 2620 2621 /* Clear Maestro_map */ 2622 for (i = 0; i < 32; i++) 2623 chip->maestro_map[i] = 0; 2624 2625 /* Clear Apu Map */ 2626 for (i = 0; i < NR_APUS; i++) 2627 chip->apu[i] = ESM_APU_FREE; 2628 2629 /* just to be sure */ 2630 pci_set_master(pci); 2631 2632 if (do_pm > 1) { 2633 /* disable power-management if not on the whitelist */ 2634 unsigned short vend; 2635 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend); 2636 for (i = 0; i < (int)ARRAY_SIZE(pm_whitelist); i++) { 2637 if (chip->type == pm_whitelist[i].type && 2638 vend == pm_whitelist[i].vendor) { 2639 do_pm = 1; 2640 break; 2641 } 2642 } 2643 if (do_pm > 1) { 2644 /* not matched; disabling pm */ 2645 printk(KERN_INFO "es1968: not attempting power management.\n"); 2646 do_pm = 0; 2647 } 2648 } 2649 chip->do_pm = do_pm; 2650 2651 snd_es1968_chip_init(chip); 2652 2653 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 2654 snd_es1968_free(chip); 2655 return err; 2656 } 2657 2658 snd_card_set_dev(card, &pci->dev); 2659 2660 *chip_ret = chip; 2661 2662 return 0; 2663} 2664 2665 2666/* 2667 */ 2668static int __devinit snd_es1968_probe(struct pci_dev *pci, 2669 const struct pci_device_id *pci_id) 2670{ 2671 static int dev; 2672 struct snd_card *card; 2673 struct es1968 *chip; 2674 unsigned int i; 2675 int err; 2676 2677 if (dev >= SNDRV_CARDS) 2678 return -ENODEV; 2679 if (!enable[dev]) { 2680 dev++; 2681 return -ENOENT; 2682 } 2683 2684 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card); 2685 if (err < 0) 2686 return err; 2687 2688 if (total_bufsize[dev] < 128) 2689 total_bufsize[dev] = 128; 2690 if (total_bufsize[dev] > 4096) 2691 total_bufsize[dev] = 4096; 2692 if ((err = snd_es1968_create(card, pci, 2693 total_bufsize[dev] * 1024, /* in bytes */ 2694 pcm_substreams_p[dev], 2695 pcm_substreams_c[dev], 2696 pci_id->driver_data, 2697 use_pm[dev], 2698 &chip)) < 0) { 2699 snd_card_free(card); 2700 return err; 2701 } 2702 card->private_data = chip; 2703 2704 switch (chip->type) { 2705 case TYPE_MAESTRO2E: 2706 strcpy(card->driver, "ES1978"); 2707 strcpy(card->shortname, "ESS ES1978 (Maestro 2E)"); 2708 break; 2709 case TYPE_MAESTRO2: 2710 strcpy(card->driver, "ES1968"); 2711 strcpy(card->shortname, "ESS ES1968 (Maestro 2)"); 2712 break; 2713 case TYPE_MAESTRO: 2714 strcpy(card->driver, "ESM1"); 2715 strcpy(card->shortname, "ESS Maestro 1"); 2716 break; 2717 } 2718 2719 if ((err = snd_es1968_pcm(chip, 0)) < 0) { 2720 snd_card_free(card); 2721 return err; 2722 } 2723 2724 if ((err = snd_es1968_mixer(chip)) < 0) { 2725 snd_card_free(card); 2726 return err; 2727 } 2728 2729 if (enable_mpu[dev] == 2) { 2730 /* check the black list */ 2731 unsigned short vend; 2732 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend); 2733 for (i = 0; i < ARRAY_SIZE(mpu_blacklist); i++) { 2734 if (chip->type == mpu_blacklist[i].type && 2735 vend == mpu_blacklist[i].vendor) { 2736 enable_mpu[dev] = 0; 2737 break; 2738 } 2739 } 2740 } 2741 if (enable_mpu[dev]) { 2742 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401, 2743 chip->io_port + ESM_MPU401_PORT, 2744 MPU401_INFO_INTEGRATED, 2745 chip->irq, 0, &chip->rmidi)) < 0) { 2746 printk(KERN_WARNING "es1968: skipping MPU-401 MIDI support..\n"); 2747 } 2748 } 2749 2750 snd_es1968_create_gameport(chip, dev); 2751 2752#ifdef CONFIG_SND_ES1968_INPUT 2753 err = snd_es1968_input_register(chip); 2754 if (err) 2755 snd_printk(KERN_WARNING "Input device registration " 2756 "failed with error %i", err); 2757#endif 2758 2759 snd_es1968_start_irq(chip); 2760 2761 chip->clock = clock[dev]; 2762 if (! chip->clock) 2763 es1968_measure_clock(chip); 2764 2765 sprintf(card->longname, "%s at 0x%lx, irq %i", 2766 card->shortname, chip->io_port, chip->irq); 2767 2768 if ((err = snd_card_register(card)) < 0) { 2769 snd_card_free(card); 2770 return err; 2771 } 2772 pci_set_drvdata(pci, card); 2773 dev++; 2774 return 0; 2775} 2776 2777static void __devexit snd_es1968_remove(struct pci_dev *pci) 2778{ 2779 snd_card_free(pci_get_drvdata(pci)); 2780 pci_set_drvdata(pci, NULL); 2781} 2782 2783static struct pci_driver driver = { 2784 .name = "ES1968 (ESS Maestro)", 2785 .id_table = snd_es1968_ids, 2786 .probe = snd_es1968_probe, 2787 .remove = __devexit_p(snd_es1968_remove), 2788#ifdef CONFIG_PM 2789 .suspend = es1968_suspend, 2790 .resume = es1968_resume, 2791#endif 2792}; 2793 2794static int __init alsa_card_es1968_init(void) 2795{ 2796 return pci_register_driver(&driver); 2797} 2798 2799static void __exit alsa_card_es1968_exit(void) 2800{ 2801 pci_unregister_driver(&driver); 2802} 2803 2804module_init(alsa_card_es1968_init) 2805module_exit(alsa_card_es1968_exit) 2806