1/* 2 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, 4 * Thomas Sailer <sailer@ife.ee.ethz.ch> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 */ 21 22 23#include <asm/io.h> 24#include <linux/delay.h> 25#include <linux/interrupt.h> 26#include <linux/init.h> 27#include <linux/pci.h> 28#include <linux/slab.h> 29#include <linux/gameport.h> 30#include <linux/moduleparam.h> 31#include <linux/mutex.h> 32 33#include <sound/core.h> 34#include <sound/control.h> 35#include <sound/pcm.h> 36#include <sound/rawmidi.h> 37#ifdef CHIP1371 38#include <sound/ac97_codec.h> 39#else 40#include <sound/ak4531_codec.h> 41#endif 42#include <sound/initval.h> 43#include <sound/asoundef.h> 44 45#ifndef CHIP1371 46#undef CHIP1370 47#define CHIP1370 48#endif 49 50#ifdef CHIP1370 51#define DRIVER_NAME "ENS1370" 52#else 53#define DRIVER_NAME "ENS1371" 54#endif 55 56 57MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>"); 58MODULE_LICENSE("GPL"); 59#ifdef CHIP1370 60MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370"); 61MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370}," 62 "{Creative Labs,SB PCI64/128 (ES1370)}}"); 63#endif 64#ifdef CHIP1371 65MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+"); 66MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73}," 67 "{Ensoniq,AudioPCI ES1373}," 68 "{Creative Labs,Ectiva EV1938}," 69 "{Creative Labs,SB PCI64/128 (ES1371/73)}," 70 "{Creative Labs,Vibra PCI128}," 71 "{Ectiva,EV1938}}"); 72#endif 73 74#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 75#define SUPPORT_JOYSTICK 76#endif 77 78static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 79static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 80static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ 81#ifdef SUPPORT_JOYSTICK 82#ifdef CHIP1371 83static int joystick_port[SNDRV_CARDS]; 84#else 85static int joystick[SNDRV_CARDS]; 86#endif 87#endif 88#ifdef CHIP1371 89static int spdif[SNDRV_CARDS]; 90static int lineio[SNDRV_CARDS]; 91#endif 92 93module_param_array(index, int, NULL, 0444); 94MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard."); 95module_param_array(id, charp, NULL, 0444); 96MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard."); 97module_param_array(enable, bool, NULL, 0444); 98MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard."); 99#ifdef SUPPORT_JOYSTICK 100#ifdef CHIP1371 101module_param_array(joystick_port, int, NULL, 0444); 102MODULE_PARM_DESC(joystick_port, "Joystick port address."); 103#else 104module_param_array(joystick, bool, NULL, 0444); 105MODULE_PARM_DESC(joystick, "Enable joystick."); 106#endif 107#endif /* SUPPORT_JOYSTICK */ 108#ifdef CHIP1371 109module_param_array(spdif, int, NULL, 0444); 110MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force)."); 111module_param_array(lineio, int, NULL, 0444); 112MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force)."); 113#endif 114 115/* ES1371 chip ID */ 116/* This is a little confusing because all ES1371 compatible chips have the 117 same DEVICE_ID, the only thing differentiating them is the REV_ID field. 118 This is only significant if you want to enable features on the later parts. 119 Yes, I know it's stupid and why didn't we use the sub IDs? 120*/ 121#define ES1371REV_ES1373_A 0x04 122#define ES1371REV_ES1373_B 0x06 123#define ES1371REV_CT5880_A 0x07 124#define CT5880REV_CT5880_C 0x02 125#define CT5880REV_CT5880_D 0x03 /* ??? -jk */ 126#define CT5880REV_CT5880_E 0x04 /* mw */ 127#define ES1371REV_ES1371_B 0x09 128#define EV1938REV_EV1938_A 0x00 129#define ES1371REV_ES1373_8 0x08 130 131/* 132 * Direct registers 133 */ 134 135#define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x) 136 137#define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */ 138#define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */ 139#define ES_1370_XCTL1 (1<<30) /* general purpose output bit */ 140#define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */ 141#define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */ 142#define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */ 143#define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */ 144#define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */ 145#define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */ 146#define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */ 147#define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */ 148#define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03) 149#define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */ 150#define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */ 151#define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */ 152#define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */ 153#define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */ 154#define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */ 155#define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */ 156#define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */ 157#define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */ 158#define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */ 159#define ES_1370_WTSRSELM (0x03<<12) /* mask for above */ 160#define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */ 161#define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */ 162#define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */ 163#define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */ 164#define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */ 165#define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */ 166#define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */ 167#define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */ 168#define ES_1371_PDLEVM (0x03<<8) /* mask for above */ 169#define ES_BREQ (1<<7) /* memory bus request enable */ 170#define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */ 171#define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */ 172#define ES_ADC_EN (1<<4) /* ADC capture channel enable */ 173#define ES_UART_EN (1<<3) /* UART enable */ 174#define ES_JYSTK_EN (1<<2) /* Joystick module enable */ 175#define ES_1370_CDC_EN (1<<1) /* Codec interface enable */ 176#define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */ 177#define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */ 178#define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */ 179#define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */ 180#define ES_INTR (1<<31) /* Interrupt is pending */ 181#define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */ 182#define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */ 183#define ES_1373_REAR_BIT26 (1<<26) 184#define ES_1373_REAR_BIT24 (1<<24) 185#define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */ 186#define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */ 187#define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */ 188#define ES_1371_TEST (1<<16) /* test ASIC */ 189#define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */ 190#define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */ 191#define ES_1370_CBUSY (1<<9) /* CODEC is busy */ 192#define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */ 193#define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */ 194#define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */ 195#define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */ 196#define ES_1371_MPWR (1<<5) /* power level interrupt pending */ 197#define ES_MCCB (1<<4) /* CCB interrupt pending */ 198#define ES_UART (1<<3) /* UART interrupt pending */ 199#define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */ 200#define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */ 201#define ES_ADC (1<<0) /* ADC channel interrupt pending */ 202#define ES_REG_UART_DATA 0x08 /* R/W: UART data register */ 203#define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */ 204#define ES_RXINT (1<<7) /* RX interrupt occurred */ 205#define ES_TXINT (1<<2) /* TX interrupt occurred */ 206#define ES_TXRDY (1<<1) /* transmitter ready */ 207#define ES_RXRDY (1<<0) /* receiver ready */ 208#define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */ 209#define ES_RXINTEN (1<<7) /* RX interrupt enable */ 210#define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */ 211#define ES_TXINTENM (0x03<<5) /* mask for above */ 212#define ES_TXINTENI(i) (((i)>>5)&0x03) 213#define ES_CNTRL(o) (((o)&0x03)<<0) /* control */ 214#define ES_CNTRLM (0x03<<0) /* mask for above */ 215#define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */ 216#define ES_TEST_MODE (1<<0) /* test mode enabled */ 217#define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */ 218#define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */ 219#define ES_MEM_PAGEM (0x0f<<0) /* mask for above */ 220#define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */ 221#define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */ 222#define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0)) 223#define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */ 224#define ES_1371_CODEC_RDY (1<<31) /* codec ready */ 225#define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */ 226#define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */ 227#define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0)) 228#define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD) 229#define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff) 230 231#define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */ 232#define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */ 233#define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */ 234#define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */ 235#define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */ 236#define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */ 237#define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */ 238#define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */ 239#define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */ 240#define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */ 241#define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */ 242#define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */ 243#define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */ 244 245#define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */ 246#define ES_1371_JFAST (1<<31) /* fast joystick timing */ 247#define ES_1371_HIB (1<<30) /* host interrupt blocking enable */ 248#define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */ 249#define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */ 250#define ES_1371_VMPUM (0x03<<27) /* mask for above */ 251#define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */ 252#define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */ 253#define ES_1371_VCDCM (0x03<<25) /* mask for above */ 254#define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */ 255#define ES_1371_FIRQ (1<<24) /* force an interrupt */ 256#define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */ 257#define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */ 258#define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */ 259#define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */ 260#define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */ 261#define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */ 262#define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */ 263#define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */ 264#define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */ 265#define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */ 266#define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */ 267#define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */ 268 269#define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */ 270 271#define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */ 272#define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */ 273#define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */ 274#define ES_P2_END_INCM (0x07<<19) /* mask for above */ 275#define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */ 276#define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */ 277#define ES_P2_ST_INCM (0x07<<16) /* mask for above */ 278#define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */ 279#define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */ 280#define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */ 281#define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */ 282#define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */ 283#define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */ 284#define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */ 285#define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */ 286#define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */ 287#define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */ 288#define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */ 289#define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */ 290#define ES_R1_MODEM (0x03<<4) /* mask for above */ 291#define ES_R1_MODEI(i) (((i)>>4)&0x03) 292#define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */ 293#define ES_P2_MODEM (0x03<<2) /* mask for above */ 294#define ES_P2_MODEI(i) (((i)>>2)&0x03) 295#define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */ 296#define ES_P1_MODEM (0x03<<0) /* mask for above */ 297#define ES_P1_MODEI(i) (((i)>>0)&0x03) 298 299#define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */ 300#define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */ 301#define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */ 302#define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff) 303#define ES_REG_COUNTO(o) (((o)&0xffff)<<0) 304#define ES_REG_COUNTM (0xffff<<0) 305#define ES_REG_COUNTI(i) (((i)>>0)&0xffff) 306 307#define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */ 308#define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */ 309#define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */ 310#define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */ 311#define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */ 312#define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */ 313#define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16) 314#define ES_REG_FCURR_COUNTM (0xffff<<16) 315#define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc) 316#define ES_REG_FSIZEO(o) (((o)&0xffff)<<0) 317#define ES_REG_FSIZEM (0xffff<<0) 318#define ES_REG_FSIZEI(i) (((i)>>0)&0xffff) 319#define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */ 320#define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */ 321 322#define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */ 323#define ES_REG_UF_VALID (1<<8) 324#define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0) 325#define ES_REG_UF_BYTEM (0xff<<0) 326#define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff) 327 328 329/* 330 * Pages 331 */ 332 333#define ES_PAGE_DAC 0x0c 334#define ES_PAGE_ADC 0x0d 335#define ES_PAGE_UART 0x0e 336#define ES_PAGE_UART1 0x0f 337 338/* 339 * Sample rate converter addresses 340 */ 341 342#define ES_SMPREG_DAC1 0x70 343#define ES_SMPREG_DAC2 0x74 344#define ES_SMPREG_ADC 0x78 345#define ES_SMPREG_VOL_ADC 0x6c 346#define ES_SMPREG_VOL_DAC1 0x7c 347#define ES_SMPREG_VOL_DAC2 0x7e 348#define ES_SMPREG_TRUNC_N 0x00 349#define ES_SMPREG_INT_REGS 0x01 350#define ES_SMPREG_ACCUM_FRAC 0x02 351#define ES_SMPREG_VFREQ_FRAC 0x03 352 353/* 354 * Some contants 355 */ 356 357#define ES_1370_SRCLOCK 1411200 358#define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2) 359 360/* 361 * Open modes 362 */ 363 364#define ES_MODE_PLAY1 0x0001 365#define ES_MODE_PLAY2 0x0002 366#define ES_MODE_CAPTURE 0x0004 367 368#define ES_MODE_OUTPUT 0x0001 /* for MIDI */ 369#define ES_MODE_INPUT 0x0002 /* for MIDI */ 370 371/* 372 373 */ 374 375struct ensoniq { 376 spinlock_t reg_lock; 377 struct mutex src_mutex; 378 379 int irq; 380 381 unsigned long playback1size; 382 unsigned long playback2size; 383 unsigned long capture3size; 384 385 unsigned long port; 386 unsigned int mode; 387 unsigned int uartm; /* UART mode */ 388 389 unsigned int ctrl; /* control register */ 390 unsigned int sctrl; /* serial control register */ 391 unsigned int cssr; /* control status register */ 392 unsigned int uartc; /* uart control register */ 393 unsigned int rev; /* chip revision */ 394 395 union { 396#ifdef CHIP1371 397 struct { 398 struct snd_ac97 *ac97; 399 } es1371; 400#else 401 struct { 402 int pclkdiv_lock; 403 struct snd_ak4531 *ak4531; 404 } es1370; 405#endif 406 } u; 407 408 struct pci_dev *pci; 409 struct snd_card *card; 410 struct snd_pcm *pcm1; /* DAC1/ADC PCM */ 411 struct snd_pcm *pcm2; /* DAC2 PCM */ 412 struct snd_pcm_substream *playback1_substream; 413 struct snd_pcm_substream *playback2_substream; 414 struct snd_pcm_substream *capture_substream; 415 unsigned int p1_dma_size; 416 unsigned int p2_dma_size; 417 unsigned int c_dma_size; 418 unsigned int p1_period_size; 419 unsigned int p2_period_size; 420 unsigned int c_period_size; 421 struct snd_rawmidi *rmidi; 422 struct snd_rawmidi_substream *midi_input; 423 struct snd_rawmidi_substream *midi_output; 424 425 unsigned int spdif; 426 unsigned int spdif_default; 427 unsigned int spdif_stream; 428 429#ifdef CHIP1370 430 struct snd_dma_buffer dma_bug; 431#endif 432 433#ifdef SUPPORT_JOYSTICK 434 struct gameport *gameport; 435#endif 436}; 437 438static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id); 439 440static DEFINE_PCI_DEVICE_TABLE(snd_audiopci_ids) = { 441#ifdef CHIP1370 442 { PCI_VDEVICE(ENSONIQ, 0x5000), 0, }, /* ES1370 */ 443#endif 444#ifdef CHIP1371 445 { PCI_VDEVICE(ENSONIQ, 0x1371), 0, }, /* ES1371 */ 446 { PCI_VDEVICE(ENSONIQ, 0x5880), 0, }, /* ES1373 - CT5880 */ 447 { PCI_VDEVICE(ECTIVA, 0x8938), 0, }, /* Ectiva EV1938 */ 448#endif 449 { 0, } 450}; 451 452MODULE_DEVICE_TABLE(pci, snd_audiopci_ids); 453 454/* 455 * constants 456 */ 457 458#define POLL_COUNT 0xa000 459 460#ifdef CHIP1370 461static unsigned int snd_es1370_fixed_rates[] = 462 {5512, 11025, 22050, 44100}; 463static struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = { 464 .count = 4, 465 .list = snd_es1370_fixed_rates, 466 .mask = 0, 467}; 468static struct snd_ratnum es1370_clock = { 469 .num = ES_1370_SRCLOCK, 470 .den_min = 29, 471 .den_max = 353, 472 .den_step = 1, 473}; 474static struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = { 475 .nrats = 1, 476 .rats = &es1370_clock, 477}; 478#else 479static struct snd_ratden es1371_dac_clock = { 480 .num_min = 3000 * (1 << 15), 481 .num_max = 48000 * (1 << 15), 482 .num_step = 3000, 483 .den = 1 << 15, 484}; 485static struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = { 486 .nrats = 1, 487 .rats = &es1371_dac_clock, 488}; 489static struct snd_ratnum es1371_adc_clock = { 490 .num = 48000 << 15, 491 .den_min = 32768, 492 .den_max = 393216, 493 .den_step = 1, 494}; 495static struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = { 496 .nrats = 1, 497 .rats = &es1371_adc_clock, 498}; 499#endif 500static const unsigned int snd_ensoniq_sample_shift[] = 501 {0, 1, 1, 2}; 502 503/* 504 * common I/O routines 505 */ 506 507#ifdef CHIP1371 508 509static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq) 510{ 511 unsigned int t, r = 0; 512 513 for (t = 0; t < POLL_COUNT; t++) { 514 r = inl(ES_REG(ensoniq, 1371_SMPRATE)); 515 if ((r & ES_1371_SRC_RAM_BUSY) == 0) 516 return r; 517 cond_resched(); 518 } 519 snd_printk(KERN_ERR "wait src ready timeout 0x%lx [0x%x]\n", 520 ES_REG(ensoniq, 1371_SMPRATE), r); 521 return 0; 522} 523 524static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg) 525{ 526 unsigned int temp, i, orig, r; 527 528 /* wait for ready */ 529 temp = orig = snd_es1371_wait_src_ready(ensoniq); 530 531 /* expose the SRC state bits */ 532 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 533 ES_1371_DIS_P2 | ES_1371_DIS_R1); 534 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000; 535 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 536 537 /* now, wait for busy and the correct time to read */ 538 temp = snd_es1371_wait_src_ready(ensoniq); 539 540 if ((temp & 0x00870000) != 0x00010000) { 541 /* wait for the right state */ 542 for (i = 0; i < POLL_COUNT; i++) { 543 temp = inl(ES_REG(ensoniq, 1371_SMPRATE)); 544 if ((temp & 0x00870000) == 0x00010000) 545 break; 546 } 547 } 548 549 /* hide the state bits */ 550 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 551 ES_1371_DIS_P2 | ES_1371_DIS_R1); 552 r |= ES_1371_SRC_RAM_ADDRO(reg); 553 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 554 555 return temp; 556} 557 558static void snd_es1371_src_write(struct ensoniq * ensoniq, 559 unsigned short reg, unsigned short data) 560{ 561 unsigned int r; 562 563 r = snd_es1371_wait_src_ready(ensoniq) & 564 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 565 ES_1371_DIS_P2 | ES_1371_DIS_R1); 566 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data); 567 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE)); 568} 569 570#endif /* CHIP1371 */ 571 572#ifdef CHIP1370 573 574static void snd_es1370_codec_write(struct snd_ak4531 *ak4531, 575 unsigned short reg, unsigned short val) 576{ 577 struct ensoniq *ensoniq = ak4531->private_data; 578 unsigned long end_time = jiffies + HZ / 10; 579 580 do { 581 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) { 582 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC)); 583 return; 584 } 585 schedule_timeout_uninterruptible(1); 586 } while (time_after(end_time, jiffies)); 587 snd_printk(KERN_ERR "codec write timeout, status = 0x%x\n", 588 inl(ES_REG(ensoniq, STATUS))); 589} 590 591#endif /* CHIP1370 */ 592 593#ifdef CHIP1371 594 595static void snd_es1371_codec_write(struct snd_ac97 *ac97, 596 unsigned short reg, unsigned short val) 597{ 598 struct ensoniq *ensoniq = ac97->private_data; 599 unsigned int t, x; 600 601 mutex_lock(&ensoniq->src_mutex); 602 for (t = 0; t < POLL_COUNT; t++) { 603 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) { 604 /* save the current state for latter */ 605 x = snd_es1371_wait_src_ready(ensoniq); 606 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 607 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000, 608 ES_REG(ensoniq, 1371_SMPRATE)); 609 /* wait for not busy (state 0) first to avoid 610 transition states */ 611 for (t = 0; t < POLL_COUNT; t++) { 612 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 613 0x00000000) 614 break; 615 } 616 /* wait for a SAFE time to write addr/data and then do it, dammit */ 617 for (t = 0; t < POLL_COUNT; t++) { 618 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 619 0x00010000) 620 break; 621 } 622 outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC)); 623 /* restore SRC reg */ 624 snd_es1371_wait_src_ready(ensoniq); 625 outl(x, ES_REG(ensoniq, 1371_SMPRATE)); 626 mutex_unlock(&ensoniq->src_mutex); 627 return; 628 } 629 } 630 mutex_unlock(&ensoniq->src_mutex); 631 snd_printk(KERN_ERR "codec write timeout at 0x%lx [0x%x]\n", 632 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC))); 633} 634 635static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97, 636 unsigned short reg) 637{ 638 struct ensoniq *ensoniq = ac97->private_data; 639 unsigned int t, x, fail = 0; 640 641 __again: 642 mutex_lock(&ensoniq->src_mutex); 643 for (t = 0; t < POLL_COUNT; t++) { 644 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) { 645 /* save the current state for latter */ 646 x = snd_es1371_wait_src_ready(ensoniq); 647 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 648 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000, 649 ES_REG(ensoniq, 1371_SMPRATE)); 650 /* wait for not busy (state 0) first to avoid 651 transition states */ 652 for (t = 0; t < POLL_COUNT; t++) { 653 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 654 0x00000000) 655 break; 656 } 657 /* wait for a SAFE time to write addr/data and then do it, dammit */ 658 for (t = 0; t < POLL_COUNT; t++) { 659 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 660 0x00010000) 661 break; 662 } 663 outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC)); 664 /* restore SRC reg */ 665 snd_es1371_wait_src_ready(ensoniq); 666 outl(x, ES_REG(ensoniq, 1371_SMPRATE)); 667 /* wait for WIP again */ 668 for (t = 0; t < POLL_COUNT; t++) { 669 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) 670 break; 671 } 672 /* now wait for the stinkin' data (RDY) */ 673 for (t = 0; t < POLL_COUNT; t++) { 674 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) { 675 mutex_unlock(&ensoniq->src_mutex); 676 return ES_1371_CODEC_READ(x); 677 } 678 } 679 mutex_unlock(&ensoniq->src_mutex); 680 if (++fail > 10) { 681 snd_printk(KERN_ERR "codec read timeout (final) " 682 "at 0x%lx, reg = 0x%x [0x%x]\n", 683 ES_REG(ensoniq, 1371_CODEC), reg, 684 inl(ES_REG(ensoniq, 1371_CODEC))); 685 return 0; 686 } 687 goto __again; 688 } 689 } 690 mutex_unlock(&ensoniq->src_mutex); 691 snd_printk(KERN_ERR "es1371: codec read timeout at 0x%lx [0x%x]\n", 692 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC))); 693 return 0; 694} 695 696static void snd_es1371_codec_wait(struct snd_ac97 *ac97) 697{ 698 msleep(750); 699 snd_es1371_codec_read(ac97, AC97_RESET); 700 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1); 701 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2); 702 msleep(50); 703} 704 705static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate) 706{ 707 unsigned int n, truncm, freq, result; 708 709 mutex_lock(&ensoniq->src_mutex); 710 n = rate / 3000; 711 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9))) 712 n--; 713 truncm = (21 * n - 1) | 1; 714 freq = ((48000UL << 15) / rate) * n; 715 result = (48000UL << 15) / (freq / n); 716 if (rate >= 24000) { 717 if (truncm > 239) 718 truncm = 239; 719 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 720 (((239 - truncm) >> 1) << 9) | (n << 4)); 721 } else { 722 if (truncm > 119) 723 truncm = 119; 724 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 725 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4)); 726 } 727 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS, 728 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC + 729 ES_SMPREG_INT_REGS) & 0x00ff) | 730 ((freq >> 5) & 0xfc00)); 731 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 732 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8); 733 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8); 734 mutex_unlock(&ensoniq->src_mutex); 735} 736 737static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate) 738{ 739 unsigned int freq, r; 740 741 mutex_lock(&ensoniq->src_mutex); 742 freq = ((rate << 15) + 1500) / 3000; 743 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 744 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 745 ES_1371_DIS_P1; 746 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 747 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 748 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 + 749 ES_SMPREG_INT_REGS) & 0x00ff) | 750 ((freq >> 5) & 0xfc00)); 751 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 752 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 753 ES_1371_DIS_P2 | ES_1371_DIS_R1)); 754 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 755 mutex_unlock(&ensoniq->src_mutex); 756} 757 758static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate) 759{ 760 unsigned int freq, r; 761 762 mutex_lock(&ensoniq->src_mutex); 763 freq = ((rate << 15) + 1500) / 3000; 764 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 765 ES_1371_DIS_P1 | ES_1371_DIS_R1)) | 766 ES_1371_DIS_P2; 767 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 768 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 769 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 + 770 ES_SMPREG_INT_REGS) & 0x00ff) | 771 ((freq >> 5) & 0xfc00)); 772 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC, 773 freq & 0x7fff); 774 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 775 ES_1371_DIS_P1 | ES_1371_DIS_R1)); 776 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 777 mutex_unlock(&ensoniq->src_mutex); 778} 779 780#endif /* CHIP1371 */ 781 782static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd) 783{ 784 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 785 switch (cmd) { 786 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 787 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 788 { 789 unsigned int what = 0; 790 struct snd_pcm_substream *s; 791 snd_pcm_group_for_each_entry(s, substream) { 792 if (s == ensoniq->playback1_substream) { 793 what |= ES_P1_PAUSE; 794 snd_pcm_trigger_done(s, substream); 795 } else if (s == ensoniq->playback2_substream) { 796 what |= ES_P2_PAUSE; 797 snd_pcm_trigger_done(s, substream); 798 } else if (s == ensoniq->capture_substream) 799 return -EINVAL; 800 } 801 spin_lock(&ensoniq->reg_lock); 802 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) 803 ensoniq->sctrl |= what; 804 else 805 ensoniq->sctrl &= ~what; 806 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 807 spin_unlock(&ensoniq->reg_lock); 808 break; 809 } 810 case SNDRV_PCM_TRIGGER_START: 811 case SNDRV_PCM_TRIGGER_STOP: 812 { 813 unsigned int what = 0; 814 struct snd_pcm_substream *s; 815 snd_pcm_group_for_each_entry(s, substream) { 816 if (s == ensoniq->playback1_substream) { 817 what |= ES_DAC1_EN; 818 snd_pcm_trigger_done(s, substream); 819 } else if (s == ensoniq->playback2_substream) { 820 what |= ES_DAC2_EN; 821 snd_pcm_trigger_done(s, substream); 822 } else if (s == ensoniq->capture_substream) { 823 what |= ES_ADC_EN; 824 snd_pcm_trigger_done(s, substream); 825 } 826 } 827 spin_lock(&ensoniq->reg_lock); 828 if (cmd == SNDRV_PCM_TRIGGER_START) 829 ensoniq->ctrl |= what; 830 else 831 ensoniq->ctrl &= ~what; 832 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 833 spin_unlock(&ensoniq->reg_lock); 834 break; 835 } 836 default: 837 return -EINVAL; 838 } 839 return 0; 840} 841 842/* 843 * PCM part 844 */ 845 846static int snd_ensoniq_hw_params(struct snd_pcm_substream *substream, 847 struct snd_pcm_hw_params *hw_params) 848{ 849 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 850} 851 852static int snd_ensoniq_hw_free(struct snd_pcm_substream *substream) 853{ 854 return snd_pcm_lib_free_pages(substream); 855} 856 857static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream) 858{ 859 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 860 struct snd_pcm_runtime *runtime = substream->runtime; 861 unsigned int mode = 0; 862 863 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream); 864 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream); 865 if (snd_pcm_format_width(runtime->format) == 16) 866 mode |= 0x02; 867 if (runtime->channels > 1) 868 mode |= 0x01; 869 spin_lock_irq(&ensoniq->reg_lock); 870 ensoniq->ctrl &= ~ES_DAC1_EN; 871#ifdef CHIP1371 872 /* 48k doesn't need SRC (it breaks AC3-passthru) */ 873 if (runtime->rate == 48000) 874 ensoniq->ctrl |= ES_1373_BYPASS_P1; 875 else 876 ensoniq->ctrl &= ~ES_1373_BYPASS_P1; 877#endif 878 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 879 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 880 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME)); 881 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE)); 882 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM); 883 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode); 884 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 885 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1, 886 ES_REG(ensoniq, DAC1_COUNT)); 887#ifdef CHIP1370 888 ensoniq->ctrl &= ~ES_1370_WTSRSELM; 889 switch (runtime->rate) { 890 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break; 891 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break; 892 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break; 893 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break; 894 default: snd_BUG(); 895 } 896#endif 897 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 898 spin_unlock_irq(&ensoniq->reg_lock); 899#ifndef CHIP1370 900 snd_es1371_dac1_rate(ensoniq, runtime->rate); 901#endif 902 return 0; 903} 904 905static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream) 906{ 907 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 908 struct snd_pcm_runtime *runtime = substream->runtime; 909 unsigned int mode = 0; 910 911 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream); 912 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream); 913 if (snd_pcm_format_width(runtime->format) == 16) 914 mode |= 0x02; 915 if (runtime->channels > 1) 916 mode |= 0x01; 917 spin_lock_irq(&ensoniq->reg_lock); 918 ensoniq->ctrl &= ~ES_DAC2_EN; 919 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 920 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 921 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME)); 922 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE)); 923 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN | 924 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM); 925 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) | 926 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0); 927 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 928 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1, 929 ES_REG(ensoniq, DAC2_COUNT)); 930#ifdef CHIP1370 931 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) { 932 ensoniq->ctrl &= ~ES_1370_PCLKDIVM; 933 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate)); 934 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2; 935 } 936#endif 937 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 938 spin_unlock_irq(&ensoniq->reg_lock); 939#ifndef CHIP1370 940 snd_es1371_dac2_rate(ensoniq, runtime->rate); 941#endif 942 return 0; 943} 944 945static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream) 946{ 947 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 948 struct snd_pcm_runtime *runtime = substream->runtime; 949 unsigned int mode = 0; 950 951 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream); 952 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream); 953 if (snd_pcm_format_width(runtime->format) == 16) 954 mode |= 0x02; 955 if (runtime->channels > 1) 956 mode |= 0x01; 957 spin_lock_irq(&ensoniq->reg_lock); 958 ensoniq->ctrl &= ~ES_ADC_EN; 959 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 960 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 961 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME)); 962 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE)); 963 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM); 964 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode); 965 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 966 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1, 967 ES_REG(ensoniq, ADC_COUNT)); 968#ifdef CHIP1370 969 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) { 970 ensoniq->ctrl &= ~ES_1370_PCLKDIVM; 971 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate)); 972 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE; 973 } 974#endif 975 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 976 spin_unlock_irq(&ensoniq->reg_lock); 977#ifndef CHIP1370 978 snd_es1371_adc_rate(ensoniq, runtime->rate); 979#endif 980 return 0; 981} 982 983static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream) 984{ 985 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 986 size_t ptr; 987 988 spin_lock(&ensoniq->reg_lock); 989 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) { 990 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 991 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE))); 992 ptr = bytes_to_frames(substream->runtime, ptr); 993 } else { 994 ptr = 0; 995 } 996 spin_unlock(&ensoniq->reg_lock); 997 return ptr; 998} 999 1000static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream) 1001{ 1002 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1003 size_t ptr; 1004 1005 spin_lock(&ensoniq->reg_lock); 1006 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) { 1007 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 1008 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE))); 1009 ptr = bytes_to_frames(substream->runtime, ptr); 1010 } else { 1011 ptr = 0; 1012 } 1013 spin_unlock(&ensoniq->reg_lock); 1014 return ptr; 1015} 1016 1017static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream) 1018{ 1019 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1020 size_t ptr; 1021 1022 spin_lock(&ensoniq->reg_lock); 1023 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) { 1024 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 1025 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE))); 1026 ptr = bytes_to_frames(substream->runtime, ptr); 1027 } else { 1028 ptr = 0; 1029 } 1030 spin_unlock(&ensoniq->reg_lock); 1031 return ptr; 1032} 1033 1034static struct snd_pcm_hardware snd_ensoniq_playback1 = 1035{ 1036 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1037 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1038 SNDRV_PCM_INFO_MMAP_VALID | 1039 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START), 1040 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1041 .rates = 1042#ifndef CHIP1370 1043 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1044#else 1045 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */ 1046 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 | 1047 SNDRV_PCM_RATE_44100), 1048#endif 1049 .rate_min = 4000, 1050 .rate_max = 48000, 1051 .channels_min = 1, 1052 .channels_max = 2, 1053 .buffer_bytes_max = (128*1024), 1054 .period_bytes_min = 64, 1055 .period_bytes_max = (128*1024), 1056 .periods_min = 1, 1057 .periods_max = 1024, 1058 .fifo_size = 0, 1059}; 1060 1061static struct snd_pcm_hardware snd_ensoniq_playback2 = 1062{ 1063 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1064 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1065 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE | 1066 SNDRV_PCM_INFO_SYNC_START), 1067 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1068 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1069 .rate_min = 4000, 1070 .rate_max = 48000, 1071 .channels_min = 1, 1072 .channels_max = 2, 1073 .buffer_bytes_max = (128*1024), 1074 .period_bytes_min = 64, 1075 .period_bytes_max = (128*1024), 1076 .periods_min = 1, 1077 .periods_max = 1024, 1078 .fifo_size = 0, 1079}; 1080 1081static struct snd_pcm_hardware snd_ensoniq_capture = 1082{ 1083 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1084 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1085 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START), 1086 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1087 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1088 .rate_min = 4000, 1089 .rate_max = 48000, 1090 .channels_min = 1, 1091 .channels_max = 2, 1092 .buffer_bytes_max = (128*1024), 1093 .period_bytes_min = 64, 1094 .period_bytes_max = (128*1024), 1095 .periods_min = 1, 1096 .periods_max = 1024, 1097 .fifo_size = 0, 1098}; 1099 1100static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream) 1101{ 1102 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1103 struct snd_pcm_runtime *runtime = substream->runtime; 1104 1105 ensoniq->mode |= ES_MODE_PLAY1; 1106 ensoniq->playback1_substream = substream; 1107 runtime->hw = snd_ensoniq_playback1; 1108 snd_pcm_set_sync(substream); 1109 spin_lock_irq(&ensoniq->reg_lock); 1110 if (ensoniq->spdif && ensoniq->playback2_substream == NULL) 1111 ensoniq->spdif_stream = ensoniq->spdif_default; 1112 spin_unlock_irq(&ensoniq->reg_lock); 1113#ifdef CHIP1370 1114 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1115 &snd_es1370_hw_constraints_rates); 1116#else 1117 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1118 &snd_es1371_hw_constraints_dac_clock); 1119#endif 1120 return 0; 1121} 1122 1123static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream) 1124{ 1125 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1126 struct snd_pcm_runtime *runtime = substream->runtime; 1127 1128 ensoniq->mode |= ES_MODE_PLAY2; 1129 ensoniq->playback2_substream = substream; 1130 runtime->hw = snd_ensoniq_playback2; 1131 snd_pcm_set_sync(substream); 1132 spin_lock_irq(&ensoniq->reg_lock); 1133 if (ensoniq->spdif && ensoniq->playback1_substream == NULL) 1134 ensoniq->spdif_stream = ensoniq->spdif_default; 1135 spin_unlock_irq(&ensoniq->reg_lock); 1136#ifdef CHIP1370 1137 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1138 &snd_es1370_hw_constraints_clock); 1139#else 1140 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1141 &snd_es1371_hw_constraints_dac_clock); 1142#endif 1143 return 0; 1144} 1145 1146static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream) 1147{ 1148 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1149 struct snd_pcm_runtime *runtime = substream->runtime; 1150 1151 ensoniq->mode |= ES_MODE_CAPTURE; 1152 ensoniq->capture_substream = substream; 1153 runtime->hw = snd_ensoniq_capture; 1154 snd_pcm_set_sync(substream); 1155#ifdef CHIP1370 1156 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1157 &snd_es1370_hw_constraints_clock); 1158#else 1159 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1160 &snd_es1371_hw_constraints_adc_clock); 1161#endif 1162 return 0; 1163} 1164 1165static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream) 1166{ 1167 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1168 1169 ensoniq->playback1_substream = NULL; 1170 ensoniq->mode &= ~ES_MODE_PLAY1; 1171 return 0; 1172} 1173 1174static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream) 1175{ 1176 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1177 1178 ensoniq->playback2_substream = NULL; 1179 spin_lock_irq(&ensoniq->reg_lock); 1180#ifdef CHIP1370 1181 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2; 1182#endif 1183 ensoniq->mode &= ~ES_MODE_PLAY2; 1184 spin_unlock_irq(&ensoniq->reg_lock); 1185 return 0; 1186} 1187 1188static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream) 1189{ 1190 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1191 1192 ensoniq->capture_substream = NULL; 1193 spin_lock_irq(&ensoniq->reg_lock); 1194#ifdef CHIP1370 1195 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE; 1196#endif 1197 ensoniq->mode &= ~ES_MODE_CAPTURE; 1198 spin_unlock_irq(&ensoniq->reg_lock); 1199 return 0; 1200} 1201 1202static struct snd_pcm_ops snd_ensoniq_playback1_ops = { 1203 .open = snd_ensoniq_playback1_open, 1204 .close = snd_ensoniq_playback1_close, 1205 .ioctl = snd_pcm_lib_ioctl, 1206 .hw_params = snd_ensoniq_hw_params, 1207 .hw_free = snd_ensoniq_hw_free, 1208 .prepare = snd_ensoniq_playback1_prepare, 1209 .trigger = snd_ensoniq_trigger, 1210 .pointer = snd_ensoniq_playback1_pointer, 1211}; 1212 1213static struct snd_pcm_ops snd_ensoniq_playback2_ops = { 1214 .open = snd_ensoniq_playback2_open, 1215 .close = snd_ensoniq_playback2_close, 1216 .ioctl = snd_pcm_lib_ioctl, 1217 .hw_params = snd_ensoniq_hw_params, 1218 .hw_free = snd_ensoniq_hw_free, 1219 .prepare = snd_ensoniq_playback2_prepare, 1220 .trigger = snd_ensoniq_trigger, 1221 .pointer = snd_ensoniq_playback2_pointer, 1222}; 1223 1224static struct snd_pcm_ops snd_ensoniq_capture_ops = { 1225 .open = snd_ensoniq_capture_open, 1226 .close = snd_ensoniq_capture_close, 1227 .ioctl = snd_pcm_lib_ioctl, 1228 .hw_params = snd_ensoniq_hw_params, 1229 .hw_free = snd_ensoniq_hw_free, 1230 .prepare = snd_ensoniq_capture_prepare, 1231 .trigger = snd_ensoniq_trigger, 1232 .pointer = snd_ensoniq_capture_pointer, 1233}; 1234 1235static int __devinit snd_ensoniq_pcm(struct ensoniq * ensoniq, int device, 1236 struct snd_pcm ** rpcm) 1237{ 1238 struct snd_pcm *pcm; 1239 int err; 1240 1241 if (rpcm) 1242 *rpcm = NULL; 1243#ifdef CHIP1370 1244 err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm); 1245#else 1246 err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm); 1247#endif 1248 if (err < 0) 1249 return err; 1250 1251#ifdef CHIP1370 1252 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops); 1253#else 1254 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops); 1255#endif 1256 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops); 1257 1258 pcm->private_data = ensoniq; 1259 pcm->info_flags = 0; 1260#ifdef CHIP1370 1261 strcpy(pcm->name, "ES1370 DAC2/ADC"); 1262#else 1263 strcpy(pcm->name, "ES1371 DAC2/ADC"); 1264#endif 1265 ensoniq->pcm1 = pcm; 1266 1267 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1268 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024); 1269 1270 if (rpcm) 1271 *rpcm = pcm; 1272 return 0; 1273} 1274 1275static int __devinit snd_ensoniq_pcm2(struct ensoniq * ensoniq, int device, 1276 struct snd_pcm ** rpcm) 1277{ 1278 struct snd_pcm *pcm; 1279 int err; 1280 1281 if (rpcm) 1282 *rpcm = NULL; 1283#ifdef CHIP1370 1284 err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm); 1285#else 1286 err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm); 1287#endif 1288 if (err < 0) 1289 return err; 1290 1291#ifdef CHIP1370 1292 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops); 1293#else 1294 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops); 1295#endif 1296 pcm->private_data = ensoniq; 1297 pcm->info_flags = 0; 1298#ifdef CHIP1370 1299 strcpy(pcm->name, "ES1370 DAC1"); 1300#else 1301 strcpy(pcm->name, "ES1371 DAC1"); 1302#endif 1303 ensoniq->pcm2 = pcm; 1304 1305 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1306 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024); 1307 1308 if (rpcm) 1309 *rpcm = pcm; 1310 return 0; 1311} 1312 1313/* 1314 * Mixer section 1315 */ 1316 1317/* 1318 * ENS1371 mixer (including SPDIF interface) 1319 */ 1320#ifdef CHIP1371 1321static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol, 1322 struct snd_ctl_elem_info *uinfo) 1323{ 1324 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1325 uinfo->count = 1; 1326 return 0; 1327} 1328 1329static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol, 1330 struct snd_ctl_elem_value *ucontrol) 1331{ 1332 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1333 spin_lock_irq(&ensoniq->reg_lock); 1334 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff; 1335 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff; 1336 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff; 1337 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff; 1338 spin_unlock_irq(&ensoniq->reg_lock); 1339 return 0; 1340} 1341 1342static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol, 1343 struct snd_ctl_elem_value *ucontrol) 1344{ 1345 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1346 unsigned int val; 1347 int change; 1348 1349 val = ((u32)ucontrol->value.iec958.status[0] << 0) | 1350 ((u32)ucontrol->value.iec958.status[1] << 8) | 1351 ((u32)ucontrol->value.iec958.status[2] << 16) | 1352 ((u32)ucontrol->value.iec958.status[3] << 24); 1353 spin_lock_irq(&ensoniq->reg_lock); 1354 change = ensoniq->spdif_default != val; 1355 ensoniq->spdif_default = val; 1356 if (change && ensoniq->playback1_substream == NULL && 1357 ensoniq->playback2_substream == NULL) 1358 outl(val, ES_REG(ensoniq, CHANNEL_STATUS)); 1359 spin_unlock_irq(&ensoniq->reg_lock); 1360 return change; 1361} 1362 1363static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol, 1364 struct snd_ctl_elem_value *ucontrol) 1365{ 1366 ucontrol->value.iec958.status[0] = 0xff; 1367 ucontrol->value.iec958.status[1] = 0xff; 1368 ucontrol->value.iec958.status[2] = 0xff; 1369 ucontrol->value.iec958.status[3] = 0xff; 1370 return 0; 1371} 1372 1373static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol, 1374 struct snd_ctl_elem_value *ucontrol) 1375{ 1376 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1377 spin_lock_irq(&ensoniq->reg_lock); 1378 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff; 1379 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff; 1380 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff; 1381 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff; 1382 spin_unlock_irq(&ensoniq->reg_lock); 1383 return 0; 1384} 1385 1386static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol, 1387 struct snd_ctl_elem_value *ucontrol) 1388{ 1389 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1390 unsigned int val; 1391 int change; 1392 1393 val = ((u32)ucontrol->value.iec958.status[0] << 0) | 1394 ((u32)ucontrol->value.iec958.status[1] << 8) | 1395 ((u32)ucontrol->value.iec958.status[2] << 16) | 1396 ((u32)ucontrol->value.iec958.status[3] << 24); 1397 spin_lock_irq(&ensoniq->reg_lock); 1398 change = ensoniq->spdif_stream != val; 1399 ensoniq->spdif_stream = val; 1400 if (change && (ensoniq->playback1_substream != NULL || 1401 ensoniq->playback2_substream != NULL)) 1402 outl(val, ES_REG(ensoniq, CHANNEL_STATUS)); 1403 spin_unlock_irq(&ensoniq->reg_lock); 1404 return change; 1405} 1406 1407#define ES1371_SPDIF(xname) \ 1408{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \ 1409 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put } 1410 1411#define snd_es1371_spdif_info snd_ctl_boolean_mono_info 1412 1413static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol, 1414 struct snd_ctl_elem_value *ucontrol) 1415{ 1416 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1417 1418 spin_lock_irq(&ensoniq->reg_lock); 1419 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0; 1420 spin_unlock_irq(&ensoniq->reg_lock); 1421 return 0; 1422} 1423 1424static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol, 1425 struct snd_ctl_elem_value *ucontrol) 1426{ 1427 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1428 unsigned int nval1, nval2; 1429 int change; 1430 1431 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0; 1432 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0; 1433 spin_lock_irq(&ensoniq->reg_lock); 1434 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1; 1435 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU; 1436 ensoniq->ctrl |= nval1; 1437 ensoniq->cssr &= ~ES_1373_SPDIF_EN; 1438 ensoniq->cssr |= nval2; 1439 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1440 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1441 spin_unlock_irq(&ensoniq->reg_lock); 1442 return change; 1443} 1444 1445 1446/* spdif controls */ 1447static struct snd_kcontrol_new snd_es1371_mixer_spdif[] __devinitdata = { 1448 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)), 1449 { 1450 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1451 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 1452 .info = snd_ens1373_spdif_info, 1453 .get = snd_ens1373_spdif_default_get, 1454 .put = snd_ens1373_spdif_default_put, 1455 }, 1456 { 1457 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1458 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1459 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), 1460 .info = snd_ens1373_spdif_info, 1461 .get = snd_ens1373_spdif_mask_get 1462 }, 1463 { 1464 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1465 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 1466 .info = snd_ens1373_spdif_info, 1467 .get = snd_ens1373_spdif_stream_get, 1468 .put = snd_ens1373_spdif_stream_put 1469 }, 1470}; 1471 1472 1473#define snd_es1373_rear_info snd_ctl_boolean_mono_info 1474 1475static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol, 1476 struct snd_ctl_elem_value *ucontrol) 1477{ 1478 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1479 int val = 0; 1480 1481 spin_lock_irq(&ensoniq->reg_lock); 1482 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26| 1483 ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26) 1484 val = 1; 1485 ucontrol->value.integer.value[0] = val; 1486 spin_unlock_irq(&ensoniq->reg_lock); 1487 return 0; 1488} 1489 1490static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol, 1491 struct snd_ctl_elem_value *ucontrol) 1492{ 1493 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1494 unsigned int nval1; 1495 int change; 1496 1497 nval1 = ucontrol->value.integer.value[0] ? 1498 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24); 1499 spin_lock_irq(&ensoniq->reg_lock); 1500 change = (ensoniq->cssr & (ES_1373_REAR_BIT27| 1501 ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1; 1502 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24); 1503 ensoniq->cssr |= nval1; 1504 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1505 spin_unlock_irq(&ensoniq->reg_lock); 1506 return change; 1507} 1508 1509static struct snd_kcontrol_new snd_ens1373_rear __devinitdata = 1510{ 1511 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1512 .name = "AC97 2ch->4ch Copy Switch", 1513 .info = snd_es1373_rear_info, 1514 .get = snd_es1373_rear_get, 1515 .put = snd_es1373_rear_put, 1516}; 1517 1518#define snd_es1373_line_info snd_ctl_boolean_mono_info 1519 1520static int snd_es1373_line_get(struct snd_kcontrol *kcontrol, 1521 struct snd_ctl_elem_value *ucontrol) 1522{ 1523 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1524 int val = 0; 1525 1526 spin_lock_irq(&ensoniq->reg_lock); 1527 if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4) 1528 val = 1; 1529 ucontrol->value.integer.value[0] = val; 1530 spin_unlock_irq(&ensoniq->reg_lock); 1531 return 0; 1532} 1533 1534static int snd_es1373_line_put(struct snd_kcontrol *kcontrol, 1535 struct snd_ctl_elem_value *ucontrol) 1536{ 1537 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1538 int changed; 1539 unsigned int ctrl; 1540 1541 spin_lock_irq(&ensoniq->reg_lock); 1542 ctrl = ensoniq->ctrl; 1543 if (ucontrol->value.integer.value[0]) 1544 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */ 1545 else 1546 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4); 1547 changed = (ctrl != ensoniq->ctrl); 1548 if (changed) 1549 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1550 spin_unlock_irq(&ensoniq->reg_lock); 1551 return changed; 1552} 1553 1554static struct snd_kcontrol_new snd_ens1373_line __devinitdata = 1555{ 1556 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1557 .name = "Line In->Rear Out Switch", 1558 .info = snd_es1373_line_info, 1559 .get = snd_es1373_line_get, 1560 .put = snd_es1373_line_put, 1561}; 1562 1563static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97) 1564{ 1565 struct ensoniq *ensoniq = ac97->private_data; 1566 ensoniq->u.es1371.ac97 = NULL; 1567} 1568 1569struct es1371_quirk { 1570 unsigned short vid; /* vendor ID */ 1571 unsigned short did; /* device ID */ 1572 unsigned char rev; /* revision */ 1573}; 1574 1575static int es1371_quirk_lookup(struct ensoniq *ensoniq, 1576 struct es1371_quirk *list) 1577{ 1578 while (list->vid != (unsigned short)PCI_ANY_ID) { 1579 if (ensoniq->pci->vendor == list->vid && 1580 ensoniq->pci->device == list->did && 1581 ensoniq->rev == list->rev) 1582 return 1; 1583 list++; 1584 } 1585 return 0; 1586} 1587 1588static struct es1371_quirk es1371_spdif_present[] __devinitdata = { 1589 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C }, 1590 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D }, 1591 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E }, 1592 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A }, 1593 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 }, 1594 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID } 1595}; 1596 1597static struct snd_pci_quirk ens1373_line_quirk[] __devinitdata = { 1598 SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */ 1599 SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */ 1600 { } /* end */ 1601}; 1602 1603static int __devinit snd_ensoniq_1371_mixer(struct ensoniq *ensoniq, 1604 int has_spdif, int has_line) 1605{ 1606 struct snd_card *card = ensoniq->card; 1607 struct snd_ac97_bus *pbus; 1608 struct snd_ac97_template ac97; 1609 int err; 1610 static struct snd_ac97_bus_ops ops = { 1611 .write = snd_es1371_codec_write, 1612 .read = snd_es1371_codec_read, 1613 .wait = snd_es1371_codec_wait, 1614 }; 1615 1616 if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0) 1617 return err; 1618 1619 memset(&ac97, 0, sizeof(ac97)); 1620 ac97.private_data = ensoniq; 1621 ac97.private_free = snd_ensoniq_mixer_free_ac97; 1622 ac97.pci = ensoniq->pci; 1623 ac97.scaps = AC97_SCAP_AUDIO; 1624 if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0) 1625 return err; 1626 if (has_spdif > 0 || 1627 (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) { 1628 struct snd_kcontrol *kctl; 1629 int i, is_spdif = 0; 1630 1631 ensoniq->spdif_default = ensoniq->spdif_stream = 1632 SNDRV_PCM_DEFAULT_CON_SPDIF; 1633 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS)); 1634 1635 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF) 1636 is_spdif++; 1637 1638 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) { 1639 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq); 1640 if (!kctl) 1641 return -ENOMEM; 1642 kctl->id.index = is_spdif; 1643 err = snd_ctl_add(card, kctl); 1644 if (err < 0) 1645 return err; 1646 } 1647 } 1648 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) { 1649 /* mirror rear to front speakers */ 1650 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24); 1651 ensoniq->cssr |= ES_1373_REAR_BIT26; 1652 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq)); 1653 if (err < 0) 1654 return err; 1655 } 1656 if (has_line > 0 || 1657 snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) { 1658 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, 1659 ensoniq)); 1660 if (err < 0) 1661 return err; 1662 } 1663 1664 return 0; 1665} 1666 1667#endif /* CHIP1371 */ 1668 1669/* generic control callbacks for ens1370 */ 1670#ifdef CHIP1370 1671#define ENSONIQ_CONTROL(xname, mask) \ 1672{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \ 1673 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \ 1674 .private_value = mask } 1675 1676#define snd_ensoniq_control_info snd_ctl_boolean_mono_info 1677 1678static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol, 1679 struct snd_ctl_elem_value *ucontrol) 1680{ 1681 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1682 int mask = kcontrol->private_value; 1683 1684 spin_lock_irq(&ensoniq->reg_lock); 1685 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0; 1686 spin_unlock_irq(&ensoniq->reg_lock); 1687 return 0; 1688} 1689 1690static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol, 1691 struct snd_ctl_elem_value *ucontrol) 1692{ 1693 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1694 int mask = kcontrol->private_value; 1695 unsigned int nval; 1696 int change; 1697 1698 nval = ucontrol->value.integer.value[0] ? mask : 0; 1699 spin_lock_irq(&ensoniq->reg_lock); 1700 change = (ensoniq->ctrl & mask) != nval; 1701 ensoniq->ctrl &= ~mask; 1702 ensoniq->ctrl |= nval; 1703 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1704 spin_unlock_irq(&ensoniq->reg_lock); 1705 return change; 1706} 1707 1708/* 1709 * ENS1370 mixer 1710 */ 1711 1712static struct snd_kcontrol_new snd_es1370_controls[2] __devinitdata = { 1713ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0), 1714ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1) 1715}; 1716 1717#define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls) 1718 1719static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531) 1720{ 1721 struct ensoniq *ensoniq = ak4531->private_data; 1722 ensoniq->u.es1370.ak4531 = NULL; 1723} 1724 1725static int __devinit snd_ensoniq_1370_mixer(struct ensoniq * ensoniq) 1726{ 1727 struct snd_card *card = ensoniq->card; 1728 struct snd_ak4531 ak4531; 1729 unsigned int idx; 1730 int err; 1731 1732 /* try reset AK4531 */ 1733 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC)); 1734 inw(ES_REG(ensoniq, 1370_CODEC)); 1735 udelay(100); 1736 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC)); 1737 inw(ES_REG(ensoniq, 1370_CODEC)); 1738 udelay(100); 1739 1740 memset(&ak4531, 0, sizeof(ak4531)); 1741 ak4531.write = snd_es1370_codec_write; 1742 ak4531.private_data = ensoniq; 1743 ak4531.private_free = snd_ensoniq_mixer_free_ak4531; 1744 if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0) 1745 return err; 1746 for (idx = 0; idx < ES1370_CONTROLS; idx++) { 1747 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq)); 1748 if (err < 0) 1749 return err; 1750 } 1751 return 0; 1752} 1753 1754#endif /* CHIP1370 */ 1755 1756#ifdef SUPPORT_JOYSTICK 1757 1758#ifdef CHIP1371 1759static int __devinit snd_ensoniq_get_joystick_port(int dev) 1760{ 1761 switch (joystick_port[dev]) { 1762 case 0: /* disabled */ 1763 case 1: /* auto-detect */ 1764 case 0x200: 1765 case 0x208: 1766 case 0x210: 1767 case 0x218: 1768 return joystick_port[dev]; 1769 1770 default: 1771 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]); 1772 return 0; 1773 } 1774} 1775#else 1776static inline int snd_ensoniq_get_joystick_port(int dev) 1777{ 1778 return joystick[dev] ? 0x200 : 0; 1779} 1780#endif 1781 1782static int __devinit snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev) 1783{ 1784 struct gameport *gp; 1785 int io_port; 1786 1787 io_port = snd_ensoniq_get_joystick_port(dev); 1788 1789 switch (io_port) { 1790 case 0: 1791 return -ENOSYS; 1792 1793 case 1: /* auto_detect */ 1794 for (io_port = 0x200; io_port <= 0x218; io_port += 8) 1795 if (request_region(io_port, 8, "ens137x: gameport")) 1796 break; 1797 if (io_port > 0x218) { 1798 printk(KERN_WARNING "ens137x: no gameport ports available\n"); 1799 return -EBUSY; 1800 } 1801 break; 1802 1803 default: 1804 if (!request_region(io_port, 8, "ens137x: gameport")) { 1805 printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n", 1806 io_port); 1807 return -EBUSY; 1808 } 1809 break; 1810 } 1811 1812 ensoniq->gameport = gp = gameport_allocate_port(); 1813 if (!gp) { 1814 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n"); 1815 release_region(io_port, 8); 1816 return -ENOMEM; 1817 } 1818 1819 gameport_set_name(gp, "ES137x"); 1820 gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci)); 1821 gameport_set_dev_parent(gp, &ensoniq->pci->dev); 1822 gp->io = io_port; 1823 1824 ensoniq->ctrl |= ES_JYSTK_EN; 1825#ifdef CHIP1371 1826 ensoniq->ctrl &= ~ES_1371_JOY_ASELM; 1827 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8); 1828#endif 1829 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1830 1831 gameport_register_port(ensoniq->gameport); 1832 1833 return 0; 1834} 1835 1836static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) 1837{ 1838 if (ensoniq->gameport) { 1839 int port = ensoniq->gameport->io; 1840 1841 gameport_unregister_port(ensoniq->gameport); 1842 ensoniq->gameport = NULL; 1843 ensoniq->ctrl &= ~ES_JYSTK_EN; 1844 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1845 release_region(port, 8); 1846 } 1847} 1848#else 1849static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; } 1850static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { } 1851#endif /* SUPPORT_JOYSTICK */ 1852 1853/* 1854 1855 */ 1856 1857static void snd_ensoniq_proc_read(struct snd_info_entry *entry, 1858 struct snd_info_buffer *buffer) 1859{ 1860 struct ensoniq *ensoniq = entry->private_data; 1861 1862#ifdef CHIP1370 1863 snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n"); 1864#else 1865 snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n"); 1866#endif 1867 snd_iprintf(buffer, "Joystick enable : %s\n", 1868 ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off"); 1869#ifdef CHIP1370 1870 snd_iprintf(buffer, "MIC +5V bias : %s\n", 1871 ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off"); 1872 snd_iprintf(buffer, "Line In to AOUT : %s\n", 1873 ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off"); 1874#else 1875 snd_iprintf(buffer, "Joystick port : 0x%x\n", 1876 (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200); 1877#endif 1878} 1879 1880static void __devinit snd_ensoniq_proc_init(struct ensoniq * ensoniq) 1881{ 1882 struct snd_info_entry *entry; 1883 1884 if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry)) 1885 snd_info_set_text_ops(entry, ensoniq, snd_ensoniq_proc_read); 1886} 1887 1888/* 1889 1890 */ 1891 1892static int snd_ensoniq_free(struct ensoniq *ensoniq) 1893{ 1894 snd_ensoniq_free_gameport(ensoniq); 1895 if (ensoniq->irq < 0) 1896 goto __hw_end; 1897#ifdef CHIP1370 1898 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */ 1899 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */ 1900#else 1901 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */ 1902 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */ 1903#endif 1904 if (ensoniq->irq >= 0) 1905 synchronize_irq(ensoniq->irq); 1906 pci_set_power_state(ensoniq->pci, 3); 1907 __hw_end: 1908#ifdef CHIP1370 1909 if (ensoniq->dma_bug.area) 1910 snd_dma_free_pages(&ensoniq->dma_bug); 1911#endif 1912 if (ensoniq->irq >= 0) 1913 free_irq(ensoniq->irq, ensoniq); 1914 pci_release_regions(ensoniq->pci); 1915 pci_disable_device(ensoniq->pci); 1916 kfree(ensoniq); 1917 return 0; 1918} 1919 1920static int snd_ensoniq_dev_free(struct snd_device *device) 1921{ 1922 struct ensoniq *ensoniq = device->device_data; 1923 return snd_ensoniq_free(ensoniq); 1924} 1925 1926#ifdef CHIP1371 1927static struct snd_pci_quirk es1371_amplifier_hack[] __devinitdata = { 1928 SND_PCI_QUIRK_ID(0x107b, 0x2150), /* Gateway Solo 2150 */ 1929 SND_PCI_QUIRK_ID(0x13bd, 0x100c), /* EV1938 on Mebius PC-MJ100V */ 1930 SND_PCI_QUIRK_ID(0x1102, 0x5938), /* Targa Xtender300 */ 1931 SND_PCI_QUIRK_ID(0x1102, 0x8938), /* IPC Topnote G notebook */ 1932 { } /* end */ 1933}; 1934 1935static struct es1371_quirk es1371_ac97_reset_hack[] = { 1936 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C }, 1937 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D }, 1938 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E }, 1939 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A }, 1940 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 }, 1941 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID } 1942}; 1943#endif 1944 1945static void snd_ensoniq_chip_init(struct ensoniq *ensoniq) 1946{ 1947#ifdef CHIP1371 1948 int idx; 1949#endif 1950 /* this code was part of snd_ensoniq_create before intruduction 1951 * of suspend/resume 1952 */ 1953#ifdef CHIP1370 1954 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1955 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 1956 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 1957 outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME)); 1958 outl(0, ES_REG(ensoniq, PHANTOM_COUNT)); 1959#else 1960 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1961 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 1962 outl(0, ES_REG(ensoniq, 1371_LEGACY)); 1963 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) { 1964 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1965 /* need to delay around 20ms(bleech) to give 1966 some CODECs enough time to wakeup */ 1967 msleep(20); 1968 } 1969 /* AC'97 warm reset to start the bitclk */ 1970 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL)); 1971 inl(ES_REG(ensoniq, CONTROL)); 1972 udelay(20); 1973 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1974 /* Init the sample rate converter */ 1975 snd_es1371_wait_src_ready(ensoniq); 1976 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE)); 1977 for (idx = 0; idx < 0x80; idx++) 1978 snd_es1371_src_write(ensoniq, idx, 0); 1979 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4); 1980 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10); 1981 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4); 1982 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10); 1983 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12); 1984 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12); 1985 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12); 1986 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12); 1987 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12); 1988 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12); 1989 snd_es1371_adc_rate(ensoniq, 22050); 1990 snd_es1371_dac1_rate(ensoniq, 22050); 1991 snd_es1371_dac2_rate(ensoniq, 22050); 1992 /* WARNING: 1993 * enabling the sample rate converter without properly programming 1994 * its parameters causes the chip to lock up (the SRC busy bit will 1995 * be stuck high, and I've found no way to rectify this other than 1996 * power cycle) - Thomas Sailer 1997 */ 1998 snd_es1371_wait_src_ready(ensoniq); 1999 outl(0, ES_REG(ensoniq, 1371_SMPRATE)); 2000 /* try reset codec directly */ 2001 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC)); 2002#endif 2003 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL)); 2004 outb(0x00, ES_REG(ensoniq, UART_RES)); 2005 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 2006 synchronize_irq(ensoniq->irq); 2007} 2008 2009#ifdef CONFIG_PM 2010static int snd_ensoniq_suspend(struct pci_dev *pci, pm_message_t state) 2011{ 2012 struct snd_card *card = pci_get_drvdata(pci); 2013 struct ensoniq *ensoniq = card->private_data; 2014 2015 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2016 2017 snd_pcm_suspend_all(ensoniq->pcm1); 2018 snd_pcm_suspend_all(ensoniq->pcm2); 2019 2020#ifdef CHIP1371 2021 snd_ac97_suspend(ensoniq->u.es1371.ac97); 2022#else 2023 /* try to reset AK4531 */ 2024 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC)); 2025 inw(ES_REG(ensoniq, 1370_CODEC)); 2026 udelay(100); 2027 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC)); 2028 inw(ES_REG(ensoniq, 1370_CODEC)); 2029 udelay(100); 2030 snd_ak4531_suspend(ensoniq->u.es1370.ak4531); 2031#endif 2032 2033 pci_disable_device(pci); 2034 pci_save_state(pci); 2035 pci_set_power_state(pci, pci_choose_state(pci, state)); 2036 return 0; 2037} 2038 2039static int snd_ensoniq_resume(struct pci_dev *pci) 2040{ 2041 struct snd_card *card = pci_get_drvdata(pci); 2042 struct ensoniq *ensoniq = card->private_data; 2043 2044 pci_set_power_state(pci, PCI_D0); 2045 pci_restore_state(pci); 2046 if (pci_enable_device(pci) < 0) { 2047 printk(KERN_ERR DRIVER_NAME ": pci_enable_device failed, " 2048 "disabling device\n"); 2049 snd_card_disconnect(card); 2050 return -EIO; 2051 } 2052 pci_set_master(pci); 2053 2054 snd_ensoniq_chip_init(ensoniq); 2055 2056#ifdef CHIP1371 2057 snd_ac97_resume(ensoniq->u.es1371.ac97); 2058#else 2059 snd_ak4531_resume(ensoniq->u.es1370.ak4531); 2060#endif 2061 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2062 return 0; 2063} 2064#endif /* CONFIG_PM */ 2065 2066 2067static int __devinit snd_ensoniq_create(struct snd_card *card, 2068 struct pci_dev *pci, 2069 struct ensoniq ** rensoniq) 2070{ 2071 struct ensoniq *ensoniq; 2072 int err; 2073 static struct snd_device_ops ops = { 2074 .dev_free = snd_ensoniq_dev_free, 2075 }; 2076 2077 *rensoniq = NULL; 2078 if ((err = pci_enable_device(pci)) < 0) 2079 return err; 2080 ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL); 2081 if (ensoniq == NULL) { 2082 pci_disable_device(pci); 2083 return -ENOMEM; 2084 } 2085 spin_lock_init(&ensoniq->reg_lock); 2086 mutex_init(&ensoniq->src_mutex); 2087 ensoniq->card = card; 2088 ensoniq->pci = pci; 2089 ensoniq->irq = -1; 2090 if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) { 2091 kfree(ensoniq); 2092 pci_disable_device(pci); 2093 return err; 2094 } 2095 ensoniq->port = pci_resource_start(pci, 0); 2096 if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED, 2097 "Ensoniq AudioPCI", ensoniq)) { 2098 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 2099 snd_ensoniq_free(ensoniq); 2100 return -EBUSY; 2101 } 2102 ensoniq->irq = pci->irq; 2103#ifdef CHIP1370 2104 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 2105 16, &ensoniq->dma_bug) < 0) { 2106 snd_printk(KERN_ERR "unable to allocate space for phantom area - dma_bug\n"); 2107 snd_ensoniq_free(ensoniq); 2108 return -EBUSY; 2109 } 2110#endif 2111 pci_set_master(pci); 2112 ensoniq->rev = pci->revision; 2113#ifdef CHIP1370 2114 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000)); 2115 ensoniq->sctrl = 0; 2116#else 2117 ensoniq->ctrl = 0; 2118 ensoniq->sctrl = 0; 2119 ensoniq->cssr = 0; 2120 if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack)) 2121 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */ 2122 2123 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) 2124 ensoniq->cssr |= ES_1371_ST_AC97_RST; 2125#endif 2126 2127 snd_ensoniq_chip_init(ensoniq); 2128 2129 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) { 2130 snd_ensoniq_free(ensoniq); 2131 return err; 2132 } 2133 2134 snd_ensoniq_proc_init(ensoniq); 2135 2136 snd_card_set_dev(card, &pci->dev); 2137 2138 *rensoniq = ensoniq; 2139 return 0; 2140} 2141 2142/* 2143 * MIDI section 2144 */ 2145 2146static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq) 2147{ 2148 struct snd_rawmidi *rmidi = ensoniq->rmidi; 2149 unsigned char status, mask, byte; 2150 2151 if (rmidi == NULL) 2152 return; 2153 /* do Rx at first */ 2154 spin_lock(&ensoniq->reg_lock); 2155 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0; 2156 while (mask) { 2157 status = inb(ES_REG(ensoniq, UART_STATUS)); 2158 if ((status & mask) == 0) 2159 break; 2160 byte = inb(ES_REG(ensoniq, UART_DATA)); 2161 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1); 2162 } 2163 spin_unlock(&ensoniq->reg_lock); 2164 2165 /* do Tx at second */ 2166 spin_lock(&ensoniq->reg_lock); 2167 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0; 2168 while (mask) { 2169 status = inb(ES_REG(ensoniq, UART_STATUS)); 2170 if ((status & mask) == 0) 2171 break; 2172 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) { 2173 ensoniq->uartc &= ~ES_TXINTENM; 2174 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2175 mask &= ~ES_TXRDY; 2176 } else { 2177 outb(byte, ES_REG(ensoniq, UART_DATA)); 2178 } 2179 } 2180 spin_unlock(&ensoniq->reg_lock); 2181} 2182 2183static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream) 2184{ 2185 struct ensoniq *ensoniq = substream->rmidi->private_data; 2186 2187 spin_lock_irq(&ensoniq->reg_lock); 2188 ensoniq->uartm |= ES_MODE_INPUT; 2189 ensoniq->midi_input = substream; 2190 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) { 2191 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL)); 2192 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2193 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2194 } 2195 spin_unlock_irq(&ensoniq->reg_lock); 2196 return 0; 2197} 2198 2199static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream) 2200{ 2201 struct ensoniq *ensoniq = substream->rmidi->private_data; 2202 2203 spin_lock_irq(&ensoniq->reg_lock); 2204 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) { 2205 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2206 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2207 } else { 2208 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL)); 2209 } 2210 ensoniq->midi_input = NULL; 2211 ensoniq->uartm &= ~ES_MODE_INPUT; 2212 spin_unlock_irq(&ensoniq->reg_lock); 2213 return 0; 2214} 2215 2216static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream) 2217{ 2218 struct ensoniq *ensoniq = substream->rmidi->private_data; 2219 2220 spin_lock_irq(&ensoniq->reg_lock); 2221 ensoniq->uartm |= ES_MODE_OUTPUT; 2222 ensoniq->midi_output = substream; 2223 if (!(ensoniq->uartm & ES_MODE_INPUT)) { 2224 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL)); 2225 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2226 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2227 } 2228 spin_unlock_irq(&ensoniq->reg_lock); 2229 return 0; 2230} 2231 2232static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream) 2233{ 2234 struct ensoniq *ensoniq = substream->rmidi->private_data; 2235 2236 spin_lock_irq(&ensoniq->reg_lock); 2237 if (!(ensoniq->uartm & ES_MODE_INPUT)) { 2238 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2239 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2240 } else { 2241 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL)); 2242 } 2243 ensoniq->midi_output = NULL; 2244 ensoniq->uartm &= ~ES_MODE_OUTPUT; 2245 spin_unlock_irq(&ensoniq->reg_lock); 2246 return 0; 2247} 2248 2249static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 2250{ 2251 unsigned long flags; 2252 struct ensoniq *ensoniq = substream->rmidi->private_data; 2253 int idx; 2254 2255 spin_lock_irqsave(&ensoniq->reg_lock, flags); 2256 if (up) { 2257 if ((ensoniq->uartc & ES_RXINTEN) == 0) { 2258 /* empty input FIFO */ 2259 for (idx = 0; idx < 32; idx++) 2260 inb(ES_REG(ensoniq, UART_DATA)); 2261 ensoniq->uartc |= ES_RXINTEN; 2262 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2263 } 2264 } else { 2265 if (ensoniq->uartc & ES_RXINTEN) { 2266 ensoniq->uartc &= ~ES_RXINTEN; 2267 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2268 } 2269 } 2270 spin_unlock_irqrestore(&ensoniq->reg_lock, flags); 2271} 2272 2273static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 2274{ 2275 unsigned long flags; 2276 struct ensoniq *ensoniq = substream->rmidi->private_data; 2277 unsigned char byte; 2278 2279 spin_lock_irqsave(&ensoniq->reg_lock, flags); 2280 if (up) { 2281 if (ES_TXINTENI(ensoniq->uartc) == 0) { 2282 ensoniq->uartc |= ES_TXINTENO(1); 2283 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ 2284 while (ES_TXINTENI(ensoniq->uartc) == 1 && 2285 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) { 2286 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { 2287 ensoniq->uartc &= ~ES_TXINTENM; 2288 } else { 2289 outb(byte, ES_REG(ensoniq, UART_DATA)); 2290 } 2291 } 2292 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2293 } 2294 } else { 2295 if (ES_TXINTENI(ensoniq->uartc) == 1) { 2296 ensoniq->uartc &= ~ES_TXINTENM; 2297 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2298 } 2299 } 2300 spin_unlock_irqrestore(&ensoniq->reg_lock, flags); 2301} 2302 2303static struct snd_rawmidi_ops snd_ensoniq_midi_output = 2304{ 2305 .open = snd_ensoniq_midi_output_open, 2306 .close = snd_ensoniq_midi_output_close, 2307 .trigger = snd_ensoniq_midi_output_trigger, 2308}; 2309 2310static struct snd_rawmidi_ops snd_ensoniq_midi_input = 2311{ 2312 .open = snd_ensoniq_midi_input_open, 2313 .close = snd_ensoniq_midi_input_close, 2314 .trigger = snd_ensoniq_midi_input_trigger, 2315}; 2316 2317static int __devinit snd_ensoniq_midi(struct ensoniq * ensoniq, int device, 2318 struct snd_rawmidi **rrawmidi) 2319{ 2320 struct snd_rawmidi *rmidi; 2321 int err; 2322 2323 if (rrawmidi) 2324 *rrawmidi = NULL; 2325 if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0) 2326 return err; 2327#ifdef CHIP1370 2328 strcpy(rmidi->name, "ES1370"); 2329#else 2330 strcpy(rmidi->name, "ES1371"); 2331#endif 2332 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output); 2333 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input); 2334 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | 2335 SNDRV_RAWMIDI_INFO_DUPLEX; 2336 rmidi->private_data = ensoniq; 2337 ensoniq->rmidi = rmidi; 2338 if (rrawmidi) 2339 *rrawmidi = rmidi; 2340 return 0; 2341} 2342 2343/* 2344 * Interrupt handler 2345 */ 2346 2347static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id) 2348{ 2349 struct ensoniq *ensoniq = dev_id; 2350 unsigned int status, sctrl; 2351 2352 if (ensoniq == NULL) 2353 return IRQ_NONE; 2354 2355 status = inl(ES_REG(ensoniq, STATUS)); 2356 if (!(status & ES_INTR)) 2357 return IRQ_NONE; 2358 2359 spin_lock(&ensoniq->reg_lock); 2360 sctrl = ensoniq->sctrl; 2361 if (status & ES_DAC1) 2362 sctrl &= ~ES_P1_INT_EN; 2363 if (status & ES_DAC2) 2364 sctrl &= ~ES_P2_INT_EN; 2365 if (status & ES_ADC) 2366 sctrl &= ~ES_R1_INT_EN; 2367 outl(sctrl, ES_REG(ensoniq, SERIAL)); 2368 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 2369 spin_unlock(&ensoniq->reg_lock); 2370 2371 if (status & ES_UART) 2372 snd_ensoniq_midi_interrupt(ensoniq); 2373 if ((status & ES_DAC2) && ensoniq->playback2_substream) 2374 snd_pcm_period_elapsed(ensoniq->playback2_substream); 2375 if ((status & ES_ADC) && ensoniq->capture_substream) 2376 snd_pcm_period_elapsed(ensoniq->capture_substream); 2377 if ((status & ES_DAC1) && ensoniq->playback1_substream) 2378 snd_pcm_period_elapsed(ensoniq->playback1_substream); 2379 return IRQ_HANDLED; 2380} 2381 2382static int __devinit snd_audiopci_probe(struct pci_dev *pci, 2383 const struct pci_device_id *pci_id) 2384{ 2385 static int dev; 2386 struct snd_card *card; 2387 struct ensoniq *ensoniq; 2388 int err, pcm_devs[2]; 2389 2390 if (dev >= SNDRV_CARDS) 2391 return -ENODEV; 2392 if (!enable[dev]) { 2393 dev++; 2394 return -ENOENT; 2395 } 2396 2397 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card); 2398 if (err < 0) 2399 return err; 2400 2401 if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) { 2402 snd_card_free(card); 2403 return err; 2404 } 2405 card->private_data = ensoniq; 2406 2407 pcm_devs[0] = 0; pcm_devs[1] = 1; 2408#ifdef CHIP1370 2409 if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) { 2410 snd_card_free(card); 2411 return err; 2412 } 2413#endif 2414#ifdef CHIP1371 2415 if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) { 2416 snd_card_free(card); 2417 return err; 2418 } 2419#endif 2420 if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) { 2421 snd_card_free(card); 2422 return err; 2423 } 2424 if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) { 2425 snd_card_free(card); 2426 return err; 2427 } 2428 if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) { 2429 snd_card_free(card); 2430 return err; 2431 } 2432 2433 snd_ensoniq_create_gameport(ensoniq, dev); 2434 2435 strcpy(card->driver, DRIVER_NAME); 2436 2437 strcpy(card->shortname, "Ensoniq AudioPCI"); 2438 sprintf(card->longname, "%s %s at 0x%lx, irq %i", 2439 card->shortname, 2440 card->driver, 2441 ensoniq->port, 2442 ensoniq->irq); 2443 2444 if ((err = snd_card_register(card)) < 0) { 2445 snd_card_free(card); 2446 return err; 2447 } 2448 2449 pci_set_drvdata(pci, card); 2450 dev++; 2451 return 0; 2452} 2453 2454static void __devexit snd_audiopci_remove(struct pci_dev *pci) 2455{ 2456 snd_card_free(pci_get_drvdata(pci)); 2457 pci_set_drvdata(pci, NULL); 2458} 2459 2460static struct pci_driver driver = { 2461 .name = DRIVER_NAME, 2462 .id_table = snd_audiopci_ids, 2463 .probe = snd_audiopci_probe, 2464 .remove = __devexit_p(snd_audiopci_remove), 2465#ifdef CONFIG_PM 2466 .suspend = snd_ensoniq_suspend, 2467 .resume = snd_ensoniq_resume, 2468#endif 2469}; 2470 2471static int __init alsa_card_ens137x_init(void) 2472{ 2473 return pci_register_driver(&driver); 2474} 2475 2476static void __exit alsa_card_ens137x_exit(void) 2477{ 2478 pci_unregister_driver(&driver); 2479} 2480 2481module_init(alsa_card_ens137x_init) 2482module_exit(alsa_card_ens137x_exit) 2483