1/* 2 * Driver for C-Media CMI8338 and 8738 PCI soundcards. 3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20/* Does not work. Warning may block system in capture mode */ 21/* #define USE_VAR48KRATE */ 22 23#include <asm/io.h> 24#include <linux/delay.h> 25#include <linux/interrupt.h> 26#include <linux/init.h> 27#include <linux/pci.h> 28#include <linux/slab.h> 29#include <linux/gameport.h> 30#include <linux/moduleparam.h> 31#include <linux/mutex.h> 32#include <sound/core.h> 33#include <sound/info.h> 34#include <sound/control.h> 35#include <sound/pcm.h> 36#include <sound/rawmidi.h> 37#include <sound/mpu401.h> 38#include <sound/opl3.h> 39#include <sound/sb.h> 40#include <sound/asoundef.h> 41#include <sound/initval.h> 42 43MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>"); 44MODULE_DESCRIPTION("C-Media CMI8x38 PCI"); 45MODULE_LICENSE("GPL"); 46MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738}," 47 "{C-Media,CMI8738B}," 48 "{C-Media,CMI8338A}," 49 "{C-Media,CMI8338B}}"); 50 51#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 52#define SUPPORT_JOYSTICK 1 53#endif 54 55static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 56static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 57static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ 58static long mpu_port[SNDRV_CARDS]; 59static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1}; 60static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1}; 61#ifdef SUPPORT_JOYSTICK 62static int joystick_port[SNDRV_CARDS]; 63#endif 64 65module_param_array(index, int, NULL, 0444); 66MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard."); 67module_param_array(id, charp, NULL, 0444); 68MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard."); 69module_param_array(enable, bool, NULL, 0444); 70MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard."); 71module_param_array(mpu_port, long, NULL, 0444); 72MODULE_PARM_DESC(mpu_port, "MPU-401 port."); 73module_param_array(fm_port, long, NULL, 0444); 74MODULE_PARM_DESC(fm_port, "FM port."); 75module_param_array(soft_ac3, bool, NULL, 0444); 76MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only)."); 77#ifdef SUPPORT_JOYSTICK 78module_param_array(joystick_port, int, NULL, 0444); 79MODULE_PARM_DESC(joystick_port, "Joystick port address."); 80#endif 81 82/* 83 * CM8x38 registers definition 84 */ 85 86#define CM_REG_FUNCTRL0 0x00 87#define CM_RST_CH1 0x00080000 88#define CM_RST_CH0 0x00040000 89#define CM_CHEN1 0x00020000 /* ch1: enable */ 90#define CM_CHEN0 0x00010000 /* ch0: enable */ 91#define CM_PAUSE1 0x00000008 /* ch1: pause */ 92#define CM_PAUSE0 0x00000004 /* ch0: pause */ 93#define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */ 94#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */ 95 96#define CM_REG_FUNCTRL1 0x04 97#define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */ 98#define CM_DSFC_SHIFT 13 99#define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */ 100#define CM_ASFC_SHIFT 10 101#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */ 102#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */ 103#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */ 104#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */ 105#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */ 106#define CM_BREQ 0x00000010 /* bus master enabled */ 107#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */ 108#define CM_UART_EN 0x00000004 /* legacy UART */ 109#define CM_JYSTK_EN 0x00000002 /* legacy joystick */ 110#define CM_ZVPORT 0x00000001 /* ZVPORT */ 111 112#define CM_REG_CHFORMAT 0x08 113 114#define CM_CHB3D5C 0x80000000 /* 5,6 channels */ 115#define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */ 116#define CM_CHB3D 0x20000000 /* 4 channels */ 117 118#define CM_CHIP_MASK1 0x1f000000 119#define CM_CHIP_037 0x01000000 120#define CM_SETLAT48 0x00800000 /* set latency timer 48h */ 121#define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */ 122#define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */ 123#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */ 124#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */ 125#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */ 126/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */ 127 128#define CM_ADCBITLEN_MASK 0x0000C000 129#define CM_ADCBITLEN_16 0x00000000 130#define CM_ADCBITLEN_15 0x00004000 131#define CM_ADCBITLEN_14 0x00008000 132#define CM_ADCBITLEN_13 0x0000C000 133 134#define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */ 135#define CM_ADCDACLEN_060 0x00000000 136#define CM_ADCDACLEN_066 0x00001000 137#define CM_ADCDACLEN_130 0x00002000 138#define CM_ADCDACLEN_280 0x00003000 139 140#define CM_ADCDLEN_MASK 0x00003000 /* model 039 */ 141#define CM_ADCDLEN_ORIGINAL 0x00000000 142#define CM_ADCDLEN_EXTRA 0x00001000 143#define CM_ADCDLEN_24K 0x00002000 144#define CM_ADCDLEN_WEIGHT 0x00003000 145 146#define CM_CH1_SRATE_176K 0x00000800 147#define CM_CH1_SRATE_96K 0x00000800 /* model 055? */ 148#define CM_CH1_SRATE_88K 0x00000400 149#define CM_CH0_SRATE_176K 0x00000200 150#define CM_CH0_SRATE_96K 0x00000200 /* model 055? */ 151#define CM_CH0_SRATE_88K 0x00000100 152#define CM_CH0_SRATE_128K 0x00000300 153#define CM_CH0_SRATE_MASK 0x00000300 154 155#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */ 156#define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */ 157#define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */ 158#define CM_SPDLOCKED 0x00000010 159 160#define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */ 161#define CM_CH1FMT_SHIFT 2 162#define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */ 163#define CM_CH0FMT_SHIFT 0 164 165#define CM_REG_INT_HLDCLR 0x0C 166#define CM_CHIP_MASK2 0xff000000 167#define CM_CHIP_8768 0x20000000 168#define CM_CHIP_055 0x08000000 169#define CM_CHIP_039 0x04000000 170#define CM_CHIP_039_6CH 0x01000000 171#define CM_UNKNOWN_INT_EN 0x00080000 /* ? */ 172#define CM_TDMA_INT_EN 0x00040000 173#define CM_CH1_INT_EN 0x00020000 174#define CM_CH0_INT_EN 0x00010000 175 176#define CM_REG_INT_STATUS 0x10 177#define CM_INTR 0x80000000 178#define CM_VCO 0x08000000 /* Voice Control? CMI8738 */ 179#define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */ 180#define CM_UARTINT 0x00010000 181#define CM_LTDMAINT 0x00008000 182#define CM_HTDMAINT 0x00004000 183#define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */ 184#define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */ 185#define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */ 186#define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */ 187#define CM_CH1BUSY 0x00000008 188#define CM_CH0BUSY 0x00000004 189#define CM_CHINT1 0x00000002 190#define CM_CHINT0 0x00000001 191 192#define CM_REG_LEGACY_CTRL 0x14 193#define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */ 194#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */ 195#define CM_VMPU_330 0x00000000 196#define CM_VMPU_320 0x20000000 197#define CM_VMPU_310 0x40000000 198#define CM_VMPU_300 0x60000000 199#define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */ 200#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */ 201#define CM_VSBSEL_220 0x00000000 202#define CM_VSBSEL_240 0x04000000 203#define CM_VSBSEL_260 0x08000000 204#define CM_VSBSEL_280 0x0C000000 205#define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */ 206#define CM_FMSEL_388 0x00000000 207#define CM_FMSEL_3C8 0x01000000 208#define CM_FMSEL_3E0 0x02000000 209#define CM_FMSEL_3E8 0x03000000 210#define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */ 211#define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */ 212#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */ 213#define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */ 214#define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */ 215#define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */ 216#define CM_C_EECS 0x00040000 217#define CM_C_EEDI46 0x00020000 218#define CM_C_EECK46 0x00010000 219#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */ 220#define CM_CENTR2LIN 0x00004000 /* line-in as center out */ 221#define CM_BASE2LIN 0x00002000 /* line-in as bass out */ 222#define CM_EXBASEN 0x00001000 /* external bass input enable */ 223 224#define CM_REG_MISC_CTRL 0x18 225#define CM_PWD 0x80000000 /* power down */ 226#define CM_RESET 0x40000000 227#define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */ 228#define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */ 229#define CM_TXVX 0x08000000 /* model 037? */ 230#define CM_N4SPK3D 0x04000000 /* copy front to rear */ 231#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */ 232#define CM_SPDIF48K 0x01000000 /* write */ 233#define CM_SPATUS48K 0x01000000 /* read */ 234#define CM_ENDBDAC 0x00800000 /* enable double dac */ 235#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */ 236#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */ 237#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */ 238#define CM_FM_EN 0x00080000 /* enable legacy FM */ 239#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */ 240#define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */ 241#define CM_VIDWPDSB 0x00010000 /* model 037? */ 242#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */ 243#define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */ 244#define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */ 245#define CM_VIDWPPRT 0x00002000 /* model 037? */ 246#define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */ 247#define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */ 248#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */ 249#define CM_ENCENTER 0x00000080 250#define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */ 251#define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */ 252#define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */ 253#define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */ 254#define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */ 255#define CM_UPDDMA_2048 0x00000000 256#define CM_UPDDMA_1024 0x00000004 257#define CM_UPDDMA_512 0x00000008 258#define CM_UPDDMA_256 0x0000000C 259#define CM_TWAIT_MASK 0x00000003 /* model 037 */ 260#define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */ 261#define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */ 262 263#define CM_REG_TDMA_POSITION 0x1C 264#define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */ 265#define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */ 266 267 /* byte */ 268#define CM_REG_MIXER0 0x20 269#define CM_REG_SBVR 0x20 /* write: sb16 version */ 270#define CM_REG_DEV 0x20 /* read: hardware device version */ 271 272#define CM_REG_MIXER21 0x21 273#define CM_UNKNOWN_21_MASK 0x78 /* ? */ 274#define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */ 275#define CM_PROINV 0x02 /* SBPro left/right channel switching */ 276#define CM_X_SB16 0x01 /* SB16 compatible */ 277 278#define CM_REG_SB16_DATA 0x22 279#define CM_REG_SB16_ADDR 0x23 280 281#define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */ 282#define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */ 283#define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */ 284#define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */ 285 286#define CM_REG_MIXER1 0x24 287#define CM_FMMUTE 0x80 /* mute FM */ 288#define CM_FMMUTE_SHIFT 7 289#define CM_WSMUTE 0x40 /* mute PCM */ 290#define CM_WSMUTE_SHIFT 6 291#define CM_REAR2LIN 0x20 /* lin-in -> rear line out */ 292#define CM_REAR2LIN_SHIFT 5 293#define CM_REAR2FRONT 0x10 /* exchange rear/front */ 294#define CM_REAR2FRONT_SHIFT 4 295#define CM_WAVEINL 0x08 /* digital wave rec. left chan */ 296#define CM_WAVEINL_SHIFT 3 297#define CM_WAVEINR 0x04 /* digical wave rec. right */ 298#define CM_WAVEINR_SHIFT 2 299#define CM_X3DEN 0x02 /* 3D surround enable */ 300#define CM_X3DEN_SHIFT 1 301#define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */ 302#define CM_CDPLAY_SHIFT 0 303 304#define CM_REG_MIXER2 0x25 305#define CM_RAUXREN 0x80 /* AUX right capture */ 306#define CM_RAUXREN_SHIFT 7 307#define CM_RAUXLEN 0x40 /* AUX left capture */ 308#define CM_RAUXLEN_SHIFT 6 309#define CM_VAUXRM 0x20 /* AUX right mute */ 310#define CM_VAUXRM_SHIFT 5 311#define CM_VAUXLM 0x10 /* AUX left mute */ 312#define CM_VAUXLM_SHIFT 4 313#define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */ 314#define CM_VADMIC_SHIFT 1 315#define CM_MICGAINZ 0x01 /* mic boost */ 316#define CM_MICGAINZ_SHIFT 0 317 318#define CM_REG_MIXER3 0x24 319#define CM_REG_AUX_VOL 0x26 320#define CM_VAUXL_MASK 0xf0 321#define CM_VAUXR_MASK 0x0f 322 323#define CM_REG_MISC 0x27 324#define CM_UNKNOWN_27_MASK 0xd8 /* ? */ 325#define CM_XGPO1 0x20 326// #define CM_XGPBIO 0x04 327#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */ 328#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */ 329#define CM_SPDVALID 0x02 /* spdif input valid check */ 330#define CM_DMAUTO 0x01 /* SB16 DMA auto detect */ 331 332#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */ 333/* 334 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738 335 * or identical with AC97 codec? 336 */ 337#define CM_REG_EXTERN_CODEC CM_REG_AC97 338 339/* 340 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6) 341 */ 342#define CM_REG_MPU_PCI 0x40 343 344/* 345 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6) 346 */ 347#define CM_REG_FM_PCI 0x50 348 349/* 350 * access from SB-mixer port 351 */ 352#define CM_REG_EXTENT_IND 0xf0 353#define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */ 354#define CM_VPHONE_SHIFT 5 355#define CM_VPHOM 0x10 /* Phone mute control */ 356#define CM_VSPKM 0x08 /* Speaker mute control, default high */ 357#define CM_RLOOPREN 0x04 /* Rec. R-channel enable */ 358#define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */ 359#define CM_VADMIC3 0x01 /* Mic record boost */ 360 361/* 362 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738): 363 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL 364 * unit (readonly?). 365 */ 366#define CM_REG_PLL 0xf8 367 368/* 369 * extended registers 370 */ 371#define CM_REG_CH0_FRAME1 0x80 /* write: base address */ 372#define CM_REG_CH0_FRAME2 0x84 /* read: current address */ 373#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */ 374#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */ 375 376#define CM_REG_EXT_MISC 0x90 377#define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */ 378#define CM_CHB3D8C 0x00200000 /* 7.1 channels support */ 379#define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */ 380#define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */ 381#define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */ 382#define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */ 383#define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */ 384#define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */ 385 386/* 387 * size of i/o region 388 */ 389#define CM_EXTENT_CODEC 0x100 390#define CM_EXTENT_MIDI 0x2 391#define CM_EXTENT_SYNTH 0x4 392 393 394/* 395 * channels for playback / capture 396 */ 397#define CM_CH_PLAY 0 398#define CM_CH_CAPT 1 399 400/* 401 * flags to check device open/close 402 */ 403#define CM_OPEN_NONE 0 404#define CM_OPEN_CH_MASK 0x01 405#define CM_OPEN_DAC 0x10 406#define CM_OPEN_ADC 0x20 407#define CM_OPEN_SPDIF 0x40 408#define CM_OPEN_MCHAN 0x80 409#define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC) 410#define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC) 411#define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN) 412#define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC) 413#define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF) 414#define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF) 415 416 417#if CM_CH_PLAY == 1 418#define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K 419#define CM_PLAYBACK_SPDF CM_SPDF_1 420#define CM_CAPTURE_SPDF CM_SPDF_0 421#else 422#define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K 423#define CM_PLAYBACK_SPDF CM_SPDF_0 424#define CM_CAPTURE_SPDF CM_SPDF_1 425#endif 426 427 428/* 429 * driver data 430 */ 431 432struct cmipci_pcm { 433 struct snd_pcm_substream *substream; 434 u8 running; /* dac/adc running? */ 435 u8 fmt; /* format bits */ 436 u8 is_dac; 437 u8 needs_silencing; 438 unsigned int dma_size; /* in frames */ 439 unsigned int shift; 440 unsigned int ch; /* channel (0/1) */ 441 unsigned int offset; /* physical address of the buffer */ 442}; 443 444/* mixer elements toggled/resumed during ac3 playback */ 445struct cmipci_mixer_auto_switches { 446 const char *name; /* switch to toggle */ 447 int toggle_on; /* value to change when ac3 mode */ 448}; 449static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = { 450 {"PCM Playback Switch", 0}, 451 {"IEC958 Output Switch", 1}, 452 {"IEC958 Mix Analog", 0}, 453 // {"IEC958 Out To DAC", 1}, // no longer used 454 {"IEC958 Loop", 0}, 455}; 456#define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer) 457 458struct cmipci { 459 struct snd_card *card; 460 461 struct pci_dev *pci; 462 unsigned int device; /* device ID */ 463 int irq; 464 465 unsigned long iobase; 466 unsigned int ctrl; /* FUNCTRL0 current value */ 467 468 struct snd_pcm *pcm; /* DAC/ADC PCM */ 469 struct snd_pcm *pcm2; /* 2nd DAC */ 470 struct snd_pcm *pcm_spdif; /* SPDIF */ 471 472 int chip_version; 473 int max_channels; 474 unsigned int can_ac3_sw: 1; 475 unsigned int can_ac3_hw: 1; 476 unsigned int can_multi_ch: 1; 477 unsigned int can_96k: 1; /* samplerate above 48k */ 478 unsigned int do_soft_ac3: 1; 479 480 unsigned int spdif_playback_avail: 1; /* spdif ready? */ 481 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */ 482 int spdif_counter; /* for software AC3 */ 483 484 unsigned int dig_status; 485 unsigned int dig_pcm_status; 486 487 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */ 488 489 int opened[2]; /* open mode */ 490 struct mutex open_mutex; 491 492 unsigned int mixer_insensitive: 1; 493 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS]; 494 int mixer_res_status[CM_SAVED_MIXERS]; 495 496 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */ 497 498 /* external MIDI */ 499 struct snd_rawmidi *rmidi; 500 501#ifdef SUPPORT_JOYSTICK 502 struct gameport *gameport; 503#endif 504 505 spinlock_t reg_lock; 506 507#ifdef CONFIG_PM 508 unsigned int saved_regs[0x20]; 509 unsigned char saved_mixers[0x20]; 510#endif 511}; 512 513 514/* read/write operations for dword register */ 515static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data) 516{ 517 outl(data, cm->iobase + cmd); 518} 519 520static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd) 521{ 522 return inl(cm->iobase + cmd); 523} 524 525/* read/write operations for word register */ 526static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data) 527{ 528 outw(data, cm->iobase + cmd); 529} 530 531static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd) 532{ 533 return inw(cm->iobase + cmd); 534} 535 536/* read/write operations for byte register */ 537static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data) 538{ 539 outb(data, cm->iobase + cmd); 540} 541 542static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd) 543{ 544 return inb(cm->iobase + cmd); 545} 546 547/* bit operations for dword register */ 548static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag) 549{ 550 unsigned int val, oval; 551 val = oval = inl(cm->iobase + cmd); 552 val |= flag; 553 if (val == oval) 554 return 0; 555 outl(val, cm->iobase + cmd); 556 return 1; 557} 558 559static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag) 560{ 561 unsigned int val, oval; 562 val = oval = inl(cm->iobase + cmd); 563 val &= ~flag; 564 if (val == oval) 565 return 0; 566 outl(val, cm->iobase + cmd); 567 return 1; 568} 569 570/* bit operations for byte register */ 571static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag) 572{ 573 unsigned char val, oval; 574 val = oval = inb(cm->iobase + cmd); 575 val |= flag; 576 if (val == oval) 577 return 0; 578 outb(val, cm->iobase + cmd); 579 return 1; 580} 581 582static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag) 583{ 584 unsigned char val, oval; 585 val = oval = inb(cm->iobase + cmd); 586 val &= ~flag; 587 if (val == oval) 588 return 0; 589 outb(val, cm->iobase + cmd); 590 return 1; 591} 592 593 594/* 595 * PCM interface 596 */ 597 598/* 599 * calculate frequency 600 */ 601 602static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 }; 603 604static unsigned int snd_cmipci_rate_freq(unsigned int rate) 605{ 606 unsigned int i; 607 608 for (i = 0; i < ARRAY_SIZE(rates); i++) { 609 if (rates[i] == rate) 610 return i; 611 } 612 snd_BUG(); 613 return 0; 614} 615 616#ifdef USE_VAR48KRATE 617/* 618 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???) 619 * does it this way .. maybe not. Never get any information from C-Media about 620 * that <werner@suse.de>. 621 */ 622static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n) 623{ 624 unsigned int delta, tolerance; 625 int xm, xn, xr; 626 627 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5)) 628 rate <<= 1; 629 *n = -1; 630 if (*r > 0xff) 631 goto out; 632 tolerance = rate*CM_TOLERANCE_RATE; 633 634 for (xn = (1+2); xn < (0x1f+2); xn++) { 635 for (xm = (1+2); xm < (0xff+2); xm++) { 636 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn; 637 638 if (xr < rate) 639 delta = rate - xr; 640 else 641 delta = xr - rate; 642 643 /* 644 * If we found one, remember this, 645 * and try to find a closer one 646 */ 647 if (delta < tolerance) { 648 tolerance = delta; 649 *m = xm - 2; 650 *n = xn - 2; 651 } 652 } 653 } 654out: 655 return (*n > -1); 656} 657 658/* 659 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff 660 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen 661 * at the register CM_REG_FUNCTRL1 (0x04). 662 * Problem: other ways are also possible (any information about that?) 663 */ 664static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot) 665{ 666 unsigned int reg = CM_REG_PLL + slot; 667 /* 668 * Guess that this programs at reg. 0x04 the pos 15:13/12:10 669 * for DSFC/ASFC (000 upto 111). 670 */ 671 672 673 snd_cmipci_write_b(cm, reg, rate>>8); 674 snd_cmipci_write_b(cm, reg, rate&0xff); 675 676} 677#endif /* USE_VAR48KRATE */ 678 679static int snd_cmipci_hw_params(struct snd_pcm_substream *substream, 680 struct snd_pcm_hw_params *hw_params) 681{ 682 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 683} 684 685static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream, 686 struct snd_pcm_hw_params *hw_params) 687{ 688 struct cmipci *cm = snd_pcm_substream_chip(substream); 689 if (params_channels(hw_params) > 2) { 690 mutex_lock(&cm->open_mutex); 691 if (cm->opened[CM_CH_PLAY]) { 692 mutex_unlock(&cm->open_mutex); 693 return -EBUSY; 694 } 695 /* reserve the channel A */ 696 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI; 697 mutex_unlock(&cm->open_mutex); 698 } 699 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 700} 701 702static void snd_cmipci_ch_reset(struct cmipci *cm, int ch) 703{ 704 int reset = CM_RST_CH0 << (cm->channel[ch].ch); 705 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); 706 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); 707 udelay(10); 708} 709 710static int snd_cmipci_hw_free(struct snd_pcm_substream *substream) 711{ 712 return snd_pcm_lib_free_pages(substream); 713} 714 715 716/* 717 */ 718 719static unsigned int hw_channels[] = {1, 2, 4, 6, 8}; 720static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = { 721 .count = 3, 722 .list = hw_channels, 723 .mask = 0, 724}; 725static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = { 726 .count = 4, 727 .list = hw_channels, 728 .mask = 0, 729}; 730static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = { 731 .count = 5, 732 .list = hw_channels, 733 .mask = 0, 734}; 735 736static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels) 737{ 738 if (channels > 2) { 739 if (!cm->can_multi_ch || !rec->ch) 740 return -EINVAL; 741 if (rec->fmt != 0x03) /* stereo 16bit only */ 742 return -EINVAL; 743 } 744 745 if (cm->can_multi_ch) { 746 spin_lock_irq(&cm->reg_lock); 747 if (channels > 2) { 748 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); 749 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 750 } else { 751 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); 752 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 753 } 754 if (channels == 8) 755 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C); 756 else 757 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C); 758 if (channels == 6) { 759 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); 760 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); 761 } else { 762 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); 763 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); 764 } 765 if (channels == 4) 766 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); 767 else 768 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); 769 spin_unlock_irq(&cm->reg_lock); 770 } 771 return 0; 772} 773 774 775/* 776 * prepare playback/capture channel 777 * channel to be used must have been set in rec->ch. 778 */ 779static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec, 780 struct snd_pcm_substream *substream) 781{ 782 unsigned int reg, freq, freq_ext, val; 783 unsigned int period_size; 784 struct snd_pcm_runtime *runtime = substream->runtime; 785 786 rec->fmt = 0; 787 rec->shift = 0; 788 if (snd_pcm_format_width(runtime->format) >= 16) { 789 rec->fmt |= 0x02; 790 if (snd_pcm_format_width(runtime->format) > 16) 791 rec->shift++; /* 24/32bit */ 792 } 793 if (runtime->channels > 1) 794 rec->fmt |= 0x01; 795 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) { 796 snd_printd("cannot set dac channels\n"); 797 return -EINVAL; 798 } 799 800 rec->offset = runtime->dma_addr; 801 /* buffer and period sizes in frame */ 802 rec->dma_size = runtime->buffer_size << rec->shift; 803 period_size = runtime->period_size << rec->shift; 804 if (runtime->channels > 2) { 805 /* multi-channels */ 806 rec->dma_size = (rec->dma_size * runtime->channels) / 2; 807 period_size = (period_size * runtime->channels) / 2; 808 } 809 810 spin_lock_irq(&cm->reg_lock); 811 812 /* set buffer address */ 813 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; 814 snd_cmipci_write(cm, reg, rec->offset); 815 /* program sample counts */ 816 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; 817 snd_cmipci_write_w(cm, reg, rec->dma_size - 1); 818 snd_cmipci_write_w(cm, reg + 2, period_size - 1); 819 820 /* set adc/dac flag */ 821 val = rec->ch ? CM_CHADC1 : CM_CHADC0; 822 if (rec->is_dac) 823 cm->ctrl &= ~val; 824 else 825 cm->ctrl |= val; 826 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 827 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl); 828 829 /* set sample rate */ 830 freq = 0; 831 freq_ext = 0; 832 if (runtime->rate > 48000) 833 switch (runtime->rate) { 834 case 88200: freq_ext = CM_CH0_SRATE_88K; break; 835 case 96000: freq_ext = CM_CH0_SRATE_96K; break; 836 case 128000: freq_ext = CM_CH0_SRATE_128K; break; 837 default: snd_BUG(); break; 838 } 839 else 840 freq = snd_cmipci_rate_freq(runtime->rate); 841 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1); 842 if (rec->ch) { 843 val &= ~CM_DSFC_MASK; 844 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK; 845 } else { 846 val &= ~CM_ASFC_MASK; 847 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK; 848 } 849 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val); 850 //snd_printd("cmipci: functrl1 = %08x\n", val); 851 852 /* set format */ 853 val = snd_cmipci_read(cm, CM_REG_CHFORMAT); 854 if (rec->ch) { 855 val &= ~CM_CH1FMT_MASK; 856 val |= rec->fmt << CM_CH1FMT_SHIFT; 857 } else { 858 val &= ~CM_CH0FMT_MASK; 859 val |= rec->fmt << CM_CH0FMT_SHIFT; 860 } 861 if (cm->can_96k) { 862 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2)); 863 val |= freq_ext << (rec->ch * 2); 864 } 865 snd_cmipci_write(cm, CM_REG_CHFORMAT, val); 866 //snd_printd("cmipci: chformat = %08x\n", val); 867 868 if (!rec->is_dac && cm->chip_version) { 869 if (runtime->rate > 44100) 870 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K); 871 else 872 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K); 873 } 874 875 rec->running = 0; 876 spin_unlock_irq(&cm->reg_lock); 877 878 return 0; 879} 880 881/* 882 * PCM trigger/stop 883 */ 884static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec, 885 int cmd) 886{ 887 unsigned int inthld, chen, reset, pause; 888 int result = 0; 889 890 inthld = CM_CH0_INT_EN << rec->ch; 891 chen = CM_CHEN0 << rec->ch; 892 reset = CM_RST_CH0 << rec->ch; 893 pause = CM_PAUSE0 << rec->ch; 894 895 spin_lock(&cm->reg_lock); 896 switch (cmd) { 897 case SNDRV_PCM_TRIGGER_START: 898 rec->running = 1; 899 /* set interrupt */ 900 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld); 901 cm->ctrl |= chen; 902 /* enable channel */ 903 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 904 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl); 905 break; 906 case SNDRV_PCM_TRIGGER_STOP: 907 rec->running = 0; 908 /* disable interrupt */ 909 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld); 910 /* reset */ 911 cm->ctrl &= ~chen; 912 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); 913 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); 914 rec->needs_silencing = rec->is_dac; 915 break; 916 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 917 case SNDRV_PCM_TRIGGER_SUSPEND: 918 cm->ctrl |= pause; 919 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 920 break; 921 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 922 case SNDRV_PCM_TRIGGER_RESUME: 923 cm->ctrl &= ~pause; 924 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 925 break; 926 default: 927 result = -EINVAL; 928 break; 929 } 930 spin_unlock(&cm->reg_lock); 931 return result; 932} 933 934/* 935 * return the current pointer 936 */ 937static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec, 938 struct snd_pcm_substream *substream) 939{ 940 size_t ptr; 941 unsigned int reg, rem, tries; 942 943 if (!rec->running) 944 return 0; 945 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; 946 for (tries = 0; tries < 3; tries++) { 947 rem = snd_cmipci_read_w(cm, reg); 948 if (rem < rec->dma_size) 949 goto ok; 950 } 951 printk(KERN_ERR "cmipci: invalid PCM pointer: %#x\n", rem); 952 return SNDRV_PCM_POS_XRUN; 953ok: 954 ptr = (rec->dma_size - (rem + 1)) >> rec->shift; 955 if (substream->runtime->channels > 2) 956 ptr = (ptr * 2) / substream->runtime->channels; 957 return ptr; 958} 959 960/* 961 * playback 962 */ 963 964static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream, 965 int cmd) 966{ 967 struct cmipci *cm = snd_pcm_substream_chip(substream); 968 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd); 969} 970 971static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream) 972{ 973 struct cmipci *cm = snd_pcm_substream_chip(substream); 974 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream); 975} 976 977 978 979/* 980 * capture 981 */ 982 983static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream, 984 int cmd) 985{ 986 struct cmipci *cm = snd_pcm_substream_chip(substream); 987 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd); 988} 989 990static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream) 991{ 992 struct cmipci *cm = snd_pcm_substream_chip(substream); 993 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream); 994} 995 996 997/* 998 * hw preparation for spdif 999 */ 1000 1001static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol, 1002 struct snd_ctl_elem_info *uinfo) 1003{ 1004 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1005 uinfo->count = 1; 1006 return 0; 1007} 1008 1009static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol, 1010 struct snd_ctl_elem_value *ucontrol) 1011{ 1012 struct cmipci *chip = snd_kcontrol_chip(kcontrol); 1013 int i; 1014 1015 spin_lock_irq(&chip->reg_lock); 1016 for (i = 0; i < 4; i++) 1017 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff; 1018 spin_unlock_irq(&chip->reg_lock); 1019 return 0; 1020} 1021 1022static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol, 1023 struct snd_ctl_elem_value *ucontrol) 1024{ 1025 struct cmipci *chip = snd_kcontrol_chip(kcontrol); 1026 int i, change; 1027 unsigned int val; 1028 1029 val = 0; 1030 spin_lock_irq(&chip->reg_lock); 1031 for (i = 0; i < 4; i++) 1032 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); 1033 change = val != chip->dig_status; 1034 chip->dig_status = val; 1035 spin_unlock_irq(&chip->reg_lock); 1036 return change; 1037} 1038 1039static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata = 1040{ 1041 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1042 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 1043 .info = snd_cmipci_spdif_default_info, 1044 .get = snd_cmipci_spdif_default_get, 1045 .put = snd_cmipci_spdif_default_put 1046}; 1047 1048static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol, 1049 struct snd_ctl_elem_info *uinfo) 1050{ 1051 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1052 uinfo->count = 1; 1053 return 0; 1054} 1055 1056static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol, 1057 struct snd_ctl_elem_value *ucontrol) 1058{ 1059 ucontrol->value.iec958.status[0] = 0xff; 1060 ucontrol->value.iec958.status[1] = 0xff; 1061 ucontrol->value.iec958.status[2] = 0xff; 1062 ucontrol->value.iec958.status[3] = 0xff; 1063 return 0; 1064} 1065 1066static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata = 1067{ 1068 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1069 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1070 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), 1071 .info = snd_cmipci_spdif_mask_info, 1072 .get = snd_cmipci_spdif_mask_get, 1073}; 1074 1075static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol, 1076 struct snd_ctl_elem_info *uinfo) 1077{ 1078 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1079 uinfo->count = 1; 1080 return 0; 1081} 1082 1083static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol, 1084 struct snd_ctl_elem_value *ucontrol) 1085{ 1086 struct cmipci *chip = snd_kcontrol_chip(kcontrol); 1087 int i; 1088 1089 spin_lock_irq(&chip->reg_lock); 1090 for (i = 0; i < 4; i++) 1091 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff; 1092 spin_unlock_irq(&chip->reg_lock); 1093 return 0; 1094} 1095 1096static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol, 1097 struct snd_ctl_elem_value *ucontrol) 1098{ 1099 struct cmipci *chip = snd_kcontrol_chip(kcontrol); 1100 int i, change; 1101 unsigned int val; 1102 1103 val = 0; 1104 spin_lock_irq(&chip->reg_lock); 1105 for (i = 0; i < 4; i++) 1106 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); 1107 change = val != chip->dig_pcm_status; 1108 chip->dig_pcm_status = val; 1109 spin_unlock_irq(&chip->reg_lock); 1110 return change; 1111} 1112 1113static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata = 1114{ 1115 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 1116 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1117 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 1118 .info = snd_cmipci_spdif_stream_info, 1119 .get = snd_cmipci_spdif_stream_get, 1120 .put = snd_cmipci_spdif_stream_put 1121}; 1122 1123/* 1124 */ 1125 1126/* save mixer setting and mute for AC3 playback */ 1127static int save_mixer_state(struct cmipci *cm) 1128{ 1129 if (! cm->mixer_insensitive) { 1130 struct snd_ctl_elem_value *val; 1131 unsigned int i; 1132 1133 val = kmalloc(sizeof(*val), GFP_ATOMIC); 1134 if (!val) 1135 return -ENOMEM; 1136 for (i = 0; i < CM_SAVED_MIXERS; i++) { 1137 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i]; 1138 if (ctl) { 1139 int event; 1140 memset(val, 0, sizeof(*val)); 1141 ctl->get(ctl, val); 1142 cm->mixer_res_status[i] = val->value.integer.value[0]; 1143 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on; 1144 event = SNDRV_CTL_EVENT_MASK_INFO; 1145 if (cm->mixer_res_status[i] != val->value.integer.value[0]) { 1146 ctl->put(ctl, val); /* toggle */ 1147 event |= SNDRV_CTL_EVENT_MASK_VALUE; 1148 } 1149 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1150 snd_ctl_notify(cm->card, event, &ctl->id); 1151 } 1152 } 1153 kfree(val); 1154 cm->mixer_insensitive = 1; 1155 } 1156 return 0; 1157} 1158 1159 1160/* restore the previously saved mixer status */ 1161static void restore_mixer_state(struct cmipci *cm) 1162{ 1163 if (cm->mixer_insensitive) { 1164 struct snd_ctl_elem_value *val; 1165 unsigned int i; 1166 1167 val = kmalloc(sizeof(*val), GFP_KERNEL); 1168 if (!val) 1169 return; 1170 cm->mixer_insensitive = 0; /* at first clear this; 1171 otherwise the changes will be ignored */ 1172 for (i = 0; i < CM_SAVED_MIXERS; i++) { 1173 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i]; 1174 if (ctl) { 1175 int event; 1176 1177 memset(val, 0, sizeof(*val)); 1178 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1179 ctl->get(ctl, val); 1180 event = SNDRV_CTL_EVENT_MASK_INFO; 1181 if (val->value.integer.value[0] != cm->mixer_res_status[i]) { 1182 val->value.integer.value[0] = cm->mixer_res_status[i]; 1183 ctl->put(ctl, val); 1184 event |= SNDRV_CTL_EVENT_MASK_VALUE; 1185 } 1186 snd_ctl_notify(cm->card, event, &ctl->id); 1187 } 1188 } 1189 kfree(val); 1190 } 1191} 1192 1193/* spinlock held! */ 1194static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate) 1195{ 1196 if (do_ac3) { 1197 /* AC3EN for 037 */ 1198 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1); 1199 /* AC3EN for 039 */ 1200 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2); 1201 1202 if (cm->can_ac3_hw) { 1203 /* SPD24SEL for 037, 0x02 */ 1204 /* SPD24SEL for 039, 0x20, but cannot be set */ 1205 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1206 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1207 } else { /* can_ac3_sw */ 1208 /* SPD32SEL for 037 & 039, 0x20 */ 1209 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1210 /* set 176K sample rate to fix 033 HW bug */ 1211 if (cm->chip_version == 33) { 1212 if (rate >= 48000) { 1213 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); 1214 } else { 1215 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); 1216 } 1217 } 1218 } 1219 1220 } else { 1221 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1); 1222 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2); 1223 1224 if (cm->can_ac3_hw) { 1225 /* chip model >= 37 */ 1226 if (snd_pcm_format_width(subs->runtime->format) > 16) { 1227 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1228 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1229 } else { 1230 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1231 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1232 } 1233 } else { 1234 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1235 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1236 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); 1237 } 1238 } 1239} 1240 1241static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3) 1242{ 1243 int rate, err; 1244 1245 rate = subs->runtime->rate; 1246 1247 if (up && do_ac3) 1248 if ((err = save_mixer_state(cm)) < 0) 1249 return err; 1250 1251 spin_lock_irq(&cm->reg_lock); 1252 cm->spdif_playback_avail = up; 1253 if (up) { 1254 /* they are controlled via "IEC958 Output Switch" */ 1255 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ 1256 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ 1257 if (cm->spdif_playback_enabled) 1258 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 1259 setup_ac3(cm, subs, do_ac3, rate); 1260 1261 if (rate == 48000 || rate == 96000) 1262 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); 1263 else 1264 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); 1265 if (rate > 48000) 1266 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); 1267 else 1268 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); 1269 } else { 1270 /* they are controlled via "IEC958 Output Switch" */ 1271 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ 1272 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ 1273 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); 1274 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 1275 setup_ac3(cm, subs, 0, 0); 1276 } 1277 spin_unlock_irq(&cm->reg_lock); 1278 return 0; 1279} 1280 1281 1282/* 1283 * preparation 1284 */ 1285 1286/* playback - enable spdif only on the certain condition */ 1287static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream) 1288{ 1289 struct cmipci *cm = snd_pcm_substream_chip(substream); 1290 int rate = substream->runtime->rate; 1291 int err, do_spdif, do_ac3 = 0; 1292 1293 do_spdif = (rate >= 44100 && rate <= 96000 && 1294 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE && 1295 substream->runtime->channels == 2); 1296 if (do_spdif && cm->can_ac3_hw) 1297 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; 1298 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0) 1299 return err; 1300 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); 1301} 1302 1303/* playback (via device #2) - enable spdif always */ 1304static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream) 1305{ 1306 struct cmipci *cm = snd_pcm_substream_chip(substream); 1307 int err, do_ac3; 1308 1309 if (cm->can_ac3_hw) 1310 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; 1311 else 1312 do_ac3 = 1; /* doesn't matter */ 1313 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0) 1314 return err; 1315 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); 1316} 1317 1318/* 1319 * Apparently, the samples last played on channel A stay in some buffer, even 1320 * after the channel is reset, and get added to the data for the rear DACs when 1321 * playing a multichannel stream on channel B. This is likely to generate 1322 * wraparounds and thus distortions. 1323 * To avoid this, we play at least one zero sample after the actual stream has 1324 * stopped. 1325 */ 1326static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec) 1327{ 1328 struct snd_pcm_runtime *runtime = rec->substream->runtime; 1329 unsigned int reg, val; 1330 1331 if (rec->needs_silencing && runtime && runtime->dma_area) { 1332 /* set up a small silence buffer */ 1333 memset(runtime->dma_area, 0, PAGE_SIZE); 1334 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; 1335 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16); 1336 snd_cmipci_write(cm, reg, val); 1337 1338 /* configure for 16 bits, 2 channels, 8 kHz */ 1339 if (runtime->channels > 2) 1340 set_dac_channels(cm, rec, 2); 1341 spin_lock_irq(&cm->reg_lock); 1342 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1); 1343 val &= ~(CM_ASFC_MASK << (rec->ch * 3)); 1344 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3); 1345 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val); 1346 val = snd_cmipci_read(cm, CM_REG_CHFORMAT); 1347 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2)); 1348 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2); 1349 if (cm->can_96k) 1350 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2)); 1351 snd_cmipci_write(cm, CM_REG_CHFORMAT, val); 1352 1353 /* start stream (we don't need interrupts) */ 1354 cm->ctrl |= CM_CHEN0 << rec->ch; 1355 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 1356 spin_unlock_irq(&cm->reg_lock); 1357 1358 msleep(1); 1359 1360 /* stop and reset stream */ 1361 spin_lock_irq(&cm->reg_lock); 1362 cm->ctrl &= ~(CM_CHEN0 << rec->ch); 1363 val = CM_RST_CH0 << rec->ch; 1364 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val); 1365 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val); 1366 spin_unlock_irq(&cm->reg_lock); 1367 1368 rec->needs_silencing = 0; 1369 } 1370} 1371 1372static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream) 1373{ 1374 struct cmipci *cm = snd_pcm_substream_chip(substream); 1375 setup_spdif_playback(cm, substream, 0, 0); 1376 restore_mixer_state(cm); 1377 snd_cmipci_silence_hack(cm, &cm->channel[0]); 1378 return snd_cmipci_hw_free(substream); 1379} 1380 1381static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream) 1382{ 1383 struct cmipci *cm = snd_pcm_substream_chip(substream); 1384 snd_cmipci_silence_hack(cm, &cm->channel[1]); 1385 return snd_cmipci_hw_free(substream); 1386} 1387 1388/* capture */ 1389static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream) 1390{ 1391 struct cmipci *cm = snd_pcm_substream_chip(substream); 1392 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); 1393} 1394 1395/* capture with spdif (via device #2) */ 1396static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream) 1397{ 1398 struct cmipci *cm = snd_pcm_substream_chip(substream); 1399 1400 spin_lock_irq(&cm->reg_lock); 1401 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); 1402 if (cm->can_96k) { 1403 if (substream->runtime->rate > 48000) 1404 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); 1405 else 1406 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS); 1407 } 1408 if (snd_pcm_format_width(substream->runtime->format) > 16) 1409 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1410 else 1411 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1412 1413 spin_unlock_irq(&cm->reg_lock); 1414 1415 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); 1416} 1417 1418static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs) 1419{ 1420 struct cmipci *cm = snd_pcm_substream_chip(subs); 1421 1422 spin_lock_irq(&cm->reg_lock); 1423 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); 1424 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1425 spin_unlock_irq(&cm->reg_lock); 1426 1427 return snd_cmipci_hw_free(subs); 1428} 1429 1430 1431/* 1432 * interrupt handler 1433 */ 1434static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id) 1435{ 1436 struct cmipci *cm = dev_id; 1437 unsigned int status, mask = 0; 1438 1439 /* fastpath out, to ease interrupt sharing */ 1440 status = snd_cmipci_read(cm, CM_REG_INT_STATUS); 1441 if (!(status & CM_INTR)) 1442 return IRQ_NONE; 1443 1444 /* acknowledge interrupt */ 1445 spin_lock(&cm->reg_lock); 1446 if (status & CM_CHINT0) 1447 mask |= CM_CH0_INT_EN; 1448 if (status & CM_CHINT1) 1449 mask |= CM_CH1_INT_EN; 1450 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask); 1451 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask); 1452 spin_unlock(&cm->reg_lock); 1453 1454 if (cm->rmidi && (status & CM_UARTINT)) 1455 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data); 1456 1457 if (cm->pcm) { 1458 if ((status & CM_CHINT0) && cm->channel[0].running) 1459 snd_pcm_period_elapsed(cm->channel[0].substream); 1460 if ((status & CM_CHINT1) && cm->channel[1].running) 1461 snd_pcm_period_elapsed(cm->channel[1].substream); 1462 } 1463 return IRQ_HANDLED; 1464} 1465 1466/* 1467 * h/w infos 1468 */ 1469 1470/* playback on channel A */ 1471static struct snd_pcm_hardware snd_cmipci_playback = 1472{ 1473 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1474 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1475 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1476 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1477 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, 1478 .rate_min = 5512, 1479 .rate_max = 48000, 1480 .channels_min = 1, 1481 .channels_max = 2, 1482 .buffer_bytes_max = (128*1024), 1483 .period_bytes_min = 64, 1484 .period_bytes_max = (128*1024), 1485 .periods_min = 2, 1486 .periods_max = 1024, 1487 .fifo_size = 0, 1488}; 1489 1490/* capture on channel B */ 1491static struct snd_pcm_hardware snd_cmipci_capture = 1492{ 1493 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1494 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1495 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1496 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1497 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, 1498 .rate_min = 5512, 1499 .rate_max = 48000, 1500 .channels_min = 1, 1501 .channels_max = 2, 1502 .buffer_bytes_max = (128*1024), 1503 .period_bytes_min = 64, 1504 .period_bytes_max = (128*1024), 1505 .periods_min = 2, 1506 .periods_max = 1024, 1507 .fifo_size = 0, 1508}; 1509 1510/* playback on channel B - stereo 16bit only? */ 1511static struct snd_pcm_hardware snd_cmipci_playback2 = 1512{ 1513 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1514 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1515 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1516 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1517 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, 1518 .rate_min = 5512, 1519 .rate_max = 48000, 1520 .channels_min = 2, 1521 .channels_max = 2, 1522 .buffer_bytes_max = (128*1024), 1523 .period_bytes_min = 64, 1524 .period_bytes_max = (128*1024), 1525 .periods_min = 2, 1526 .periods_max = 1024, 1527 .fifo_size = 0, 1528}; 1529 1530/* spdif playback on channel A */ 1531static struct snd_pcm_hardware snd_cmipci_playback_spdif = 1532{ 1533 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1534 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1535 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1536 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1537 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, 1538 .rate_min = 44100, 1539 .rate_max = 48000, 1540 .channels_min = 2, 1541 .channels_max = 2, 1542 .buffer_bytes_max = (128*1024), 1543 .period_bytes_min = 64, 1544 .period_bytes_max = (128*1024), 1545 .periods_min = 2, 1546 .periods_max = 1024, 1547 .fifo_size = 0, 1548}; 1549 1550/* spdif playback on channel A (32bit, IEC958 subframes) */ 1551static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe = 1552{ 1553 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1554 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1555 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1556 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1557 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, 1558 .rate_min = 44100, 1559 .rate_max = 48000, 1560 .channels_min = 2, 1561 .channels_max = 2, 1562 .buffer_bytes_max = (128*1024), 1563 .period_bytes_min = 64, 1564 .period_bytes_max = (128*1024), 1565 .periods_min = 2, 1566 .periods_max = 1024, 1567 .fifo_size = 0, 1568}; 1569 1570/* spdif capture on channel B */ 1571static struct snd_pcm_hardware snd_cmipci_capture_spdif = 1572{ 1573 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1574 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1575 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID), 1576 .formats = SNDRV_PCM_FMTBIT_S16_LE | 1577 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1578 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, 1579 .rate_min = 44100, 1580 .rate_max = 48000, 1581 .channels_min = 2, 1582 .channels_max = 2, 1583 .buffer_bytes_max = (128*1024), 1584 .period_bytes_min = 64, 1585 .period_bytes_max = (128*1024), 1586 .periods_min = 2, 1587 .periods_max = 1024, 1588 .fifo_size = 0, 1589}; 1590 1591static unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050, 1592 32000, 44100, 48000, 88200, 96000, 128000 }; 1593static struct snd_pcm_hw_constraint_list hw_constraints_rates = { 1594 .count = ARRAY_SIZE(rate_constraints), 1595 .list = rate_constraints, 1596 .mask = 0, 1597}; 1598 1599/* 1600 * check device open/close 1601 */ 1602static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs) 1603{ 1604 int ch = mode & CM_OPEN_CH_MASK; 1605 1606 mutex_lock(&cm->open_mutex); 1607 if (cm->opened[ch]) { 1608 mutex_unlock(&cm->open_mutex); 1609 return -EBUSY; 1610 } 1611 cm->opened[ch] = mode; 1612 cm->channel[ch].substream = subs; 1613 if (! (mode & CM_OPEN_DAC)) { 1614 /* disable dual DAC mode */ 1615 cm->channel[ch].is_dac = 0; 1616 spin_lock_irq(&cm->reg_lock); 1617 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); 1618 spin_unlock_irq(&cm->reg_lock); 1619 } 1620 mutex_unlock(&cm->open_mutex); 1621 return 0; 1622} 1623 1624static void close_device_check(struct cmipci *cm, int mode) 1625{ 1626 int ch = mode & CM_OPEN_CH_MASK; 1627 1628 mutex_lock(&cm->open_mutex); 1629 if (cm->opened[ch] == mode) { 1630 if (cm->channel[ch].substream) { 1631 snd_cmipci_ch_reset(cm, ch); 1632 cm->channel[ch].running = 0; 1633 cm->channel[ch].substream = NULL; 1634 } 1635 cm->opened[ch] = 0; 1636 if (! cm->channel[ch].is_dac) { 1637 /* enable dual DAC mode again */ 1638 cm->channel[ch].is_dac = 1; 1639 spin_lock_irq(&cm->reg_lock); 1640 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); 1641 spin_unlock_irq(&cm->reg_lock); 1642 } 1643 } 1644 mutex_unlock(&cm->open_mutex); 1645} 1646 1647/* 1648 */ 1649 1650static int snd_cmipci_playback_open(struct snd_pcm_substream *substream) 1651{ 1652 struct cmipci *cm = snd_pcm_substream_chip(substream); 1653 struct snd_pcm_runtime *runtime = substream->runtime; 1654 int err; 1655 1656 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0) 1657 return err; 1658 runtime->hw = snd_cmipci_playback; 1659 if (cm->chip_version == 68) { 1660 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | 1661 SNDRV_PCM_RATE_96000; 1662 runtime->hw.rate_max = 96000; 1663 } else if (cm->chip_version == 55) { 1664 err = snd_pcm_hw_constraint_list(runtime, 0, 1665 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates); 1666 if (err < 0) 1667 return err; 1668 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 1669 runtime->hw.rate_max = 128000; 1670 } 1671 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1672 cm->dig_pcm_status = cm->dig_status; 1673 return 0; 1674} 1675 1676static int snd_cmipci_capture_open(struct snd_pcm_substream *substream) 1677{ 1678 struct cmipci *cm = snd_pcm_substream_chip(substream); 1679 struct snd_pcm_runtime *runtime = substream->runtime; 1680 int err; 1681 1682 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0) 1683 return err; 1684 runtime->hw = snd_cmipci_capture; 1685 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording 1686 runtime->hw.rate_min = 41000; 1687 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000; 1688 } else if (cm->chip_version == 55) { 1689 err = snd_pcm_hw_constraint_list(runtime, 0, 1690 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates); 1691 if (err < 0) 1692 return err; 1693 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 1694 runtime->hw.rate_max = 128000; 1695 } 1696 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1697 return 0; 1698} 1699 1700static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream) 1701{ 1702 struct cmipci *cm = snd_pcm_substream_chip(substream); 1703 struct snd_pcm_runtime *runtime = substream->runtime; 1704 int err; 1705 1706 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */ 1707 return err; 1708 runtime->hw = snd_cmipci_playback2; 1709 mutex_lock(&cm->open_mutex); 1710 if (! cm->opened[CM_CH_PLAY]) { 1711 if (cm->can_multi_ch) { 1712 runtime->hw.channels_max = cm->max_channels; 1713 if (cm->max_channels == 4) 1714 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4); 1715 else if (cm->max_channels == 6) 1716 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6); 1717 else if (cm->max_channels == 8) 1718 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8); 1719 } 1720 } 1721 mutex_unlock(&cm->open_mutex); 1722 if (cm->chip_version == 68) { 1723 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | 1724 SNDRV_PCM_RATE_96000; 1725 runtime->hw.rate_max = 96000; 1726 } else if (cm->chip_version == 55) { 1727 err = snd_pcm_hw_constraint_list(runtime, 0, 1728 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates); 1729 if (err < 0) 1730 return err; 1731 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 1732 runtime->hw.rate_max = 128000; 1733 } 1734 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1735 return 0; 1736} 1737 1738static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream) 1739{ 1740 struct cmipci *cm = snd_pcm_substream_chip(substream); 1741 struct snd_pcm_runtime *runtime = substream->runtime; 1742 int err; 1743 1744 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */ 1745 return err; 1746 if (cm->can_ac3_hw) { 1747 runtime->hw = snd_cmipci_playback_spdif; 1748 if (cm->chip_version >= 37) { 1749 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; 1750 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 1751 } 1752 if (cm->can_96k) { 1753 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | 1754 SNDRV_PCM_RATE_96000; 1755 runtime->hw.rate_max = 96000; 1756 } 1757 } else { 1758 runtime->hw = snd_cmipci_playback_iec958_subframe; 1759 } 1760 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); 1761 cm->dig_pcm_status = cm->dig_status; 1762 return 0; 1763} 1764 1765static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream) 1766{ 1767 struct cmipci *cm = snd_pcm_substream_chip(substream); 1768 struct snd_pcm_runtime *runtime = substream->runtime; 1769 int err; 1770 1771 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */ 1772 return err; 1773 runtime->hw = snd_cmipci_capture_spdif; 1774 if (cm->can_96k && !(cm->chip_version == 68)) { 1775 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | 1776 SNDRV_PCM_RATE_96000; 1777 runtime->hw.rate_max = 96000; 1778 } 1779 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); 1780 return 0; 1781} 1782 1783 1784/* 1785 */ 1786 1787static int snd_cmipci_playback_close(struct snd_pcm_substream *substream) 1788{ 1789 struct cmipci *cm = snd_pcm_substream_chip(substream); 1790 close_device_check(cm, CM_OPEN_PLAYBACK); 1791 return 0; 1792} 1793 1794static int snd_cmipci_capture_close(struct snd_pcm_substream *substream) 1795{ 1796 struct cmipci *cm = snd_pcm_substream_chip(substream); 1797 close_device_check(cm, CM_OPEN_CAPTURE); 1798 return 0; 1799} 1800 1801static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream) 1802{ 1803 struct cmipci *cm = snd_pcm_substream_chip(substream); 1804 close_device_check(cm, CM_OPEN_PLAYBACK2); 1805 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI); 1806 return 0; 1807} 1808 1809static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream) 1810{ 1811 struct cmipci *cm = snd_pcm_substream_chip(substream); 1812 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK); 1813 return 0; 1814} 1815 1816static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream) 1817{ 1818 struct cmipci *cm = snd_pcm_substream_chip(substream); 1819 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE); 1820 return 0; 1821} 1822 1823 1824/* 1825 */ 1826 1827static struct snd_pcm_ops snd_cmipci_playback_ops = { 1828 .open = snd_cmipci_playback_open, 1829 .close = snd_cmipci_playback_close, 1830 .ioctl = snd_pcm_lib_ioctl, 1831 .hw_params = snd_cmipci_hw_params, 1832 .hw_free = snd_cmipci_playback_hw_free, 1833 .prepare = snd_cmipci_playback_prepare, 1834 .trigger = snd_cmipci_playback_trigger, 1835 .pointer = snd_cmipci_playback_pointer, 1836}; 1837 1838static struct snd_pcm_ops snd_cmipci_capture_ops = { 1839 .open = snd_cmipci_capture_open, 1840 .close = snd_cmipci_capture_close, 1841 .ioctl = snd_pcm_lib_ioctl, 1842 .hw_params = snd_cmipci_hw_params, 1843 .hw_free = snd_cmipci_hw_free, 1844 .prepare = snd_cmipci_capture_prepare, 1845 .trigger = snd_cmipci_capture_trigger, 1846 .pointer = snd_cmipci_capture_pointer, 1847}; 1848 1849static struct snd_pcm_ops snd_cmipci_playback2_ops = { 1850 .open = snd_cmipci_playback2_open, 1851 .close = snd_cmipci_playback2_close, 1852 .ioctl = snd_pcm_lib_ioctl, 1853 .hw_params = snd_cmipci_playback2_hw_params, 1854 .hw_free = snd_cmipci_playback2_hw_free, 1855 .prepare = snd_cmipci_capture_prepare, /* channel B */ 1856 .trigger = snd_cmipci_capture_trigger, /* channel B */ 1857 .pointer = snd_cmipci_capture_pointer, /* channel B */ 1858}; 1859 1860static struct snd_pcm_ops snd_cmipci_playback_spdif_ops = { 1861 .open = snd_cmipci_playback_spdif_open, 1862 .close = snd_cmipci_playback_spdif_close, 1863 .ioctl = snd_pcm_lib_ioctl, 1864 .hw_params = snd_cmipci_hw_params, 1865 .hw_free = snd_cmipci_playback_hw_free, 1866 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */ 1867 .trigger = snd_cmipci_playback_trigger, 1868 .pointer = snd_cmipci_playback_pointer, 1869}; 1870 1871static struct snd_pcm_ops snd_cmipci_capture_spdif_ops = { 1872 .open = snd_cmipci_capture_spdif_open, 1873 .close = snd_cmipci_capture_spdif_close, 1874 .ioctl = snd_pcm_lib_ioctl, 1875 .hw_params = snd_cmipci_hw_params, 1876 .hw_free = snd_cmipci_capture_spdif_hw_free, 1877 .prepare = snd_cmipci_capture_spdif_prepare, 1878 .trigger = snd_cmipci_capture_trigger, 1879 .pointer = snd_cmipci_capture_pointer, 1880}; 1881 1882 1883/* 1884 */ 1885 1886static int __devinit snd_cmipci_pcm_new(struct cmipci *cm, int device) 1887{ 1888 struct snd_pcm *pcm; 1889 int err; 1890 1891 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); 1892 if (err < 0) 1893 return err; 1894 1895 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops); 1896 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops); 1897 1898 pcm->private_data = cm; 1899 pcm->info_flags = 0; 1900 strcpy(pcm->name, "C-Media PCI DAC/ADC"); 1901 cm->pcm = pcm; 1902 1903 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1904 snd_dma_pci_data(cm->pci), 64*1024, 128*1024); 1905 1906 return 0; 1907} 1908 1909static int __devinit snd_cmipci_pcm2_new(struct cmipci *cm, int device) 1910{ 1911 struct snd_pcm *pcm; 1912 int err; 1913 1914 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm); 1915 if (err < 0) 1916 return err; 1917 1918 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops); 1919 1920 pcm->private_data = cm; 1921 pcm->info_flags = 0; 1922 strcpy(pcm->name, "C-Media PCI 2nd DAC"); 1923 cm->pcm2 = pcm; 1924 1925 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1926 snd_dma_pci_data(cm->pci), 64*1024, 128*1024); 1927 1928 return 0; 1929} 1930 1931static int __devinit snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device) 1932{ 1933 struct snd_pcm *pcm; 1934 int err; 1935 1936 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); 1937 if (err < 0) 1938 return err; 1939 1940 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops); 1941 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops); 1942 1943 pcm->private_data = cm; 1944 pcm->info_flags = 0; 1945 strcpy(pcm->name, "C-Media PCI IEC958"); 1946 cm->pcm_spdif = pcm; 1947 1948 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1949 snd_dma_pci_data(cm->pci), 64*1024, 128*1024); 1950 1951 return 0; 1952} 1953 1954/* 1955 * mixer interface: 1956 * - CM8338/8738 has a compatible mixer interface with SB16, but 1957 * lack of some elements like tone control, i/o gain and AGC. 1958 * - Access to native registers: 1959 * - A 3D switch 1960 * - Output mute switches 1961 */ 1962 1963static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data) 1964{ 1965 outb(idx, s->iobase + CM_REG_SB16_ADDR); 1966 outb(data, s->iobase + CM_REG_SB16_DATA); 1967} 1968 1969static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx) 1970{ 1971 unsigned char v; 1972 1973 outb(idx, s->iobase + CM_REG_SB16_ADDR); 1974 v = inb(s->iobase + CM_REG_SB16_DATA); 1975 return v; 1976} 1977 1978/* 1979 * general mixer element 1980 */ 1981struct cmipci_sb_reg { 1982 unsigned int left_reg, right_reg; 1983 unsigned int left_shift, right_shift; 1984 unsigned int mask; 1985 unsigned int invert: 1; 1986 unsigned int stereo: 1; 1987}; 1988 1989#define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \ 1990 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23)) 1991 1992#define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \ 1993{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1994 .info = snd_cmipci_info_volume, \ 1995 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \ 1996 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \ 1997} 1998 1999#define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1) 2000#define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0) 2001#define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1) 2002#define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0) 2003 2004static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val) 2005{ 2006 r->left_reg = val & 0xff; 2007 r->right_reg = (val >> 8) & 0xff; 2008 r->left_shift = (val >> 16) & 0x07; 2009 r->right_shift = (val >> 19) & 0x07; 2010 r->invert = (val >> 22) & 1; 2011 r->stereo = (val >> 23) & 1; 2012 r->mask = (val >> 24) & 0xff; 2013} 2014 2015static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol, 2016 struct snd_ctl_elem_info *uinfo) 2017{ 2018 struct cmipci_sb_reg reg; 2019 2020 cmipci_sb_reg_decode(®, kcontrol->private_value); 2021 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 2022 uinfo->count = reg.stereo + 1; 2023 uinfo->value.integer.min = 0; 2024 uinfo->value.integer.max = reg.mask; 2025 return 0; 2026} 2027 2028static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol, 2029 struct snd_ctl_elem_value *ucontrol) 2030{ 2031 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2032 struct cmipci_sb_reg reg; 2033 int val; 2034 2035 cmipci_sb_reg_decode(®, kcontrol->private_value); 2036 spin_lock_irq(&cm->reg_lock); 2037 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask; 2038 if (reg.invert) 2039 val = reg.mask - val; 2040 ucontrol->value.integer.value[0] = val; 2041 if (reg.stereo) { 2042 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask; 2043 if (reg.invert) 2044 val = reg.mask - val; 2045 ucontrol->value.integer.value[1] = val; 2046 } 2047 spin_unlock_irq(&cm->reg_lock); 2048 return 0; 2049} 2050 2051static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol, 2052 struct snd_ctl_elem_value *ucontrol) 2053{ 2054 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2055 struct cmipci_sb_reg reg; 2056 int change; 2057 int left, right, oleft, oright; 2058 2059 cmipci_sb_reg_decode(®, kcontrol->private_value); 2060 left = ucontrol->value.integer.value[0] & reg.mask; 2061 if (reg.invert) 2062 left = reg.mask - left; 2063 left <<= reg.left_shift; 2064 if (reg.stereo) { 2065 right = ucontrol->value.integer.value[1] & reg.mask; 2066 if (reg.invert) 2067 right = reg.mask - right; 2068 right <<= reg.right_shift; 2069 } else 2070 right = 0; 2071 spin_lock_irq(&cm->reg_lock); 2072 oleft = snd_cmipci_mixer_read(cm, reg.left_reg); 2073 left |= oleft & ~(reg.mask << reg.left_shift); 2074 change = left != oleft; 2075 if (reg.stereo) { 2076 if (reg.left_reg != reg.right_reg) { 2077 snd_cmipci_mixer_write(cm, reg.left_reg, left); 2078 oright = snd_cmipci_mixer_read(cm, reg.right_reg); 2079 } else 2080 oright = left; 2081 right |= oright & ~(reg.mask << reg.right_shift); 2082 change |= right != oright; 2083 snd_cmipci_mixer_write(cm, reg.right_reg, right); 2084 } else 2085 snd_cmipci_mixer_write(cm, reg.left_reg, left); 2086 spin_unlock_irq(&cm->reg_lock); 2087 return change; 2088} 2089 2090/* 2091 * input route (left,right) -> (left,right) 2092 */ 2093#define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \ 2094{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2095 .info = snd_cmipci_info_input_sw, \ 2096 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \ 2097 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \ 2098} 2099 2100static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol, 2101 struct snd_ctl_elem_info *uinfo) 2102{ 2103 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2104 uinfo->count = 4; 2105 uinfo->value.integer.min = 0; 2106 uinfo->value.integer.max = 1; 2107 return 0; 2108} 2109 2110static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol, 2111 struct snd_ctl_elem_value *ucontrol) 2112{ 2113 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2114 struct cmipci_sb_reg reg; 2115 int val1, val2; 2116 2117 cmipci_sb_reg_decode(®, kcontrol->private_value); 2118 spin_lock_irq(&cm->reg_lock); 2119 val1 = snd_cmipci_mixer_read(cm, reg.left_reg); 2120 val2 = snd_cmipci_mixer_read(cm, reg.right_reg); 2121 spin_unlock_irq(&cm->reg_lock); 2122 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1; 2123 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1; 2124 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1; 2125 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1; 2126 return 0; 2127} 2128 2129static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol, 2130 struct snd_ctl_elem_value *ucontrol) 2131{ 2132 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2133 struct cmipci_sb_reg reg; 2134 int change; 2135 int val1, val2, oval1, oval2; 2136 2137 cmipci_sb_reg_decode(®, kcontrol->private_value); 2138 spin_lock_irq(&cm->reg_lock); 2139 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg); 2140 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg); 2141 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); 2142 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); 2143 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift; 2144 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift; 2145 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift; 2146 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift; 2147 change = val1 != oval1 || val2 != oval2; 2148 snd_cmipci_mixer_write(cm, reg.left_reg, val1); 2149 snd_cmipci_mixer_write(cm, reg.right_reg, val2); 2150 spin_unlock_irq(&cm->reg_lock); 2151 return change; 2152} 2153 2154/* 2155 * native mixer switches/volumes 2156 */ 2157 2158#define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \ 2159{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2160 .info = snd_cmipci_info_native_mixer, \ 2161 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 2162 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \ 2163} 2164 2165#define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \ 2166{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2167 .info = snd_cmipci_info_native_mixer, \ 2168 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 2169 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \ 2170} 2171 2172#define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \ 2173{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2174 .info = snd_cmipci_info_native_mixer, \ 2175 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 2176 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \ 2177} 2178 2179#define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \ 2180{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2181 .info = snd_cmipci_info_native_mixer, \ 2182 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 2183 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \ 2184} 2185 2186static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol, 2187 struct snd_ctl_elem_info *uinfo) 2188{ 2189 struct cmipci_sb_reg reg; 2190 2191 cmipci_sb_reg_decode(®, kcontrol->private_value); 2192 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 2193 uinfo->count = reg.stereo + 1; 2194 uinfo->value.integer.min = 0; 2195 uinfo->value.integer.max = reg.mask; 2196 return 0; 2197 2198} 2199 2200static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol, 2201 struct snd_ctl_elem_value *ucontrol) 2202{ 2203 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2204 struct cmipci_sb_reg reg; 2205 unsigned char oreg, val; 2206 2207 cmipci_sb_reg_decode(®, kcontrol->private_value); 2208 spin_lock_irq(&cm->reg_lock); 2209 oreg = inb(cm->iobase + reg.left_reg); 2210 val = (oreg >> reg.left_shift) & reg.mask; 2211 if (reg.invert) 2212 val = reg.mask - val; 2213 ucontrol->value.integer.value[0] = val; 2214 if (reg.stereo) { 2215 val = (oreg >> reg.right_shift) & reg.mask; 2216 if (reg.invert) 2217 val = reg.mask - val; 2218 ucontrol->value.integer.value[1] = val; 2219 } 2220 spin_unlock_irq(&cm->reg_lock); 2221 return 0; 2222} 2223 2224static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol, 2225 struct snd_ctl_elem_value *ucontrol) 2226{ 2227 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2228 struct cmipci_sb_reg reg; 2229 unsigned char oreg, nreg, val; 2230 2231 cmipci_sb_reg_decode(®, kcontrol->private_value); 2232 spin_lock_irq(&cm->reg_lock); 2233 oreg = inb(cm->iobase + reg.left_reg); 2234 val = ucontrol->value.integer.value[0] & reg.mask; 2235 if (reg.invert) 2236 val = reg.mask - val; 2237 nreg = oreg & ~(reg.mask << reg.left_shift); 2238 nreg |= (val << reg.left_shift); 2239 if (reg.stereo) { 2240 val = ucontrol->value.integer.value[1] & reg.mask; 2241 if (reg.invert) 2242 val = reg.mask - val; 2243 nreg &= ~(reg.mask << reg.right_shift); 2244 nreg |= (val << reg.right_shift); 2245 } 2246 outb(nreg, cm->iobase + reg.left_reg); 2247 spin_unlock_irq(&cm->reg_lock); 2248 return (nreg != oreg); 2249} 2250 2251/* 2252 * special case - check mixer sensitivity 2253 */ 2254static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol, 2255 struct snd_ctl_elem_value *ucontrol) 2256{ 2257 //struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2258 return snd_cmipci_get_native_mixer(kcontrol, ucontrol); 2259} 2260 2261static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol, 2262 struct snd_ctl_elem_value *ucontrol) 2263{ 2264 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2265 if (cm->mixer_insensitive) { 2266 /* ignored */ 2267 return 0; 2268 } 2269 return snd_cmipci_put_native_mixer(kcontrol, ucontrol); 2270} 2271 2272 2273static struct snd_kcontrol_new snd_cmipci_mixers[] __devinitdata = { 2274 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31), 2275 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0), 2276 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31), 2277 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1), 2278 { /* switch with sensitivity */ 2279 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2280 .name = "PCM Playback Switch", 2281 .info = snd_cmipci_info_native_mixer, 2282 .get = snd_cmipci_get_native_mixer_sensitive, 2283 .put = snd_cmipci_put_native_mixer_sensitive, 2284 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0), 2285 }, 2286 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0), 2287 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31), 2288 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1), 2289 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5), 2290 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31), 2291 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1), 2292 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1), 2293 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31), 2294 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3), 2295 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3), 2296 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31), 2297 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0), 2298 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0), 2299 CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3), 2300 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15), 2301 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0), 2302 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0), 2303 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1), 2304 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7), 2305 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7), 2306 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0), 2307 CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0), 2308 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0), 2309}; 2310 2311/* 2312 * other switches 2313 */ 2314 2315struct cmipci_switch_args { 2316 int reg; /* register index */ 2317 unsigned int mask; /* mask bits */ 2318 unsigned int mask_on; /* mask bits to turn on */ 2319 unsigned int is_byte: 1; /* byte access? */ 2320 unsigned int ac3_sensitive: 1; /* access forbidden during 2321 * non-audio operation? 2322 */ 2323}; 2324 2325#define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info 2326 2327static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol, 2328 struct snd_ctl_elem_value *ucontrol, 2329 struct cmipci_switch_args *args) 2330{ 2331 unsigned int val; 2332 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2333 2334 spin_lock_irq(&cm->reg_lock); 2335 if (args->ac3_sensitive && cm->mixer_insensitive) { 2336 ucontrol->value.integer.value[0] = 0; 2337 spin_unlock_irq(&cm->reg_lock); 2338 return 0; 2339 } 2340 if (args->is_byte) 2341 val = inb(cm->iobase + args->reg); 2342 else 2343 val = snd_cmipci_read(cm, args->reg); 2344 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0; 2345 spin_unlock_irq(&cm->reg_lock); 2346 return 0; 2347} 2348 2349static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol, 2350 struct snd_ctl_elem_value *ucontrol) 2351{ 2352 struct cmipci_switch_args *args; 2353 args = (struct cmipci_switch_args *)kcontrol->private_value; 2354 if (snd_BUG_ON(!args)) 2355 return -EINVAL; 2356 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args); 2357} 2358 2359static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol, 2360 struct snd_ctl_elem_value *ucontrol, 2361 struct cmipci_switch_args *args) 2362{ 2363 unsigned int val; 2364 int change; 2365 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2366 2367 spin_lock_irq(&cm->reg_lock); 2368 if (args->ac3_sensitive && cm->mixer_insensitive) { 2369 /* ignored */ 2370 spin_unlock_irq(&cm->reg_lock); 2371 return 0; 2372 } 2373 if (args->is_byte) 2374 val = inb(cm->iobase + args->reg); 2375 else 2376 val = snd_cmipci_read(cm, args->reg); 2377 change = (val & args->mask) != (ucontrol->value.integer.value[0] ? 2378 args->mask_on : (args->mask & ~args->mask_on)); 2379 if (change) { 2380 val &= ~args->mask; 2381 if (ucontrol->value.integer.value[0]) 2382 val |= args->mask_on; 2383 else 2384 val |= (args->mask & ~args->mask_on); 2385 if (args->is_byte) 2386 outb((unsigned char)val, cm->iobase + args->reg); 2387 else 2388 snd_cmipci_write(cm, args->reg, val); 2389 } 2390 spin_unlock_irq(&cm->reg_lock); 2391 return change; 2392} 2393 2394static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol, 2395 struct snd_ctl_elem_value *ucontrol) 2396{ 2397 struct cmipci_switch_args *args; 2398 args = (struct cmipci_switch_args *)kcontrol->private_value; 2399 if (snd_BUG_ON(!args)) 2400 return -EINVAL; 2401 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args); 2402} 2403 2404#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \ 2405static struct cmipci_switch_args cmipci_switch_arg_##sname = { \ 2406 .reg = xreg, \ 2407 .mask = xmask, \ 2408 .mask_on = xmask_on, \ 2409 .is_byte = xis_byte, \ 2410 .ac3_sensitive = xac3, \ 2411} 2412 2413#define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \ 2414 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3) 2415 2416DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0); 2417DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0); 2418DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0); 2419DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1); 2420DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0); 2421DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0); 2422DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1); 2423DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */ 2424// DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1); 2425DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1); 2426DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0); 2427/* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */ 2428DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0); 2429DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0); 2430#if CM_CH_PLAY == 1 2431DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */ 2432#else 2433DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0); 2434#endif 2435DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0); 2436// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0); 2437// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0); 2438// DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */ 2439DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0); 2440 2441#define DEFINE_SWITCH(sname, stype, sarg) \ 2442{ .name = sname, \ 2443 .iface = stype, \ 2444 .info = snd_cmipci_uswitch_info, \ 2445 .get = snd_cmipci_uswitch_get, \ 2446 .put = snd_cmipci_uswitch_put, \ 2447 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\ 2448} 2449 2450#define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg) 2451#define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg) 2452 2453 2454/* 2455 * callbacks for spdif output switch 2456 * needs toggle two registers.. 2457 */ 2458static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol, 2459 struct snd_ctl_elem_value *ucontrol) 2460{ 2461 int changed; 2462 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); 2463 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); 2464 return changed; 2465} 2466 2467static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol, 2468 struct snd_ctl_elem_value *ucontrol) 2469{ 2470 struct cmipci *chip = snd_kcontrol_chip(kcontrol); 2471 int changed; 2472 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); 2473 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); 2474 if (changed) { 2475 if (ucontrol->value.integer.value[0]) { 2476 if (chip->spdif_playback_avail) 2477 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 2478 } else { 2479 if (chip->spdif_playback_avail) 2480 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 2481 } 2482 } 2483 chip->spdif_playback_enabled = ucontrol->value.integer.value[0]; 2484 return changed; 2485} 2486 2487 2488static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol, 2489 struct snd_ctl_elem_info *uinfo) 2490{ 2491 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2492 static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" }; 2493 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2494 uinfo->count = 1; 2495 uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2; 2496 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2497 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2498 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2499 return 0; 2500} 2501 2502static inline unsigned int get_line_in_mode(struct cmipci *cm) 2503{ 2504 unsigned int val; 2505 if (cm->chip_version >= 39) { 2506 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL); 2507 if (val & (CM_CENTR2LIN | CM_BASE2LIN)) 2508 return 2; 2509 } 2510 val = snd_cmipci_read_b(cm, CM_REG_MIXER1); 2511 if (val & CM_REAR2LIN) 2512 return 1; 2513 return 0; 2514} 2515 2516static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol, 2517 struct snd_ctl_elem_value *ucontrol) 2518{ 2519 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2520 2521 spin_lock_irq(&cm->reg_lock); 2522 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm); 2523 spin_unlock_irq(&cm->reg_lock); 2524 return 0; 2525} 2526 2527static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol, 2528 struct snd_ctl_elem_value *ucontrol) 2529{ 2530 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2531 int change; 2532 2533 spin_lock_irq(&cm->reg_lock); 2534 if (ucontrol->value.enumerated.item[0] == 2) 2535 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN); 2536 else 2537 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN); 2538 if (ucontrol->value.enumerated.item[0] == 1) 2539 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN); 2540 else 2541 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN); 2542 spin_unlock_irq(&cm->reg_lock); 2543 return change; 2544} 2545 2546static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol, 2547 struct snd_ctl_elem_info *uinfo) 2548{ 2549 static char *texts[2] = { "Mic-In", "Center/LFE Output" }; 2550 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2551 uinfo->count = 1; 2552 uinfo->value.enumerated.items = 2; 2553 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2554 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2555 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2556 return 0; 2557} 2558 2559static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol, 2560 struct snd_ctl_elem_value *ucontrol) 2561{ 2562 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2563 /* same bit as spdi_phase */ 2564 spin_lock_irq(&cm->reg_lock); 2565 ucontrol->value.enumerated.item[0] = 2566 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0; 2567 spin_unlock_irq(&cm->reg_lock); 2568 return 0; 2569} 2570 2571static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol, 2572 struct snd_ctl_elem_value *ucontrol) 2573{ 2574 struct cmipci *cm = snd_kcontrol_chip(kcontrol); 2575 int change; 2576 2577 spin_lock_irq(&cm->reg_lock); 2578 if (ucontrol->value.enumerated.item[0]) 2579 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE); 2580 else 2581 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE); 2582 spin_unlock_irq(&cm->reg_lock); 2583 return change; 2584} 2585 2586/* both for CM8338/8738 */ 2587static struct snd_kcontrol_new snd_cmipci_mixer_switches[] __devinitdata = { 2588 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch), 2589 { 2590 .name = "Line-In Mode", 2591 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2592 .info = snd_cmipci_line_in_mode_info, 2593 .get = snd_cmipci_line_in_mode_get, 2594 .put = snd_cmipci_line_in_mode_put, 2595 }, 2596}; 2597 2598/* for non-multichannel chips */ 2599static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata = 2600DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac); 2601 2602/* only for CM8738 */ 2603static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] __devinitdata = { 2604 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable), 2605 { .name = "IEC958 Output Switch", 2606 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2607 .info = snd_cmipci_uswitch_info, 2608 .get = snd_cmipci_spdout_enable_get, 2609 .put = snd_cmipci_spdout_enable_put, 2610 }, 2611 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid), 2612 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright), 2613 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v), 2614// DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k), 2615 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop), 2616 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor), 2617}; 2618 2619/* only for model 033/037 */ 2620static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] __devinitdata = { 2621 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out), 2622 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase), 2623 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1), 2624}; 2625 2626/* only for model 039 or later */ 2627static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] __devinitdata = { 2628 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2), 2629 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2), 2630 { 2631 .name = "Mic-In Mode", 2632 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2633 .info = snd_cmipci_mic_in_mode_info, 2634 .get = snd_cmipci_mic_in_mode_get, 2635 .put = snd_cmipci_mic_in_mode_put, 2636 } 2637}; 2638 2639/* card control switches */ 2640static struct snd_kcontrol_new snd_cmipci_modem_switch __devinitdata = 2641DEFINE_CARD_SWITCH("Modem", modem); 2642 2643 2644static int __devinit snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device) 2645{ 2646 struct snd_card *card; 2647 struct snd_kcontrol_new *sw; 2648 struct snd_kcontrol *kctl; 2649 unsigned int idx; 2650 int err; 2651 2652 if (snd_BUG_ON(!cm || !cm->card)) 2653 return -EINVAL; 2654 2655 card = cm->card; 2656 2657 strcpy(card->mixername, "CMedia PCI"); 2658 2659 spin_lock_irq(&cm->reg_lock); 2660 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */ 2661 spin_unlock_irq(&cm->reg_lock); 2662 2663 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) { 2664 if (cm->chip_version == 68) { // 8768 has no PCM volume 2665 if (!strcmp(snd_cmipci_mixers[idx].name, 2666 "PCM Playback Volume")) 2667 continue; 2668 } 2669 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0) 2670 return err; 2671 } 2672 2673 /* mixer switches */ 2674 sw = snd_cmipci_mixer_switches; 2675 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) { 2676 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2677 if (err < 0) 2678 return err; 2679 } 2680 if (! cm->can_multi_ch) { 2681 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm)); 2682 if (err < 0) 2683 return err; 2684 } 2685 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 || 2686 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) { 2687 sw = snd_cmipci_8738_mixer_switches; 2688 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) { 2689 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2690 if (err < 0) 2691 return err; 2692 } 2693 if (cm->can_ac3_hw) { 2694 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0) 2695 return err; 2696 kctl->id.device = pcm_spdif_device; 2697 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0) 2698 return err; 2699 kctl->id.device = pcm_spdif_device; 2700 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0) 2701 return err; 2702 kctl->id.device = pcm_spdif_device; 2703 } 2704 if (cm->chip_version <= 37) { 2705 sw = snd_cmipci_old_mixer_switches; 2706 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) { 2707 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2708 if (err < 0) 2709 return err; 2710 } 2711 } 2712 } 2713 if (cm->chip_version >= 39) { 2714 sw = snd_cmipci_extra_mixer_switches; 2715 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) { 2716 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2717 if (err < 0) 2718 return err; 2719 } 2720 } 2721 2722 /* card switches */ 2723 /* 2724 * newer chips don't have the register bits to force modem link 2725 * detection; the bit that was FLINKON now mutes CH1 2726 */ 2727 if (cm->chip_version < 39) { 2728 err = snd_ctl_add(cm->card, 2729 snd_ctl_new1(&snd_cmipci_modem_switch, cm)); 2730 if (err < 0) 2731 return err; 2732 } 2733 2734 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) { 2735 struct snd_ctl_elem_id elem_id; 2736 struct snd_kcontrol *ctl; 2737 memset(&elem_id, 0, sizeof(elem_id)); 2738 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2739 strcpy(elem_id.name, cm_saved_mixer[idx].name); 2740 ctl = snd_ctl_find_id(cm->card, &elem_id); 2741 if (ctl) 2742 cm->mixer_res_ctl[idx] = ctl; 2743 } 2744 2745 return 0; 2746} 2747 2748 2749/* 2750 * proc interface 2751 */ 2752 2753#ifdef CONFIG_PROC_FS 2754static void snd_cmipci_proc_read(struct snd_info_entry *entry, 2755 struct snd_info_buffer *buffer) 2756{ 2757 struct cmipci *cm = entry->private_data; 2758 int i, v; 2759 2760 snd_iprintf(buffer, "%s\n", cm->card->longname); 2761 for (i = 0; i < 0x94; i++) { 2762 if (i == 0x28) 2763 i = 0x90; 2764 v = inb(cm->iobase + i); 2765 if (i % 4 == 0) 2766 snd_iprintf(buffer, "\n%02x:", i); 2767 snd_iprintf(buffer, " %02x", v); 2768 } 2769 snd_iprintf(buffer, "\n"); 2770} 2771 2772static void __devinit snd_cmipci_proc_init(struct cmipci *cm) 2773{ 2774 struct snd_info_entry *entry; 2775 2776 if (! snd_card_proc_new(cm->card, "cmipci", &entry)) 2777 snd_info_set_text_ops(entry, cm, snd_cmipci_proc_read); 2778} 2779#else /* !CONFIG_PROC_FS */ 2780static inline void snd_cmipci_proc_init(struct cmipci *cm) {} 2781#endif 2782 2783 2784static DEFINE_PCI_DEVICE_TABLE(snd_cmipci_ids) = { 2785 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0}, 2786 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0}, 2787 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0}, 2788 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0}, 2789 {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0}, 2790 {0,}, 2791}; 2792 2793 2794/* 2795 * check chip version and capabilities 2796 * driver name is modified according to the chip model 2797 */ 2798static void __devinit query_chip(struct cmipci *cm) 2799{ 2800 unsigned int detect; 2801 2802 /* check reg 0Ch, bit 24-31 */ 2803 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2; 2804 if (! detect) { 2805 /* check reg 08h, bit 24-28 */ 2806 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1; 2807 switch (detect) { 2808 case 0: 2809 cm->chip_version = 33; 2810 if (cm->do_soft_ac3) 2811 cm->can_ac3_sw = 1; 2812 else 2813 cm->can_ac3_hw = 1; 2814 break; 2815 case CM_CHIP_037: 2816 cm->chip_version = 37; 2817 cm->can_ac3_hw = 1; 2818 break; 2819 default: 2820 cm->chip_version = 39; 2821 cm->can_ac3_hw = 1; 2822 break; 2823 } 2824 cm->max_channels = 2; 2825 } else { 2826 if (detect & CM_CHIP_039) { 2827 cm->chip_version = 39; 2828 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */ 2829 cm->max_channels = 6; 2830 else 2831 cm->max_channels = 4; 2832 } else if (detect & CM_CHIP_8768) { 2833 cm->chip_version = 68; 2834 cm->max_channels = 8; 2835 cm->can_96k = 1; 2836 } else { 2837 cm->chip_version = 55; 2838 cm->max_channels = 6; 2839 cm->can_96k = 1; 2840 } 2841 cm->can_ac3_hw = 1; 2842 cm->can_multi_ch = 1; 2843 } 2844} 2845 2846#ifdef SUPPORT_JOYSTICK 2847static int __devinit snd_cmipci_create_gameport(struct cmipci *cm, int dev) 2848{ 2849 static int ports[] = { 0x201, 0x200, 0 }; 2850 struct gameport *gp; 2851 struct resource *r = NULL; 2852 int i, io_port = 0; 2853 2854 if (joystick_port[dev] == 0) 2855 return -ENODEV; 2856 2857 if (joystick_port[dev] == 1) { /* auto-detect */ 2858 for (i = 0; ports[i]; i++) { 2859 io_port = ports[i]; 2860 r = request_region(io_port, 1, "CMIPCI gameport"); 2861 if (r) 2862 break; 2863 } 2864 } else { 2865 io_port = joystick_port[dev]; 2866 r = request_region(io_port, 1, "CMIPCI gameport"); 2867 } 2868 2869 if (!r) { 2870 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n"); 2871 return -EBUSY; 2872 } 2873 2874 cm->gameport = gp = gameport_allocate_port(); 2875 if (!gp) { 2876 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n"); 2877 release_and_free_resource(r); 2878 return -ENOMEM; 2879 } 2880 gameport_set_name(gp, "C-Media Gameport"); 2881 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci)); 2882 gameport_set_dev_parent(gp, &cm->pci->dev); 2883 gp->io = io_port; 2884 gameport_set_port_data(gp, r); 2885 2886 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); 2887 2888 gameport_register_port(cm->gameport); 2889 2890 return 0; 2891} 2892 2893static void snd_cmipci_free_gameport(struct cmipci *cm) 2894{ 2895 if (cm->gameport) { 2896 struct resource *r = gameport_get_port_data(cm->gameport); 2897 2898 gameport_unregister_port(cm->gameport); 2899 cm->gameport = NULL; 2900 2901 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); 2902 release_and_free_resource(r); 2903 } 2904} 2905#else 2906static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; } 2907static inline void snd_cmipci_free_gameport(struct cmipci *cm) { } 2908#endif 2909 2910static int snd_cmipci_free(struct cmipci *cm) 2911{ 2912 if (cm->irq >= 0) { 2913 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); 2914 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); 2915 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ 2916 snd_cmipci_ch_reset(cm, CM_CH_PLAY); 2917 snd_cmipci_ch_reset(cm, CM_CH_CAPT); 2918 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ 2919 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); 2920 2921 /* reset mixer */ 2922 snd_cmipci_mixer_write(cm, 0, 0); 2923 2924 free_irq(cm->irq, cm); 2925 } 2926 2927 snd_cmipci_free_gameport(cm); 2928 pci_release_regions(cm->pci); 2929 pci_disable_device(cm->pci); 2930 kfree(cm); 2931 return 0; 2932} 2933 2934static int snd_cmipci_dev_free(struct snd_device *device) 2935{ 2936 struct cmipci *cm = device->device_data; 2937 return snd_cmipci_free(cm); 2938} 2939 2940static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port) 2941{ 2942 long iosynth; 2943 unsigned int val; 2944 struct snd_opl3 *opl3; 2945 int err; 2946 2947 if (!fm_port) 2948 goto disable_fm; 2949 2950 if (cm->chip_version >= 39) { 2951 /* first try FM regs in PCI port range */ 2952 iosynth = cm->iobase + CM_REG_FM_PCI; 2953 err = snd_opl3_create(cm->card, iosynth, iosynth + 2, 2954 OPL3_HW_OPL3, 1, &opl3); 2955 } else { 2956 err = -EIO; 2957 } 2958 if (err < 0) { 2959 /* then try legacy ports */ 2960 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK; 2961 iosynth = fm_port; 2962 switch (iosynth) { 2963 case 0x3E8: val |= CM_FMSEL_3E8; break; 2964 case 0x3E0: val |= CM_FMSEL_3E0; break; 2965 case 0x3C8: val |= CM_FMSEL_3C8; break; 2966 case 0x388: val |= CM_FMSEL_388; break; 2967 default: 2968 goto disable_fm; 2969 } 2970 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); 2971 /* enable FM */ 2972 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); 2973 2974 if (snd_opl3_create(cm->card, iosynth, iosynth + 2, 2975 OPL3_HW_OPL3, 0, &opl3) < 0) { 2976 printk(KERN_ERR "cmipci: no OPL device at %#lx, " 2977 "skipping...\n", iosynth); 2978 goto disable_fm; 2979 } 2980 } 2981 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) { 2982 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n"); 2983 return err; 2984 } 2985 return 0; 2986 2987 disable_fm: 2988 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK); 2989 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); 2990 return 0; 2991} 2992 2993static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pci, 2994 int dev, struct cmipci **rcmipci) 2995{ 2996 struct cmipci *cm; 2997 int err; 2998 static struct snd_device_ops ops = { 2999 .dev_free = snd_cmipci_dev_free, 3000 }; 3001 unsigned int val; 3002 long iomidi = 0; 3003 int integrated_midi = 0; 3004 char modelstr[16]; 3005 int pcm_index, pcm_spdif_index; 3006 static DEFINE_PCI_DEVICE_TABLE(intel_82437vx) = { 3007 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) }, 3008 { }, 3009 }; 3010 3011 *rcmipci = NULL; 3012 3013 if ((err = pci_enable_device(pci)) < 0) 3014 return err; 3015 3016 cm = kzalloc(sizeof(*cm), GFP_KERNEL); 3017 if (cm == NULL) { 3018 pci_disable_device(pci); 3019 return -ENOMEM; 3020 } 3021 3022 spin_lock_init(&cm->reg_lock); 3023 mutex_init(&cm->open_mutex); 3024 cm->device = pci->device; 3025 cm->card = card; 3026 cm->pci = pci; 3027 cm->irq = -1; 3028 cm->channel[0].ch = 0; 3029 cm->channel[1].ch = 1; 3030 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */ 3031 3032 if ((err = pci_request_regions(pci, card->driver)) < 0) { 3033 kfree(cm); 3034 pci_disable_device(pci); 3035 return err; 3036 } 3037 cm->iobase = pci_resource_start(pci, 0); 3038 3039 if (request_irq(pci->irq, snd_cmipci_interrupt, 3040 IRQF_SHARED, card->driver, cm)) { 3041 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 3042 snd_cmipci_free(cm); 3043 return -EBUSY; 3044 } 3045 cm->irq = pci->irq; 3046 3047 pci_set_master(cm->pci); 3048 3049 /* 3050 * check chip version, max channels and capabilities 3051 */ 3052 3053 cm->chip_version = 0; 3054 cm->max_channels = 2; 3055 cm->do_soft_ac3 = soft_ac3[dev]; 3056 3057 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A && 3058 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B) 3059 query_chip(cm); 3060 /* added -MCx suffix for chip supporting multi-channels */ 3061 if (cm->can_multi_ch) 3062 sprintf(cm->card->driver + strlen(cm->card->driver), 3063 "-MC%d", cm->max_channels); 3064 else if (cm->can_ac3_sw) 3065 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC"); 3066 3067 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF; 3068 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF; 3069 3070#if CM_CH_PLAY == 1 3071 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */ 3072#else 3073 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */ 3074#endif 3075 3076 /* initialize codec registers */ 3077 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET); 3078 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET); 3079 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ 3080 snd_cmipci_ch_reset(cm, CM_CH_PLAY); 3081 snd_cmipci_ch_reset(cm, CM_CH_CAPT); 3082 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ 3083 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); 3084 3085 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0); 3086 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D); 3087#if CM_CH_PLAY == 1 3088 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 3089#else 3090 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 3091#endif 3092 if (cm->chip_version) { 3093 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */ 3094 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */ 3095 } 3096 /* Set Bus Master Request */ 3097 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ); 3098 3099 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */ 3100 switch (pci->device) { 3101 case PCI_DEVICE_ID_CMEDIA_CM8738: 3102 case PCI_DEVICE_ID_CMEDIA_CM8738B: 3103 if (!pci_dev_present(intel_82437vx)) 3104 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX); 3105 break; 3106 default: 3107 break; 3108 } 3109 3110 if (cm->chip_version < 68) { 3111 val = pci->device < 0x110 ? 8338 : 8738; 3112 } else { 3113 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) { 3114 case 0: 3115 val = 8769; 3116 break; 3117 case 2: 3118 val = 8762; 3119 break; 3120 default: 3121 switch ((pci->subsystem_vendor << 16) | 3122 pci->subsystem_device) { 3123 case 0x13f69761: 3124 case 0x584d3741: 3125 case 0x584d3751: 3126 case 0x584d3761: 3127 case 0x584d3771: 3128 case 0x72848384: 3129 val = 8770; 3130 break; 3131 default: 3132 val = 8768; 3133 break; 3134 } 3135 } 3136 } 3137 sprintf(card->shortname, "C-Media CMI%d", val); 3138 if (cm->chip_version < 68) 3139 sprintf(modelstr, " (model %d)", cm->chip_version); 3140 else 3141 modelstr[0] = '\0'; 3142 sprintf(card->longname, "%s%s at %#lx, irq %i", 3143 card->shortname, modelstr, cm->iobase, cm->irq); 3144 3145 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) { 3146 snd_cmipci_free(cm); 3147 return err; 3148 } 3149 3150 if (cm->chip_version >= 39) { 3151 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1); 3152 if (val != 0x00 && val != 0xff) { 3153 iomidi = cm->iobase + CM_REG_MPU_PCI; 3154 integrated_midi = 1; 3155 } 3156 } 3157 if (!integrated_midi) { 3158 val = 0; 3159 iomidi = mpu_port[dev]; 3160 switch (iomidi) { 3161 case 0x320: val = CM_VMPU_320; break; 3162 case 0x310: val = CM_VMPU_310; break; 3163 case 0x300: val = CM_VMPU_300; break; 3164 case 0x330: val = CM_VMPU_330; break; 3165 default: 3166 iomidi = 0; break; 3167 } 3168 if (iomidi > 0) { 3169 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); 3170 /* enable UART */ 3171 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN); 3172 if (inb(iomidi + 1) == 0xff) { 3173 snd_printk(KERN_ERR "cannot enable MPU-401 port" 3174 " at %#lx\n", iomidi); 3175 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, 3176 CM_UART_EN); 3177 iomidi = 0; 3178 } 3179 } 3180 } 3181 3182 if (cm->chip_version < 68) { 3183 err = snd_cmipci_create_fm(cm, fm_port[dev]); 3184 if (err < 0) 3185 return err; 3186 } 3187 3188 /* reset mixer */ 3189 snd_cmipci_mixer_write(cm, 0, 0); 3190 3191 snd_cmipci_proc_init(cm); 3192 3193 /* create pcm devices */ 3194 pcm_index = pcm_spdif_index = 0; 3195 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0) 3196 return err; 3197 pcm_index++; 3198 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0) 3199 return err; 3200 pcm_index++; 3201 if (cm->can_ac3_hw || cm->can_ac3_sw) { 3202 pcm_spdif_index = pcm_index; 3203 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0) 3204 return err; 3205 } 3206 3207 /* create mixer interface & switches */ 3208 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0) 3209 return err; 3210 3211 if (iomidi > 0) { 3212 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI, 3213 iomidi, 3214 (integrated_midi ? 3215 MPU401_INFO_INTEGRATED : 0), 3216 cm->irq, 0, &cm->rmidi)) < 0) { 3217 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi); 3218 } 3219 } 3220 3221#ifdef USE_VAR48KRATE 3222 for (val = 0; val < ARRAY_SIZE(rates); val++) 3223 snd_cmipci_set_pll(cm, rates[val], val); 3224 3225 /* 3226 * (Re-)Enable external switch spdo_48k 3227 */ 3228 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97); 3229#endif /* USE_VAR48KRATE */ 3230 3231 if (snd_cmipci_create_gameport(cm, dev) < 0) 3232 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); 3233 3234 snd_card_set_dev(card, &pci->dev); 3235 3236 *rcmipci = cm; 3237 return 0; 3238} 3239 3240/* 3241 */ 3242 3243MODULE_DEVICE_TABLE(pci, snd_cmipci_ids); 3244 3245static int __devinit snd_cmipci_probe(struct pci_dev *pci, 3246 const struct pci_device_id *pci_id) 3247{ 3248 static int dev; 3249 struct snd_card *card; 3250 struct cmipci *cm; 3251 int err; 3252 3253 if (dev >= SNDRV_CARDS) 3254 return -ENODEV; 3255 if (! enable[dev]) { 3256 dev++; 3257 return -ENOENT; 3258 } 3259 3260 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card); 3261 if (err < 0) 3262 return err; 3263 3264 switch (pci->device) { 3265 case PCI_DEVICE_ID_CMEDIA_CM8738: 3266 case PCI_DEVICE_ID_CMEDIA_CM8738B: 3267 strcpy(card->driver, "CMI8738"); 3268 break; 3269 case PCI_DEVICE_ID_CMEDIA_CM8338A: 3270 case PCI_DEVICE_ID_CMEDIA_CM8338B: 3271 strcpy(card->driver, "CMI8338"); 3272 break; 3273 default: 3274 strcpy(card->driver, "CMIPCI"); 3275 break; 3276 } 3277 3278 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) { 3279 snd_card_free(card); 3280 return err; 3281 } 3282 card->private_data = cm; 3283 3284 if ((err = snd_card_register(card)) < 0) { 3285 snd_card_free(card); 3286 return err; 3287 } 3288 pci_set_drvdata(pci, card); 3289 dev++; 3290 return 0; 3291 3292} 3293 3294static void __devexit snd_cmipci_remove(struct pci_dev *pci) 3295{ 3296 snd_card_free(pci_get_drvdata(pci)); 3297 pci_set_drvdata(pci, NULL); 3298} 3299 3300 3301#ifdef CONFIG_PM 3302/* 3303 * power management 3304 */ 3305static unsigned char saved_regs[] = { 3306 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL, 3307 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL, 3308 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2, 3309 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC, 3310 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0, 3311}; 3312 3313static unsigned char saved_mixers[] = { 3314 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1, 3315 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1, 3316 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1, 3317 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1, 3318 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1, 3319 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV, 3320 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW, 3321 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 3322}; 3323 3324static int snd_cmipci_suspend(struct pci_dev *pci, pm_message_t state) 3325{ 3326 struct snd_card *card = pci_get_drvdata(pci); 3327 struct cmipci *cm = card->private_data; 3328 int i; 3329 3330 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 3331 3332 snd_pcm_suspend_all(cm->pcm); 3333 snd_pcm_suspend_all(cm->pcm2); 3334 snd_pcm_suspend_all(cm->pcm_spdif); 3335 3336 /* save registers */ 3337 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3338 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]); 3339 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++) 3340 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]); 3341 3342 /* disable ints */ 3343 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); 3344 3345 pci_disable_device(pci); 3346 pci_save_state(pci); 3347 pci_set_power_state(pci, pci_choose_state(pci, state)); 3348 return 0; 3349} 3350 3351static int snd_cmipci_resume(struct pci_dev *pci) 3352{ 3353 struct snd_card *card = pci_get_drvdata(pci); 3354 struct cmipci *cm = card->private_data; 3355 int i; 3356 3357 pci_set_power_state(pci, PCI_D0); 3358 pci_restore_state(pci); 3359 if (pci_enable_device(pci) < 0) { 3360 printk(KERN_ERR "cmipci: pci_enable_device failed, " 3361 "disabling device\n"); 3362 snd_card_disconnect(card); 3363 return -EIO; 3364 } 3365 pci_set_master(pci); 3366 3367 /* reset / initialize to a sane state */ 3368 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); 3369 snd_cmipci_ch_reset(cm, CM_CH_PLAY); 3370 snd_cmipci_ch_reset(cm, CM_CH_CAPT); 3371 snd_cmipci_mixer_write(cm, 0, 0); 3372 3373 /* restore registers */ 3374 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3375 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]); 3376 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++) 3377 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]); 3378 3379 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 3380 return 0; 3381} 3382#endif /* CONFIG_PM */ 3383 3384static struct pci_driver driver = { 3385 .name = "C-Media PCI", 3386 .id_table = snd_cmipci_ids, 3387 .probe = snd_cmipci_probe, 3388 .remove = __devexit_p(snd_cmipci_remove), 3389#ifdef CONFIG_PM 3390 .suspend = snd_cmipci_suspend, 3391 .resume = snd_cmipci_resume, 3392#endif 3393}; 3394 3395static int __init alsa_card_cmipci_init(void) 3396{ 3397 return pci_register_driver(&driver); 3398} 3399 3400static void __exit alsa_card_cmipci_exit(void) 3401{ 3402 pci_unregister_driver(&driver); 3403} 3404 3405module_init(alsa_card_cmipci_init) 3406module_exit(alsa_card_cmipci_exit) 3407