1/* 2 cx25840.h - definition for cx25840/1/2/3 inputs 3 4 Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl) 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19*/ 20 21#ifndef _CX25840_H_ 22#define _CX25840_H_ 23 24/* Note that the cx25840 driver requires that the bridge driver calls the 25 v4l2_subdev's init operation in order to load the driver's firmware. 26 Without this the audio standard detection will fail and you will 27 only get mono. 28 29 Since loading the firmware is often problematic when the driver is 30 compiled into the kernel I recommend postponing calling this function 31 until the first open of the video device. Another reason for 32 postponing it is that loading this firmware takes a long time (seconds) 33 due to the slow i2c bus speed. So it will speed up the boot process if 34 you can avoid loading the fw as long as the video device isn't used. */ 35 36enum cx25840_video_input { 37 /* Composite video inputs In1-In8 */ 38 CX25840_COMPOSITE1 = 1, 39 CX25840_COMPOSITE2, 40 CX25840_COMPOSITE3, 41 CX25840_COMPOSITE4, 42 CX25840_COMPOSITE5, 43 CX25840_COMPOSITE6, 44 CX25840_COMPOSITE7, 45 CX25840_COMPOSITE8, 46 47 /* S-Video inputs consist of one luma input (In1-In8) ORed with one 48 chroma input (In5-In8) */ 49 CX25840_SVIDEO_LUMA1 = 0x10, 50 CX25840_SVIDEO_LUMA2 = 0x20, 51 CX25840_SVIDEO_LUMA3 = 0x30, 52 CX25840_SVIDEO_LUMA4 = 0x40, 53 CX25840_SVIDEO_LUMA5 = 0x50, 54 CX25840_SVIDEO_LUMA6 = 0x60, 55 CX25840_SVIDEO_LUMA7 = 0x70, 56 CX25840_SVIDEO_LUMA8 = 0x80, 57 CX25840_SVIDEO_CHROMA4 = 0x400, 58 CX25840_SVIDEO_CHROMA5 = 0x500, 59 CX25840_SVIDEO_CHROMA6 = 0x600, 60 CX25840_SVIDEO_CHROMA7 = 0x700, 61 CX25840_SVIDEO_CHROMA8 = 0x800, 62 63 /* S-Video aliases for common luma/chroma combinations */ 64 CX25840_SVIDEO1 = 0x510, 65 CX25840_SVIDEO2 = 0x620, 66 CX25840_SVIDEO3 = 0x730, 67 CX25840_SVIDEO4 = 0x840, 68 69 /* Allow frames to specify specific input configurations */ 70 CX25840_VIN1_CH1 = 0x80000000, 71 CX25840_VIN2_CH1 = 0x80000001, 72 CX25840_VIN3_CH1 = 0x80000002, 73 CX25840_VIN4_CH1 = 0x80000003, 74 CX25840_VIN5_CH1 = 0x80000004, 75 CX25840_VIN6_CH1 = 0x80000005, 76 CX25840_VIN7_CH1 = 0x80000006, 77 CX25840_VIN8_CH1 = 0x80000007, 78 CX25840_VIN4_CH2 = 0x80000000, 79 CX25840_VIN5_CH2 = 0x80000010, 80 CX25840_VIN6_CH2 = 0x80000020, 81 CX25840_NONE_CH2 = 0x80000030, 82 CX25840_VIN7_CH3 = 0x80000000, 83 CX25840_VIN8_CH3 = 0x80000040, 84 CX25840_NONE0_CH3 = 0x80000080, 85 CX25840_NONE1_CH3 = 0x800000c0, 86 CX25840_SVIDEO_ON = 0x80000100, 87 CX25840_COMPONENT_ON = 0x80000200, 88}; 89 90enum cx25840_audio_input { 91 /* Audio inputs: serial or In4-In8 */ 92 CX25840_AUDIO_SERIAL, 93 CX25840_AUDIO4 = 4, 94 CX25840_AUDIO5, 95 CX25840_AUDIO6, 96 CX25840_AUDIO7, 97 CX25840_AUDIO8, 98}; 99 100enum cx25840_io_pin { 101 CX25840_PIN_DVALID_PRGM0 = 0, 102 CX25840_PIN_FIELD_PRGM1, 103 CX25840_PIN_HRESET_PRGM2, 104 CX25840_PIN_VRESET_HCTL_PRGM3, 105 CX25840_PIN_IRQ_N_PRGM4, 106 CX25840_PIN_IR_TX_PRGM6, 107 CX25840_PIN_IR_RX_PRGM5, 108 CX25840_PIN_GPIO0_PRGM8, 109 CX25840_PIN_GPIO1_PRGM9, 110 CX25840_PIN_SA_SDIN, /* Alternate GP Input only */ 111 CX25840_PIN_SA_SDOUT, /* Alternate GP Input only */ 112 CX25840_PIN_PLL_CLK_PRGM7, 113 CX25840_PIN_CHIP_SEL_VIPCLK, /* Output only */ 114}; 115 116enum cx25840_io_pad { 117 /* Output pads */ 118 CX25840_PAD_DEFAULT = 0, 119 CX25840_PAD_ACTIVE, 120 CX25840_PAD_VACTIVE, 121 CX25840_PAD_CBFLAG, 122 CX25840_PAD_VID_DATA_EXT0, 123 CX25840_PAD_VID_DATA_EXT1, 124 CX25840_PAD_GPO0, 125 CX25840_PAD_GPO1, 126 CX25840_PAD_GPO2, 127 CX25840_PAD_GPO3, 128 CX25840_PAD_IRQ_N, 129 CX25840_PAD_AC_SYNC, 130 CX25840_PAD_AC_SDOUT, 131 CX25840_PAD_PLL_CLK, 132 CX25840_PAD_VRESET, 133 CX25840_PAD_RESERVED, 134 /* Pads for PLL_CLK output only */ 135 CX25840_PAD_XTI_X5_DLL, 136 CX25840_PAD_AUX_PLL, 137 CX25840_PAD_VID_PLL, 138 CX25840_PAD_XTI, 139 /* Input Pads */ 140 CX25840_PAD_GPI0, 141 CX25840_PAD_GPI1, 142 CX25840_PAD_GPI2, 143 CX25840_PAD_GPI3, 144}; 145 146enum cx25840_io_pin_strength { 147 CX25840_PIN_DRIVE_MEDIUM = 0, 148 CX25840_PIN_DRIVE_SLOW, 149 CX25840_PIN_DRIVE_FAST, 150}; 151 152enum cx23885_io_pin { 153 CX23885_PIN_IR_RX_GPIO19, 154 CX23885_PIN_IR_TX_GPIO20, 155 CX23885_PIN_I2S_SDAT_GPIO21, 156 CX23885_PIN_I2S_WCLK_GPIO22, 157 CX23885_PIN_I2S_BCLK_GPIO23, 158 CX23885_PIN_IRQ_N_GPIO16, 159}; 160 161enum cx23885_io_pad { 162 CX23885_PAD_IR_RX, 163 CX23885_PAD_GPIO19, 164 CX23885_PAD_IR_TX, 165 CX23885_PAD_GPIO20, 166 CX23885_PAD_I2S_SDAT, 167 CX23885_PAD_GPIO21, 168 CX23885_PAD_I2S_WCLK, 169 CX23885_PAD_GPIO22, 170 CX23885_PAD_I2S_BCLK, 171 CX23885_PAD_GPIO23, 172 CX23885_PAD_IRQ_N, 173 CX23885_PAD_GPIO16, 174}; 175 176struct cx25840_platform_data { 177 int pvr150_workaround; 178}; 179 180#endif 181