1/* 2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. 3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. 4 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public 7 * License as published by the Free Software Foundation; 8 * either version 2, or (at your option) any later version. 9 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even 12 * the implied warranty of MERCHANTABILITY or FITNESS FOR 13 * A PARTICULAR PURPOSE.See the GNU General Public License 14 * for more details. 15 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 */ 21 22#include <linux/via-core.h> 23#include "global.h" 24struct res_map_refresh res_map_refresh_tbl[] = { 25/*hres, vres, vclock, vmode_refresh*/ 26 {480, 640, RES_480X640_60HZ_PIXCLOCK, 60}, 27 {640, 480, RES_640X480_60HZ_PIXCLOCK, 60}, 28 {640, 480, RES_640X480_75HZ_PIXCLOCK, 75}, 29 {640, 480, RES_640X480_85HZ_PIXCLOCK, 85}, 30 {640, 480, RES_640X480_100HZ_PIXCLOCK, 100}, 31 {640, 480, RES_640X480_120HZ_PIXCLOCK, 120}, 32 {720, 480, RES_720X480_60HZ_PIXCLOCK, 60}, 33 {720, 576, RES_720X576_60HZ_PIXCLOCK, 60}, 34 {800, 480, RES_800X480_60HZ_PIXCLOCK, 60}, 35 {800, 600, RES_800X600_60HZ_PIXCLOCK, 60}, 36 {800, 600, RES_800X600_75HZ_PIXCLOCK, 75}, 37 {800, 600, RES_800X600_85HZ_PIXCLOCK, 85}, 38 {800, 600, RES_800X600_100HZ_PIXCLOCK, 100}, 39 {800, 600, RES_800X600_120HZ_PIXCLOCK, 120}, 40 {848, 480, RES_848X480_60HZ_PIXCLOCK, 60}, 41 {856, 480, RES_856X480_60HZ_PIXCLOCK, 60}, 42 {1024, 512, RES_1024X512_60HZ_PIXCLOCK, 60}, 43 {1024, 600, RES_1024X600_60HZ_PIXCLOCK, 60}, 44 {1024, 768, RES_1024X768_60HZ_PIXCLOCK, 60}, 45 {1024, 768, RES_1024X768_75HZ_PIXCLOCK, 75}, 46 {1024, 768, RES_1024X768_85HZ_PIXCLOCK, 85}, 47 {1024, 768, RES_1024X768_100HZ_PIXCLOCK, 100}, 48/* {1152,864, RES_1152X864_70HZ_PIXCLOCK, 70},*/ 49 {1152, 864, RES_1152X864_75HZ_PIXCLOCK, 75}, 50 {1280, 768, RES_1280X768_60HZ_PIXCLOCK, 60}, 51 {1280, 800, RES_1280X800_60HZ_PIXCLOCK, 60}, 52 {1280, 960, RES_1280X960_60HZ_PIXCLOCK, 60}, 53 {1280, 1024, RES_1280X1024_60HZ_PIXCLOCK, 60}, 54 {1280, 1024, RES_1280X1024_75HZ_PIXCLOCK, 75}, 55 {1280, 1024, RES_1280X768_85HZ_PIXCLOCK, 85}, 56 {1440, 1050, RES_1440X1050_60HZ_PIXCLOCK, 60}, 57 {1600, 1200, RES_1600X1200_60HZ_PIXCLOCK, 60}, 58 {1600, 1200, RES_1600X1200_75HZ_PIXCLOCK, 75}, 59 {1280, 720, RES_1280X720_60HZ_PIXCLOCK, 60}, 60 {1920, 1080, RES_1920X1080_60HZ_PIXCLOCK, 60}, 61 {1400, 1050, RES_1400X1050_60HZ_PIXCLOCK, 60}, 62 {1400, 1050, RES_1400X1050_75HZ_PIXCLOCK, 75}, 63 {1368, 768, RES_1368X768_60HZ_PIXCLOCK, 60}, 64 {960, 600, RES_960X600_60HZ_PIXCLOCK, 60}, 65 {1000, 600, RES_1000X600_60HZ_PIXCLOCK, 60}, 66 {1024, 576, RES_1024X576_60HZ_PIXCLOCK, 60}, 67 {1088, 612, RES_1088X612_60HZ_PIXCLOCK, 60}, 68 {1152, 720, RES_1152X720_60HZ_PIXCLOCK, 60}, 69 {1200, 720, RES_1200X720_60HZ_PIXCLOCK, 60}, 70 {1200, 900, RES_1200X900_60HZ_PIXCLOCK, 60}, 71 {1280, 600, RES_1280X600_60HZ_PIXCLOCK, 60}, 72 {1280, 720, RES_1280X720_50HZ_PIXCLOCK, 50}, 73 {1280, 768, RES_1280X768_50HZ_PIXCLOCK, 50}, 74 {1360, 768, RES_1360X768_60HZ_PIXCLOCK, 60}, 75 {1366, 768, RES_1366X768_50HZ_PIXCLOCK, 50}, 76 {1366, 768, RES_1366X768_60HZ_PIXCLOCK, 60}, 77 {1440, 900, RES_1440X900_60HZ_PIXCLOCK, 60}, 78 {1440, 900, RES_1440X900_75HZ_PIXCLOCK, 75}, 79 {1600, 900, RES_1600X900_60HZ_PIXCLOCK, 60}, 80 {1600, 1024, RES_1600X1024_60HZ_PIXCLOCK, 60}, 81 {1680, 1050, RES_1680X1050_60HZ_PIXCLOCK, 60}, 82 {1680, 1050, RES_1680X1050_75HZ_PIXCLOCK, 75}, 83 {1792, 1344, RES_1792X1344_60HZ_PIXCLOCK, 60}, 84 {1856, 1392, RES_1856X1392_60HZ_PIXCLOCK, 60}, 85 {1920, 1200, RES_1920X1200_60HZ_PIXCLOCK, 60}, 86 {1920, 1440, RES_1920X1440_60HZ_PIXCLOCK, 60}, 87 {1920, 1440, RES_1920X1440_75HZ_PIXCLOCK, 75}, 88 {2048, 1536, RES_2048X1536_60HZ_PIXCLOCK, 60} 89}; 90 91struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01}, 92{VIASR, SR15, 0x02, 0x02}, 93{VIASR, SR16, 0xBF, 0x08}, 94{VIASR, SR17, 0xFF, 0x1F}, 95{VIASR, SR18, 0xFF, 0x4E}, 96{VIASR, SR1A, 0xFB, 0x08}, 97{VIASR, SR1E, 0x0F, 0x01}, 98{VIASR, SR2A, 0xFF, 0x00}, 99{VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */ 100{VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */ 101{VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */ 102{VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */ 103{VIACR, CR32, 0xFF, 0x00}, 104{VIACR, CR33, 0xFF, 0x00}, 105{VIACR, CR35, 0xFF, 0x00}, 106{VIACR, CR36, 0x08, 0x00}, 107{VIACR, CR69, 0xFF, 0x00}, 108{VIACR, CR6A, 0xFF, 0x40}, 109{VIACR, CR6B, 0xFF, 0x00}, 110{VIACR, CR6C, 0xFF, 0x00}, 111{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */ 112{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */ 113{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */ 114{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */ 115{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */ 116{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */ 117{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */ 118{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */ 119{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */ 120{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */ 121{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */ 122{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */ 123{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */ 124{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */ 125{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ 126{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ 127{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ 128{VIACR, CR8B, 0xFF, 0x69}, /* LCD Power Sequence Control 0 */ 129{VIACR, CR8C, 0xFF, 0x57}, /* LCD Power Sequence Control 1 */ 130{VIACR, CR8D, 0xFF, 0x00}, /* LCD Power Sequence Control 2 */ 131{VIACR, CR8E, 0xFF, 0x7B}, /* LCD Power Sequence Control 3 */ 132{VIACR, CR8F, 0xFF, 0x03}, /* LCD Power Sequence Control 4 */ 133{VIACR, CR90, 0xFF, 0x30}, /* LCD Power Sequence Control 5 */ 134{VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */ 135{VIACR, CR96, 0xFF, 0x00}, 136{VIACR, CR97, 0xFF, 0x00}, 137{VIACR, CR99, 0xFF, 0x00}, 138{VIACR, CR9B, 0xFF, 0x00} 139}; 140 141/* Video Mode Table for VT3314 chipset*/ 142/* Common Setting for Video Mode */ 143struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01}, 144{VIASR, SR15, 0x02, 0x02}, 145{VIASR, SR16, 0xBF, 0x08}, 146{VIASR, SR17, 0xFF, 0x1F}, 147{VIASR, SR18, 0xFF, 0x4E}, 148{VIASR, SR1A, 0xFB, 0x82}, 149{VIASR, SR1B, 0xFF, 0xF0}, 150{VIASR, SR1F, 0xFF, 0x00}, 151{VIASR, SR1E, 0xFF, 0x01}, 152{VIASR, SR22, 0xFF, 0x1F}, 153{VIASR, SR2A, 0x0F, 0x00}, 154{VIASR, SR2E, 0xFF, 0xFF}, 155{VIASR, SR3F, 0xFF, 0xFF}, 156{VIASR, SR40, 0xF7, 0x00}, 157{VIASR, CR30, 0xFF, 0x04}, 158{VIACR, CR32, 0xFF, 0x00}, 159{VIACR, CR33, 0x7F, 0x00}, 160{VIACR, CR35, 0xFF, 0x00}, 161{VIACR, CR36, 0xFF, 0x31}, 162{VIACR, CR41, 0xFF, 0x80}, 163{VIACR, CR42, 0xFF, 0x00}, 164{VIACR, CR55, 0x80, 0x00}, 165{VIACR, CR5D, 0x80, 0x00}, /*Horizontal Retrace Start bit[11] should be 0*/ 166{VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */ 167{VIACR, CR69, 0xFF, 0x00}, 168{VIACR, CR6A, 0xFD, 0x40}, 169{VIACR, CR6B, 0xFF, 0x00}, 170{VIACR, CR6C, 0xFF, 0x00}, 171{VIACR, CR77, 0xFF, 0x00}, /* LCD scaling Factor */ 172{VIACR, CR78, 0xFF, 0x00}, /* LCD scaling Factor */ 173{VIACR, CR79, 0xFF, 0x00}, /* LCD scaling Factor */ 174{VIACR, CR9F, 0x03, 0x00}, /* LCD scaling Factor */ 175{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */ 176{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */ 177{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */ 178{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */ 179{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */ 180{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */ 181{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */ 182{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */ 183{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */ 184{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */ 185{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */ 186{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */ 187{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */ 188{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */ 189{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ 190{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ 191{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ 192{VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */ 193{VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */ 194{VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */ 195{VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */ 196{VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */ 197{VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */ 198{VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */ 199{VIACR, CR96, 0xFF, 0x00}, 200{VIACR, CR97, 0xFF, 0x00}, 201{VIACR, CR99, 0xFF, 0x00}, 202{VIACR, CR9B, 0xFF, 0x00}, 203{VIACR, CR9D, 0xFF, 0x80}, 204{VIACR, CR9E, 0xFF, 0x80} 205}; 206 207struct io_reg KM400_ModeXregs[] = { 208 {VIASR, SR10, 0xFF, 0x01}, /* Unlock Register */ 209 {VIASR, SR16, 0xFF, 0x08}, /* Display FIFO threshold Control */ 210 {VIASR, SR17, 0xFF, 0x1F}, /* Display FIFO Control */ 211 {VIASR, SR18, 0xFF, 0x4E}, /* GFX PREQ threshold */ 212 {VIASR, SR1A, 0xFF, 0x0a}, /* GFX PREQ threshold */ 213 {VIASR, SR1F, 0xFF, 0x00}, /* Memory Control 0 */ 214 {VIASR, SR1B, 0xFF, 0xF0}, /* Power Management Control 0 */ 215 {VIASR, SR1E, 0xFF, 0x01}, /* Power Management Control */ 216 {VIASR, SR20, 0xFF, 0x00}, /* Sequencer Arbiter Control 0 */ 217 {VIASR, SR21, 0xFF, 0x00}, /* Sequencer Arbiter Control 1 */ 218 {VIASR, SR22, 0xFF, 0x1F}, /* Display Arbiter Control 1 */ 219 {VIASR, SR2A, 0xFF, 0x00}, /* Power Management Control 5 */ 220 {VIASR, SR2D, 0xFF, 0xFF}, /* Power Management Control 1 */ 221 {VIASR, SR2E, 0xFF, 0xFF}, /* Power Management Control 2 */ 222 {VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */ 223 {VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */ 224 {VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */ 225 {VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */ 226 {VIACR, CR33, 0xFF, 0x00}, 227 {VIACR, CR55, 0x80, 0x00}, 228 {VIACR, CR5D, 0x80, 0x00}, 229 {VIACR, CR36, 0xFF, 0x01}, /* Power Mangement 3 */ 230 {VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */ 231 {VIACR, CR6A, 0x20, 0x20}, /* Extended FIFO On */ 232 {VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */ 233 {VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */ 234 {VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */ 235 {VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */ 236 {VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */ 237 {VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */ 238 {VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */ 239 {VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */ 240 {VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */ 241 {VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */ 242 {VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */ 243 {VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */ 244 {VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */ 245 {VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */ 246 {VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ 247 {VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ 248 {VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ 249 {VIACR, CR8B, 0xFF, 0x2D}, /* LCD Power Sequence Control 0 */ 250 {VIACR, CR8C, 0xFF, 0x2D}, /* LCD Power Sequence Control 1 */ 251 {VIACR, CR8D, 0xFF, 0xC8}, /* LCD Power Sequence Control 2 */ 252 {VIACR, CR8E, 0xFF, 0x36}, /* LCD Power Sequence Control 3 */ 253 {VIACR, CR8F, 0xFF, 0x00}, /* LCD Power Sequence Control 4 */ 254 {VIACR, CR90, 0xFF, 0x10}, /* LCD Power Sequence Control 5 */ 255 {VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */ 256 {VIACR, CR96, 0xFF, 0x03}, /* DVP0 ; DVP0 Clock Skew */ 257 {VIACR, CR97, 0xFF, 0x03}, /* DFP high ; DFPH Clock Skew */ 258 {VIACR, CR99, 0xFF, 0x03}, /* DFP low ; DFPL Clock Skew*/ 259 {VIACR, CR9B, 0xFF, 0x07} /* DVI on DVP1 ; DVP1 Clock Skew*/ 260}; 261 262/* For VT3324: Common Setting for Video Mode */ 263struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01}, 264{VIASR, SR15, 0x02, 0x02}, 265{VIASR, SR16, 0xBF, 0x08}, 266{VIASR, SR17, 0xFF, 0x1F}, 267{VIASR, SR18, 0xFF, 0x4E}, 268{VIASR, SR1A, 0xFB, 0x08}, 269{VIASR, SR1B, 0xFF, 0xF0}, 270{VIASR, SR1E, 0xFF, 0x01}, 271{VIASR, SR2A, 0xFF, 0x00}, 272{VIASR, SR2D, 0xFF, 0xFF}, /* VCK and LCK PLL power on. */ 273{VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */ 274{VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */ 275{VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */ 276{VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */ 277{VIACR, CR32, 0xFF, 0x00}, 278{VIACR, CR33, 0xFF, 0x00}, 279{VIACR, CR35, 0xFF, 0x00}, 280{VIACR, CR36, 0x08, 0x00}, 281{VIACR, CR47, 0xC8, 0x00}, /* Clear VCK Plus. */ 282{VIACR, CR69, 0xFF, 0x00}, 283{VIACR, CR6A, 0xFF, 0x40}, 284{VIACR, CR6B, 0xFF, 0x00}, 285{VIACR, CR6C, 0xFF, 0x00}, 286{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */ 287{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */ 288{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */ 289{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */ 290{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */ 291{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */ 292{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */ 293{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */ 294{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */ 295{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */ 296{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */ 297{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */ 298{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */ 299{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */ 300{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ 301{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ 302{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ 303{VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */ 304{VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */ 305{VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */ 306{VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */ 307{VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */ 308{VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */ 309{VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */ 310{VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */ 311{VIACR, CR96, 0xFF, 0x00}, 312{VIACR, CR97, 0xFF, 0x00}, 313{VIACR, CR99, 0xFF, 0x00}, 314{VIACR, CR9B, 0xFF, 0x00} 315}; 316 317struct io_reg VX855_ModeXregs[] = { 318{VIASR, SR10, 0xFF, 0x01}, 319{VIASR, SR15, 0x02, 0x02}, 320{VIASR, SR16, 0xBF, 0x08}, 321{VIASR, SR17, 0xFF, 0x1F}, 322{VIASR, SR18, 0xFF, 0x4E}, 323{VIASR, SR1A, 0xFB, 0x08}, 324{VIASR, SR1B, 0xFF, 0xF0}, 325{VIASR, SR1E, 0x07, 0x01}, 326{VIASR, SR2A, 0xF0, 0x00}, 327{VIASR, SR58, 0xFF, 0x00}, 328{VIASR, SR59, 0xFF, 0x00}, 329{VIASR, SR2D, 0xFF, 0xFF}, /* VCK and LCK PLL power on. */ 330{VIACR, CR09, 0xFF, 0x00}, /* Initial CR09=0*/ 331{VIACR, CR11, 0x8F, 0x00}, /* IGA1 initial Vertical end */ 332{VIACR, CR17, 0x7F, 0x00}, /* IGA1 CRT Mode control init */ 333{VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */ 334{VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */ 335{VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */ 336{VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */ 337{VIACR, CR32, 0xFF, 0x00}, 338{VIACR, CR33, 0x7F, 0x00}, 339{VIACR, CR35, 0xFF, 0x00}, 340{VIACR, CR36, 0x08, 0x00}, 341{VIACR, CR69, 0xFF, 0x00}, 342{VIACR, CR6A, 0xFD, 0x60}, 343{VIACR, CR6B, 0xFF, 0x00}, 344{VIACR, CR6C, 0xFF, 0x00}, 345{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */ 346{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */ 347{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */ 348{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */ 349{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */ 350{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */ 351{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */ 352{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */ 353{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */ 354{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */ 355{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */ 356{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */ 357{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */ 358{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */ 359{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ 360{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ 361{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ 362{VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */ 363{VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */ 364{VIACR, CR96, 0xFF, 0x00}, 365{VIACR, CR97, 0xFF, 0x00}, 366{VIACR, CR99, 0xFF, 0x00}, 367{VIACR, CR9B, 0xFF, 0x00}, 368{VIACR, CRD2, 0xFF, 0xFF} /* TMDS/LVDS control register. */ 369}; 370 371/* Video Mode Table */ 372/* Common Setting for Video Mode */ 373struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00}, 374{VIASR, SR2A, 0x0F, 0x00}, 375{VIASR, SR15, 0x02, 0x02}, 376{VIASR, SR16, 0xBF, 0x08}, 377{VIASR, SR17, 0xFF, 0x1F}, 378{VIASR, SR18, 0xFF, 0x4E}, 379{VIASR, SR1A, 0xFB, 0x08}, 380 381{VIACR, CR32, 0xFF, 0x00}, 382{VIACR, CR35, 0xFF, 0x00}, 383{VIACR, CR36, 0x08, 0x00}, 384{VIACR, CR6A, 0xFF, 0x80}, 385{VIACR, CR6A, 0xFF, 0xC0}, 386 387{VIACR, CR55, 0x80, 0x00}, 388{VIACR, CR5D, 0x80, 0x00}, 389 390{VIAGR, GR20, 0xFF, 0x00}, 391{VIAGR, GR21, 0xFF, 0x00}, 392{VIAGR, GR22, 0xFF, 0x00}, 393 /* LCD Parameters */ 394{VIACR, CR7A, 0xFF, 0x01}, /* LCD Parameter 1 */ 395{VIACR, CR7B, 0xFF, 0x02}, /* LCD Parameter 2 */ 396{VIACR, CR7C, 0xFF, 0x03}, /* LCD Parameter 3 */ 397{VIACR, CR7D, 0xFF, 0x04}, /* LCD Parameter 4 */ 398{VIACR, CR7E, 0xFF, 0x07}, /* LCD Parameter 5 */ 399{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Parameter 6 */ 400{VIACR, CR80, 0xFF, 0x0D}, /* LCD Parameter 7 */ 401{VIACR, CR81, 0xFF, 0x13}, /* LCD Parameter 8 */ 402{VIACR, CR82, 0xFF, 0x16}, /* LCD Parameter 9 */ 403{VIACR, CR83, 0xFF, 0x19}, /* LCD Parameter 10 */ 404{VIACR, CR84, 0xFF, 0x1C}, /* LCD Parameter 11 */ 405{VIACR, CR85, 0xFF, 0x1D}, /* LCD Parameter 12 */ 406{VIACR, CR86, 0xFF, 0x1E}, /* LCD Parameter 13 */ 407{VIACR, CR87, 0xFF, 0x1F}, /* LCD Parameter 14 */ 408 409}; 410 411/* Mode:1024X768 */ 412struct io_reg PM1024x768[] = { {VIASR, 0x16, 0xBF, 0x0C}, 413{VIASR, 0x18, 0xFF, 0x4C} 414}; 415 416struct patch_table res_patch_table[] = { 417 {ARRAY_SIZE(PM1024x768), PM1024x768} 418}; 419 420/* struct VPITTable { 421 unsigned char Misc; 422 unsigned char SR[StdSR]; 423 unsigned char CR[StdCR]; 424 unsigned char GR[StdGR]; 425 unsigned char AR[StdAR]; 426 };*/ 427 428struct VPITTable VPIT = { 429 /* Msic */ 430 0xC7, 431 /* Sequencer */ 432 {0x01, 0x0F, 0x00, 0x0E}, 433 /* Graphic Controller */ 434 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF}, 435 /* Attribute Controller */ 436 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 437 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 438 0x01, 0x00, 0x0F, 0x00} 439}; 440 441/********************/ 442/* Mode Table */ 443/********************/ 444 445/* 480x640 */ 446struct crt_mode_table CRTM480x640[] = { 447 /* r_rate, vclk, hsp, vsp */ 448 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 449 {REFRESH_60, CLK_25_175M, M480X640_R60_HSP, M480X640_R60_VSP, 450 {624, 480, 480, 144, 504, 48, 663, 640, 640, 23, 641, 3} } /* GTF*/ 451}; 452 453/* 640x480*/ 454struct crt_mode_table CRTM640x480[] = { 455 /*r_rate,vclk,hsp,vsp */ 456 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 457 {REFRESH_60, CLK_25_175M, M640X480_R60_HSP, M640X480_R60_VSP, 458 {800, 640, 648, 144, 656, 96, 525, 480, 480, 45, 490, 2} }, 459 {REFRESH_75, CLK_31_500M, M640X480_R75_HSP, M640X480_R75_VSP, 460 {840, 640, 640, 200, 656, 64, 500, 480, 480, 20, 481, 3} }, 461 {REFRESH_85, CLK_36_000M, M640X480_R85_HSP, M640X480_R85_VSP, 462 {832, 640, 640, 192, 696, 56, 509, 480, 480, 29, 481, 3} }, 463 {REFRESH_100, CLK_43_163M, M640X480_R100_HSP, M640X480_R100_VSP, 464 {848, 640, 640, 208, 680, 64, 509, 480, 480, 29, 481, 3} }, /*GTF*/ 465 {REFRESH_120, CLK_52_406M, M640X480_R120_HSP, 466 M640X480_R120_VSP, 467 {848, 640, 640, 208, 680, 64, 515, 480, 480, 35, 481, 468 3} } /*GTF*/ 469}; 470 471/*720x480 (GTF)*/ 472struct crt_mode_table CRTM720x480[] = { 473 /*r_rate,vclk,hsp,vsp */ 474 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 475 {REFRESH_60, CLK_26_880M, M720X480_R60_HSP, M720X480_R60_VSP, 476 {896, 720, 720, 176, 736, 72, 497, 480, 480, 17, 481, 3} } 477 478}; 479 480/*720x576 (GTF)*/ 481struct crt_mode_table CRTM720x576[] = { 482 /*r_rate,vclk,hsp,vsp */ 483 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 484 {REFRESH_60, CLK_32_668M, M720X576_R60_HSP, M720X576_R60_VSP, 485 {912, 720, 720, 192, 744, 72, 597, 576, 576, 21, 577, 3} } 486}; 487 488/* 800x480 (CVT) */ 489struct crt_mode_table CRTM800x480[] = { 490 /* r_rate, vclk, hsp, vsp */ 491 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 492 {REFRESH_60, CLK_29_581M, M800X480_R60_HSP, M800X480_R60_VSP, 493 {992, 800, 800, 192, 824, 72, 500, 480, 480, 20, 483, 7} } 494}; 495 496/* 800x600*/ 497struct crt_mode_table CRTM800x600[] = { 498 /*r_rate,vclk,hsp,vsp */ 499 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 500 {REFRESH_60, CLK_40_000M, M800X600_R60_HSP, M800X600_R60_VSP, 501 {1056, 800, 800, 256, 840, 128, 628, 600, 600, 28, 601, 4} }, 502 {REFRESH_75, CLK_49_500M, M800X600_R75_HSP, M800X600_R75_VSP, 503 {1056, 800, 800, 256, 816, 80, 625, 600, 600, 25, 601, 3} }, 504 {REFRESH_85, CLK_56_250M, M800X600_R85_HSP, M800X600_R85_VSP, 505 {1048, 800, 800, 248, 832, 64, 631, 600, 600, 31, 601, 3} }, 506 {REFRESH_100, CLK_68_179M, M800X600_R100_HSP, M800X600_R100_VSP, 507 {1072, 800, 800, 272, 848, 88, 636, 600, 600, 36, 601, 3} }, 508 {REFRESH_120, CLK_83_950M, M800X600_R120_HSP, 509 M800X600_R120_VSP, 510 {1088, 800, 800, 288, 856, 88, 643, 600, 600, 43, 601, 511 3} } 512}; 513 514/* 848x480 (CVT) */ 515struct crt_mode_table CRTM848x480[] = { 516 /* r_rate, vclk, hsp, vsp */ 517 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 518 {REFRESH_60, CLK_31_500M, M848X480_R60_HSP, M848X480_R60_VSP, 519 {1056, 848, 848, 208, 872, 80, 500, 480, 480, 20, 483, 5} } 520}; 521 522/*856x480 (GTF) convert to 852x480*/ 523struct crt_mode_table CRTM852x480[] = { 524 /*r_rate,vclk,hsp,vsp */ 525 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 526 {REFRESH_60, CLK_31_728M, M852X480_R60_HSP, M852X480_R60_VSP, 527 {1064, 856, 856, 208, 872, 88, 497, 480, 480, 17, 481, 3} } 528}; 529 530/*1024x512 (GTF)*/ 531struct crt_mode_table CRTM1024x512[] = { 532 /*r_rate,vclk,hsp,vsp */ 533 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 534 {REFRESH_60, CLK_41_291M, M1024X512_R60_HSP, M1024X512_R60_VSP, 535 {1296, 1024, 1024, 272, 1056, 104, 531, 512, 512, 19, 513, 3} } 536 537}; 538 539/* 1024x600*/ 540struct crt_mode_table CRTM1024x600[] = { 541 /*r_rate,vclk,hsp,vsp */ 542 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 543 {REFRESH_60, CLK_48_875M, M1024X600_R60_HSP, M1024X600_R60_VSP, 544 {1312, 1024, 1024, 288, 1064, 104, 622, 600, 600, 22, 601, 3} }, 545}; 546 547/* 1024x768*/ 548struct crt_mode_table CRTM1024x768[] = { 549 /*r_rate,vclk,hsp,vsp */ 550 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 551 {REFRESH_60, CLK_65_000M, M1024X768_R60_HSP, M1024X768_R60_VSP, 552 {1344, 1024, 1024, 320, 1048, 136, 806, 768, 768, 38, 771, 6} }, 553 {REFRESH_75, CLK_78_750M, M1024X768_R75_HSP, M1024X768_R75_VSP, 554 {1312, 1024, 1024, 288, 1040, 96, 800, 768, 768, 32, 769, 3} }, 555 {REFRESH_85, CLK_94_500M, M1024X768_R85_HSP, M1024X768_R85_VSP, 556 {1376, 1024, 1024, 352, 1072, 96, 808, 768, 768, 40, 769, 3} }, 557 {REFRESH_100, CLK_113_309M, M1024X768_R100_HSP, M1024X768_R100_VSP, 558 {1392, 1024, 1024, 368, 1096, 112, 814, 768, 768, 46, 769, 3} } 559}; 560 561/* 1152x864*/ 562struct crt_mode_table CRTM1152x864[] = { 563 /*r_rate,vclk,hsp,vsp */ 564 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 565 {REFRESH_75, CLK_108_000M, M1152X864_R75_HSP, M1152X864_R75_VSP, 566 {1600, 1152, 1152, 448, 1216, 128, 900, 864, 864, 36, 865, 3} } 567 568}; 569 570/* 1280x720 (HDMI 720P)*/ 571struct crt_mode_table CRTM1280x720[] = { 572 /*r_rate,vclk,hsp,vsp */ 573 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 574 {REFRESH_60, CLK_74_481M, M1280X720_R60_HSP, M1280X720_R60_VSP, 575 {1648, 1280, 1280, 368, 1392, 40, 750, 720, 720, 30, 725, 5} }, 576 {REFRESH_50, CLK_60_466M, M1280X720_R50_HSP, M1280X720_R50_VSP, 577 {1632, 1280, 1280, 352, 1328, 128, 741, 720, 720, 21, 721, 3} } 578}; 579 580/*1280x768 (GTF)*/ 581struct crt_mode_table CRTM1280x768[] = { 582 /*r_rate,vclk,hsp,vsp */ 583 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 584 {REFRESH_60, CLK_80_136M, M1280X768_R60_HSP, M1280X768_R60_VSP, 585 {1680, 1280, 1280, 400, 1344, 136, 795, 768, 768, 27, 769, 3} }, 586 {REFRESH_50, CLK_65_178M, M1280X768_R50_HSP, M1280X768_R50_VSP, 587 {1648, 1280, 1280, 368, 1336, 128, 791, 768, 768, 23, 769, 3} } 588}; 589 590/* 1280x800 (CVT) */ 591struct crt_mode_table CRTM1280x800[] = { 592 /* r_rate, vclk, hsp, vsp */ 593 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 594 {REFRESH_60, CLK_83_375M, M1280X800_R60_HSP, M1280X800_R60_VSP, 595 {1680, 1280, 1280, 400, 1352, 128, 831, 800, 800, 31, 803, 6} } 596}; 597 598/*1280x960*/ 599struct crt_mode_table CRTM1280x960[] = { 600 /*r_rate,vclk,hsp,vsp */ 601 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 602 {REFRESH_60, CLK_108_000M, M1280X960_R60_HSP, M1280X960_R60_VSP, 603 {1800, 1280, 1280, 520, 1376, 112, 1000, 960, 960, 40, 961, 3} } 604}; 605 606/* 1280x1024*/ 607struct crt_mode_table CRTM1280x1024[] = { 608 /*r_rate,vclk,,hsp,vsp */ 609 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 610 {REFRESH_60, CLK_108_000M, M1280X1024_R60_HSP, M1280X1024_R60_VSP, 611 {1688, 1280, 1280, 408, 1328, 112, 1066, 1024, 1024, 42, 1025, 612 3} }, 613 {REFRESH_75, CLK_135_000M, M1280X1024_R75_HSP, M1280X1024_R75_VSP, 614 {1688, 1280, 1280, 408, 1296, 144, 1066, 1024, 1024, 42, 1025, 615 3} }, 616 {REFRESH_85, CLK_157_500M, M1280X1024_R85_HSP, M1280X1024_R85_VSP, 617 {1728, 1280, 1280, 448, 1344, 160, 1072, 1024, 1024, 48, 1025, 3} } 618}; 619 620/* 1368x768 (GTF) */ 621struct crt_mode_table CRTM1368x768[] = { 622 /* r_rate, vclk, hsp, vsp */ 623 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 624 {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP, 625 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} } 626}; 627 628/*1440x1050 (GTF)*/ 629struct crt_mode_table CRTM1440x1050[] = { 630 /*r_rate,vclk,hsp,vsp */ 631 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 632 {REFRESH_60, CLK_125_104M, M1440X1050_R60_HSP, M1440X1050_R60_VSP, 633 {1936, 1440, 1440, 496, 1536, 152, 1077, 1040, 1040, 37, 1041, 3} } 634}; 635 636/* 1600x1200*/ 637struct crt_mode_table CRTM1600x1200[] = { 638 /*r_rate,vclk,hsp,vsp */ 639 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 640 {REFRESH_60, CLK_162_000M, M1600X1200_R60_HSP, M1600X1200_R60_VSP, 641 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 642 3} }, 643 {REFRESH_75, CLK_202_500M, M1600X1200_R75_HSP, M1600X1200_R75_VSP, 644 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 3} } 645 646}; 647 648/* 1680x1050 (CVT) */ 649struct crt_mode_table CRTM1680x1050[] = { 650 /* r_rate, vclk, hsp, vsp */ 651 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 652 {REFRESH_60, CLK_146_760M, M1680x1050_R60_HSP, M1680x1050_R60_VSP, 653 {2240, 1680, 1680, 560, 1784, 176, 1089, 1050, 1050, 39, 1053, 654 6} }, 655 {REFRESH_75, CLK_187_000M, M1680x1050_R75_HSP, M1680x1050_R75_VSP, 656 {2272, 1680, 1680, 592, 1800, 176, 1099, 1050, 1050, 49, 1053, 6} } 657}; 658 659/* 1680x1050 (CVT Reduce Blanking) */ 660struct crt_mode_table CRTM1680x1050_RB[] = { 661 /* r_rate, vclk, hsp, vsp */ 662 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 663 {REFRESH_60, CLK_119_000M, M1680x1050_RB_R60_HSP, 664 M1680x1050_RB_R60_VSP, 665 {1840, 1680, 1680, 160, 1728, 32, 1080, 1050, 1050, 30, 1053, 6} } 666}; 667 668/* 1920x1080 (CVT)*/ 669struct crt_mode_table CRTM1920x1080[] = { 670 /*r_rate,vclk,hsp,vsp */ 671 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 672 {REFRESH_60, CLK_172_798M, M1920X1080_R60_HSP, M1920X1080_R60_VSP, 673 {2576, 1920, 1920, 656, 2048, 200, 1120, 1080, 1080, 40, 1083, 5} } 674}; 675 676/* 1920x1080 (CVT with Reduce Blanking) */ 677struct crt_mode_table CRTM1920x1080_RB[] = { 678 /* r_rate, vclk, hsp, vsp */ 679 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 680 {REFRESH_60, CLK_138_400M, M1920X1080_RB_R60_HSP, 681 M1920X1080_RB_R60_VSP, 682 {2080, 1920, 1920, 160, 1968, 32, 1111, 1080, 1080, 31, 1083, 5} } 683}; 684 685/* 1920x1440*/ 686struct crt_mode_table CRTM1920x1440[] = { 687 /*r_rate,vclk,hsp,vsp */ 688 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 689 {REFRESH_60, CLK_234_000M, M1920X1440_R60_HSP, M1920X1440_R60_VSP, 690 {2600, 1920, 1920, 680, 2048, 208, 1500, 1440, 1440, 60, 1441, 691 3} }, 692 {REFRESH_75, CLK_297_500M, M1920X1440_R75_HSP, M1920X1440_R75_VSP, 693 {2640, 1920, 1920, 720, 2064, 224, 1500, 1440, 1440, 60, 1441, 3} } 694}; 695 696/* 1400x1050 (CVT) */ 697struct crt_mode_table CRTM1400x1050[] = { 698 /* r_rate, vclk, hsp, vsp */ 699 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 700 {REFRESH_60, CLK_121_750M, M1400X1050_R60_HSP, M1400X1050_R60_VSP, 701 {1864, 1400, 1400, 464, 1488, 144, 1089, 1050, 1050, 39, 1053, 702 4} }, 703 {REFRESH_75, CLK_156_000M, M1400X1050_R75_HSP, M1400X1050_R75_VSP, 704 {1896, 1400, 1400, 496, 1504, 144, 1099, 1050, 1050, 49, 1053, 4} } 705}; 706 707/* 1400x1050 (CVT Reduce Blanking) */ 708struct crt_mode_table CRTM1400x1050_RB[] = { 709 /* r_rate, vclk, hsp, vsp */ 710 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 711 {REFRESH_60, CLK_101_000M, M1400X1050_RB_R60_HSP, 712 M1400X1050_RB_R60_VSP, 713 {1560, 1400, 1400, 160, 1448, 32, 1080, 1050, 1050, 30, 1053, 4} } 714}; 715 716/* 960x600 (CVT) */ 717struct crt_mode_table CRTM960x600[] = { 718 /* r_rate, vclk, hsp, vsp */ 719 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 720 {REFRESH_60, CLK_45_250M, M960X600_R60_HSP, M960X600_R60_VSP, 721 {1216, 960, 960, 256, 992, 96, 624, 600, 600, 24, 603, 6} } 722}; 723 724/* 1000x600 (GTF) */ 725struct crt_mode_table CRTM1000x600[] = { 726 /* r_rate, vclk, hsp, vsp */ 727 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 728 {REFRESH_60, CLK_48_000M, M1000X600_R60_HSP, M1000X600_R60_VSP, 729 {1288, 1000, 1000, 288, 1040, 104, 622, 600, 600, 22, 601, 3} } 730}; 731 732/* 1024x576 (GTF) */ 733struct crt_mode_table CRTM1024x576[] = { 734 /* r_rate, vclk, hsp, vsp */ 735 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 736 {REFRESH_60, CLK_46_996M, M1024X576_R60_HSP, M1024X576_R60_VSP, 737 {1312, 1024, 1024, 288, 1064, 104, 597, 576, 576, 21, 577, 3} } 738}; 739 740/* 1088x612 (CVT) */ 741struct crt_mode_table CRTM1088x612[] = { 742 /* r_rate, vclk, hsp, vsp */ 743 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 744 {REFRESH_60, CLK_52_977M, M1088X612_R60_HSP, M1088X612_R60_VSP, 745 {1392, 1088, 1088, 304, 1136, 104, 636, 612, 612, 24, 615, 5} } 746}; 747 748/* 1152x720 (CVT) */ 749struct crt_mode_table CRTM1152x720[] = { 750 /* r_rate, vclk, hsp, vsp */ 751 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 752 {REFRESH_60, CLK_66_750M, M1152X720_R60_HSP, M1152X720_R60_VSP, 753 {1488, 1152, 1152, 336, 1208, 112, 748, 720, 720, 28, 723, 6} } 754}; 755 756/* 1200x720 (GTF) */ 757struct crt_mode_table CRTM1200x720[] = { 758 /* r_rate, vclk, hsp, vsp */ 759 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 760 {REFRESH_60, CLK_70_159M, M1200X720_R60_HSP, M1200X720_R60_VSP, 761 {1568, 1200, 1200, 368, 1256, 128, 746, 720, 720, 26, 721, 3} } 762}; 763 764/* 1200x900 (DCON) */ 765struct crt_mode_table DCON1200x900[] = { 766 /* r_rate, vclk, hsp, vsp */ 767 {REFRESH_60, CLK_57_275M, M1200X900_R60_HSP, M1200X900_R60_VSP, 768 /* The correct htotal is 1240, but this doesn't raster on VX855. */ 769 /* Via suggested changing to a multiple of 16, hence 1264. */ 770 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 771 {1264, 1200, 1200, 64, 1211, 32, 912, 900, 900, 12, 901, 10} } 772}; 773 774/* 1280x600 (GTF) */ 775struct crt_mode_table CRTM1280x600[] = { 776 /* r_rate, vclk, hsp, vsp */ 777 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 778 {REFRESH_60, CLK_61_500M, M1280x600_R60_HSP, M1280x600_R60_VSP, 779 {1648, 1280, 1280, 368, 1336, 128, 622, 600, 600, 22, 601, 3} } 780}; 781 782/* 1360x768 (CVT) */ 783struct crt_mode_table CRTM1360x768[] = { 784 /* r_rate, vclk, hsp, vsp */ 785 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 786 {REFRESH_60, CLK_84_750M, M1360X768_R60_HSP, M1360X768_R60_VSP, 787 {1776, 1360, 1360, 416, 1432, 136, 798, 768, 768, 30, 771, 5} } 788}; 789 790/* 1360x768 (CVT Reduce Blanking) */ 791struct crt_mode_table CRTM1360x768_RB[] = { 792 /* r_rate, vclk, hsp, vsp */ 793 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 794 {REFRESH_60, CLK_72_000M, M1360X768_RB_R60_HSP, 795 M1360X768_RB_R60_VSP, 796 {1520, 1360, 1360, 160, 1408, 32, 790, 768, 768, 22, 771, 5} } 797}; 798 799/* 1366x768 (GTF) */ 800struct crt_mode_table CRTM1366x768[] = { 801 /* r_rate, vclk, hsp, vsp */ 802 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 803 {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP, 804 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} }, 805 {REFRESH_50, CLK_69_924M, M1368X768_R50_HSP, M1368X768_R50_VSP, 806 {1768, 1368, 1368, 400, 1424, 144, 791, 768, 768, 23, 769, 3} } 807}; 808 809/* 1440x900 (CVT) */ 810struct crt_mode_table CRTM1440x900[] = { 811 /* r_rate, vclk, hsp, vsp */ 812 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 813 {REFRESH_60, CLK_106_500M, M1440X900_R60_HSP, M1440X900_R60_VSP, 814 {1904, 1440, 1440, 464, 1520, 152, 934, 900, 900, 34, 903, 6} }, 815 {REFRESH_75, CLK_136_700M, M1440X900_R75_HSP, M1440X900_R75_VSP, 816 {1936, 1440, 1440, 496, 1536, 152, 942, 900, 900, 42, 903, 6} } 817}; 818 819/* 1440x900 (CVT Reduce Blanking) */ 820struct crt_mode_table CRTM1440x900_RB[] = { 821 /* r_rate, vclk, hsp, vsp */ 822 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 823 {REFRESH_60, CLK_88_750M, M1440X900_RB_R60_HSP, 824 M1440X900_RB_R60_VSP, 825 {1600, 1440, 1440, 160, 1488, 32, 926, 900, 900, 26, 903, 6} } 826}; 827 828/* 1600x900 (CVT) */ 829struct crt_mode_table CRTM1600x900[] = { 830 /* r_rate, vclk, hsp, vsp */ 831 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 832 {REFRESH_60, CLK_118_840M, M1600X900_R60_HSP, M1600X900_R60_VSP, 833 {2112, 1600, 1600, 512, 1688, 168, 934, 900, 900, 34, 903, 5} } 834}; 835 836/* 1600x900 (CVT Reduce Blanking) */ 837struct crt_mode_table CRTM1600x900_RB[] = { 838 /* r_rate, vclk, hsp, vsp */ 839 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 840 {REFRESH_60, CLK_97_750M, M1600X900_RB_R60_HSP, 841 M1600X900_RB_R60_VSP, 842 {1760, 1600, 1600, 160, 1648, 32, 926, 900, 900, 26, 903, 5} } 843}; 844 845/* 1600x1024 (GTF) */ 846struct crt_mode_table CRTM1600x1024[] = { 847 /* r_rate, vclk, hsp, vsp */ 848 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 849 {REFRESH_60, CLK_136_700M, M1600X1024_R60_HSP, M1600X1024_R60_VSP, 850 {2144, 1600, 1600, 544, 1704, 168, 1060, 1024, 1024, 36, 1025, 3} } 851}; 852 853/* 1792x1344 (DMT) */ 854struct crt_mode_table CRTM1792x1344[] = { 855 /* r_rate, vclk, hsp, vsp */ 856 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 857 {REFRESH_60, CLK_204_000M, M1792x1344_R60_HSP, M1792x1344_R60_VSP, 858 {2448, 1792, 1792, 656, 1920, 200, 1394, 1344, 1344, 50, 1345, 3} } 859}; 860 861/* 1856x1392 (DMT) */ 862struct crt_mode_table CRTM1856x1392[] = { 863 /* r_rate, vclk, hsp, vsp */ 864 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 865 {REFRESH_60, CLK_218_500M, M1856x1392_R60_HSP, M1856x1392_R60_VSP, 866 {2528, 1856, 1856, 672, 1952, 224, 1439, 1392, 1392, 47, 1393, 3} } 867}; 868 869/* 1920x1200 (CVT) */ 870struct crt_mode_table CRTM1920x1200[] = { 871 /* r_rate, vclk, hsp, vsp */ 872 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 873 {REFRESH_60, CLK_193_295M, M1920X1200_R60_HSP, M1920X1200_R60_VSP, 874 {2592, 1920, 1920, 672, 2056, 200, 1245, 1200, 1200, 45, 1203, 6} } 875}; 876 877/* 1920x1200 (CVT with Reduce Blanking) */ 878struct crt_mode_table CRTM1920x1200_RB[] = { 879 /* r_rate, vclk, hsp, vsp */ 880 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 881 {REFRESH_60, CLK_153_920M, M1920X1200_RB_R60_HSP, 882 M1920X1200_RB_R60_VSP, 883 {2080, 1920, 1920, 160, 1968, 32, 1235, 1200, 1200, 35, 1203, 6} } 884}; 885 886/* 2048x1536 (CVT) */ 887struct crt_mode_table CRTM2048x1536[] = { 888 /* r_rate, vclk, hsp, vsp */ 889 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 890 {REFRESH_60, CLK_267_250M, M2048x1536_R60_HSP, M2048x1536_R60_VSP, 891 {2800, 2048, 2048, 752, 2200, 224, 1592, 1536, 1536, 56, 1539, 4} } 892}; 893 894struct VideoModeTable viafb_modes[] = { 895 /* Display : 480x640 (GTF) */ 896 {CRTM480x640, ARRAY_SIZE(CRTM480x640)}, 897 898 /* Display : 640x480 */ 899 {CRTM640x480, ARRAY_SIZE(CRTM640x480)}, 900 901 /* Display : 720x480 (GTF) */ 902 {CRTM720x480, ARRAY_SIZE(CRTM720x480)}, 903 904 /* Display : 720x576 (GTF) */ 905 {CRTM720x576, ARRAY_SIZE(CRTM720x576)}, 906 907 /* Display : 800x600 */ 908 {CRTM800x600, ARRAY_SIZE(CRTM800x600)}, 909 910 /* Display : 800x480 (CVT) */ 911 {CRTM800x480, ARRAY_SIZE(CRTM800x480)}, 912 913 /* Display : 848x480 (CVT) */ 914 {CRTM848x480, ARRAY_SIZE(CRTM848x480)}, 915 916 /* Display : 852x480 (GTF) */ 917 {CRTM852x480, ARRAY_SIZE(CRTM852x480)}, 918 919 /* Display : 1024x512 (GTF) */ 920 {CRTM1024x512, ARRAY_SIZE(CRTM1024x512)}, 921 922 /* Display : 1024x600 */ 923 {CRTM1024x600, ARRAY_SIZE(CRTM1024x600)}, 924 925 /* Display : 1024x768 */ 926 {CRTM1024x768, ARRAY_SIZE(CRTM1024x768)}, 927 928 /* Display : 1152x864 */ 929 {CRTM1152x864, ARRAY_SIZE(CRTM1152x864)}, 930 931 /* Display : 1280x768 (GTF) */ 932 {CRTM1280x768, ARRAY_SIZE(CRTM1280x768)}, 933 934 /* Display : 960x600 (CVT) */ 935 {CRTM960x600, ARRAY_SIZE(CRTM960x600)}, 936 937 /* Display : 1000x600 (GTF) */ 938 {CRTM1000x600, ARRAY_SIZE(CRTM1000x600)}, 939 940 /* Display : 1024x576 (GTF) */ 941 {CRTM1024x576, ARRAY_SIZE(CRTM1024x576)}, 942 943 /* Display : 1088x612 (GTF) */ 944 {CRTM1088x612, ARRAY_SIZE(CRTM1088x612)}, 945 946 /* Display : 1152x720 (CVT) */ 947 {CRTM1152x720, ARRAY_SIZE(CRTM1152x720)}, 948 949 /* Display : 1200x720 (GTF) */ 950 {CRTM1200x720, ARRAY_SIZE(CRTM1200x720)}, 951 952 /* Display : 1200x900 (DCON) */ 953 {DCON1200x900, ARRAY_SIZE(DCON1200x900)}, 954 955 /* Display : 1280x600 (GTF) */ 956 {CRTM1280x600, ARRAY_SIZE(CRTM1280x600)}, 957 958 /* Display : 1280x800 (CVT) */ 959 {CRTM1280x800, ARRAY_SIZE(CRTM1280x800)}, 960 961 /* Display : 1280x960 */ 962 {CRTM1280x960, ARRAY_SIZE(CRTM1280x960)}, 963 964 /* Display : 1280x1024 */ 965 {CRTM1280x1024, ARRAY_SIZE(CRTM1280x1024)}, 966 967 /* Display : 1360x768 (CVT) */ 968 {CRTM1360x768, ARRAY_SIZE(CRTM1360x768)}, 969 970 /* Display : 1366x768 */ 971 {CRTM1366x768, ARRAY_SIZE(CRTM1366x768)}, 972 973 /* Display : 1368x768 (GTF) */ 974 {CRTM1368x768, ARRAY_SIZE(CRTM1368x768)}, 975 976 /* Display : 1440x900 (CVT) */ 977 {CRTM1440x900, ARRAY_SIZE(CRTM1440x900)}, 978 979 /* Display : 1440x1050 (GTF) */ 980 {CRTM1440x1050, ARRAY_SIZE(CRTM1440x1050)}, 981 982 /* Display : 1600x900 (CVT) */ 983 {CRTM1600x900, ARRAY_SIZE(CRTM1600x900)}, 984 985 /* Display : 1600x1024 (GTF) */ 986 {CRTM1600x1024, ARRAY_SIZE(CRTM1600x1024)}, 987 988 /* Display : 1600x1200 */ 989 {CRTM1600x1200, ARRAY_SIZE(CRTM1600x1200)}, 990 991 /* Display : 1680x1050 (CVT) */ 992 {CRTM1680x1050, ARRAY_SIZE(CRTM1680x1050)}, 993 994 /* Display : 1792x1344 (DMT) */ 995 {CRTM1792x1344, ARRAY_SIZE(CRTM1792x1344)}, 996 997 /* Display : 1856x1392 (DMT) */ 998 {CRTM1856x1392, ARRAY_SIZE(CRTM1856x1392)}, 999 1000 /* Display : 1920x1440 */ 1001 {CRTM1920x1440, ARRAY_SIZE(CRTM1920x1440)}, 1002 1003 /* Display : 2048x1536 */ 1004 {CRTM2048x1536, ARRAY_SIZE(CRTM2048x1536)}, 1005 1006 /* Display : 1280x720 */ 1007 {CRTM1280x720, ARRAY_SIZE(CRTM1280x720)}, 1008 1009 /* Display : 1920x1080 (CVT) */ 1010 {CRTM1920x1080, ARRAY_SIZE(CRTM1920x1080)}, 1011 1012 /* Display : 1920x1200 (CVT) */ 1013 {CRTM1920x1200, ARRAY_SIZE(CRTM1920x1200)}, 1014 1015 /* Display : 1400x1050 (CVT) */ 1016 {CRTM1400x1050, ARRAY_SIZE(CRTM1400x1050)} 1017}; 1018 1019struct VideoModeTable viafb_rb_modes[] = { 1020 /* Display : 1360x768 (CVT Reduce Blanking) */ 1021 {CRTM1360x768_RB, ARRAY_SIZE(CRTM1360x768_RB)}, 1022 1023 /* Display : 1440x900 (CVT Reduce Blanking) */ 1024 {CRTM1440x900_RB, ARRAY_SIZE(CRTM1440x900_RB)}, 1025 1026 /* Display : 1400x1050 (CVT Reduce Blanking) */ 1027 {CRTM1400x1050_RB, ARRAY_SIZE(CRTM1400x1050_RB)}, 1028 1029 /* Display : 1600x900 (CVT Reduce Blanking) */ 1030 {CRTM1600x900_RB, ARRAY_SIZE(CRTM1600x900_RB)}, 1031 1032 /* Display : 1680x1050 (CVT Reduce Blanking) */ 1033 {CRTM1680x1050_RB, ARRAY_SIZE(CRTM1680x1050_RB)}, 1034 1035 /* Display : 1920x1080 (CVT Reduce Blanking) */ 1036 {CRTM1920x1080_RB, ARRAY_SIZE(CRTM1920x1080_RB)}, 1037 1038 /* Display : 1920x1200 (CVT Reduce Blanking) */ 1039 {CRTM1920x1200_RB, ARRAY_SIZE(CRTM1920x1200_RB)} 1040}; 1041 1042struct crt_mode_table CEAM1280x720[] = { 1043 {REFRESH_60, CLK_74_270M, M1280X720_CEA_R60_HSP, 1044 M1280X720_CEA_R60_VSP, 1045 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 1046 {1650, 1280, 1280, 370, 1390, 40, 750, 720, 720, 30, 725, 5} } 1047}; 1048struct crt_mode_table CEAM1920x1080[] = { 1049 {REFRESH_60, CLK_148_500M, M1920X1080_CEA_R60_HSP, 1050 M1920X1080_CEA_R60_VSP, 1051 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ 1052 {2200, 1920, 1920, 300, 2008, 44, 1125, 1080, 1080, 45, 1084, 5} } 1053}; 1054struct VideoModeTable CEA_HDMI_Modes[] = { 1055 /* Display : 1280x720 */ 1056 {CEAM1280x720, ARRAY_SIZE(CEAM1280x720)}, 1057 {CEAM1920x1080, ARRAY_SIZE(CEAM1920x1080)} 1058}; 1059 1060int NUM_TOTAL_RES_MAP_REFRESH = ARRAY_SIZE(res_map_refresh_tbl); 1061int NUM_TOTAL_CEA_MODES = ARRAY_SIZE(CEA_HDMI_Modes); 1062int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs); 1063int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs); 1064int NUM_TOTAL_KM400_ModeXregs = ARRAY_SIZE(KM400_ModeXregs); 1065int NUM_TOTAL_CX700_ModeXregs = ARRAY_SIZE(CX700_ModeXregs); 1066int NUM_TOTAL_VX855_ModeXregs = ARRAY_SIZE(VX855_ModeXregs); 1067int NUM_TOTAL_CLE266_ModeXregs = ARRAY_SIZE(CLE266_ModeXregs); 1068int NUM_TOTAL_PATCH_MODE = ARRAY_SIZE(res_patch_table); 1069 1070 1071struct VideoModeTable *viafb_get_mode(int hres, int vres) 1072{ 1073 u32 i; 1074 for (i = 0; i < ARRAY_SIZE(viafb_modes); i++) 1075 if (viafb_modes[i].mode_array && 1076 viafb_modes[i].crtc[0].crtc.hor_addr == hres && 1077 viafb_modes[i].crtc[0].crtc.ver_addr == vres) 1078 return &viafb_modes[i]; 1079 1080 return NULL; 1081} 1082 1083struct VideoModeTable *viafb_get_rb_mode(int hres, int vres) 1084{ 1085 u32 i; 1086 for (i = 0; i < ARRAY_SIZE(viafb_rb_modes); i++) 1087 if (viafb_rb_modes[i].mode_array && 1088 viafb_rb_modes[i].crtc[0].crtc.hor_addr == hres && 1089 viafb_rb_modes[i].crtc[0].crtc.ver_addr == vres) 1090 return &viafb_rb_modes[i]; 1091 1092 return NULL; 1093} 1094