1/* 2 * 3 * tdfxfb.c 4 * 5 * Author: Hannu Mallat <hmallat@cc.hut.fi> 6 * 7 * Copyright �� 1999 Hannu Mallat 8 * All rights reserved 9 * 10 * Created : Thu Sep 23 18:17:43 1999, hmallat 11 * Last modified: Tue Nov 2 21:19:47 1999, hmallat 12 * 13 * I2C part copied from the i2c-voodoo3.c driver by: 14 * Frodo Looijaard <frodol@dds.nl>, 15 * Philip Edelbrock <phil@netroedge.com>, 16 * Ralph Metzler <rjkm@thp.uni-koeln.de>, and 17 * Mark D. Studebaker <mdsxyz123@yahoo.com> 18 * 19 * Lots of the information here comes from the Daryll Strauss' Banshee 20 * patches to the XF86 server, and the rest comes from the 3dfx 21 * Banshee specification. I'm very much indebted to Daryll for his 22 * work on the X server. 23 * 24 * Voodoo3 support was contributed Harold Oga. Lots of additions 25 * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila 26 * Kesmarki. Thanks guys! 27 * 28 * Voodoo1 and Voodoo2 support aren't relevant to this driver as they 29 * behave very differently from the Voodoo3/4/5. For anyone wanting to 30 * use frame buffer on the Voodoo1/2, see the sstfb driver (which is 31 * located at http://www.sourceforge.net/projects/sstfb). 32 * 33 * While I _am_ grateful to 3Dfx for releasing the specs for Banshee, 34 * I do wish the next version is a bit more complete. Without the XF86 35 * patches I couldn't have gotten even this far... for instance, the 36 * extensions to the VGA register set go completely unmentioned in the 37 * spec! Also, lots of references are made to the 'SST core', but no 38 * spec is publicly available, AFAIK. 39 * 40 * The structure of this driver comes pretty much from the Permedia 41 * driver by Ilario Nardinocchi, which in turn is based on skeletonfb. 42 * 43 * TODO: 44 * - multihead support (basically need to support an array of fb_infos) 45 * - support other architectures (PPC, Alpha); does the fact that the VGA 46 * core can be accessed only thru I/O (not memory mapped) complicate 47 * things? 48 * 49 * Version history: 50 * 51 * 0.1.4 (released 2002-05-28) ported over to new fbdev api by James Simmons 52 * 53 * 0.1.3 (released 1999-11-02) added Attila's panning support, code 54 * reorg, hwcursor address page size alignment 55 * (for mmapping both frame buffer and regs), 56 * and my changes to get rid of hardcoded 57 * VGA i/o register locations (uses PCI 58 * configuration info now) 59 * 0.1.2 (released 1999-10-19) added Attila Kesmarki's bug fixes and 60 * improvements 61 * 0.1.1 (released 1999-10-07) added Voodoo3 support by Harold Oga. 62 * 0.1.0 (released 1999-10-06) initial version 63 * 64 */ 65 66#include <linux/module.h> 67#include <linux/kernel.h> 68#include <linux/errno.h> 69#include <linux/string.h> 70#include <linux/mm.h> 71#include <linux/slab.h> 72#include <linux/fb.h> 73#include <linux/init.h> 74#include <linux/pci.h> 75#include <asm/io.h> 76 77#include <video/tdfx.h> 78 79#define DPRINTK(a, b...) pr_debug("fb: %s: " a, __func__ , ## b) 80 81#ifdef CONFIG_MTRR 82#include <asm/mtrr.h> 83#else 84/* duplicate asm/mtrr.h defines to work on archs without mtrr */ 85#define MTRR_TYPE_WRCOMB 1 86 87static inline int mtrr_add(unsigned long base, unsigned long size, 88 unsigned int type, char increment) 89{ 90 return -ENODEV; 91} 92static inline int mtrr_del(int reg, unsigned long base, 93 unsigned long size) 94{ 95 return -ENODEV; 96} 97#endif 98 99#define BANSHEE_MAX_PIXCLOCK 270000 100#define VOODOO3_MAX_PIXCLOCK 300000 101#define VOODOO5_MAX_PIXCLOCK 350000 102 103static struct fb_fix_screeninfo tdfx_fix __devinitdata = { 104 .type = FB_TYPE_PACKED_PIXELS, 105 .visual = FB_VISUAL_PSEUDOCOLOR, 106 .ypanstep = 1, 107 .ywrapstep = 1, 108 .accel = FB_ACCEL_3DFX_BANSHEE 109}; 110 111static struct fb_var_screeninfo tdfx_var __devinitdata = { 112 /* "640x480, 8 bpp @ 60 Hz */ 113 .xres = 640, 114 .yres = 480, 115 .xres_virtual = 640, 116 .yres_virtual = 1024, 117 .bits_per_pixel = 8, 118 .red = {0, 8, 0}, 119 .blue = {0, 8, 0}, 120 .green = {0, 8, 0}, 121 .activate = FB_ACTIVATE_NOW, 122 .height = -1, 123 .width = -1, 124 .accel_flags = FB_ACCELF_TEXT, 125 .pixclock = 39722, 126 .left_margin = 40, 127 .right_margin = 24, 128 .upper_margin = 32, 129 .lower_margin = 11, 130 .hsync_len = 96, 131 .vsync_len = 2, 132 .vmode = FB_VMODE_NONINTERLACED 133}; 134 135/* 136 * PCI driver prototypes 137 */ 138static int __devinit tdfxfb_probe(struct pci_dev *pdev, 139 const struct pci_device_id *id); 140static void __devexit tdfxfb_remove(struct pci_dev *pdev); 141 142static struct pci_device_id tdfxfb_id_table[] = { 143 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE, 144 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, 145 0xff0000, 0 }, 146 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3, 147 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, 148 0xff0000, 0 }, 149 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO5, 150 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, 151 0xff0000, 0 }, 152 { 0, } 153}; 154 155static struct pci_driver tdfxfb_driver = { 156 .name = "tdfxfb", 157 .id_table = tdfxfb_id_table, 158 .probe = tdfxfb_probe, 159 .remove = __devexit_p(tdfxfb_remove), 160}; 161 162MODULE_DEVICE_TABLE(pci, tdfxfb_id_table); 163 164/* 165 * Driver data 166 */ 167static int nopan; 168static int nowrap = 1; /* not implemented (yet) */ 169static int hwcursor = 1; 170static char *mode_option __devinitdata; 171/* mtrr option */ 172static int nomtrr __devinitdata; 173 174/* ------------------------------------------------------------------------- 175 * Hardware-specific funcions 176 * ------------------------------------------------------------------------- */ 177 178static inline u8 vga_inb(struct tdfx_par *par, u32 reg) 179{ 180 return inb(par->iobase + reg - 0x300); 181} 182 183static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) 184{ 185 outb(val, par->iobase + reg - 0x300); 186} 187 188static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val) 189{ 190 vga_outb(par, GRA_I, idx); 191 wmb(); 192 vga_outb(par, GRA_D, val); 193 wmb(); 194} 195 196static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val) 197{ 198 vga_outb(par, SEQ_I, idx); 199 wmb(); 200 vga_outb(par, SEQ_D, val); 201 wmb(); 202} 203 204static inline u8 seq_inb(struct tdfx_par *par, u32 idx) 205{ 206 vga_outb(par, SEQ_I, idx); 207 mb(); 208 return vga_inb(par, SEQ_D); 209} 210 211static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val) 212{ 213 vga_outb(par, CRT_I, idx); 214 wmb(); 215 vga_outb(par, CRT_D, val); 216 wmb(); 217} 218 219static inline u8 crt_inb(struct tdfx_par *par, u32 idx) 220{ 221 vga_outb(par, CRT_I, idx); 222 mb(); 223 return vga_inb(par, CRT_D); 224} 225 226static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val) 227{ 228 unsigned char tmp; 229 230 tmp = vga_inb(par, IS1_R); 231 vga_outb(par, ATT_IW, idx); 232 vga_outb(par, ATT_IW, val); 233} 234 235static inline void vga_disable_video(struct tdfx_par *par) 236{ 237 unsigned char s; 238 239 s = seq_inb(par, 0x01) | 0x20; 240 seq_outb(par, 0x00, 0x01); 241 seq_outb(par, 0x01, s); 242 seq_outb(par, 0x00, 0x03); 243} 244 245static inline void vga_enable_video(struct tdfx_par *par) 246{ 247 unsigned char s; 248 249 s = seq_inb(par, 0x01) & 0xdf; 250 seq_outb(par, 0x00, 0x01); 251 seq_outb(par, 0x01, s); 252 seq_outb(par, 0x00, 0x03); 253} 254 255static inline void vga_enable_palette(struct tdfx_par *par) 256{ 257 vga_inb(par, IS1_R); 258 mb(); 259 vga_outb(par, ATT_IW, 0x20); 260} 261 262static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg) 263{ 264 return readl(par->regbase_virt + reg); 265} 266 267static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val) 268{ 269 writel(val, par->regbase_virt + reg); 270} 271 272static inline void banshee_make_room(struct tdfx_par *par, int size) 273{ 274 /* Note: The Voodoo3's onboard FIFO has 32 slots. This loop 275 * won't quit if you ask for more. */ 276 while ((tdfx_inl(par, STATUS) & 0x1f) < size - 1) 277 cpu_relax(); 278} 279 280static int banshee_wait_idle(struct fb_info *info) 281{ 282 struct tdfx_par *par = info->par; 283 int i = 0; 284 285 banshee_make_room(par, 1); 286 tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP); 287 288 do { 289 if ((tdfx_inl(par, STATUS) & STATUS_BUSY) == 0) 290 i++; 291 } while (i < 3); 292 293 return 0; 294} 295 296/* 297 * Set the color of a palette entry in 8bpp mode 298 */ 299static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c) 300{ 301 banshee_make_room(par, 2); 302 tdfx_outl(par, DACADDR, regno); 303 /* read after write makes it working */ 304 tdfx_inl(par, DACADDR); 305 tdfx_outl(par, DACDATA, c); 306} 307 308static u32 do_calc_pll(int freq, int *freq_out) 309{ 310 int m, n, k, best_m, best_n, best_k, best_error; 311 int fref = 14318; 312 313 best_error = freq; 314 best_n = best_m = best_k = 0; 315 316 for (k = 3; k >= 0; k--) { 317 for (m = 63; m >= 0; m--) { 318 /* 319 * Estimate value of n that produces target frequency 320 * with current m and k 321 */ 322 int n_estimated = ((freq * (m + 2) << k) / fref) - 2; 323 324 /* Search neighborhood of estimated n */ 325 for (n = max(0, n_estimated); 326 n <= min(255, n_estimated + 1); 327 n++) { 328 /* 329 * Calculate PLL freqency with current m, k and 330 * estimated n 331 */ 332 int f = (fref * (n + 2) / (m + 2)) >> k; 333 int error = abs(f - freq); 334 335 /* 336 * If this is the closest we've come to the 337 * target frequency then remember n, m and k 338 */ 339 if (error < best_error) { 340 best_error = error; 341 best_n = n; 342 best_m = m; 343 best_k = k; 344 } 345 } 346 } 347 } 348 349 n = best_n; 350 m = best_m; 351 k = best_k; 352 *freq_out = (fref * (n + 2) / (m + 2)) >> k; 353 354 return (n << 8) | (m << 2) | k; 355} 356 357static void do_write_regs(struct fb_info *info, struct banshee_reg *reg) 358{ 359 struct tdfx_par *par = info->par; 360 int i; 361 362 banshee_wait_idle(info); 363 364 tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01); 365 366 crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */ 367 368 banshee_make_room(par, 3); 369 tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF); 370 tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001); 371 tdfx_outl(par, PLLCTRL0, reg->vidpll); 372 373 vga_outb(par, MISC_W, reg->misc[0x00] | 0x01); 374 375 for (i = 0; i < 5; i++) 376 seq_outb(par, i, reg->seq[i]); 377 378 for (i = 0; i < 25; i++) 379 crt_outb(par, i, reg->crt[i]); 380 381 for (i = 0; i < 9; i++) 382 gra_outb(par, i, reg->gra[i]); 383 384 for (i = 0; i < 21; i++) 385 att_outb(par, i, reg->att[i]); 386 387 crt_outb(par, 0x1a, reg->ext[0]); 388 crt_outb(par, 0x1b, reg->ext[1]); 389 390 vga_enable_palette(par); 391 vga_enable_video(par); 392 393 banshee_make_room(par, 9); 394 tdfx_outl(par, VGAINIT0, reg->vgainit0); 395 tdfx_outl(par, DACMODE, reg->dacmode); 396 tdfx_outl(par, VIDDESKSTRIDE, reg->stride); 397 tdfx_outl(par, HWCURPATADDR, reg->curspataddr); 398 399 tdfx_outl(par, VIDSCREENSIZE, reg->screensize); 400 tdfx_outl(par, VIDDESKSTART, reg->startaddr); 401 tdfx_outl(par, VIDPROCCFG, reg->vidcfg); 402 tdfx_outl(par, VGAINIT1, reg->vgainit1); 403 tdfx_outl(par, MISCINIT0, reg->miscinit0); 404 405 banshee_make_room(par, 8); 406 tdfx_outl(par, SRCBASE, reg->startaddr); 407 tdfx_outl(par, DSTBASE, reg->startaddr); 408 tdfx_outl(par, COMMANDEXTRA_2D, 0); 409 tdfx_outl(par, CLIP0MIN, 0); 410 tdfx_outl(par, CLIP0MAX, 0x0fff0fff); 411 tdfx_outl(par, CLIP1MIN, 0); 412 tdfx_outl(par, CLIP1MAX, 0x0fff0fff); 413 tdfx_outl(par, SRCXY, 0); 414 415 banshee_wait_idle(info); 416} 417 418static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id) 419{ 420 u32 draminit0 = tdfx_inl(par, DRAMINIT0); 421 u32 draminit1 = tdfx_inl(par, DRAMINIT1); 422 u32 miscinit1; 423 int num_chips = (draminit0 & DRAMINIT0_SGRAM_NUM) ? 8 : 4; 424 int chip_size; /* in MB */ 425 int has_sgram = draminit1 & DRAMINIT1_MEM_SDRAM; 426 427 if (dev_id < PCI_DEVICE_ID_3DFX_VOODOO5) { 428 /* Banshee/Voodoo3 */ 429 chip_size = 2; 430 if (has_sgram && !(draminit0 & DRAMINIT0_SGRAM_TYPE)) 431 chip_size = 1; 432 } else { 433 /* Voodoo4/5 */ 434 has_sgram = 0; 435 chip_size = draminit0 & DRAMINIT0_SGRAM_TYPE_MASK; 436 chip_size = 1 << (chip_size >> DRAMINIT0_SGRAM_TYPE_SHIFT); 437 } 438 439 /* disable block writes for SDRAM */ 440 miscinit1 = tdfx_inl(par, MISCINIT1); 441 miscinit1 |= has_sgram ? 0 : MISCINIT1_2DBLOCK_DIS; 442 miscinit1 |= MISCINIT1_CLUT_INV; 443 444 banshee_make_room(par, 1); 445 tdfx_outl(par, MISCINIT1, miscinit1); 446 return num_chips * chip_size * 1024l * 1024; 447} 448 449/* ------------------------------------------------------------------------- */ 450 451static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 452{ 453 struct tdfx_par *par = info->par; 454 u32 lpitch; 455 456 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 && 457 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) { 458 DPRINTK("depth not supported: %u\n", var->bits_per_pixel); 459 return -EINVAL; 460 } 461 462 if (var->xres != var->xres_virtual) 463 var->xres_virtual = var->xres; 464 465 if (var->yres > var->yres_virtual) 466 var->yres_virtual = var->yres; 467 468 if (var->xoffset) { 469 DPRINTK("xoffset not supported\n"); 470 return -EINVAL; 471 } 472 var->yoffset = 0; 473 474 /* 475 * Banshee doesn't support interlace, but Voodoo4/5 and probably 476 * Voodoo3 do. 477 * no direct information about device id now? 478 * use max_pixclock for this... 479 */ 480 if (((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) && 481 (par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) { 482 DPRINTK("interlace not supported\n"); 483 return -EINVAL; 484 } 485 486 if (info->monspecs.hfmax && info->monspecs.vfmax && 487 info->monspecs.dclkmax && fb_validate_mode(var, info) < 0) { 488 DPRINTK("mode outside monitor's specs\n"); 489 return -EINVAL; 490 } 491 492 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */ 493 lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3); 494 495 if (var->xres < 320 || var->xres > 2048) { 496 DPRINTK("width not supported: %u\n", var->xres); 497 return -EINVAL; 498 } 499 500 if (var->yres < 200 || var->yres > 2048) { 501 DPRINTK("height not supported: %u\n", var->yres); 502 return -EINVAL; 503 } 504 505 if (lpitch * var->yres_virtual > info->fix.smem_len) { 506 var->yres_virtual = info->fix.smem_len / lpitch; 507 if (var->yres_virtual < var->yres) { 508 DPRINTK("no memory for screen (%ux%ux%u)\n", 509 var->xres, var->yres_virtual, 510 var->bits_per_pixel); 511 return -EINVAL; 512 } 513 } 514 515 if (PICOS2KHZ(var->pixclock) > par->max_pixclock) { 516 DPRINTK("pixclock too high (%ldKHz)\n", 517 PICOS2KHZ(var->pixclock)); 518 return -EINVAL; 519 } 520 521 var->transp.offset = 0; 522 var->transp.length = 0; 523 switch (var->bits_per_pixel) { 524 case 8: 525 var->red.length = 8; 526 var->red.offset = 0; 527 var->green = var->red; 528 var->blue = var->red; 529 break; 530 case 16: 531 var->red.offset = 11; 532 var->red.length = 5; 533 var->green.offset = 5; 534 var->green.length = 6; 535 var->blue.offset = 0; 536 var->blue.length = 5; 537 break; 538 case 32: 539 var->transp.offset = 24; 540 var->transp.length = 8; 541 case 24: 542 var->red.offset = 16; 543 var->green.offset = 8; 544 var->blue.offset = 0; 545 var->red.length = var->green.length = var->blue.length = 8; 546 break; 547 } 548 var->width = -1; 549 var->height = -1; 550 551 var->accel_flags = FB_ACCELF_TEXT; 552 553 DPRINTK("Checking graphics mode at %dx%d depth %d\n", 554 var->xres, var->yres, var->bits_per_pixel); 555 return 0; 556} 557 558static int tdfxfb_set_par(struct fb_info *info) 559{ 560 struct tdfx_par *par = info->par; 561 u32 hdispend = info->var.xres; 562 u32 hsyncsta = hdispend + info->var.right_margin; 563 u32 hsyncend = hsyncsta + info->var.hsync_len; 564 u32 htotal = hsyncend + info->var.left_margin; 565 u32 hd, hs, he, ht, hbs, hbe; 566 u32 vd, vs, ve, vt, vbs, vbe; 567 struct banshee_reg reg; 568 int fout, freq; 569 u32 wd; 570 u32 cpp = (info->var.bits_per_pixel + 7) >> 3; 571 572 memset(®, 0, sizeof(reg)); 573 574 reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE | 575 VIDCFG_CURS_X11 | 576 ((cpp - 1) << VIDCFG_PIXFMT_SHIFT) | 577 (cpp != 1 ? VIDCFG_CLUT_BYPASS : 0); 578 579 /* PLL settings */ 580 freq = PICOS2KHZ(info->var.pixclock); 581 582 reg.vidcfg &= ~VIDCFG_2X; 583 584 if (freq > par->max_pixclock / 2) { 585 freq = freq > par->max_pixclock ? par->max_pixclock : freq; 586 reg.dacmode |= DACMODE_2X; 587 reg.vidcfg |= VIDCFG_2X; 588 hdispend >>= 1; 589 hsyncsta >>= 1; 590 hsyncend >>= 1; 591 htotal >>= 1; 592 } 593 594 wd = (hdispend >> 3) - 1; 595 hd = wd; 596 hs = (hsyncsta >> 3) - 1; 597 he = (hsyncend >> 3) - 1; 598 ht = (htotal >> 3) - 1; 599 hbs = hd; 600 hbe = ht; 601 602 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) { 603 vd = (info->var.yres << 1) - 1; 604 vs = vd + (info->var.lower_margin << 1); 605 ve = vs + (info->var.vsync_len << 1); 606 vt = ve + (info->var.upper_margin << 1) - 1; 607 reg.screensize = info->var.xres | (info->var.yres << 13); 608 reg.vidcfg |= VIDCFG_HALF_MODE; 609 reg.crt[0x09] = 0x80; 610 } else { 611 vd = info->var.yres - 1; 612 vs = vd + info->var.lower_margin; 613 ve = vs + info->var.vsync_len; 614 vt = ve + info->var.upper_margin - 1; 615 reg.screensize = info->var.xres | (info->var.yres << 12); 616 reg.vidcfg &= ~VIDCFG_HALF_MODE; 617 } 618 vbs = vd; 619 vbe = vt; 620 621 /* this is all pretty standard VGA register stuffing */ 622 reg.misc[0x00] = 0x0f | 623 (info->var.xres < 400 ? 0xa0 : 624 info->var.xres < 480 ? 0x60 : 625 info->var.xres < 768 ? 0xe0 : 0x20); 626 627 reg.gra[0x05] = 0x40; 628 reg.gra[0x06] = 0x05; 629 reg.gra[0x07] = 0x0f; 630 reg.gra[0x08] = 0xff; 631 632 reg.att[0x00] = 0x00; 633 reg.att[0x01] = 0x01; 634 reg.att[0x02] = 0x02; 635 reg.att[0x03] = 0x03; 636 reg.att[0x04] = 0x04; 637 reg.att[0x05] = 0x05; 638 reg.att[0x06] = 0x06; 639 reg.att[0x07] = 0x07; 640 reg.att[0x08] = 0x08; 641 reg.att[0x09] = 0x09; 642 reg.att[0x0a] = 0x0a; 643 reg.att[0x0b] = 0x0b; 644 reg.att[0x0c] = 0x0c; 645 reg.att[0x0d] = 0x0d; 646 reg.att[0x0e] = 0x0e; 647 reg.att[0x0f] = 0x0f; 648 reg.att[0x10] = 0x41; 649 reg.att[0x12] = 0x0f; 650 651 reg.seq[0x00] = 0x03; 652 reg.seq[0x01] = 0x01; 653 reg.seq[0x02] = 0x0f; 654 reg.seq[0x03] = 0x00; 655 reg.seq[0x04] = 0x0e; 656 657 reg.crt[0x00] = ht - 4; 658 reg.crt[0x01] = hd; 659 reg.crt[0x02] = hbs; 660 reg.crt[0x03] = 0x80 | (hbe & 0x1f); 661 reg.crt[0x04] = hs; 662 reg.crt[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f); 663 reg.crt[0x06] = vt; 664 reg.crt[0x07] = ((vs & 0x200) >> 2) | 665 ((vd & 0x200) >> 3) | 666 ((vt & 0x200) >> 4) | 0x10 | 667 ((vbs & 0x100) >> 5) | 668 ((vs & 0x100) >> 6) | 669 ((vd & 0x100) >> 7) | 670 ((vt & 0x100) >> 8); 671 reg.crt[0x09] |= 0x40 | ((vbs & 0x200) >> 4); 672 reg.crt[0x10] = vs; 673 reg.crt[0x11] = (ve & 0x0f) | 0x20; 674 reg.crt[0x12] = vd; 675 reg.crt[0x13] = wd; 676 reg.crt[0x15] = vbs; 677 reg.crt[0x16] = vbe + 1; 678 reg.crt[0x17] = 0xc3; 679 reg.crt[0x18] = 0xff; 680 681 /* Banshee's nonvga stuff */ 682 reg.ext[0x00] = (((ht & 0x100) >> 8) | 683 ((hd & 0x100) >> 6) | 684 ((hbs & 0x100) >> 4) | 685 ((hbe & 0x40) >> 1) | 686 ((hs & 0x100) >> 2) | 687 ((he & 0x20) << 2)); 688 reg.ext[0x01] = (((vt & 0x400) >> 10) | 689 ((vd & 0x400) >> 8) | 690 ((vbs & 0x400) >> 6) | 691 ((vbe & 0x400) >> 4)); 692 693 reg.vgainit0 = VGAINIT0_8BIT_DAC | 694 VGAINIT0_EXT_ENABLE | 695 VGAINIT0_WAKEUP_3C3 | 696 VGAINIT0_ALT_READBACK | 697 VGAINIT0_EXTSHIFTOUT; 698 reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff; 699 700 if (hwcursor) 701 reg.curspataddr = info->fix.smem_len; 702 703 reg.cursloc = 0; 704 705 reg.cursc0 = 0; 706 reg.cursc1 = 0xffffff; 707 708 reg.stride = info->var.xres * cpp; 709 reg.startaddr = info->var.yoffset * reg.stride 710 + info->var.xoffset * cpp; 711 712 reg.vidpll = do_calc_pll(freq, &fout); 713 714 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) 715 reg.vidcfg |= VIDCFG_INTERLACE; 716 reg.miscinit0 = tdfx_inl(par, MISCINIT0); 717 718#if defined(__BIG_ENDIAN) 719 switch (info->var.bits_per_pixel) { 720 case 8: 721 case 24: 722 reg.miscinit0 &= ~(1 << 30); 723 reg.miscinit0 &= ~(1 << 31); 724 break; 725 case 16: 726 reg.miscinit0 |= (1 << 30); 727 reg.miscinit0 |= (1 << 31); 728 break; 729 case 32: 730 reg.miscinit0 |= (1 << 30); 731 reg.miscinit0 &= ~(1 << 31); 732 break; 733 } 734#endif 735 do_write_regs(info, ®); 736 737 /* Now change fb_fix_screeninfo according to changes in par */ 738 info->fix.line_length = reg.stride; 739 info->fix.visual = (info->var.bits_per_pixel == 8) 740 ? FB_VISUAL_PSEUDOCOLOR 741 : FB_VISUAL_TRUECOLOR; 742 DPRINTK("Graphics mode is now set at %dx%d depth %d\n", 743 info->var.xres, info->var.yres, info->var.bits_per_pixel); 744 return 0; 745} 746 747/* A handy macro shamelessly pinched from matroxfb */ 748#define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16) 749 750static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green, 751 unsigned blue, unsigned transp, 752 struct fb_info *info) 753{ 754 struct tdfx_par *par = info->par; 755 u32 rgbcol; 756 757 if (regno >= info->cmap.len || regno > 255) 758 return 1; 759 760 /* grayscale works only partially under directcolor */ 761 if (info->var.grayscale) { 762 /* grayscale = 0.30*R + 0.59*G + 0.11*B */ 763 blue = (red * 77 + green * 151 + blue * 28) >> 8; 764 green = blue; 765 red = blue; 766 } 767 768 switch (info->fix.visual) { 769 case FB_VISUAL_PSEUDOCOLOR: 770 rgbcol = (((u32)red & 0xff00) << 8) | 771 (((u32)green & 0xff00) << 0) | 772 (((u32)blue & 0xff00) >> 8); 773 do_setpalentry(par, regno, rgbcol); 774 break; 775 /* Truecolor has no hardware color palettes. */ 776 case FB_VISUAL_TRUECOLOR: 777 if (regno < 16) { 778 rgbcol = (CNVT_TOHW(red, info->var.red.length) << 779 info->var.red.offset) | 780 (CNVT_TOHW(green, info->var.green.length) << 781 info->var.green.offset) | 782 (CNVT_TOHW(blue, info->var.blue.length) << 783 info->var.blue.offset) | 784 (CNVT_TOHW(transp, info->var.transp.length) << 785 info->var.transp.offset); 786 par->palette[regno] = rgbcol; 787 } 788 789 break; 790 default: 791 DPRINTK("bad depth %u\n", info->var.bits_per_pixel); 792 break; 793 } 794 795 return 0; 796} 797 798/* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */ 799static int tdfxfb_blank(int blank, struct fb_info *info) 800{ 801 struct tdfx_par *par = info->par; 802 int vgablank = 1; 803 u32 dacmode = tdfx_inl(par, DACMODE); 804 805 dacmode &= ~(BIT(1) | BIT(3)); 806 807 switch (blank) { 808 case FB_BLANK_UNBLANK: /* Screen: On; HSync: On, VSync: On */ 809 vgablank = 0; 810 break; 811 case FB_BLANK_NORMAL: /* Screen: Off; HSync: On, VSync: On */ 812 break; 813 case FB_BLANK_VSYNC_SUSPEND: /* Screen: Off; HSync: On, VSync: Off */ 814 dacmode |= BIT(3); 815 break; 816 case FB_BLANK_HSYNC_SUSPEND: /* Screen: Off; HSync: Off, VSync: On */ 817 dacmode |= BIT(1); 818 break; 819 case FB_BLANK_POWERDOWN: /* Screen: Off; HSync: Off, VSync: Off */ 820 dacmode |= BIT(1) | BIT(3); 821 break; 822 } 823 824 banshee_make_room(par, 1); 825 tdfx_outl(par, DACMODE, dacmode); 826 if (vgablank) 827 vga_disable_video(par); 828 else 829 vga_enable_video(par); 830 return 0; 831} 832 833/* 834 * Set the starting position of the visible screen to var->yoffset 835 */ 836static int tdfxfb_pan_display(struct fb_var_screeninfo *var, 837 struct fb_info *info) 838{ 839 struct tdfx_par *par = info->par; 840 u32 addr = var->yoffset * info->fix.line_length; 841 842 if (nopan || var->xoffset) 843 return -EINVAL; 844 845 banshee_make_room(par, 1); 846 tdfx_outl(par, VIDDESKSTART, addr); 847 848 return 0; 849} 850 851#ifdef CONFIG_FB_3DFX_ACCEL 852/* 853 * FillRect 2D command (solidfill or invert (via ROP_XOR)) 854 */ 855static void tdfxfb_fillrect(struct fb_info *info, 856 const struct fb_fillrect *rect) 857{ 858 struct tdfx_par *par = info->par; 859 u32 bpp = info->var.bits_per_pixel; 860 u32 stride = info->fix.line_length; 861 u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13); 862 int tdfx_rop; 863 u32 dx = rect->dx; 864 u32 dy = rect->dy; 865 u32 dstbase = 0; 866 867 if (rect->rop == ROP_COPY) 868 tdfx_rop = TDFX_ROP_COPY; 869 else 870 tdfx_rop = TDFX_ROP_XOR; 871 872 /* asume always rect->height < 4096 */ 873 if (dy + rect->height > 4095) { 874 dstbase = stride * dy; 875 dy = 0; 876 } 877 /* asume always rect->width < 4096 */ 878 if (dx + rect->width > 4095) { 879 dstbase += dx * bpp >> 3; 880 dx = 0; 881 } 882 banshee_make_room(par, 6); 883 tdfx_outl(par, DSTFORMAT, fmt); 884 if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) { 885 tdfx_outl(par, COLORFORE, rect->color); 886 } else { /* FB_VISUAL_TRUECOLOR */ 887 tdfx_outl(par, COLORFORE, par->palette[rect->color]); 888 } 889 tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24)); 890 tdfx_outl(par, DSTBASE, dstbase); 891 tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16)); 892 tdfx_outl(par, LAUNCH_2D, dx | (dy << 16)); 893} 894 895/* 896 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.) 897 */ 898static void tdfxfb_copyarea(struct fb_info *info, 899 const struct fb_copyarea *area) 900{ 901 struct tdfx_par *par = info->par; 902 u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy; 903 u32 bpp = info->var.bits_per_pixel; 904 u32 stride = info->fix.line_length; 905 u32 blitcmd = COMMAND_2D_S2S_BITBLT | (TDFX_ROP_COPY << 24); 906 u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13); 907 u32 dstbase = 0; 908 u32 srcbase = 0; 909 910 /* asume always area->height < 4096 */ 911 if (sy + area->height > 4095) { 912 srcbase = stride * sy; 913 sy = 0; 914 } 915 /* asume always area->width < 4096 */ 916 if (sx + area->width > 4095) { 917 srcbase += sx * bpp >> 3; 918 sx = 0; 919 } 920 /* asume always area->height < 4096 */ 921 if (dy + area->height > 4095) { 922 dstbase = stride * dy; 923 dy = 0; 924 } 925 /* asume always area->width < 4096 */ 926 if (dx + area->width > 4095) { 927 dstbase += dx * bpp >> 3; 928 dx = 0; 929 } 930 931 if (area->sx <= area->dx) { 932 /* -X */ 933 blitcmd |= BIT(14); 934 sx += area->width - 1; 935 dx += area->width - 1; 936 } 937 if (area->sy <= area->dy) { 938 /* -Y */ 939 blitcmd |= BIT(15); 940 sy += area->height - 1; 941 dy += area->height - 1; 942 } 943 944 banshee_make_room(par, 8); 945 946 tdfx_outl(par, SRCFORMAT, fmt); 947 tdfx_outl(par, DSTFORMAT, fmt); 948 tdfx_outl(par, COMMAND_2D, blitcmd); 949 tdfx_outl(par, DSTSIZE, area->width | (area->height << 16)); 950 tdfx_outl(par, DSTXY, dx | (dy << 16)); 951 tdfx_outl(par, SRCBASE, srcbase); 952 tdfx_outl(par, DSTBASE, dstbase); 953 tdfx_outl(par, LAUNCH_2D, sx | (sy << 16)); 954} 955 956static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image) 957{ 958 struct tdfx_par *par = info->par; 959 int size = image->height * ((image->width * image->depth + 7) >> 3); 960 int fifo_free; 961 int i, stride = info->fix.line_length; 962 u32 bpp = info->var.bits_per_pixel; 963 u32 dstfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13); 964 u8 *chardata = (u8 *) image->data; 965 u32 srcfmt; 966 u32 dx = image->dx; 967 u32 dy = image->dy; 968 u32 dstbase = 0; 969 970 if (image->depth != 1) { 971#ifdef BROKEN_CODE 972 banshee_make_room(par, 6 + ((size + 3) >> 2)); 973 srcfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13) | 974 0x400000; 975#else 976 cfb_imageblit(info, image); 977#endif 978 return; 979 } 980 banshee_make_room(par, 9); 981 switch (info->fix.visual) { 982 case FB_VISUAL_PSEUDOCOLOR: 983 tdfx_outl(par, COLORFORE, image->fg_color); 984 tdfx_outl(par, COLORBACK, image->bg_color); 985 break; 986 case FB_VISUAL_TRUECOLOR: 987 default: 988 tdfx_outl(par, COLORFORE, 989 par->palette[image->fg_color]); 990 tdfx_outl(par, COLORBACK, 991 par->palette[image->bg_color]); 992 } 993#ifdef __BIG_ENDIAN 994 srcfmt = 0x400000 | BIT(20); 995#else 996 srcfmt = 0x400000; 997#endif 998 /* asume always image->height < 4096 */ 999 if (dy + image->height > 4095) { 1000 dstbase = stride * dy; 1001 dy = 0; 1002 } 1003 /* asume always image->width < 4096 */ 1004 if (dx + image->width > 4095) { 1005 dstbase += dx * bpp >> 3; 1006 dx = 0; 1007 } 1008 1009 tdfx_outl(par, DSTBASE, dstbase); 1010 tdfx_outl(par, SRCXY, 0); 1011 tdfx_outl(par, DSTXY, dx | (dy << 16)); 1012 tdfx_outl(par, COMMAND_2D, 1013 COMMAND_2D_H2S_BITBLT | (TDFX_ROP_COPY << 24)); 1014 tdfx_outl(par, SRCFORMAT, srcfmt); 1015 tdfx_outl(par, DSTFORMAT, dstfmt); 1016 tdfx_outl(par, DSTSIZE, image->width | (image->height << 16)); 1017 1018 /* A count of how many free FIFO entries we've requested. 1019 * When this goes negative, we need to request more. */ 1020 fifo_free = 0; 1021 1022 /* Send four bytes at a time of data */ 1023 for (i = (size >> 2); i > 0; i--) { 1024 if (--fifo_free < 0) { 1025 fifo_free = 31; 1026 banshee_make_room(par, fifo_free); 1027 } 1028 tdfx_outl(par, LAUNCH_2D, *(u32 *)chardata); 1029 chardata += 4; 1030 } 1031 1032 /* Send the leftovers now */ 1033 banshee_make_room(par, 3); 1034 switch (size % 4) { 1035 case 0: 1036 break; 1037 case 1: 1038 tdfx_outl(par, LAUNCH_2D, *chardata); 1039 break; 1040 case 2: 1041 tdfx_outl(par, LAUNCH_2D, *(u16 *)chardata); 1042 break; 1043 case 3: 1044 tdfx_outl(par, LAUNCH_2D, 1045 *(u16 *)chardata | (chardata[3] << 24)); 1046 break; 1047 } 1048} 1049#endif /* CONFIG_FB_3DFX_ACCEL */ 1050 1051static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor) 1052{ 1053 struct tdfx_par *par = info->par; 1054 u32 vidcfg; 1055 1056 if (!hwcursor) 1057 return -EINVAL; /* just to force soft_cursor() call */ 1058 1059 /* Too large of a cursor or wrong bpp :-( */ 1060 if (cursor->image.width > 64 || 1061 cursor->image.height > 64 || 1062 cursor->image.depth > 1) 1063 return -EINVAL; 1064 1065 vidcfg = tdfx_inl(par, VIDPROCCFG); 1066 if (cursor->enable) 1067 tdfx_outl(par, VIDPROCCFG, vidcfg | VIDCFG_HWCURSOR_ENABLE); 1068 else 1069 tdfx_outl(par, VIDPROCCFG, vidcfg & ~VIDCFG_HWCURSOR_ENABLE); 1070 1071 /* 1072 * If the cursor is not be changed this means either we want the 1073 * current cursor state (if enable is set) or we want to query what 1074 * we can do with the cursor (if enable is not set) 1075 */ 1076 if (!cursor->set) 1077 return 0; 1078 1079 /* fix cursor color - XFree86 forgets to restore it properly */ 1080 if (cursor->set & FB_CUR_SETCMAP) { 1081 struct fb_cmap cmap = info->cmap; 1082 u32 bg_idx = cursor->image.bg_color; 1083 u32 fg_idx = cursor->image.fg_color; 1084 unsigned long bg_color, fg_color; 1085 1086 fg_color = (((u32)cmap.red[fg_idx] & 0xff00) << 8) | 1087 (((u32)cmap.green[fg_idx] & 0xff00) << 0) | 1088 (((u32)cmap.blue[fg_idx] & 0xff00) >> 8); 1089 bg_color = (((u32)cmap.red[bg_idx] & 0xff00) << 8) | 1090 (((u32)cmap.green[bg_idx] & 0xff00) << 0) | 1091 (((u32)cmap.blue[bg_idx] & 0xff00) >> 8); 1092 banshee_make_room(par, 2); 1093 tdfx_outl(par, HWCURC0, bg_color); 1094 tdfx_outl(par, HWCURC1, fg_color); 1095 } 1096 1097 if (cursor->set & FB_CUR_SETPOS) { 1098 int x = cursor->image.dx; 1099 int y = cursor->image.dy - info->var.yoffset; 1100 1101 x += 63; 1102 y += 63; 1103 banshee_make_room(par, 1); 1104 tdfx_outl(par, HWCURLOC, (y << 16) + x); 1105 } 1106 if (cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) { 1107 /* 1108 * Voodoo 3 and above cards use 2 monochrome cursor patterns. 1109 * The reason is so the card can fetch 8 words at a time 1110 * and are stored on chip for use for the next 8 scanlines. 1111 * This reduces the number of times for access to draw the 1112 * cursor for each screen refresh. 1113 * Each pattern is a bitmap of 64 bit wide and 64 bit high 1114 * (total of 8192 bits or 1024 bytes). The two patterns are 1115 * stored in such a way that pattern 0 always resides in the 1116 * lower half (least significant 64 bits) of a 128 bit word 1117 * and pattern 1 the upper half. If you examine the data of 1118 * the cursor image the graphics card uses then from the 1119 * begining you see line one of pattern 0, line one of 1120 * pattern 1, line two of pattern 0, line two of pattern 1, 1121 * etc etc. The linear stride for the cursor is always 16 bytes 1122 * (128 bits) which is the maximum cursor width times two for 1123 * the two monochrome patterns. 1124 */ 1125 u8 __iomem *cursorbase = info->screen_base + info->fix.smem_len; 1126 u8 *bitmap = (u8 *)cursor->image.data; 1127 u8 *mask = (u8 *)cursor->mask; 1128 int i; 1129 1130 fb_memset(cursorbase, 0, 1024); 1131 1132 for (i = 0; i < cursor->image.height; i++) { 1133 int h = 0; 1134 int j = (cursor->image.width + 7) >> 3; 1135 1136 for (; j > 0; j--) { 1137 u8 data = *mask ^ *bitmap; 1138 if (cursor->rop == ROP_COPY) 1139 data = *mask & *bitmap; 1140 /* Pattern 0. Copy the cursor mask to it */ 1141 fb_writeb(*mask, cursorbase + h); 1142 mask++; 1143 /* Pattern 1. Copy the cursor bitmap to it */ 1144 fb_writeb(data, cursorbase + h + 8); 1145 bitmap++; 1146 h++; 1147 } 1148 cursorbase += 16; 1149 } 1150 } 1151 return 0; 1152} 1153 1154static struct fb_ops tdfxfb_ops = { 1155 .owner = THIS_MODULE, 1156 .fb_check_var = tdfxfb_check_var, 1157 .fb_set_par = tdfxfb_set_par, 1158 .fb_setcolreg = tdfxfb_setcolreg, 1159 .fb_blank = tdfxfb_blank, 1160 .fb_pan_display = tdfxfb_pan_display, 1161 .fb_sync = banshee_wait_idle, 1162 .fb_cursor = tdfxfb_cursor, 1163#ifdef CONFIG_FB_3DFX_ACCEL 1164 .fb_fillrect = tdfxfb_fillrect, 1165 .fb_copyarea = tdfxfb_copyarea, 1166 .fb_imageblit = tdfxfb_imageblit, 1167#else 1168 .fb_fillrect = cfb_fillrect, 1169 .fb_copyarea = cfb_copyarea, 1170 .fb_imageblit = cfb_imageblit, 1171#endif 1172}; 1173 1174#ifdef CONFIG_FB_3DFX_I2C 1175/* The voo GPIO registers don't have individual masks for each bit 1176 so we always have to read before writing. */ 1177 1178static void tdfxfb_i2c_setscl(void *data, int val) 1179{ 1180 struct tdfxfb_i2c_chan *chan = data; 1181 struct tdfx_par *par = chan->par; 1182 unsigned int r; 1183 1184 r = tdfx_inl(par, VIDSERPARPORT); 1185 if (val) 1186 r |= I2C_SCL_OUT; 1187 else 1188 r &= ~I2C_SCL_OUT; 1189 tdfx_outl(par, VIDSERPARPORT, r); 1190 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */ 1191} 1192 1193static void tdfxfb_i2c_setsda(void *data, int val) 1194{ 1195 struct tdfxfb_i2c_chan *chan = data; 1196 struct tdfx_par *par = chan->par; 1197 unsigned int r; 1198 1199 r = tdfx_inl(par, VIDSERPARPORT); 1200 if (val) 1201 r |= I2C_SDA_OUT; 1202 else 1203 r &= ~I2C_SDA_OUT; 1204 tdfx_outl(par, VIDSERPARPORT, r); 1205 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */ 1206} 1207 1208/* The GPIO pins are open drain, so the pins always remain outputs. 1209 We rely on the i2c-algo-bit routines to set the pins high before 1210 reading the input from other chips. */ 1211 1212static int tdfxfb_i2c_getscl(void *data) 1213{ 1214 struct tdfxfb_i2c_chan *chan = data; 1215 struct tdfx_par *par = chan->par; 1216 1217 return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SCL_IN)); 1218} 1219 1220static int tdfxfb_i2c_getsda(void *data) 1221{ 1222 struct tdfxfb_i2c_chan *chan = data; 1223 struct tdfx_par *par = chan->par; 1224 1225 return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SDA_IN)); 1226} 1227 1228static void tdfxfb_ddc_setscl(void *data, int val) 1229{ 1230 struct tdfxfb_i2c_chan *chan = data; 1231 struct tdfx_par *par = chan->par; 1232 unsigned int r; 1233 1234 r = tdfx_inl(par, VIDSERPARPORT); 1235 if (val) 1236 r |= DDC_SCL_OUT; 1237 else 1238 r &= ~DDC_SCL_OUT; 1239 tdfx_outl(par, VIDSERPARPORT, r); 1240 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */ 1241} 1242 1243static void tdfxfb_ddc_setsda(void *data, int val) 1244{ 1245 struct tdfxfb_i2c_chan *chan = data; 1246 struct tdfx_par *par = chan->par; 1247 unsigned int r; 1248 1249 r = tdfx_inl(par, VIDSERPARPORT); 1250 if (val) 1251 r |= DDC_SDA_OUT; 1252 else 1253 r &= ~DDC_SDA_OUT; 1254 tdfx_outl(par, VIDSERPARPORT, r); 1255 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */ 1256} 1257 1258static int tdfxfb_ddc_getscl(void *data) 1259{ 1260 struct tdfxfb_i2c_chan *chan = data; 1261 struct tdfx_par *par = chan->par; 1262 1263 return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SCL_IN)); 1264} 1265 1266static int tdfxfb_ddc_getsda(void *data) 1267{ 1268 struct tdfxfb_i2c_chan *chan = data; 1269 struct tdfx_par *par = chan->par; 1270 1271 return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SDA_IN)); 1272} 1273 1274static int __devinit tdfxfb_setup_ddc_bus(struct tdfxfb_i2c_chan *chan, 1275 const char *name, struct device *dev) 1276{ 1277 int rc; 1278 1279 strlcpy(chan->adapter.name, name, sizeof(chan->adapter.name)); 1280 chan->adapter.owner = THIS_MODULE; 1281 chan->adapter.class = I2C_CLASS_DDC; 1282 chan->adapter.algo_data = &chan->algo; 1283 chan->adapter.dev.parent = dev; 1284 chan->algo.setsda = tdfxfb_ddc_setsda; 1285 chan->algo.setscl = tdfxfb_ddc_setscl; 1286 chan->algo.getsda = tdfxfb_ddc_getsda; 1287 chan->algo.getscl = tdfxfb_ddc_getscl; 1288 chan->algo.udelay = 10; 1289 chan->algo.timeout = msecs_to_jiffies(500); 1290 chan->algo.data = chan; 1291 1292 i2c_set_adapdata(&chan->adapter, chan); 1293 1294 rc = i2c_bit_add_bus(&chan->adapter); 1295 if (rc == 0) 1296 DPRINTK("I2C bus %s registered.\n", name); 1297 else 1298 chan->par = NULL; 1299 1300 return rc; 1301} 1302 1303static int __devinit tdfxfb_setup_i2c_bus(struct tdfxfb_i2c_chan *chan, 1304 const char *name, struct device *dev) 1305{ 1306 int rc; 1307 1308 strlcpy(chan->adapter.name, name, sizeof(chan->adapter.name)); 1309 chan->adapter.owner = THIS_MODULE; 1310 chan->adapter.algo_data = &chan->algo; 1311 chan->adapter.dev.parent = dev; 1312 chan->algo.setsda = tdfxfb_i2c_setsda; 1313 chan->algo.setscl = tdfxfb_i2c_setscl; 1314 chan->algo.getsda = tdfxfb_i2c_getsda; 1315 chan->algo.getscl = tdfxfb_i2c_getscl; 1316 chan->algo.udelay = 10; 1317 chan->algo.timeout = msecs_to_jiffies(500); 1318 chan->algo.data = chan; 1319 1320 i2c_set_adapdata(&chan->adapter, chan); 1321 1322 rc = i2c_bit_add_bus(&chan->adapter); 1323 if (rc == 0) 1324 DPRINTK("I2C bus %s registered.\n", name); 1325 else 1326 chan->par = NULL; 1327 1328 return rc; 1329} 1330 1331static void __devinit tdfxfb_create_i2c_busses(struct fb_info *info) 1332{ 1333 struct tdfx_par *par = info->par; 1334 1335 tdfx_outl(par, VIDINFORMAT, 0x8160); 1336 tdfx_outl(par, VIDSERPARPORT, 0xcffc0020); 1337 1338 par->chan[0].par = par; 1339 par->chan[1].par = par; 1340 1341 tdfxfb_setup_ddc_bus(&par->chan[0], "Voodoo3-DDC", info->dev); 1342 tdfxfb_setup_i2c_bus(&par->chan[1], "Voodoo3-I2C", info->dev); 1343} 1344 1345static void tdfxfb_delete_i2c_busses(struct tdfx_par *par) 1346{ 1347 if (par->chan[0].par) 1348 i2c_del_adapter(&par->chan[0].adapter); 1349 par->chan[0].par = NULL; 1350 1351 if (par->chan[1].par) 1352 i2c_del_adapter(&par->chan[1].adapter); 1353 par->chan[1].par = NULL; 1354} 1355 1356static int tdfxfb_probe_i2c_connector(struct tdfx_par *par, 1357 struct fb_monspecs *specs) 1358{ 1359 u8 *edid = NULL; 1360 1361 DPRINTK("Probe DDC Bus\n"); 1362 if (par->chan[0].par) 1363 edid = fb_ddc_read(&par->chan[0].adapter); 1364 1365 if (edid) { 1366 fb_edid_to_monspecs(edid, specs); 1367 kfree(edid); 1368 return 0; 1369 } 1370 return 1; 1371} 1372#endif /* CONFIG_FB_3DFX_I2C */ 1373 1374/** 1375 * tdfxfb_probe - Device Initializiation 1376 * 1377 * @pdev: PCI Device to initialize 1378 * @id: PCI Device ID 1379 * 1380 * Initializes and allocates resources for PCI device @pdev. 1381 * 1382 */ 1383static int __devinit tdfxfb_probe(struct pci_dev *pdev, 1384 const struct pci_device_id *id) 1385{ 1386 struct tdfx_par *default_par; 1387 struct fb_info *info; 1388 int err, lpitch; 1389 struct fb_monspecs *specs; 1390 bool found; 1391 1392 err = pci_enable_device(pdev); 1393 if (err) { 1394 printk(KERN_ERR "tdfxfb: Can't enable pdev: %d\n", err); 1395 return err; 1396 } 1397 1398 info = framebuffer_alloc(sizeof(struct tdfx_par), &pdev->dev); 1399 1400 if (!info) 1401 return -ENOMEM; 1402 1403 default_par = info->par; 1404 info->fix = tdfx_fix; 1405 1406 /* Configure the default fb_fix_screeninfo first */ 1407 switch (pdev->device) { 1408 case PCI_DEVICE_ID_3DFX_BANSHEE: 1409 strcpy(info->fix.id, "3Dfx Banshee"); 1410 default_par->max_pixclock = BANSHEE_MAX_PIXCLOCK; 1411 break; 1412 case PCI_DEVICE_ID_3DFX_VOODOO3: 1413 strcpy(info->fix.id, "3Dfx Voodoo3"); 1414 default_par->max_pixclock = VOODOO3_MAX_PIXCLOCK; 1415 break; 1416 case PCI_DEVICE_ID_3DFX_VOODOO5: 1417 strcpy(info->fix.id, "3Dfx Voodoo5"); 1418 default_par->max_pixclock = VOODOO5_MAX_PIXCLOCK; 1419 break; 1420 } 1421 1422 info->fix.mmio_start = pci_resource_start(pdev, 0); 1423 info->fix.mmio_len = pci_resource_len(pdev, 0); 1424 if (!request_mem_region(info->fix.mmio_start, info->fix.mmio_len, 1425 "tdfx regbase")) { 1426 printk(KERN_ERR "tdfxfb: Can't reserve regbase\n"); 1427 goto out_err; 1428 } 1429 1430 default_par->regbase_virt = 1431 ioremap_nocache(info->fix.mmio_start, info->fix.mmio_len); 1432 if (!default_par->regbase_virt) { 1433 printk(KERN_ERR "fb: Can't remap %s register area.\n", 1434 info->fix.id); 1435 goto out_err_regbase; 1436 } 1437 1438 info->fix.smem_start = pci_resource_start(pdev, 1); 1439 info->fix.smem_len = do_lfb_size(default_par, pdev->device); 1440 if (!info->fix.smem_len) { 1441 printk(KERN_ERR "fb: Can't count %s memory.\n", info->fix.id); 1442 goto out_err_regbase; 1443 } 1444 1445 if (!request_mem_region(info->fix.smem_start, 1446 pci_resource_len(pdev, 1), "tdfx smem")) { 1447 printk(KERN_ERR "tdfxfb: Can't reserve smem\n"); 1448 goto out_err_regbase; 1449 } 1450 1451 info->screen_base = ioremap_nocache(info->fix.smem_start, 1452 info->fix.smem_len); 1453 if (!info->screen_base) { 1454 printk(KERN_ERR "fb: Can't remap %s framebuffer.\n", 1455 info->fix.id); 1456 goto out_err_screenbase; 1457 } 1458 1459 default_par->iobase = pci_resource_start(pdev, 2); 1460 1461 if (!request_region(pci_resource_start(pdev, 2), 1462 pci_resource_len(pdev, 2), "tdfx iobase")) { 1463 printk(KERN_ERR "tdfxfb: Can't reserve iobase\n"); 1464 goto out_err_screenbase; 1465 } 1466 1467 printk(KERN_INFO "fb: %s memory = %dK\n", info->fix.id, 1468 info->fix.smem_len >> 10); 1469 1470 default_par->mtrr_handle = -1; 1471 if (!nomtrr) 1472 default_par->mtrr_handle = 1473 mtrr_add(info->fix.smem_start, info->fix.smem_len, 1474 MTRR_TYPE_WRCOMB, 1); 1475 1476 info->fix.ypanstep = nopan ? 0 : 1; 1477 info->fix.ywrapstep = nowrap ? 0 : 1; 1478 1479 info->fbops = &tdfxfb_ops; 1480 info->pseudo_palette = default_par->palette; 1481 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; 1482#ifdef CONFIG_FB_3DFX_ACCEL 1483 info->flags |= FBINFO_HWACCEL_FILLRECT | 1484 FBINFO_HWACCEL_COPYAREA | 1485 FBINFO_HWACCEL_IMAGEBLIT | 1486 FBINFO_READS_FAST; 1487#endif 1488 /* reserve 8192 bits for cursor */ 1489 /* the 2.4 driver says PAGE_MASK boundary is not enough for Voodoo4 */ 1490 if (hwcursor) 1491 info->fix.smem_len = (info->fix.smem_len - 1024) & 1492 (PAGE_MASK << 1); 1493 specs = &info->monspecs; 1494 found = false; 1495 info->var.bits_per_pixel = 8; 1496#ifdef CONFIG_FB_3DFX_I2C 1497 tdfxfb_create_i2c_busses(info); 1498 err = tdfxfb_probe_i2c_connector(default_par, specs); 1499 1500 if (!err) { 1501 if (specs->modedb == NULL) 1502 DPRINTK("Unable to get Mode Database\n"); 1503 else { 1504 const struct fb_videomode *m; 1505 1506 fb_videomode_to_modelist(specs->modedb, 1507 specs->modedb_len, 1508 &info->modelist); 1509 m = fb_find_best_display(specs, &info->modelist); 1510 if (m) { 1511 fb_videomode_to_var(&info->var, m); 1512 /* fill all other info->var's fields */ 1513 if (tdfxfb_check_var(&info->var, info) < 0) 1514 info->var = tdfx_var; 1515 else 1516 found = true; 1517 } 1518 } 1519 } 1520#endif 1521 if (!mode_option && !found) 1522 mode_option = "640x480@60"; 1523 1524 if (mode_option) { 1525 err = fb_find_mode(&info->var, info, mode_option, 1526 specs->modedb, specs->modedb_len, 1527 NULL, info->var.bits_per_pixel); 1528 if (!err || err == 4) 1529 info->var = tdfx_var; 1530 } 1531 1532 if (found) { 1533 fb_destroy_modedb(specs->modedb); 1534 specs->modedb = NULL; 1535 } 1536 1537 /* maximize virtual vertical length */ 1538 lpitch = info->var.xres_virtual * ((info->var.bits_per_pixel + 7) >> 3); 1539 info->var.yres_virtual = info->fix.smem_len / lpitch; 1540 if (info->var.yres_virtual < info->var.yres) 1541 goto out_err_iobase; 1542 1543 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) { 1544 printk(KERN_ERR "tdfxfb: Can't allocate color map\n"); 1545 goto out_err_iobase; 1546 } 1547 1548 if (register_framebuffer(info) < 0) { 1549 printk(KERN_ERR "tdfxfb: can't register framebuffer\n"); 1550 fb_dealloc_cmap(&info->cmap); 1551 goto out_err_iobase; 1552 } 1553 /* 1554 * Our driver data 1555 */ 1556 pci_set_drvdata(pdev, info); 1557 return 0; 1558 1559out_err_iobase: 1560#ifdef CONFIG_FB_3DFX_I2C 1561 tdfxfb_delete_i2c_busses(default_par); 1562#endif 1563 if (default_par->mtrr_handle >= 0) 1564 mtrr_del(default_par->mtrr_handle, info->fix.smem_start, 1565 info->fix.smem_len); 1566 release_region(pci_resource_start(pdev, 2), 1567 pci_resource_len(pdev, 2)); 1568out_err_screenbase: 1569 if (info->screen_base) 1570 iounmap(info->screen_base); 1571 release_mem_region(info->fix.smem_start, pci_resource_len(pdev, 1)); 1572out_err_regbase: 1573 /* 1574 * Cleanup after anything that was remapped/allocated. 1575 */ 1576 if (default_par->regbase_virt) 1577 iounmap(default_par->regbase_virt); 1578 release_mem_region(info->fix.mmio_start, info->fix.mmio_len); 1579out_err: 1580 framebuffer_release(info); 1581 return -ENXIO; 1582} 1583 1584#ifndef MODULE 1585static void __init tdfxfb_setup(char *options) 1586{ 1587 char *this_opt; 1588 1589 if (!options || !*options) 1590 return; 1591 1592 while ((this_opt = strsep(&options, ",")) != NULL) { 1593 if (!*this_opt) 1594 continue; 1595 if (!strcmp(this_opt, "nopan")) { 1596 nopan = 1; 1597 } else if (!strcmp(this_opt, "nowrap")) { 1598 nowrap = 1; 1599 } else if (!strncmp(this_opt, "hwcursor=", 9)) { 1600 hwcursor = simple_strtoul(this_opt + 9, NULL, 0); 1601#ifdef CONFIG_MTRR 1602 } else if (!strncmp(this_opt, "nomtrr", 6)) { 1603 nomtrr = 1; 1604#endif 1605 } else { 1606 mode_option = this_opt; 1607 } 1608 } 1609} 1610#endif 1611 1612/** 1613 * tdfxfb_remove - Device removal 1614 * 1615 * @pdev: PCI Device to cleanup 1616 * 1617 * Releases all resources allocated during the course of the driver's 1618 * lifetime for the PCI device @pdev. 1619 * 1620 */ 1621static void __devexit tdfxfb_remove(struct pci_dev *pdev) 1622{ 1623 struct fb_info *info = pci_get_drvdata(pdev); 1624 struct tdfx_par *par = info->par; 1625 1626 unregister_framebuffer(info); 1627#ifdef CONFIG_FB_3DFX_I2C 1628 tdfxfb_delete_i2c_busses(par); 1629#endif 1630 if (par->mtrr_handle >= 0) 1631 mtrr_del(par->mtrr_handle, info->fix.smem_start, 1632 info->fix.smem_len); 1633 iounmap(par->regbase_virt); 1634 iounmap(info->screen_base); 1635 1636 /* Clean up after reserved regions */ 1637 release_region(pci_resource_start(pdev, 2), 1638 pci_resource_len(pdev, 2)); 1639 release_mem_region(pci_resource_start(pdev, 1), 1640 pci_resource_len(pdev, 1)); 1641 release_mem_region(pci_resource_start(pdev, 0), 1642 pci_resource_len(pdev, 0)); 1643 pci_set_drvdata(pdev, NULL); 1644 fb_dealloc_cmap(&info->cmap); 1645 framebuffer_release(info); 1646} 1647 1648static int __init tdfxfb_init(void) 1649{ 1650#ifndef MODULE 1651 char *option = NULL; 1652 1653 if (fb_get_options("tdfxfb", &option)) 1654 return -ENODEV; 1655 1656 tdfxfb_setup(option); 1657#endif 1658 return pci_register_driver(&tdfxfb_driver); 1659} 1660 1661static void __exit tdfxfb_exit(void) 1662{ 1663 pci_unregister_driver(&tdfxfb_driver); 1664} 1665 1666MODULE_AUTHOR("Hannu Mallat <hmallat@cc.hut.fi>"); 1667MODULE_DESCRIPTION("3Dfx framebuffer device driver"); 1668MODULE_LICENSE("GPL"); 1669 1670module_param(hwcursor, int, 0644); 1671MODULE_PARM_DESC(hwcursor, "Enable hardware cursor " 1672 "(1=enable, 0=disable, default=1)"); 1673module_param(mode_option, charp, 0); 1674MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'"); 1675#ifdef CONFIG_MTRR 1676module_param(nomtrr, bool, 0); 1677MODULE_PARM_DESC(nomtrr, "Disable MTRR support (default: enabled)"); 1678#endif 1679 1680module_init(tdfxfb_init); 1681module_exit(tdfxfb_exit); 1682