1/* 2 * drivers/video/imsttfb.c -- frame buffer device for IMS TwinTurbo 3 * 4 * This file is derived from the powermac console "imstt" driver: 5 * Copyright (C) 1997 Sigurdur Asgeirsson 6 * With additional hacking by Jeffrey Kuskin (jsk@mojave.stanford.edu) 7 * Modified by Danilo Beuche 1998 8 * Some register values added by Damien Doligez, INRIA Rocquencourt 9 * Various cleanups by Paul Mundt (lethal@chaoticdreams.org) 10 * 11 * This file was written by Ryan Nielsen (ran@krazynet.com) 12 * Most of the frame buffer device stuff was copied from atyfb.c 13 * 14 * This file is subject to the terms and conditions of the GNU General Public 15 * License. See the file COPYING in the main directory of this archive for 16 * more details. 17 */ 18 19#include <linux/module.h> 20#include <linux/kernel.h> 21#include <linux/errno.h> 22#include <linux/string.h> 23#include <linux/mm.h> 24#include <linux/vmalloc.h> 25#include <linux/delay.h> 26#include <linux/interrupt.h> 27#include <linux/fb.h> 28#include <linux/init.h> 29#include <linux/pci.h> 30#include <asm/io.h> 31#include <linux/uaccess.h> 32 33#if defined(CONFIG_PPC) 34#include <linux/nvram.h> 35#include <asm/prom.h> 36#include <asm/pci-bridge.h> 37#include "macmodes.h" 38#endif 39 40#ifndef __powerpc__ 41#define eieio() /* Enforce In-order Execution of I/O */ 42#endif 43 44/* TwinTurbo (Cosmo) registers */ 45enum { 46 S1SA = 0, /* 0x00 */ 47 S2SA = 1, /* 0x04 */ 48 SP = 2, /* 0x08 */ 49 DSA = 3, /* 0x0C */ 50 CNT = 4, /* 0x10 */ 51 DP_OCTL = 5, /* 0x14 */ 52 CLR = 6, /* 0x18 */ 53 BI = 8, /* 0x20 */ 54 MBC = 9, /* 0x24 */ 55 BLTCTL = 10, /* 0x28 */ 56 57 /* Scan Timing Generator Registers */ 58 HES = 12, /* 0x30 */ 59 HEB = 13, /* 0x34 */ 60 HSB = 14, /* 0x38 */ 61 HT = 15, /* 0x3C */ 62 VES = 16, /* 0x40 */ 63 VEB = 17, /* 0x44 */ 64 VSB = 18, /* 0x48 */ 65 VT = 19, /* 0x4C */ 66 HCIV = 20, /* 0x50 */ 67 VCIV = 21, /* 0x54 */ 68 TCDR = 22, /* 0x58 */ 69 VIL = 23, /* 0x5C */ 70 STGCTL = 24, /* 0x60 */ 71 72 /* Screen Refresh Generator Registers */ 73 SSR = 25, /* 0x64 */ 74 HRIR = 26, /* 0x68 */ 75 SPR = 27, /* 0x6C */ 76 CMR = 28, /* 0x70 */ 77 SRGCTL = 29, /* 0x74 */ 78 79 /* RAM Refresh Generator Registers */ 80 RRCIV = 30, /* 0x78 */ 81 RRSC = 31, /* 0x7C */ 82 RRCR = 34, /* 0x88 */ 83 84 /* System Registers */ 85 GIOE = 32, /* 0x80 */ 86 GIO = 33, /* 0x84 */ 87 SCR = 35, /* 0x8C */ 88 SSTATUS = 36, /* 0x90 */ 89 PRC = 37, /* 0x94 */ 90 91}; 92 93/* IBM 624 RAMDAC Direct Registers */ 94enum { 95 PADDRW = 0x00, 96 PDATA = 0x04, 97 PPMASK = 0x08, 98 PADDRR = 0x0c, 99 PIDXLO = 0x10, 100 PIDXHI = 0x14, 101 PIDXDATA= 0x18, 102 PIDXCTL = 0x1c 103}; 104 105/* IBM 624 RAMDAC Indirect Registers */ 106enum { 107 CLKCTL = 0x02, /* (0x01) Miscellaneous Clock Control */ 108 SYNCCTL = 0x03, /* (0x00) Sync Control */ 109 HSYNCPOS = 0x04, /* (0x00) Horizontal Sync Position */ 110 PWRMNGMT = 0x05, /* (0x00) Power Management */ 111 DACOP = 0x06, /* (0x02) DAC Operation */ 112 PALETCTL = 0x07, /* (0x00) Palette Control */ 113 SYSCLKCTL = 0x08, /* (0x01) System Clock Control */ 114 PIXFMT = 0x0a, /* () Pixel Format [bpp >> 3 + 2] */ 115 BPP8 = 0x0b, /* () 8 Bits/Pixel Control */ 116 BPP16 = 0x0c, /* () 16 Bits/Pixel Control [bit 1=1 for 565] */ 117 BPP24 = 0x0d, /* () 24 Bits/Pixel Control */ 118 BPP32 = 0x0e, /* () 32 Bits/Pixel Control */ 119 PIXCTL1 = 0x10, /* (0x05) Pixel PLL Control 1 */ 120 PIXCTL2 = 0x11, /* (0x00) Pixel PLL Control 2 */ 121 SYSCLKN = 0x15, /* () System Clock N (System PLL Reference Divider) */ 122 SYSCLKM = 0x16, /* () System Clock M (System PLL VCO Divider) */ 123 SYSCLKP = 0x17, /* () System Clock P */ 124 SYSCLKC = 0x18, /* () System Clock C */ 125 /* 126 * Dot clock rate is 20MHz * (m + 1) / ((n + 1) * (p ? 2 * p : 1) 127 * c is charge pump bias which depends on the VCO frequency 128 */ 129 PIXM0 = 0x20, /* () Pixel M 0 */ 130 PIXN0 = 0x21, /* () Pixel N 0 */ 131 PIXP0 = 0x22, /* () Pixel P 0 */ 132 PIXC0 = 0x23, /* () Pixel C 0 */ 133 CURSCTL = 0x30, /* (0x00) Cursor Control */ 134 CURSXLO = 0x31, /* () Cursor X position, low 8 bits */ 135 CURSXHI = 0x32, /* () Cursor X position, high 8 bits */ 136 CURSYLO = 0x33, /* () Cursor Y position, low 8 bits */ 137 CURSYHI = 0x34, /* () Cursor Y position, high 8 bits */ 138 CURSHOTX = 0x35, /* () Cursor Hot Spot X */ 139 CURSHOTY = 0x36, /* () Cursor Hot Spot Y */ 140 CURSACCTL = 0x37, /* () Advanced Cursor Control Enable */ 141 CURSACATTR = 0x38, /* () Advanced Cursor Attribute */ 142 CURS1R = 0x40, /* () Cursor 1 Red */ 143 CURS1G = 0x41, /* () Cursor 1 Green */ 144 CURS1B = 0x42, /* () Cursor 1 Blue */ 145 CURS2R = 0x43, /* () Cursor 2 Red */ 146 CURS2G = 0x44, /* () Cursor 2 Green */ 147 CURS2B = 0x45, /* () Cursor 2 Blue */ 148 CURS3R = 0x46, /* () Cursor 3 Red */ 149 CURS3G = 0x47, /* () Cursor 3 Green */ 150 CURS3B = 0x48, /* () Cursor 3 Blue */ 151 BORDR = 0x60, /* () Border Color Red */ 152 BORDG = 0x61, /* () Border Color Green */ 153 BORDB = 0x62, /* () Border Color Blue */ 154 MISCTL1 = 0x70, /* (0x00) Miscellaneous Control 1 */ 155 MISCTL2 = 0x71, /* (0x00) Miscellaneous Control 2 */ 156 MISCTL3 = 0x72, /* (0x00) Miscellaneous Control 3 */ 157 KEYCTL = 0x78 /* (0x00) Key Control/DB Operation */ 158}; 159 160/* TI TVP 3030 RAMDAC Direct Registers */ 161enum { 162 TVPADDRW = 0x00, /* 0 Palette/Cursor RAM Write Address/Index */ 163 TVPPDATA = 0x04, /* 1 Palette Data RAM Data */ 164 TVPPMASK = 0x08, /* 2 Pixel Read-Mask */ 165 TVPPADRR = 0x0c, /* 3 Palette/Cursor RAM Read Address */ 166 TVPCADRW = 0x10, /* 4 Cursor/Overscan Color Write Address */ 167 TVPCDATA = 0x14, /* 5 Cursor/Overscan Color Data */ 168 /* 6 reserved */ 169 TVPCADRR = 0x1c, /* 7 Cursor/Overscan Color Read Address */ 170 /* 8 reserved */ 171 TVPDCCTL = 0x24, /* 9 Direct Cursor Control */ 172 TVPIDATA = 0x28, /* 10 Index Data */ 173 TVPCRDAT = 0x2c, /* 11 Cursor RAM Data */ 174 TVPCXPOL = 0x30, /* 12 Cursor-Position X LSB */ 175 TVPCXPOH = 0x34, /* 13 Cursor-Position X MSB */ 176 TVPCYPOL = 0x38, /* 14 Cursor-Position Y LSB */ 177 TVPCYPOH = 0x3c, /* 15 Cursor-Position Y MSB */ 178}; 179 180/* TI TVP 3030 RAMDAC Indirect Registers */ 181enum { 182 TVPIRREV = 0x01, /* Silicon Revision [RO] */ 183 TVPIRICC = 0x06, /* Indirect Cursor Control (0x00) */ 184 TVPIRBRC = 0x07, /* Byte Router Control (0xe4) */ 185 TVPIRLAC = 0x0f, /* Latch Control (0x06) */ 186 TVPIRTCC = 0x18, /* True Color Control (0x80) */ 187 TVPIRMXC = 0x19, /* Multiplex Control (0x98) */ 188 TVPIRCLS = 0x1a, /* Clock Selection (0x07) */ 189 TVPIRPPG = 0x1c, /* Palette Page (0x00) */ 190 TVPIRGEC = 0x1d, /* General Control (0x00) */ 191 TVPIRMIC = 0x1e, /* Miscellaneous Control (0x00) */ 192 TVPIRPLA = 0x2c, /* PLL Address */ 193 TVPIRPPD = 0x2d, /* Pixel Clock PLL Data */ 194 TVPIRMPD = 0x2e, /* Memory Clock PLL Data */ 195 TVPIRLPD = 0x2f, /* Loop Clock PLL Data */ 196 TVPIRCKL = 0x30, /* Color-Key Overlay Low */ 197 TVPIRCKH = 0x31, /* Color-Key Overlay High */ 198 TVPIRCRL = 0x32, /* Color-Key Red Low */ 199 TVPIRCRH = 0x33, /* Color-Key Red High */ 200 TVPIRCGL = 0x34, /* Color-Key Green Low */ 201 TVPIRCGH = 0x35, /* Color-Key Green High */ 202 TVPIRCBL = 0x36, /* Color-Key Blue Low */ 203 TVPIRCBH = 0x37, /* Color-Key Blue High */ 204 TVPIRCKC = 0x38, /* Color-Key Control (0x00) */ 205 TVPIRMLC = 0x39, /* MCLK/Loop Clock Control (0x18) */ 206 TVPIRSEN = 0x3a, /* Sense Test (0x00) */ 207 TVPIRTMD = 0x3b, /* Test Mode Data */ 208 TVPIRRML = 0x3c, /* CRC Remainder LSB [RO] */ 209 TVPIRRMM = 0x3d, /* CRC Remainder MSB [RO] */ 210 TVPIRRMS = 0x3e, /* CRC Bit Select [WO] */ 211 TVPIRDID = 0x3f, /* Device ID [RO] (0x30) */ 212 TVPIRRES = 0xff /* Software Reset [WO] */ 213}; 214 215struct initvalues { 216 __u8 addr, value; 217}; 218 219static struct initvalues ibm_initregs[] __devinitdata = { 220 { CLKCTL, 0x21 }, 221 { SYNCCTL, 0x00 }, 222 { HSYNCPOS, 0x00 }, 223 { PWRMNGMT, 0x00 }, 224 { DACOP, 0x02 }, 225 { PALETCTL, 0x00 }, 226 { SYSCLKCTL, 0x01 }, 227 228 /* 229 * Note that colors in X are correct only if all video data is 230 * passed through the palette in the DAC. That is, "indirect 231 * color" must be configured. This is the case for the IBM DAC 232 * used in the 2MB and 4MB cards, at least. 233 */ 234 { BPP8, 0x00 }, 235 { BPP16, 0x01 }, 236 { BPP24, 0x00 }, 237 { BPP32, 0x00 }, 238 239 { PIXCTL1, 0x05 }, 240 { PIXCTL2, 0x00 }, 241 { SYSCLKN, 0x08 }, 242 { SYSCLKM, 0x4f }, 243 { SYSCLKP, 0x00 }, 244 { SYSCLKC, 0x00 }, 245 { CURSCTL, 0x00 }, 246 { CURSACCTL, 0x01 }, 247 { CURSACATTR, 0xa8 }, 248 { CURS1R, 0xff }, 249 { CURS1G, 0xff }, 250 { CURS1B, 0xff }, 251 { CURS2R, 0xff }, 252 { CURS2G, 0xff }, 253 { CURS2B, 0xff }, 254 { CURS3R, 0xff }, 255 { CURS3G, 0xff }, 256 { CURS3B, 0xff }, 257 { BORDR, 0xff }, 258 { BORDG, 0xff }, 259 { BORDB, 0xff }, 260 { MISCTL1, 0x01 }, 261 { MISCTL2, 0x45 }, 262 { MISCTL3, 0x00 }, 263 { KEYCTL, 0x00 } 264}; 265 266static struct initvalues tvp_initregs[] __devinitdata = { 267 { TVPIRICC, 0x00 }, 268 { TVPIRBRC, 0xe4 }, 269 { TVPIRLAC, 0x06 }, 270 { TVPIRTCC, 0x80 }, 271 { TVPIRMXC, 0x4d }, 272 { TVPIRCLS, 0x05 }, 273 { TVPIRPPG, 0x00 }, 274 { TVPIRGEC, 0x00 }, 275 { TVPIRMIC, 0x08 }, 276 { TVPIRCKL, 0xff }, 277 { TVPIRCKH, 0xff }, 278 { TVPIRCRL, 0xff }, 279 { TVPIRCRH, 0xff }, 280 { TVPIRCGL, 0xff }, 281 { TVPIRCGH, 0xff }, 282 { TVPIRCBL, 0xff }, 283 { TVPIRCBH, 0xff }, 284 { TVPIRCKC, 0x00 }, 285 { TVPIRPLA, 0x00 }, 286 { TVPIRPPD, 0xc0 }, 287 { TVPIRPPD, 0xd5 }, 288 { TVPIRPPD, 0xea }, 289 { TVPIRPLA, 0x00 }, 290 { TVPIRMPD, 0xb9 }, 291 { TVPIRMPD, 0x3a }, 292 { TVPIRMPD, 0xb1 }, 293 { TVPIRPLA, 0x00 }, 294 { TVPIRLPD, 0xc1 }, 295 { TVPIRLPD, 0x3d }, 296 { TVPIRLPD, 0xf3 }, 297}; 298 299struct imstt_regvals { 300 __u32 pitch; 301 __u16 hes, heb, hsb, ht, ves, veb, vsb, vt, vil; 302 __u8 pclk_m, pclk_n, pclk_p; 303 /* Values of the tvp which change depending on colormode x resolution */ 304 __u8 mlc[3]; /* Memory Loop Config 0x39 */ 305 __u8 lckl_p[3]; /* P value of LCKL PLL */ 306}; 307 308struct imstt_par { 309 struct imstt_regvals init; 310 __u32 __iomem *dc_regs; 311 unsigned long cmap_regs_phys; 312 __u8 *cmap_regs; 313 __u32 ramdac; 314 __u32 palette[16]; 315}; 316 317enum { 318 IBM = 0, 319 TVP = 1 320}; 321 322#define USE_NV_MODES 1 323#define INIT_BPP 8 324#define INIT_XRES 640 325#define INIT_YRES 480 326 327static int inverse = 0; 328static char fontname[40] __initdata = { 0 }; 329#if defined(CONFIG_PPC) 330static signed char init_vmode __devinitdata = -1, init_cmode __devinitdata = -1; 331#endif 332 333static struct imstt_regvals tvp_reg_init_2 = { 334 512, 335 0x0002, 0x0006, 0x0026, 0x0028, 0x0003, 0x0016, 0x0196, 0x0197, 0x0196, 336 0xec, 0x2a, 0xf3, 337 { 0x3c, 0x3b, 0x39 }, { 0xf3, 0xf3, 0xf3 } 338}; 339 340static struct imstt_regvals tvp_reg_init_6 = { 341 640, 342 0x0004, 0x0009, 0x0031, 0x0036, 0x0003, 0x002a, 0x020a, 0x020d, 0x020a, 343 0xef, 0x2e, 0xb2, 344 { 0x39, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 } 345}; 346 347static struct imstt_regvals tvp_reg_init_12 = { 348 800, 349 0x0005, 0x000e, 0x0040, 0x0042, 0x0003, 0x018, 0x270, 0x271, 0x270, 350 0xf6, 0x2e, 0xf2, 351 { 0x3a, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 } 352}; 353 354static struct imstt_regvals tvp_reg_init_13 = { 355 832, 356 0x0004, 0x0011, 0x0045, 0x0048, 0x0003, 0x002a, 0x029a, 0x029b, 0x0000, 357 0xfe, 0x3e, 0xf1, 358 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 } 359}; 360 361static struct imstt_regvals tvp_reg_init_17 = { 362 1024, 363 0x0006, 0x0210, 0x0250, 0x0053, 0x1003, 0x0021, 0x0321, 0x0324, 0x0000, 364 0xfc, 0x3a, 0xf1, 365 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 } 366}; 367 368static struct imstt_regvals tvp_reg_init_18 = { 369 1152, 370 0x0009, 0x0011, 0x059, 0x5b, 0x0003, 0x0031, 0x0397, 0x039a, 0x0000, 371 0xfd, 0x3a, 0xf1, 372 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 } 373}; 374 375static struct imstt_regvals tvp_reg_init_19 = { 376 1280, 377 0x0009, 0x0016, 0x0066, 0x0069, 0x0003, 0x0027, 0x03e7, 0x03e8, 0x03e7, 378 0xf7, 0x36, 0xf0, 379 { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 } 380}; 381 382static struct imstt_regvals tvp_reg_init_20 = { 383 1280, 384 0x0009, 0x0018, 0x0068, 0x006a, 0x0003, 0x0029, 0x0429, 0x042a, 0x0000, 385 0xf0, 0x2d, 0xf0, 386 { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 } 387}; 388 389/* 390 * PCI driver prototypes 391 */ 392static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent); 393static void imsttfb_remove(struct pci_dev *pdev); 394 395/* 396 * Register access 397 */ 398static inline u32 read_reg_le32(volatile u32 __iomem *base, int regindex) 399{ 400#ifdef __powerpc__ 401 return in_le32(base + regindex); 402#else 403 return readl(base + regindex); 404#endif 405} 406 407static inline void write_reg_le32(volatile u32 __iomem *base, int regindex, u32 val) 408{ 409#ifdef __powerpc__ 410 out_le32(base + regindex, val); 411#else 412 writel(val, base + regindex); 413#endif 414} 415 416static __u32 417getclkMHz(struct imstt_par *par) 418{ 419 __u32 clk_m, clk_n, clk_p; 420 421 clk_m = par->init.pclk_m; 422 clk_n = par->init.pclk_n; 423 clk_p = par->init.pclk_p; 424 425 return 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1)); 426} 427 428static void 429setclkMHz(struct imstt_par *par, __u32 MHz) 430{ 431 __u32 clk_m, clk_n, x, stage, spilled; 432 433 clk_m = clk_n = 0; 434 stage = spilled = 0; 435 for (;;) { 436 switch (stage) { 437 case 0: 438 clk_m++; 439 break; 440 case 1: 441 clk_n++; 442 break; 443 } 444 x = 20 * (clk_m + 1) / (clk_n + 1); 445 if (x == MHz) 446 break; 447 if (x > MHz) { 448 spilled = 1; 449 stage = 1; 450 } else if (spilled && x < MHz) { 451 stage = 0; 452 } 453 } 454 455 par->init.pclk_m = clk_m; 456 par->init.pclk_n = clk_n; 457 par->init.pclk_p = 0; 458} 459 460static struct imstt_regvals * 461compute_imstt_regvals_ibm(struct imstt_par *par, int xres, int yres) 462{ 463 struct imstt_regvals *init = &par->init; 464 __u32 MHz, hes, heb, veb, htp, vtp; 465 466 switch (xres) { 467 case 640: 468 hes = 0x0008; heb = 0x0012; veb = 0x002a; htp = 10; vtp = 2; 469 MHz = 30 /* .25 */ ; 470 break; 471 case 832: 472 hes = 0x0005; heb = 0x0020; veb = 0x0028; htp = 8; vtp = 3; 473 MHz = 57 /* .27_ */ ; 474 break; 475 case 1024: 476 hes = 0x000a; heb = 0x001c; veb = 0x0020; htp = 8; vtp = 3; 477 MHz = 80; 478 break; 479 case 1152: 480 hes = 0x0012; heb = 0x0022; veb = 0x0031; htp = 4; vtp = 3; 481 MHz = 101 /* .6_ */ ; 482 break; 483 case 1280: 484 hes = 0x0012; heb = 0x002f; veb = 0x0029; htp = 4; vtp = 1; 485 MHz = yres == 960 ? 126 : 135; 486 break; 487 case 1600: 488 hes = 0x0018; heb = 0x0040; veb = 0x002a; htp = 4; vtp = 3; 489 MHz = 200; 490 break; 491 default: 492 return NULL; 493 } 494 495 setclkMHz(par, MHz); 496 497 init->hes = hes; 498 init->heb = heb; 499 init->hsb = init->heb + (xres >> 3); 500 init->ht = init->hsb + htp; 501 init->ves = 0x0003; 502 init->veb = veb; 503 init->vsb = init->veb + yres; 504 init->vt = init->vsb + vtp; 505 init->vil = init->vsb; 506 507 init->pitch = xres; 508 return init; 509} 510 511static struct imstt_regvals * 512compute_imstt_regvals_tvp(struct imstt_par *par, int xres, int yres) 513{ 514 struct imstt_regvals *init; 515 516 switch (xres) { 517 case 512: 518 init = &tvp_reg_init_2; 519 break; 520 case 640: 521 init = &tvp_reg_init_6; 522 break; 523 case 800: 524 init = &tvp_reg_init_12; 525 break; 526 case 832: 527 init = &tvp_reg_init_13; 528 break; 529 case 1024: 530 init = &tvp_reg_init_17; 531 break; 532 case 1152: 533 init = &tvp_reg_init_18; 534 break; 535 case 1280: 536 init = yres == 960 ? &tvp_reg_init_19 : &tvp_reg_init_20; 537 break; 538 default: 539 return NULL; 540 } 541 par->init = *init; 542 return init; 543} 544 545static struct imstt_regvals * 546compute_imstt_regvals (struct imstt_par *par, u_int xres, u_int yres) 547{ 548 if (par->ramdac == IBM) 549 return compute_imstt_regvals_ibm(par, xres, yres); 550 else 551 return compute_imstt_regvals_tvp(par, xres, yres); 552} 553 554static void 555set_imstt_regvals_ibm (struct imstt_par *par, u_int bpp) 556{ 557 struct imstt_regvals *init = &par->init; 558 __u8 pformat = (bpp >> 3) + 2; 559 560 par->cmap_regs[PIDXHI] = 0; eieio(); 561 par->cmap_regs[PIDXLO] = PIXM0; eieio(); 562 par->cmap_regs[PIDXDATA] = init->pclk_m;eieio(); 563 par->cmap_regs[PIDXLO] = PIXN0; eieio(); 564 par->cmap_regs[PIDXDATA] = init->pclk_n;eieio(); 565 par->cmap_regs[PIDXLO] = PIXP0; eieio(); 566 par->cmap_regs[PIDXDATA] = init->pclk_p;eieio(); 567 par->cmap_regs[PIDXLO] = PIXC0; eieio(); 568 par->cmap_regs[PIDXDATA] = 0x02; eieio(); 569 570 par->cmap_regs[PIDXLO] = PIXFMT; eieio(); 571 par->cmap_regs[PIDXDATA] = pformat; eieio(); 572} 573 574static void 575set_imstt_regvals_tvp (struct imstt_par *par, u_int bpp) 576{ 577 struct imstt_regvals *init = &par->init; 578 __u8 tcc, mxc, lckl_n, mic; 579 __u8 mlc, lckl_p; 580 581 switch (bpp) { 582 default: 583 case 8: 584 tcc = 0x80; 585 mxc = 0x4d; 586 lckl_n = 0xc1; 587 mlc = init->mlc[0]; 588 lckl_p = init->lckl_p[0]; 589 break; 590 case 16: 591 tcc = 0x44; 592 mxc = 0x55; 593 lckl_n = 0xe1; 594 mlc = init->mlc[1]; 595 lckl_p = init->lckl_p[1]; 596 break; 597 case 24: 598 tcc = 0x5e; 599 mxc = 0x5d; 600 lckl_n = 0xf1; 601 mlc = init->mlc[2]; 602 lckl_p = init->lckl_p[2]; 603 break; 604 case 32: 605 tcc = 0x46; 606 mxc = 0x5d; 607 lckl_n = 0xf1; 608 mlc = init->mlc[2]; 609 lckl_p = init->lckl_p[2]; 610 break; 611 } 612 mic = 0x08; 613 614 par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio(); 615 par->cmap_regs[TVPIDATA] = 0x00; eieio(); 616 par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio(); 617 par->cmap_regs[TVPIDATA] = init->pclk_m; eieio(); 618 par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio(); 619 par->cmap_regs[TVPIDATA] = init->pclk_n; eieio(); 620 par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio(); 621 par->cmap_regs[TVPIDATA] = init->pclk_p; eieio(); 622 623 par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio(); 624 par->cmap_regs[TVPIDATA] = tcc; eieio(); 625 par->cmap_regs[TVPADDRW] = TVPIRMXC; eieio(); 626 par->cmap_regs[TVPIDATA] = mxc; eieio(); 627 par->cmap_regs[TVPADDRW] = TVPIRMIC; eieio(); 628 par->cmap_regs[TVPIDATA] = mic; eieio(); 629 630 par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio(); 631 par->cmap_regs[TVPIDATA] = 0x00; eieio(); 632 par->cmap_regs[TVPADDRW] = TVPIRLPD; eieio(); 633 par->cmap_regs[TVPIDATA] = lckl_n; eieio(); 634 635 par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio(); 636 par->cmap_regs[TVPIDATA] = 0x15; eieio(); 637 par->cmap_regs[TVPADDRW] = TVPIRMLC; eieio(); 638 par->cmap_regs[TVPIDATA] = mlc; eieio(); 639 640 par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio(); 641 par->cmap_regs[TVPIDATA] = 0x2a; eieio(); 642 par->cmap_regs[TVPADDRW] = TVPIRLPD; eieio(); 643 par->cmap_regs[TVPIDATA] = lckl_p; eieio(); 644} 645 646static void 647set_imstt_regvals (struct fb_info *info, u_int bpp) 648{ 649 struct imstt_par *par = info->par; 650 struct imstt_regvals *init = &par->init; 651 __u32 ctl, pitch, byteswap, scr; 652 653 if (par->ramdac == IBM) 654 set_imstt_regvals_ibm(par, bpp); 655 else 656 set_imstt_regvals_tvp(par, bpp); 657 658 /* 659 * From what I (jsk) can gather poking around with MacsBug, 660 * bits 8 and 9 in the SCR register control endianness 661 * correction (byte swapping). These bits must be set according 662 * to the color depth as follows: 663 * Color depth Bit 9 Bit 8 664 * ========== ===== ===== 665 * 8bpp 0 0 666 * 16bpp 0 1 667 * 32bpp 1 1 668 */ 669 switch (bpp) { 670 default: 671 case 8: 672 ctl = 0x17b1; 673 pitch = init->pitch >> 2; 674 byteswap = 0x000; 675 break; 676 case 16: 677 ctl = 0x17b3; 678 pitch = init->pitch >> 1; 679 byteswap = 0x100; 680 break; 681 case 24: 682 ctl = 0x17b9; 683 pitch = init->pitch - (init->pitch >> 2); 684 byteswap = 0x200; 685 break; 686 case 32: 687 ctl = 0x17b5; 688 pitch = init->pitch; 689 byteswap = 0x300; 690 break; 691 } 692 if (par->ramdac == TVP) 693 ctl -= 0x30; 694 695 write_reg_le32(par->dc_regs, HES, init->hes); 696 write_reg_le32(par->dc_regs, HEB, init->heb); 697 write_reg_le32(par->dc_regs, HSB, init->hsb); 698 write_reg_le32(par->dc_regs, HT, init->ht); 699 write_reg_le32(par->dc_regs, VES, init->ves); 700 write_reg_le32(par->dc_regs, VEB, init->veb); 701 write_reg_le32(par->dc_regs, VSB, init->vsb); 702 write_reg_le32(par->dc_regs, VT, init->vt); 703 write_reg_le32(par->dc_regs, VIL, init->vil); 704 write_reg_le32(par->dc_regs, HCIV, 1); 705 write_reg_le32(par->dc_regs, VCIV, 1); 706 write_reg_le32(par->dc_regs, TCDR, 4); 707 write_reg_le32(par->dc_regs, RRCIV, 1); 708 write_reg_le32(par->dc_regs, RRSC, 0x980); 709 write_reg_le32(par->dc_regs, RRCR, 0x11); 710 711 if (par->ramdac == IBM) { 712 write_reg_le32(par->dc_regs, HRIR, 0x0100); 713 write_reg_le32(par->dc_regs, CMR, 0x00ff); 714 write_reg_le32(par->dc_regs, SRGCTL, 0x0073); 715 } else { 716 write_reg_le32(par->dc_regs, HRIR, 0x0200); 717 write_reg_le32(par->dc_regs, CMR, 0x01ff); 718 write_reg_le32(par->dc_regs, SRGCTL, 0x0003); 719 } 720 721 switch (info->fix.smem_len) { 722 case 0x200000: 723 scr = 0x059d | byteswap; 724 break; 725 /* case 0x400000: 726 case 0x800000: */ 727 default: 728 pitch >>= 1; 729 scr = 0x150dd | byteswap; 730 break; 731 } 732 733 write_reg_le32(par->dc_regs, SCR, scr); 734 write_reg_le32(par->dc_regs, SPR, pitch); 735 write_reg_le32(par->dc_regs, STGCTL, ctl); 736} 737 738static inline void 739set_offset (struct fb_var_screeninfo *var, struct fb_info *info) 740{ 741 struct imstt_par *par = info->par; 742 __u32 off = var->yoffset * (info->fix.line_length >> 3) 743 + ((var->xoffset * (var->bits_per_pixel >> 3)) >> 3); 744 write_reg_le32(par->dc_regs, SSR, off); 745} 746 747static inline void 748set_555 (struct imstt_par *par) 749{ 750 if (par->ramdac == IBM) { 751 par->cmap_regs[PIDXHI] = 0; eieio(); 752 par->cmap_regs[PIDXLO] = BPP16; eieio(); 753 par->cmap_regs[PIDXDATA] = 0x01; eieio(); 754 } else { 755 par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio(); 756 par->cmap_regs[TVPIDATA] = 0x44; eieio(); 757 } 758} 759 760static inline void 761set_565 (struct imstt_par *par) 762{ 763 if (par->ramdac == IBM) { 764 par->cmap_regs[PIDXHI] = 0; eieio(); 765 par->cmap_regs[PIDXLO] = BPP16; eieio(); 766 par->cmap_regs[PIDXDATA] = 0x03; eieio(); 767 } else { 768 par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio(); 769 par->cmap_regs[TVPIDATA] = 0x45; eieio(); 770 } 771} 772 773static int 774imsttfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 775{ 776 if ((var->bits_per_pixel != 8 && var->bits_per_pixel != 16 777 && var->bits_per_pixel != 24 && var->bits_per_pixel != 32) 778 || var->xres_virtual < var->xres || var->yres_virtual < var->yres 779 || var->nonstd 780 || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) 781 return -EINVAL; 782 783 if ((var->xres * var->yres) * (var->bits_per_pixel >> 3) > info->fix.smem_len 784 || (var->xres_virtual * var->yres_virtual) * (var->bits_per_pixel >> 3) > info->fix.smem_len) 785 return -EINVAL; 786 787 switch (var->bits_per_pixel) { 788 case 8: 789 var->red.offset = 0; 790 var->red.length = 8; 791 var->green.offset = 0; 792 var->green.length = 8; 793 var->blue.offset = 0; 794 var->blue.length = 8; 795 var->transp.offset = 0; 796 var->transp.length = 0; 797 break; 798 case 16: /* RGB 555 or 565 */ 799 if (var->green.length != 6) 800 var->red.offset = 10; 801 var->red.length = 5; 802 var->green.offset = 5; 803 if (var->green.length != 6) 804 var->green.length = 5; 805 var->blue.offset = 0; 806 var->blue.length = 5; 807 var->transp.offset = 0; 808 var->transp.length = 0; 809 break; 810 case 24: /* RGB 888 */ 811 var->red.offset = 16; 812 var->red.length = 8; 813 var->green.offset = 8; 814 var->green.length = 8; 815 var->blue.offset = 0; 816 var->blue.length = 8; 817 var->transp.offset = 0; 818 var->transp.length = 0; 819 break; 820 case 32: /* RGBA 8888 */ 821 var->red.offset = 16; 822 var->red.length = 8; 823 var->green.offset = 8; 824 var->green.length = 8; 825 var->blue.offset = 0; 826 var->blue.length = 8; 827 var->transp.offset = 24; 828 var->transp.length = 8; 829 break; 830 } 831 832 if (var->yres == var->yres_virtual) { 833 __u32 vram = (info->fix.smem_len - (PAGE_SIZE << 2)); 834 var->yres_virtual = ((vram << 3) / var->bits_per_pixel) / var->xres_virtual; 835 if (var->yres_virtual < var->yres) 836 var->yres_virtual = var->yres; 837 } 838 839 var->red.msb_right = 0; 840 var->green.msb_right = 0; 841 var->blue.msb_right = 0; 842 var->transp.msb_right = 0; 843 var->height = -1; 844 var->width = -1; 845 var->vmode = FB_VMODE_NONINTERLACED; 846 var->left_margin = var->right_margin = 16; 847 var->upper_margin = var->lower_margin = 16; 848 var->hsync_len = var->vsync_len = 8; 849 return 0; 850} 851 852static int 853imsttfb_set_par(struct fb_info *info) 854{ 855 struct imstt_par *par = info->par; 856 857 if (!compute_imstt_regvals(par, info->var.xres, info->var.yres)) 858 return -EINVAL; 859 860 if (info->var.green.length == 6) 861 set_565(par); 862 else 863 set_555(par); 864 set_imstt_regvals(info, info->var.bits_per_pixel); 865 info->var.pixclock = 1000000 / getclkMHz(par); 866 return 0; 867} 868 869static int 870imsttfb_setcolreg (u_int regno, u_int red, u_int green, u_int blue, 871 u_int transp, struct fb_info *info) 872{ 873 struct imstt_par *par = info->par; 874 u_int bpp = info->var.bits_per_pixel; 875 876 if (regno > 255) 877 return 1; 878 879 red >>= 8; 880 green >>= 8; 881 blue >>= 8; 882 883 /* PADDRW/PDATA are the same as TVPPADDRW/TVPPDATA */ 884 if (0 && bpp == 16) /* screws up X */ 885 par->cmap_regs[PADDRW] = regno << 3; 886 else 887 par->cmap_regs[PADDRW] = regno; 888 eieio(); 889 890 par->cmap_regs[PDATA] = red; eieio(); 891 par->cmap_regs[PDATA] = green; eieio(); 892 par->cmap_regs[PDATA] = blue; eieio(); 893 894 if (regno < 16) 895 switch (bpp) { 896 case 16: 897 par->palette[regno] = 898 (regno << (info->var.green.length == 899 5 ? 10 : 11)) | (regno << 5) | regno; 900 break; 901 case 24: 902 par->palette[regno] = 903 (regno << 16) | (regno << 8) | regno; 904 break; 905 case 32: { 906 int i = (regno << 8) | regno; 907 par->palette[regno] = (i << 16) |i; 908 break; 909 } 910 } 911 return 0; 912} 913 914static int 915imsttfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) 916{ 917 if (var->xoffset + info->var.xres > info->var.xres_virtual 918 || var->yoffset + info->var.yres > info->var.yres_virtual) 919 return -EINVAL; 920 921 info->var.xoffset = var->xoffset; 922 info->var.yoffset = var->yoffset; 923 set_offset(var, info); 924 return 0; 925} 926 927static int 928imsttfb_blank(int blank, struct fb_info *info) 929{ 930 struct imstt_par *par = info->par; 931 __u32 ctrl; 932 933 ctrl = read_reg_le32(par->dc_regs, STGCTL); 934 if (blank > 0) { 935 switch (blank) { 936 case FB_BLANK_NORMAL: 937 case FB_BLANK_POWERDOWN: 938 ctrl &= ~0x00000380; 939 if (par->ramdac == IBM) { 940 par->cmap_regs[PIDXHI] = 0; eieio(); 941 par->cmap_regs[PIDXLO] = MISCTL2; eieio(); 942 par->cmap_regs[PIDXDATA] = 0x55; eieio(); 943 par->cmap_regs[PIDXLO] = MISCTL1; eieio(); 944 par->cmap_regs[PIDXDATA] = 0x11; eieio(); 945 par->cmap_regs[PIDXLO] = SYNCCTL; eieio(); 946 par->cmap_regs[PIDXDATA] = 0x0f; eieio(); 947 par->cmap_regs[PIDXLO] = PWRMNGMT; eieio(); 948 par->cmap_regs[PIDXDATA] = 0x1f; eieio(); 949 par->cmap_regs[PIDXLO] = CLKCTL; eieio(); 950 par->cmap_regs[PIDXDATA] = 0xc0; 951 } 952 break; 953 case FB_BLANK_VSYNC_SUSPEND: 954 ctrl &= ~0x00000020; 955 break; 956 case FB_BLANK_HSYNC_SUSPEND: 957 ctrl &= ~0x00000010; 958 break; 959 } 960 } else { 961 if (par->ramdac == IBM) { 962 ctrl |= 0x000017b0; 963 par->cmap_regs[PIDXHI] = 0; eieio(); 964 par->cmap_regs[PIDXLO] = CLKCTL; eieio(); 965 par->cmap_regs[PIDXDATA] = 0x01; eieio(); 966 par->cmap_regs[PIDXLO] = PWRMNGMT; eieio(); 967 par->cmap_regs[PIDXDATA] = 0x00; eieio(); 968 par->cmap_regs[PIDXLO] = SYNCCTL; eieio(); 969 par->cmap_regs[PIDXDATA] = 0x00; eieio(); 970 par->cmap_regs[PIDXLO] = MISCTL1; eieio(); 971 par->cmap_regs[PIDXDATA] = 0x01; eieio(); 972 par->cmap_regs[PIDXLO] = MISCTL2; eieio(); 973 par->cmap_regs[PIDXDATA] = 0x45; eieio(); 974 } else 975 ctrl |= 0x00001780; 976 } 977 write_reg_le32(par->dc_regs, STGCTL, ctrl); 978 return 0; 979} 980 981static void 982imsttfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 983{ 984 struct imstt_par *par = info->par; 985 __u32 Bpp, line_pitch, bgc, dx, dy, width, height; 986 987 bgc = rect->color; 988 bgc |= (bgc << 8); 989 bgc |= (bgc << 16); 990 991 Bpp = info->var.bits_per_pixel >> 3, 992 line_pitch = info->fix.line_length; 993 994 dy = rect->dy * line_pitch; 995 dx = rect->dx * Bpp; 996 height = rect->height; 997 height--; 998 width = rect->width * Bpp; 999 width--; 1000 1001 if (rect->rop == ROP_COPY) { 1002 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80); 1003 write_reg_le32(par->dc_regs, DSA, dy + dx); 1004 write_reg_le32(par->dc_regs, CNT, (height << 16) | width); 1005 write_reg_le32(par->dc_regs, DP_OCTL, line_pitch); 1006 write_reg_le32(par->dc_regs, BI, 0xffffffff); 1007 write_reg_le32(par->dc_regs, MBC, 0xffffffff); 1008 write_reg_le32(par->dc_regs, CLR, bgc); 1009 write_reg_le32(par->dc_regs, BLTCTL, 0x840); /* 0x200000 */ 1010 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80); 1011 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40); 1012 } else { 1013 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80); 1014 write_reg_le32(par->dc_regs, DSA, dy + dx); 1015 write_reg_le32(par->dc_regs, S1SA, dy + dx); 1016 write_reg_le32(par->dc_regs, CNT, (height << 16) | width); 1017 write_reg_le32(par->dc_regs, DP_OCTL, line_pitch); 1018 write_reg_le32(par->dc_regs, SP, line_pitch); 1019 write_reg_le32(par->dc_regs, BLTCTL, 0x40005); 1020 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80); 1021 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40); 1022 } 1023} 1024 1025static void 1026imsttfb_copyarea(struct fb_info *info, const struct fb_copyarea *area) 1027{ 1028 struct imstt_par *par = info->par; 1029 __u32 Bpp, line_pitch, fb_offset_old, fb_offset_new, sp, dp_octl; 1030 __u32 cnt, bltctl, sx, sy, dx, dy, height, width; 1031 1032 Bpp = info->var.bits_per_pixel >> 3, 1033 1034 sx = area->sx * Bpp; 1035 sy = area->sy; 1036 dx = area->dx * Bpp; 1037 dy = area->dy; 1038 height = area->height; 1039 height--; 1040 width = area->width * Bpp; 1041 width--; 1042 1043 line_pitch = info->fix.line_length; 1044 bltctl = 0x05; 1045 sp = line_pitch << 16; 1046 cnt = height << 16; 1047 1048 if (sy < dy) { 1049 sy += height; 1050 dy += height; 1051 sp |= -(line_pitch) & 0xffff; 1052 dp_octl = -(line_pitch) & 0xffff; 1053 } else { 1054 sp |= line_pitch; 1055 dp_octl = line_pitch; 1056 } 1057 if (sx < dx) { 1058 sx += width; 1059 dx += width; 1060 bltctl |= 0x80; 1061 cnt |= -(width) & 0xffff; 1062 } else { 1063 cnt |= width; 1064 } 1065 fb_offset_old = sy * line_pitch + sx; 1066 fb_offset_new = dy * line_pitch + dx; 1067 1068 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80); 1069 write_reg_le32(par->dc_regs, S1SA, fb_offset_old); 1070 write_reg_le32(par->dc_regs, SP, sp); 1071 write_reg_le32(par->dc_regs, DSA, fb_offset_new); 1072 write_reg_le32(par->dc_regs, CNT, cnt); 1073 write_reg_le32(par->dc_regs, DP_OCTL, dp_octl); 1074 write_reg_le32(par->dc_regs, BLTCTL, bltctl); 1075 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80); 1076 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40); 1077} 1078 1079 1080#define FBIMSTT_SETREG 0x545401 1081#define FBIMSTT_GETREG 0x545402 1082#define FBIMSTT_SETCMAPREG 0x545403 1083#define FBIMSTT_GETCMAPREG 0x545404 1084#define FBIMSTT_SETIDXREG 0x545405 1085#define FBIMSTT_GETIDXREG 0x545406 1086 1087static int 1088imsttfb_ioctl(struct fb_info *info, u_int cmd, u_long arg) 1089{ 1090 struct imstt_par *par = info->par; 1091 void __user *argp = (void __user *)arg; 1092 __u32 reg[2]; 1093 __u8 idx[2]; 1094 1095 switch (cmd) { 1096 case FBIMSTT_SETREG: 1097 if (copy_from_user(reg, argp, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0])) 1098 return -EFAULT; 1099 write_reg_le32(par->dc_regs, reg[0], reg[1]); 1100 return 0; 1101 case FBIMSTT_GETREG: 1102 if (copy_from_user(reg, argp, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0])) 1103 return -EFAULT; 1104 reg[1] = read_reg_le32(par->dc_regs, reg[0]); 1105 if (copy_to_user((void __user *)(arg + 4), ®[1], 4)) 1106 return -EFAULT; 1107 return 0; 1108 case FBIMSTT_SETCMAPREG: 1109 if (copy_from_user(reg, argp, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0])) 1110 return -EFAULT; 1111 write_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0], reg[1]); 1112 return 0; 1113 case FBIMSTT_GETCMAPREG: 1114 if (copy_from_user(reg, argp, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0])) 1115 return -EFAULT; 1116 reg[1] = read_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0]); 1117 if (copy_to_user((void __user *)(arg + 4), ®[1], 4)) 1118 return -EFAULT; 1119 return 0; 1120 case FBIMSTT_SETIDXREG: 1121 if (copy_from_user(idx, argp, 2)) 1122 return -EFAULT; 1123 par->cmap_regs[PIDXHI] = 0; eieio(); 1124 par->cmap_regs[PIDXLO] = idx[0]; eieio(); 1125 par->cmap_regs[PIDXDATA] = idx[1]; eieio(); 1126 return 0; 1127 case FBIMSTT_GETIDXREG: 1128 if (copy_from_user(idx, argp, 1)) 1129 return -EFAULT; 1130 par->cmap_regs[PIDXHI] = 0; eieio(); 1131 par->cmap_regs[PIDXLO] = idx[0]; eieio(); 1132 idx[1] = par->cmap_regs[PIDXDATA]; 1133 if (copy_to_user((void __user *)(arg + 1), &idx[1], 1)) 1134 return -EFAULT; 1135 return 0; 1136 default: 1137 return -ENOIOCTLCMD; 1138 } 1139} 1140 1141static struct pci_device_id imsttfb_pci_tbl[] = { 1142 { PCI_VENDOR_ID_IMS, PCI_DEVICE_ID_IMS_TT128, 1143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, IBM }, 1144 { PCI_VENDOR_ID_IMS, PCI_DEVICE_ID_IMS_TT3D, 1145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TVP }, 1146 { 0, } 1147}; 1148 1149MODULE_DEVICE_TABLE(pci, imsttfb_pci_tbl); 1150 1151static struct pci_driver imsttfb_pci_driver = { 1152 .name = "imsttfb", 1153 .id_table = imsttfb_pci_tbl, 1154 .probe = imsttfb_probe, 1155 .remove = __devexit_p(imsttfb_remove), 1156}; 1157 1158static struct fb_ops imsttfb_ops = { 1159 .owner = THIS_MODULE, 1160 .fb_check_var = imsttfb_check_var, 1161 .fb_set_par = imsttfb_set_par, 1162 .fb_setcolreg = imsttfb_setcolreg, 1163 .fb_pan_display = imsttfb_pan_display, 1164 .fb_blank = imsttfb_blank, 1165 .fb_fillrect = imsttfb_fillrect, 1166 .fb_copyarea = imsttfb_copyarea, 1167 .fb_imageblit = cfb_imageblit, 1168 .fb_ioctl = imsttfb_ioctl, 1169}; 1170 1171static void __devinit 1172init_imstt(struct fb_info *info) 1173{ 1174 struct imstt_par *par = info->par; 1175 __u32 i, tmp, *ip, *end; 1176 1177 tmp = read_reg_le32(par->dc_regs, PRC); 1178 if (par->ramdac == IBM) 1179 info->fix.smem_len = (tmp & 0x0004) ? 0x400000 : 0x200000; 1180 else 1181 info->fix.smem_len = 0x800000; 1182 1183 ip = (__u32 *)info->screen_base; 1184 end = (__u32 *)(info->screen_base + info->fix.smem_len); 1185 while (ip < end) 1186 *ip++ = 0; 1187 1188 /* initialize the card */ 1189 tmp = read_reg_le32(par->dc_regs, STGCTL); 1190 write_reg_le32(par->dc_regs, STGCTL, tmp & ~0x1); 1191 write_reg_le32(par->dc_regs, SSR, 0); 1192 1193 /* set default values for DAC registers */ 1194 if (par->ramdac == IBM) { 1195 par->cmap_regs[PPMASK] = 0xff; 1196 eieio(); 1197 par->cmap_regs[PIDXHI] = 0; 1198 eieio(); 1199 for (i = 0; i < ARRAY_SIZE(ibm_initregs); i++) { 1200 par->cmap_regs[PIDXLO] = ibm_initregs[i].addr; 1201 eieio(); 1202 par->cmap_regs[PIDXDATA] = ibm_initregs[i].value; 1203 eieio(); 1204 } 1205 } else { 1206 for (i = 0; i < ARRAY_SIZE(tvp_initregs); i++) { 1207 par->cmap_regs[TVPADDRW] = tvp_initregs[i].addr; 1208 eieio(); 1209 par->cmap_regs[TVPIDATA] = tvp_initregs[i].value; 1210 eieio(); 1211 } 1212 } 1213 1214#if USE_NV_MODES && defined(CONFIG_PPC32) 1215 { 1216 int vmode = init_vmode, cmode = init_cmode; 1217 1218 if (vmode == -1) { 1219 vmode = nvram_read_byte(NV_VMODE); 1220 if (vmode <= 0 || vmode > VMODE_MAX) 1221 vmode = VMODE_640_480_67; 1222 } 1223 if (cmode == -1) { 1224 cmode = nvram_read_byte(NV_CMODE); 1225 if (cmode < CMODE_8 || cmode > CMODE_32) 1226 cmode = CMODE_8; 1227 } 1228 if (mac_vmode_to_var(vmode, cmode, &info->var)) { 1229 info->var.xres = info->var.xres_virtual = INIT_XRES; 1230 info->var.yres = info->var.yres_virtual = INIT_YRES; 1231 info->var.bits_per_pixel = INIT_BPP; 1232 } 1233 } 1234#else 1235 info->var.xres = info->var.xres_virtual = INIT_XRES; 1236 info->var.yres = info->var.yres_virtual = INIT_YRES; 1237 info->var.bits_per_pixel = INIT_BPP; 1238#endif 1239 1240 if ((info->var.xres * info->var.yres) * (info->var.bits_per_pixel >> 3) > info->fix.smem_len 1241 || !(compute_imstt_regvals(par, info->var.xres, info->var.yres))) { 1242 printk("imsttfb: %ux%ux%u not supported\n", info->var.xres, info->var.yres, info->var.bits_per_pixel); 1243 framebuffer_release(info); 1244 return; 1245 } 1246 1247 sprintf(info->fix.id, "IMS TT (%s)", par->ramdac == IBM ? "IBM" : "TVP"); 1248 info->fix.mmio_len = 0x1000; 1249 info->fix.accel = FB_ACCEL_IMS_TWINTURBO; 1250 info->fix.type = FB_TYPE_PACKED_PIXELS; 1251 info->fix.visual = info->var.bits_per_pixel == 8 ? FB_VISUAL_PSEUDOCOLOR 1252 : FB_VISUAL_DIRECTCOLOR; 1253 info->fix.line_length = info->var.xres * (info->var.bits_per_pixel >> 3); 1254 info->fix.xpanstep = 8; 1255 info->fix.ypanstep = 1; 1256 info->fix.ywrapstep = 0; 1257 1258 info->var.accel_flags = FB_ACCELF_TEXT; 1259 1260// if (par->ramdac == IBM) 1261// imstt_cursor_init(info); 1262 if (info->var.green.length == 6) 1263 set_565(par); 1264 else 1265 set_555(par); 1266 set_imstt_regvals(info, info->var.bits_per_pixel); 1267 1268 info->var.pixclock = 1000000 / getclkMHz(par); 1269 1270 info->fbops = &imsttfb_ops; 1271 info->flags = FBINFO_DEFAULT | 1272 FBINFO_HWACCEL_COPYAREA | 1273 FBINFO_HWACCEL_FILLRECT | 1274 FBINFO_HWACCEL_YPAN; 1275 1276 fb_alloc_cmap(&info->cmap, 0, 0); 1277 1278 if (register_framebuffer(info) < 0) { 1279 framebuffer_release(info); 1280 return; 1281 } 1282 1283 tmp = (read_reg_le32(par->dc_regs, SSTATUS) & 0x0f00) >> 8; 1284 printk("fb%u: %s frame buffer; %uMB vram; chip version %u\n", 1285 info->node, info->fix.id, info->fix.smem_len >> 20, tmp); 1286} 1287 1288static int __devinit 1289imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1290{ 1291 unsigned long addr, size; 1292 struct imstt_par *par; 1293 struct fb_info *info; 1294#ifdef CONFIG_PPC_OF 1295 struct device_node *dp; 1296 1297 dp = pci_device_to_OF_node(pdev); 1298 if(dp) 1299 printk(KERN_INFO "%s: OF name %s\n",__func__, dp->name); 1300 else 1301 printk(KERN_ERR "imsttfb: no OF node for pci device\n"); 1302#endif /* CONFIG_PPC_OF */ 1303 1304 info = framebuffer_alloc(sizeof(struct imstt_par), &pdev->dev); 1305 1306 if (!info) { 1307 printk(KERN_ERR "imsttfb: Can't allocate memory\n"); 1308 return -ENOMEM; 1309 } 1310 1311 par = info->par; 1312 1313 addr = pci_resource_start (pdev, 0); 1314 size = pci_resource_len (pdev, 0); 1315 1316 if (!request_mem_region(addr, size, "imsttfb")) { 1317 printk(KERN_ERR "imsttfb: Can't reserve memory region\n"); 1318 framebuffer_release(info); 1319 return -ENODEV; 1320 } 1321 1322 switch (pdev->device) { 1323 case PCI_DEVICE_ID_IMS_TT128: /* IMS,tt128mbA */ 1324 par->ramdac = IBM; 1325#ifdef CONFIG_PPC_OF 1326 if (dp && ((strcmp(dp->name, "IMS,tt128mb8") == 0) || 1327 (strcmp(dp->name, "IMS,tt128mb8A") == 0))) 1328 par->ramdac = TVP; 1329#endif /* CONFIG_PPC_OF */ 1330 break; 1331 case PCI_DEVICE_ID_IMS_TT3D: /* IMS,tt3d */ 1332 par->ramdac = TVP; 1333 break; 1334 default: 1335 printk(KERN_INFO "imsttfb: Device 0x%x unknown, " 1336 "contact maintainer.\n", pdev->device); 1337 release_mem_region(addr, size); 1338 framebuffer_release(info); 1339 return -ENODEV; 1340 } 1341 1342 info->fix.smem_start = addr; 1343 info->screen_base = (__u8 *)ioremap(addr, par->ramdac == IBM ? 1344 0x400000 : 0x800000); 1345 info->fix.mmio_start = addr + 0x800000; 1346 par->dc_regs = ioremap(addr + 0x800000, 0x1000); 1347 par->cmap_regs_phys = addr + 0x840000; 1348 par->cmap_regs = (__u8 *)ioremap(addr + 0x840000, 0x1000); 1349 info->pseudo_palette = par->palette; 1350 init_imstt(info); 1351 1352 pci_set_drvdata(pdev, info); 1353 return 0; 1354} 1355 1356static void __devexit 1357imsttfb_remove(struct pci_dev *pdev) 1358{ 1359 struct fb_info *info = pci_get_drvdata(pdev); 1360 struct imstt_par *par = info->par; 1361 int size = pci_resource_len(pdev, 0); 1362 1363 unregister_framebuffer(info); 1364 iounmap(par->cmap_regs); 1365 iounmap(par->dc_regs); 1366 iounmap(info->screen_base); 1367 release_mem_region(info->fix.smem_start, size); 1368 framebuffer_release(info); 1369} 1370 1371#ifndef MODULE 1372static int __init 1373imsttfb_setup(char *options) 1374{ 1375 char *this_opt; 1376 1377 if (!options || !*options) 1378 return 0; 1379 1380 while ((this_opt = strsep(&options, ",")) != NULL) { 1381 if (!strncmp(this_opt, "font:", 5)) { 1382 char *p; 1383 int i; 1384 1385 p = this_opt + 5; 1386 for (i = 0; i < sizeof(fontname) - 1; i++) 1387 if (!*p || *p == ' ' || *p == ',') 1388 break; 1389 memcpy(fontname, this_opt + 5, i); 1390 fontname[i] = 0; 1391 } else if (!strncmp(this_opt, "inverse", 7)) { 1392 inverse = 1; 1393 fb_invert_cmaps(); 1394 } 1395#if defined(CONFIG_PPC) 1396 else if (!strncmp(this_opt, "vmode:", 6)) { 1397 int vmode = simple_strtoul(this_opt+6, NULL, 0); 1398 if (vmode > 0 && vmode <= VMODE_MAX) 1399 init_vmode = vmode; 1400 } else if (!strncmp(this_opt, "cmode:", 6)) { 1401 int cmode = simple_strtoul(this_opt+6, NULL, 0); 1402 switch (cmode) { 1403 case CMODE_8: 1404 case 8: 1405 init_cmode = CMODE_8; 1406 break; 1407 case CMODE_16: 1408 case 15: 1409 case 16: 1410 init_cmode = CMODE_16; 1411 break; 1412 case CMODE_32: 1413 case 24: 1414 case 32: 1415 init_cmode = CMODE_32; 1416 break; 1417 } 1418 } 1419#endif 1420 } 1421 return 0; 1422} 1423 1424#endif /* MODULE */ 1425 1426static int __init imsttfb_init(void) 1427{ 1428#ifndef MODULE 1429 char *option = NULL; 1430 1431 if (fb_get_options("imsttfb", &option)) 1432 return -ENODEV; 1433 1434 imsttfb_setup(option); 1435#endif 1436 return pci_register_driver(&imsttfb_pci_driver); 1437} 1438 1439static void __exit imsttfb_exit(void) 1440{ 1441 pci_unregister_driver(&imsttfb_pci_driver); 1442} 1443 1444MODULE_LICENSE("GPL"); 1445 1446module_init(imsttfb_init); 1447module_exit(imsttfb_exit); 1448