1/* 2 * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface 3 * 4 * Copyright (C) 2006 Nokia Corporation 5 * Tony Lindgren <tony@atomide.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/module.h> 12#include <linux/kernel.h> 13#include <linux/errno.h> 14#include <linux/init.h> 15#include <linux/usb.h> 16#include <linux/platform_device.h> 17#include <linux/dma-mapping.h> 18#include <linux/slab.h> 19#include <plat/dma.h> 20#include <plat/mux.h> 21 22#include "musb_core.h" 23 24#define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data) 25 26#define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */ 27 28struct tusb_omap_dma_ch { 29 struct musb *musb; 30 void __iomem *tbase; 31 unsigned long phys_offset; 32 int epnum; 33 u8 tx; 34 struct musb_hw_ep *hw_ep; 35 36 int ch; 37 s8 dmareq; 38 s8 sync_dev; 39 40 struct tusb_omap_dma *tusb_dma; 41 42 dma_addr_t dma_addr; 43 44 u32 len; 45 u16 packet_sz; 46 u16 transfer_packet_sz; 47 u32 transfer_len; 48 u32 completed_len; 49}; 50 51struct tusb_omap_dma { 52 struct dma_controller controller; 53 struct musb *musb; 54 void __iomem *tbase; 55 56 int ch; 57 s8 dmareq; 58 s8 sync_dev; 59 unsigned multichannel:1; 60}; 61 62static int tusb_omap_dma_start(struct dma_controller *c) 63{ 64 struct tusb_omap_dma *tusb_dma; 65 66 tusb_dma = container_of(c, struct tusb_omap_dma, controller); 67 68 /* DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */ 69 70 return 0; 71} 72 73static int tusb_omap_dma_stop(struct dma_controller *c) 74{ 75 struct tusb_omap_dma *tusb_dma; 76 77 tusb_dma = container_of(c, struct tusb_omap_dma, controller); 78 79 /* DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */ 80 81 return 0; 82} 83 84/* 85 * Allocate dmareq0 to the current channel unless it's already taken 86 */ 87static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat) 88{ 89 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 90 91 if (reg != 0) { 92 DBG(3, "ep%i dmareq0 is busy for ep%i\n", 93 chdat->epnum, reg & 0xf); 94 return -EAGAIN; 95 } 96 97 if (chdat->tx) 98 reg = (1 << 4) | chdat->epnum; 99 else 100 reg = chdat->epnum; 101 102 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); 103 104 return 0; 105} 106 107static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat) 108{ 109 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 110 111 if ((reg & 0xf) != chdat->epnum) { 112 printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n", 113 chdat->epnum, reg & 0xf); 114 return; 115 } 116 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0); 117} 118 119/* 120 * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in 121 * musb_gadget.c. 122 */ 123static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data) 124{ 125 struct dma_channel *channel = (struct dma_channel *)data; 126 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 127 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 128 struct musb *musb = chdat->musb; 129 struct device *dev = musb->controller; 130 struct musb_hw_ep *hw_ep = chdat->hw_ep; 131 void __iomem *ep_conf = hw_ep->conf; 132 void __iomem *mbase = musb->mregs; 133 unsigned long remaining, flags, pio; 134 int ch; 135 136 spin_lock_irqsave(&musb->lock, flags); 137 138 if (tusb_dma->multichannel) 139 ch = chdat->ch; 140 else 141 ch = tusb_dma->ch; 142 143 if (ch_status != OMAP_DMA_BLOCK_IRQ) 144 printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status); 145 146 DBG(3, "ep%i %s dma callback ch: %i status: %x\n", 147 chdat->epnum, chdat->tx ? "tx" : "rx", 148 ch, ch_status); 149 150 if (chdat->tx) 151 remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET); 152 else 153 remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET); 154 155 remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining); 156 157 /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */ 158 if (unlikely(remaining > chdat->transfer_len)) { 159 DBG(2, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n", 160 chdat->tx ? "tx" : "rx", chdat->ch, 161 remaining); 162 remaining = 0; 163 } 164 165 channel->actual_len = chdat->transfer_len - remaining; 166 pio = chdat->len - channel->actual_len; 167 168 DBG(3, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len); 169 170 /* Transfer remaining 1 - 31 bytes */ 171 if (pio > 0 && pio < 32) { 172 u8 *buf; 173 174 DBG(3, "Using PIO for remaining %lu bytes\n", pio); 175 buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len; 176 if (chdat->tx) { 177 dma_unmap_single(dev, chdat->dma_addr, 178 chdat->transfer_len, 179 DMA_TO_DEVICE); 180 musb_write_fifo(hw_ep, pio, buf); 181 } else { 182 dma_unmap_single(dev, chdat->dma_addr, 183 chdat->transfer_len, 184 DMA_FROM_DEVICE); 185 musb_read_fifo(hw_ep, pio, buf); 186 } 187 channel->actual_len += pio; 188 } 189 190 if (!tusb_dma->multichannel) 191 tusb_omap_free_shared_dmareq(chdat); 192 193 channel->status = MUSB_DMA_STATUS_FREE; 194 195 /* Handle only RX callbacks here. TX callbacks must be handled based 196 * on the TUSB DMA status interrupt. 197 * REVISIT: Use both TUSB DMA status interrupt and OMAP DMA callback 198 * interrupt for RX and TX. 199 */ 200 if (!chdat->tx) 201 musb_dma_completion(musb, chdat->epnum, chdat->tx); 202 203 /* We must terminate short tx transfers manually by setting TXPKTRDY. 204 * REVISIT: This same problem may occur with other MUSB dma as well. 205 * Easy to test with g_ether by pinging the MUSB board with ping -s54. 206 */ 207 if ((chdat->transfer_len < chdat->packet_sz) 208 || (chdat->transfer_len % chdat->packet_sz != 0)) { 209 u16 csr; 210 211 if (chdat->tx) { 212 DBG(3, "terminating short tx packet\n"); 213 musb_ep_select(mbase, chdat->epnum); 214 csr = musb_readw(hw_ep->regs, MUSB_TXCSR); 215 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY 216 | MUSB_TXCSR_P_WZC_BITS; 217 musb_writew(hw_ep->regs, MUSB_TXCSR, csr); 218 } 219 } 220 221 spin_unlock_irqrestore(&musb->lock, flags); 222} 223 224static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz, 225 u8 rndis_mode, dma_addr_t dma_addr, u32 len) 226{ 227 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 228 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 229 struct musb *musb = chdat->musb; 230 struct device *dev = musb->controller; 231 struct musb_hw_ep *hw_ep = chdat->hw_ep; 232 void __iomem *mbase = musb->mregs; 233 void __iomem *ep_conf = hw_ep->conf; 234 dma_addr_t fifo = hw_ep->fifo_sync; 235 struct omap_dma_channel_params dma_params; 236 u32 dma_remaining; 237 int src_burst, dst_burst; 238 u16 csr; 239 int ch; 240 s8 dmareq; 241 s8 sync_dev; 242 243 if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz)) 244 return false; 245 246 /* 247 * HW issue #10: Async dma will eventually corrupt the XFR_SIZE 248 * register which will cause missed DMA interrupt. We could try to 249 * use a timer for the callback, but it is unsafe as the XFR_SIZE 250 * register is corrupt, and we won't know if the DMA worked. 251 */ 252 if (dma_addr & 0x2) 253 return false; 254 255 /* 256 * Because of HW issue #10, it seems like mixing sync DMA and async 257 * PIO access can confuse the DMA. Make sure XFR_SIZE is reset before 258 * using the channel for DMA. 259 */ 260 if (chdat->tx) 261 dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET); 262 else 263 dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET); 264 265 dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining); 266 if (dma_remaining) { 267 DBG(2, "Busy %s dma ch%i, not using: %08x\n", 268 chdat->tx ? "tx" : "rx", chdat->ch, 269 dma_remaining); 270 return false; 271 } 272 273 chdat->transfer_len = len & ~0x1f; 274 275 if (len < packet_sz) 276 chdat->transfer_packet_sz = chdat->transfer_len; 277 else 278 chdat->transfer_packet_sz = packet_sz; 279 280 if (tusb_dma->multichannel) { 281 ch = chdat->ch; 282 dmareq = chdat->dmareq; 283 sync_dev = chdat->sync_dev; 284 } else { 285 if (tusb_omap_use_shared_dmareq(chdat) != 0) { 286 DBG(3, "could not get dma for ep%i\n", chdat->epnum); 287 return false; 288 } 289 if (tusb_dma->ch < 0) { 290 /* REVISIT: This should get blocked earlier, happens 291 * with MSC ErrorRecoveryTest 292 */ 293 WARN_ON(1); 294 return false; 295 } 296 297 ch = tusb_dma->ch; 298 dmareq = tusb_dma->dmareq; 299 sync_dev = tusb_dma->sync_dev; 300 omap_set_dma_callback(ch, tusb_omap_dma_cb, channel); 301 } 302 303 chdat->packet_sz = packet_sz; 304 chdat->len = len; 305 channel->actual_len = 0; 306 chdat->dma_addr = dma_addr; 307 channel->status = MUSB_DMA_STATUS_BUSY; 308 309 /* Since we're recycling dma areas, we need to clean or invalidate */ 310 if (chdat->tx) 311 dma_map_single(dev, phys_to_virt(dma_addr), len, 312 DMA_TO_DEVICE); 313 else 314 dma_map_single(dev, phys_to_virt(dma_addr), len, 315 DMA_FROM_DEVICE); 316 317 /* Use 16-bit transfer if dma_addr is not 32-bit aligned */ 318 if ((dma_addr & 0x3) == 0) { 319 dma_params.data_type = OMAP_DMA_DATA_TYPE_S32; 320 dma_params.elem_count = 8; /* Elements in frame */ 321 } else { 322 dma_params.data_type = OMAP_DMA_DATA_TYPE_S16; 323 dma_params.elem_count = 16; /* Elements in frame */ 324 fifo = hw_ep->fifo_async; 325 } 326 327 dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */ 328 329 DBG(3, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n", 330 chdat->epnum, chdat->tx ? "tx" : "rx", 331 ch, dma_addr, chdat->transfer_len, len, 332 chdat->transfer_packet_sz, packet_sz); 333 334 /* 335 * Prepare omap DMA for transfer 336 */ 337 if (chdat->tx) { 338 dma_params.src_amode = OMAP_DMA_AMODE_POST_INC; 339 dma_params.src_start = (unsigned long)dma_addr; 340 dma_params.src_ei = 0; 341 dma_params.src_fi = 0; 342 343 dma_params.dst_amode = OMAP_DMA_AMODE_DOUBLE_IDX; 344 dma_params.dst_start = (unsigned long)fifo; 345 dma_params.dst_ei = 1; 346 dma_params.dst_fi = -31; /* Loop 32 byte window */ 347 348 dma_params.trigger = sync_dev; 349 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME; 350 dma_params.src_or_dst_synch = 0; /* Dest sync */ 351 352 src_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 read */ 353 dst_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 write */ 354 } else { 355 dma_params.src_amode = OMAP_DMA_AMODE_DOUBLE_IDX; 356 dma_params.src_start = (unsigned long)fifo; 357 dma_params.src_ei = 1; 358 dma_params.src_fi = -31; /* Loop 32 byte window */ 359 360 dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC; 361 dma_params.dst_start = (unsigned long)dma_addr; 362 dma_params.dst_ei = 0; 363 dma_params.dst_fi = 0; 364 365 dma_params.trigger = sync_dev; 366 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME; 367 dma_params.src_or_dst_synch = 1; /* Source sync */ 368 369 src_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 read */ 370 dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */ 371 } 372 373 DBG(3, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n", 374 chdat->epnum, chdat->tx ? "tx" : "rx", 375 (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16, 376 ((dma_addr & 0x3) == 0) ? "sync" : "async", 377 dma_params.src_start, dma_params.dst_start); 378 379 omap_set_dma_params(ch, &dma_params); 380 omap_set_dma_src_burst_mode(ch, src_burst); 381 omap_set_dma_dest_burst_mode(ch, dst_burst); 382 omap_set_dma_write_mode(ch, OMAP_DMA_WRITE_LAST_NON_POSTED); 383 384 /* 385 * Prepare MUSB for DMA transfer 386 */ 387 if (chdat->tx) { 388 musb_ep_select(mbase, chdat->epnum); 389 csr = musb_readw(hw_ep->regs, MUSB_TXCSR); 390 csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB 391 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE); 392 csr &= ~MUSB_TXCSR_P_UNDERRUN; 393 musb_writew(hw_ep->regs, MUSB_TXCSR, csr); 394 } else { 395 musb_ep_select(mbase, chdat->epnum); 396 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 397 csr |= MUSB_RXCSR_DMAENAB; 398 csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE); 399 musb_writew(hw_ep->regs, MUSB_RXCSR, 400 csr | MUSB_RXCSR_P_WZC_BITS); 401 } 402 403 /* 404 * Start DMA transfer 405 */ 406 omap_start_dma(ch); 407 408 if (chdat->tx) { 409 /* Send transfer_packet_sz packets at a time */ 410 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, 411 chdat->transfer_packet_sz); 412 413 musb_writel(ep_conf, TUSB_EP_TX_OFFSET, 414 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len)); 415 } else { 416 /* Receive transfer_packet_sz packets at a time */ 417 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, 418 chdat->transfer_packet_sz << 16); 419 420 musb_writel(ep_conf, TUSB_EP_RX_OFFSET, 421 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len)); 422 } 423 424 return true; 425} 426 427static int tusb_omap_dma_abort(struct dma_channel *channel) 428{ 429 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 430 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 431 432 if (!tusb_dma->multichannel) { 433 if (tusb_dma->ch >= 0) { 434 omap_stop_dma(tusb_dma->ch); 435 omap_free_dma(tusb_dma->ch); 436 tusb_dma->ch = -1; 437 } 438 439 tusb_dma->dmareq = -1; 440 tusb_dma->sync_dev = -1; 441 } 442 443 channel->status = MUSB_DMA_STATUS_FREE; 444 445 return 0; 446} 447 448static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat) 449{ 450 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 451 int i, dmareq_nr = -1; 452 453 const int sync_dev[6] = { 454 OMAP24XX_DMA_EXT_DMAREQ0, 455 OMAP24XX_DMA_EXT_DMAREQ1, 456 OMAP242X_DMA_EXT_DMAREQ2, 457 OMAP242X_DMA_EXT_DMAREQ3, 458 OMAP242X_DMA_EXT_DMAREQ4, 459 OMAP242X_DMA_EXT_DMAREQ5, 460 }; 461 462 for (i = 0; i < MAX_DMAREQ; i++) { 463 int cur = (reg & (0xf << (i * 5))) >> (i * 5); 464 if (cur == 0) { 465 dmareq_nr = i; 466 break; 467 } 468 } 469 470 if (dmareq_nr == -1) 471 return -EAGAIN; 472 473 reg |= (chdat->epnum << (dmareq_nr * 5)); 474 if (chdat->tx) 475 reg |= ((1 << 4) << (dmareq_nr * 5)); 476 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); 477 478 chdat->dmareq = dmareq_nr; 479 chdat->sync_dev = sync_dev[chdat->dmareq]; 480 481 return 0; 482} 483 484static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat) 485{ 486 u32 reg; 487 488 if (!chdat || chdat->dmareq < 0) 489 return; 490 491 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 492 reg &= ~(0x1f << (chdat->dmareq * 5)); 493 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); 494 495 chdat->dmareq = -1; 496 chdat->sync_dev = -1; 497} 498 499static struct dma_channel *dma_channel_pool[MAX_DMAREQ]; 500 501static struct dma_channel * 502tusb_omap_dma_allocate(struct dma_controller *c, 503 struct musb_hw_ep *hw_ep, 504 u8 tx) 505{ 506 int ret, i; 507 const char *dev_name; 508 struct tusb_omap_dma *tusb_dma; 509 struct musb *musb; 510 void __iomem *tbase; 511 struct dma_channel *channel = NULL; 512 struct tusb_omap_dma_ch *chdat = NULL; 513 u32 reg; 514 515 tusb_dma = container_of(c, struct tusb_omap_dma, controller); 516 musb = tusb_dma->musb; 517 tbase = musb->ctrl_base; 518 519 reg = musb_readl(tbase, TUSB_DMA_INT_MASK); 520 if (tx) 521 reg &= ~(1 << hw_ep->epnum); 522 else 523 reg &= ~(1 << (hw_ep->epnum + 15)); 524 musb_writel(tbase, TUSB_DMA_INT_MASK, reg); 525 526 /* REVISIT: Why does dmareq5 not work? */ 527 if (hw_ep->epnum == 0) { 528 DBG(3, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx"); 529 return NULL; 530 } 531 532 for (i = 0; i < MAX_DMAREQ; i++) { 533 struct dma_channel *ch = dma_channel_pool[i]; 534 if (ch->status == MUSB_DMA_STATUS_UNKNOWN) { 535 ch->status = MUSB_DMA_STATUS_FREE; 536 channel = ch; 537 chdat = ch->private_data; 538 break; 539 } 540 } 541 542 if (!channel) 543 return NULL; 544 545 if (tx) { 546 chdat->tx = 1; 547 dev_name = "TUSB transmit"; 548 } else { 549 chdat->tx = 0; 550 dev_name = "TUSB receive"; 551 } 552 553 chdat->musb = tusb_dma->musb; 554 chdat->tbase = tusb_dma->tbase; 555 chdat->hw_ep = hw_ep; 556 chdat->epnum = hw_ep->epnum; 557 chdat->dmareq = -1; 558 chdat->completed_len = 0; 559 chdat->tusb_dma = tusb_dma; 560 561 channel->max_len = 0x7fffffff; 562 channel->desired_mode = 0; 563 channel->actual_len = 0; 564 565 if (tusb_dma->multichannel) { 566 ret = tusb_omap_dma_allocate_dmareq(chdat); 567 if (ret != 0) 568 goto free_dmareq; 569 570 ret = omap_request_dma(chdat->sync_dev, dev_name, 571 tusb_omap_dma_cb, channel, &chdat->ch); 572 if (ret != 0) 573 goto free_dmareq; 574 } else if (tusb_dma->ch == -1) { 575 tusb_dma->dmareq = 0; 576 tusb_dma->sync_dev = OMAP24XX_DMA_EXT_DMAREQ0; 577 578 /* Callback data gets set later in the shared dmareq case */ 579 ret = omap_request_dma(tusb_dma->sync_dev, "TUSB shared", 580 tusb_omap_dma_cb, NULL, &tusb_dma->ch); 581 if (ret != 0) 582 goto free_dmareq; 583 584 chdat->dmareq = -1; 585 chdat->ch = -1; 586 } 587 588 DBG(3, "ep%i %s dma: %s dma%i dmareq%i sync%i\n", 589 chdat->epnum, 590 chdat->tx ? "tx" : "rx", 591 chdat->ch >= 0 ? "dedicated" : "shared", 592 chdat->ch >= 0 ? chdat->ch : tusb_dma->ch, 593 chdat->dmareq >= 0 ? chdat->dmareq : tusb_dma->dmareq, 594 chdat->sync_dev >= 0 ? chdat->sync_dev : tusb_dma->sync_dev); 595 596 return channel; 597 598free_dmareq: 599 tusb_omap_dma_free_dmareq(chdat); 600 601 DBG(3, "ep%i: Could not get a DMA channel\n", chdat->epnum); 602 channel->status = MUSB_DMA_STATUS_UNKNOWN; 603 604 return NULL; 605} 606 607static void tusb_omap_dma_release(struct dma_channel *channel) 608{ 609 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 610 struct musb *musb = chdat->musb; 611 void __iomem *tbase = musb->ctrl_base; 612 u32 reg; 613 614 DBG(3, "ep%i ch%i\n", chdat->epnum, chdat->ch); 615 616 reg = musb_readl(tbase, TUSB_DMA_INT_MASK); 617 if (chdat->tx) 618 reg |= (1 << chdat->epnum); 619 else 620 reg |= (1 << (chdat->epnum + 15)); 621 musb_writel(tbase, TUSB_DMA_INT_MASK, reg); 622 623 reg = musb_readl(tbase, TUSB_DMA_INT_CLEAR); 624 if (chdat->tx) 625 reg |= (1 << chdat->epnum); 626 else 627 reg |= (1 << (chdat->epnum + 15)); 628 musb_writel(tbase, TUSB_DMA_INT_CLEAR, reg); 629 630 channel->status = MUSB_DMA_STATUS_UNKNOWN; 631 632 if (chdat->ch >= 0) { 633 omap_stop_dma(chdat->ch); 634 omap_free_dma(chdat->ch); 635 chdat->ch = -1; 636 } 637 638 if (chdat->dmareq >= 0) 639 tusb_omap_dma_free_dmareq(chdat); 640 641 channel = NULL; 642} 643 644void dma_controller_destroy(struct dma_controller *c) 645{ 646 struct tusb_omap_dma *tusb_dma; 647 int i; 648 649 tusb_dma = container_of(c, struct tusb_omap_dma, controller); 650 for (i = 0; i < MAX_DMAREQ; i++) { 651 struct dma_channel *ch = dma_channel_pool[i]; 652 if (ch) { 653 kfree(ch->private_data); 654 kfree(ch); 655 } 656 } 657 658 if (tusb_dma && !tusb_dma->multichannel && tusb_dma->ch >= 0) 659 omap_free_dma(tusb_dma->ch); 660 661 kfree(tusb_dma); 662} 663 664struct dma_controller *__init 665dma_controller_create(struct musb *musb, void __iomem *base) 666{ 667 void __iomem *tbase = musb->ctrl_base; 668 struct tusb_omap_dma *tusb_dma; 669 int i; 670 671 /* REVISIT: Get dmareq lines used from board-*.c */ 672 673 musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff); 674 musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0); 675 676 musb_writel(tbase, TUSB_DMA_REQ_CONF, 677 TUSB_DMA_REQ_CONF_BURST_SIZE(2) 678 | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) 679 | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); 680 681 tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL); 682 if (!tusb_dma) 683 goto cleanup; 684 685 tusb_dma->musb = musb; 686 tusb_dma->tbase = musb->ctrl_base; 687 688 tusb_dma->ch = -1; 689 tusb_dma->dmareq = -1; 690 tusb_dma->sync_dev = -1; 691 692 tusb_dma->controller.start = tusb_omap_dma_start; 693 tusb_dma->controller.stop = tusb_omap_dma_stop; 694 tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate; 695 tusb_dma->controller.channel_release = tusb_omap_dma_release; 696 tusb_dma->controller.channel_program = tusb_omap_dma_program; 697 tusb_dma->controller.channel_abort = tusb_omap_dma_abort; 698 699 if (tusb_get_revision(musb) >= TUSB_REV_30) 700 tusb_dma->multichannel = 1; 701 702 for (i = 0; i < MAX_DMAREQ; i++) { 703 struct dma_channel *ch; 704 struct tusb_omap_dma_ch *chdat; 705 706 ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL); 707 if (!ch) 708 goto cleanup; 709 710 dma_channel_pool[i] = ch; 711 712 chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL); 713 if (!chdat) 714 goto cleanup; 715 716 ch->status = MUSB_DMA_STATUS_UNKNOWN; 717 ch->private_data = chdat; 718 } 719 720 return &tusb_dma->controller; 721 722cleanup: 723 dma_controller_destroy(&tusb_dma->controller); 724 725 return NULL; 726} 727