1/* 2 * omap_udc.c -- for OMAP full speed udc; most chips support OTG. 3 * 4 * Copyright (C) 2004 Texas Instruments, Inc. 5 * Copyright (C) 2004-2005 David Brownell 6 * 7 * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 */ 23 24#undef DEBUG 25#undef VERBOSE 26 27#include <linux/module.h> 28#include <linux/kernel.h> 29#include <linux/ioport.h> 30#include <linux/types.h> 31#include <linux/errno.h> 32#include <linux/delay.h> 33#include <linux/slab.h> 34#include <linux/init.h> 35#include <linux/timer.h> 36#include <linux/list.h> 37#include <linux/interrupt.h> 38#include <linux/proc_fs.h> 39#include <linux/mm.h> 40#include <linux/moduleparam.h> 41#include <linux/platform_device.h> 42#include <linux/usb/ch9.h> 43#include <linux/usb/gadget.h> 44#include <linux/usb/otg.h> 45#include <linux/dma-mapping.h> 46#include <linux/clk.h> 47 48#include <asm/byteorder.h> 49#include <asm/io.h> 50#include <asm/irq.h> 51#include <asm/system.h> 52#include <asm/unaligned.h> 53#include <asm/mach-types.h> 54 55#include <plat/dma.h> 56#include <plat/usb.h> 57#include <plat/control.h> 58 59#include "omap_udc.h" 60 61#undef USB_TRACE 62 63/* bulk DMA seems to be behaving for both IN and OUT */ 64#define USE_DMA 65 66/* ISO too */ 67#define USE_ISO 68 69#define DRIVER_DESC "OMAP UDC driver" 70#define DRIVER_VERSION "4 October 2004" 71 72#define DMA_ADDR_INVALID (~(dma_addr_t)0) 73 74#define OMAP2_DMA_CH(ch) (((ch) - 1) << 1) 75#define OMAP24XX_DMA(name, ch) (OMAP24XX_DMA_##name + OMAP2_DMA_CH(ch)) 76 77/* 78 * The OMAP UDC needs _very_ early endpoint setup: before enabling the 79 * D+ pullup to allow enumeration. That's too early for the gadget 80 * framework to use from usb_endpoint_enable(), which happens after 81 * enumeration as part of activating an interface. (But if we add an 82 * optional new "UDC not yet running" state to the gadget driver model, 83 * even just during driver binding, the endpoint autoconfig logic is the 84 * natural spot to manufacture new endpoints.) 85 * 86 * So instead of using endpoint enable calls to control the hardware setup, 87 * this driver defines a "fifo mode" parameter. It's used during driver 88 * initialization to choose among a set of pre-defined endpoint configs. 89 * See omap_udc_setup() for available modes, or to add others. That code 90 * lives in an init section, so use this driver as a module if you need 91 * to change the fifo mode after the kernel boots. 92 * 93 * Gadget drivers normally ignore endpoints they don't care about, and 94 * won't include them in configuration descriptors. That means only 95 * misbehaving hosts would even notice they exist. 96 */ 97#ifdef USE_ISO 98static unsigned fifo_mode = 3; 99#else 100static unsigned fifo_mode = 0; 101#endif 102 103/* "modprobe omap_udc fifo_mode=42", or else as a kernel 104 * boot parameter "omap_udc:fifo_mode=42" 105 */ 106module_param (fifo_mode, uint, 0); 107MODULE_PARM_DESC (fifo_mode, "endpoint configuration"); 108 109#ifdef USE_DMA 110static unsigned use_dma = 1; 111 112/* "modprobe omap_udc use_dma=y", or else as a kernel 113 * boot parameter "omap_udc:use_dma=y" 114 */ 115module_param (use_dma, bool, 0); 116MODULE_PARM_DESC (use_dma, "enable/disable DMA"); 117#else /* !USE_DMA */ 118 119/* save a bit of code */ 120#define use_dma 0 121#endif /* !USE_DMA */ 122 123 124static const char driver_name [] = "omap_udc"; 125static const char driver_desc [] = DRIVER_DESC; 126 127/*-------------------------------------------------------------------------*/ 128 129/* there's a notion of "current endpoint" for modifying endpoint 130 * state, and PIO access to its FIFO. 131 */ 132 133static void use_ep(struct omap_ep *ep, u16 select) 134{ 135 u16 num = ep->bEndpointAddress & 0x0f; 136 137 if (ep->bEndpointAddress & USB_DIR_IN) 138 num |= UDC_EP_DIR; 139 omap_writew(num | select, UDC_EP_NUM); 140 /* when select, MUST deselect later !! */ 141} 142 143static inline void deselect_ep(void) 144{ 145 u16 w; 146 147 w = omap_readw(UDC_EP_NUM); 148 w &= ~UDC_EP_SEL; 149 omap_writew(w, UDC_EP_NUM); 150 /* 6 wait states before TX will happen */ 151} 152 153static void dma_channel_claim(struct omap_ep *ep, unsigned preferred); 154 155/*-------------------------------------------------------------------------*/ 156 157static int omap_ep_enable(struct usb_ep *_ep, 158 const struct usb_endpoint_descriptor *desc) 159{ 160 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); 161 struct omap_udc *udc; 162 unsigned long flags; 163 u16 maxp; 164 165 /* catch various bogus parameters */ 166 if (!_ep || !desc || ep->desc 167 || desc->bDescriptorType != USB_DT_ENDPOINT 168 || ep->bEndpointAddress != desc->bEndpointAddress 169 || ep->maxpacket < le16_to_cpu 170 (desc->wMaxPacketSize)) { 171 DBG("%s, bad ep or descriptor\n", __func__); 172 return -EINVAL; 173 } 174 maxp = le16_to_cpu (desc->wMaxPacketSize); 175 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK 176 && maxp != ep->maxpacket) 177 || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket 178 || !desc->wMaxPacketSize) { 179 DBG("%s, bad %s maxpacket\n", __func__, _ep->name); 180 return -ERANGE; 181 } 182 183#ifdef USE_ISO 184 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC 185 && desc->bInterval != 1)) { 186 /* hardware wants period = 1; USB allows 2^(Interval-1) */ 187 DBG("%s, unsupported ISO period %dms\n", _ep->name, 188 1 << (desc->bInterval - 1)); 189 return -EDOM; 190 } 191#else 192 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { 193 DBG("%s, ISO nyet\n", _ep->name); 194 return -EDOM; 195 } 196#endif 197 198 /* xfer types must match, except that interrupt ~= bulk */ 199 if (ep->bmAttributes != desc->bmAttributes 200 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK 201 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { 202 DBG("%s, %s type mismatch\n", __func__, _ep->name); 203 return -EINVAL; 204 } 205 206 udc = ep->udc; 207 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { 208 DBG("%s, bogus device state\n", __func__); 209 return -ESHUTDOWN; 210 } 211 212 spin_lock_irqsave(&udc->lock, flags); 213 214 ep->desc = desc; 215 ep->irqs = 0; 216 ep->stopped = 0; 217 ep->ep.maxpacket = maxp; 218 219 /* set endpoint to initial state */ 220 ep->dma_channel = 0; 221 ep->has_dma = 0; 222 ep->lch = -1; 223 use_ep(ep, UDC_EP_SEL); 224 omap_writew(udc->clr_halt, UDC_CTRL); 225 ep->ackwait = 0; 226 deselect_ep(); 227 228 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) 229 list_add(&ep->iso, &udc->iso); 230 231 /* maybe assign a DMA channel to this endpoint */ 232 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK) 233 dma_channel_claim(ep, 0); 234 235 /* PIO OUT may RX packets */ 236 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC 237 && !ep->has_dma 238 && !(ep->bEndpointAddress & USB_DIR_IN)) { 239 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 240 ep->ackwait = 1 + ep->double_buf; 241 } 242 243 spin_unlock_irqrestore(&udc->lock, flags); 244 VDBG("%s enabled\n", _ep->name); 245 return 0; 246} 247 248static void nuke(struct omap_ep *, int status); 249 250static int omap_ep_disable(struct usb_ep *_ep) 251{ 252 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); 253 unsigned long flags; 254 255 if (!_ep || !ep->desc) { 256 DBG("%s, %s not enabled\n", __func__, 257 _ep ? ep->ep.name : NULL); 258 return -EINVAL; 259 } 260 261 spin_lock_irqsave(&ep->udc->lock, flags); 262 ep->desc = NULL; 263 nuke (ep, -ESHUTDOWN); 264 ep->ep.maxpacket = ep->maxpacket; 265 ep->has_dma = 0; 266 omap_writew(UDC_SET_HALT, UDC_CTRL); 267 list_del_init(&ep->iso); 268 del_timer(&ep->timer); 269 270 spin_unlock_irqrestore(&ep->udc->lock, flags); 271 272 VDBG("%s disabled\n", _ep->name); 273 return 0; 274} 275 276/*-------------------------------------------------------------------------*/ 277 278static struct usb_request * 279omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) 280{ 281 struct omap_req *req; 282 283 req = kzalloc(sizeof(*req), gfp_flags); 284 if (req) { 285 req->req.dma = DMA_ADDR_INVALID; 286 INIT_LIST_HEAD (&req->queue); 287 } 288 return &req->req; 289} 290 291static void 292omap_free_request(struct usb_ep *ep, struct usb_request *_req) 293{ 294 struct omap_req *req = container_of(_req, struct omap_req, req); 295 296 if (_req) 297 kfree (req); 298} 299 300/*-------------------------------------------------------------------------*/ 301 302static void 303done(struct omap_ep *ep, struct omap_req *req, int status) 304{ 305 unsigned stopped = ep->stopped; 306 307 list_del_init(&req->queue); 308 309 if (req->req.status == -EINPROGRESS) 310 req->req.status = status; 311 else 312 status = req->req.status; 313 314 if (use_dma && ep->has_dma) { 315 if (req->mapped) { 316 dma_unmap_single(ep->udc->gadget.dev.parent, 317 req->req.dma, req->req.length, 318 (ep->bEndpointAddress & USB_DIR_IN) 319 ? DMA_TO_DEVICE 320 : DMA_FROM_DEVICE); 321 req->req.dma = DMA_ADDR_INVALID; 322 req->mapped = 0; 323 } else 324 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent, 325 req->req.dma, req->req.length, 326 (ep->bEndpointAddress & USB_DIR_IN) 327 ? DMA_TO_DEVICE 328 : DMA_FROM_DEVICE); 329 } 330 331#ifndef USB_TRACE 332 if (status && status != -ESHUTDOWN) 333#endif 334 VDBG("complete %s req %p stat %d len %u/%u\n", 335 ep->ep.name, &req->req, status, 336 req->req.actual, req->req.length); 337 338 /* don't modify queue heads during completion callback */ 339 ep->stopped = 1; 340 spin_unlock(&ep->udc->lock); 341 req->req.complete(&ep->ep, &req->req); 342 spin_lock(&ep->udc->lock); 343 ep->stopped = stopped; 344} 345 346/*-------------------------------------------------------------------------*/ 347 348#define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL) 349#define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL) 350 351#define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY) 352#define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY) 353 354static inline int 355write_packet(u8 *buf, struct omap_req *req, unsigned max) 356{ 357 unsigned len; 358 u16 *wp; 359 360 len = min(req->req.length - req->req.actual, max); 361 req->req.actual += len; 362 363 max = len; 364 if (likely((((int)buf) & 1) == 0)) { 365 wp = (u16 *)buf; 366 while (max >= 2) { 367 omap_writew(*wp++, UDC_DATA); 368 max -= 2; 369 } 370 buf = (u8 *)wp; 371 } 372 while (max--) 373 omap_writeb(*buf++, UDC_DATA); 374 return len; 375} 376 377 378 379// return: 0 = still running, 1 = completed, negative = errno 380static int write_fifo(struct omap_ep *ep, struct omap_req *req) 381{ 382 u8 *buf; 383 unsigned count; 384 int is_last; 385 u16 ep_stat; 386 387 buf = req->req.buf + req->req.actual; 388 prefetch(buf); 389 390 /* PIO-IN isn't double buffered except for iso */ 391 ep_stat = omap_readw(UDC_STAT_FLG); 392 if (ep_stat & UDC_FIFO_UNWRITABLE) 393 return 0; 394 395 count = ep->ep.maxpacket; 396 count = write_packet(buf, req, count); 397 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 398 ep->ackwait = 1; 399 400 /* last packet is often short (sometimes a zlp) */ 401 if (count != ep->ep.maxpacket) 402 is_last = 1; 403 else if (req->req.length == req->req.actual 404 && !req->req.zero) 405 is_last = 1; 406 else 407 is_last = 0; 408 409 /* NOTE: requests complete when all IN data is in a 410 * FIFO (or sometimes later, if a zlp was needed). 411 * Use usb_ep_fifo_status() where needed. 412 */ 413 if (is_last) 414 done(ep, req, 0); 415 return is_last; 416} 417 418static inline int 419read_packet(u8 *buf, struct omap_req *req, unsigned avail) 420{ 421 unsigned len; 422 u16 *wp; 423 424 len = min(req->req.length - req->req.actual, avail); 425 req->req.actual += len; 426 avail = len; 427 428 if (likely((((int)buf) & 1) == 0)) { 429 wp = (u16 *)buf; 430 while (avail >= 2) { 431 *wp++ = omap_readw(UDC_DATA); 432 avail -= 2; 433 } 434 buf = (u8 *)wp; 435 } 436 while (avail--) 437 *buf++ = omap_readb(UDC_DATA); 438 return len; 439} 440 441// return: 0 = still running, 1 = queue empty, negative = errno 442static int read_fifo(struct omap_ep *ep, struct omap_req *req) 443{ 444 u8 *buf; 445 unsigned count, avail; 446 int is_last; 447 448 buf = req->req.buf + req->req.actual; 449 prefetchw(buf); 450 451 for (;;) { 452 u16 ep_stat = omap_readw(UDC_STAT_FLG); 453 454 is_last = 0; 455 if (ep_stat & FIFO_EMPTY) { 456 if (!ep->double_buf) 457 break; 458 ep->fnf = 1; 459 } 460 if (ep_stat & UDC_EP_HALTED) 461 break; 462 463 if (ep_stat & UDC_FIFO_FULL) 464 avail = ep->ep.maxpacket; 465 else { 466 avail = omap_readw(UDC_RXFSTAT); 467 ep->fnf = ep->double_buf; 468 } 469 count = read_packet(buf, req, avail); 470 471 /* partial packet reads may not be errors */ 472 if (count < ep->ep.maxpacket) { 473 is_last = 1; 474 /* overflowed this request? flush extra data */ 475 if (count != avail) { 476 req->req.status = -EOVERFLOW; 477 avail -= count; 478 while (avail--) 479 omap_readw(UDC_DATA); 480 } 481 } else if (req->req.length == req->req.actual) 482 is_last = 1; 483 else 484 is_last = 0; 485 486 if (!ep->bEndpointAddress) 487 break; 488 if (is_last) 489 done(ep, req, 0); 490 break; 491 } 492 return is_last; 493} 494 495/*-------------------------------------------------------------------------*/ 496 497static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start) 498{ 499 dma_addr_t end; 500 501 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports 502 * the last transfer's bytecount by more than a FIFO's worth. 503 */ 504 if (cpu_is_omap15xx()) 505 return 0; 506 507 end = omap_get_dma_src_pos(ep->lch); 508 if (end == ep->dma_counter) 509 return 0; 510 511 end |= start & (0xffff << 16); 512 if (end < start) 513 end += 0x10000; 514 return end - start; 515} 516 517static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start) 518{ 519 dma_addr_t end; 520 521 end = omap_get_dma_dst_pos(ep->lch); 522 if (end == ep->dma_counter) 523 return 0; 524 525 end |= start & (0xffff << 16); 526 if (cpu_is_omap15xx()) 527 end++; 528 if (end < start) 529 end += 0x10000; 530 return end - start; 531} 532 533 534/* Each USB transfer request using DMA maps to one or more DMA transfers. 535 * When DMA completion isn't request completion, the UDC continues with 536 * the next DMA transfer for that USB transfer. 537 */ 538 539static void next_in_dma(struct omap_ep *ep, struct omap_req *req) 540{ 541 u16 txdma_ctrl, w; 542 unsigned length = req->req.length - req->req.actual; 543 const int sync_mode = cpu_is_omap15xx() 544 ? OMAP_DMA_SYNC_FRAME 545 : OMAP_DMA_SYNC_ELEMENT; 546 int dma_trigger = 0; 547 548 if (cpu_is_omap24xx()) 549 dma_trigger = OMAP24XX_DMA(USB_W2FC_TX0, ep->dma_channel); 550 551 /* measure length in either bytes or packets */ 552 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC) 553 || (cpu_is_omap24xx() && length < ep->maxpacket) 554 || (cpu_is_omap15xx() && length < ep->maxpacket)) { 555 txdma_ctrl = UDC_TXN_EOT | length; 556 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8, 557 length, 1, sync_mode, dma_trigger, 0); 558 } else { 559 length = min(length / ep->maxpacket, 560 (unsigned) UDC_TXN_TSC + 1); 561 txdma_ctrl = length; 562 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16, 563 ep->ep.maxpacket >> 1, length, sync_mode, 564 dma_trigger, 0); 565 length *= ep->maxpacket; 566 } 567 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF, 568 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual, 569 0, 0); 570 571 omap_start_dma(ep->lch); 572 ep->dma_counter = omap_get_dma_src_pos(ep->lch); 573 w = omap_readw(UDC_DMA_IRQ_EN); 574 w |= UDC_TX_DONE_IE(ep->dma_channel); 575 omap_writew(w, UDC_DMA_IRQ_EN); 576 omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel)); 577 req->dma_bytes = length; 578} 579 580static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status) 581{ 582 u16 w; 583 584 if (status == 0) { 585 req->req.actual += req->dma_bytes; 586 587 /* return if this request needs to send data or zlp */ 588 if (req->req.actual < req->req.length) 589 return; 590 if (req->req.zero 591 && req->dma_bytes != 0 592 && (req->req.actual % ep->maxpacket) == 0) 593 return; 594 } else 595 req->req.actual += dma_src_len(ep, req->req.dma 596 + req->req.actual); 597 598 /* tx completion */ 599 omap_stop_dma(ep->lch); 600 w = omap_readw(UDC_DMA_IRQ_EN); 601 w &= ~UDC_TX_DONE_IE(ep->dma_channel); 602 omap_writew(w, UDC_DMA_IRQ_EN); 603 done(ep, req, status); 604} 605 606static void next_out_dma(struct omap_ep *ep, struct omap_req *req) 607{ 608 unsigned packets = req->req.length - req->req.actual; 609 int dma_trigger = 0; 610 u16 w; 611 612 if (cpu_is_omap24xx()) 613 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel); 614 615 /* NOTE: we filtered out "short reads" before, so we know 616 * the buffer has only whole numbers of packets. 617 * except MODE SELECT(6) sent the 24 bytes data in OMAP24XX DMA mode 618 */ 619 if (cpu_is_omap24xx() && packets < ep->maxpacket) { 620 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8, 621 packets, 1, OMAP_DMA_SYNC_ELEMENT, 622 dma_trigger, 0); 623 req->dma_bytes = packets; 624 } else { 625 /* set up this DMA transfer, enable the fifo, start */ 626 packets /= ep->ep.maxpacket; 627 packets = min(packets, (unsigned)UDC_RXN_TC + 1); 628 req->dma_bytes = packets * ep->ep.maxpacket; 629 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16, 630 ep->ep.maxpacket >> 1, packets, 631 OMAP_DMA_SYNC_ELEMENT, 632 dma_trigger, 0); 633 } 634 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF, 635 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual, 636 0, 0); 637 ep->dma_counter = omap_get_dma_dst_pos(ep->lch); 638 639 omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel)); 640 w = omap_readw(UDC_DMA_IRQ_EN); 641 w |= UDC_RX_EOT_IE(ep->dma_channel); 642 omap_writew(w, UDC_DMA_IRQ_EN); 643 omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM); 644 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 645 646 omap_start_dma(ep->lch); 647} 648 649static void 650finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one) 651{ 652 u16 count, w; 653 654 if (status == 0) 655 ep->dma_counter = (u16) (req->req.dma + req->req.actual); 656 count = dma_dest_len(ep, req->req.dma + req->req.actual); 657 count += req->req.actual; 658 if (one) 659 count--; 660 if (count <= req->req.length) 661 req->req.actual = count; 662 663 if (count != req->dma_bytes || status) 664 omap_stop_dma(ep->lch); 665 666 /* if this wasn't short, request may need another transfer */ 667 else if (req->req.actual < req->req.length) 668 return; 669 670 /* rx completion */ 671 w = omap_readw(UDC_DMA_IRQ_EN); 672 w &= ~UDC_RX_EOT_IE(ep->dma_channel); 673 omap_writew(w, UDC_DMA_IRQ_EN); 674 done(ep, req, status); 675} 676 677static void dma_irq(struct omap_udc *udc, u16 irq_src) 678{ 679 u16 dman_stat = omap_readw(UDC_DMAN_STAT); 680 struct omap_ep *ep; 681 struct omap_req *req; 682 683 /* IN dma: tx to host */ 684 if (irq_src & UDC_TXN_DONE) { 685 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)]; 686 ep->irqs++; 687 /* can see TXN_DONE after dma abort */ 688 if (!list_empty(&ep->queue)) { 689 req = container_of(ep->queue.next, 690 struct omap_req, queue); 691 finish_in_dma(ep, req, 0); 692 } 693 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC); 694 695 if (!list_empty (&ep->queue)) { 696 req = container_of(ep->queue.next, 697 struct omap_req, queue); 698 next_in_dma(ep, req); 699 } 700 } 701 702 /* OUT dma: rx from host */ 703 if (irq_src & UDC_RXN_EOT) { 704 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)]; 705 ep->irqs++; 706 /* can see RXN_EOT after dma abort */ 707 if (!list_empty(&ep->queue)) { 708 req = container_of(ep->queue.next, 709 struct omap_req, queue); 710 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB); 711 } 712 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC); 713 714 if (!list_empty (&ep->queue)) { 715 req = container_of(ep->queue.next, 716 struct omap_req, queue); 717 next_out_dma(ep, req); 718 } 719 } 720 721 if (irq_src & UDC_RXN_CNT) { 722 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)]; 723 ep->irqs++; 724 /* omap15xx does this unasked... */ 725 VDBG("%s, RX_CNT irq?\n", ep->ep.name); 726 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC); 727 } 728} 729 730static void dma_error(int lch, u16 ch_status, void *data) 731{ 732 struct omap_ep *ep = data; 733 734 /* if ch_status & OMAP_DMA_DROP_IRQ ... */ 735 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */ 736 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status); 737 738 /* complete current transfer ... */ 739} 740 741static void dma_channel_claim(struct omap_ep *ep, unsigned channel) 742{ 743 u16 reg; 744 int status, restart, is_in; 745 int dma_channel; 746 747 is_in = ep->bEndpointAddress & USB_DIR_IN; 748 if (is_in) 749 reg = omap_readw(UDC_TXDMA_CFG); 750 else 751 reg = omap_readw(UDC_RXDMA_CFG); 752 reg |= UDC_DMA_REQ; /* "pulse" activated */ 753 754 ep->dma_channel = 0; 755 ep->lch = -1; 756 if (channel == 0 || channel > 3) { 757 if ((reg & 0x0f00) == 0) 758 channel = 3; 759 else if ((reg & 0x00f0) == 0) 760 channel = 2; 761 else if ((reg & 0x000f) == 0) /* preferred for ISO */ 762 channel = 1; 763 else { 764 status = -EMLINK; 765 goto just_restart; 766 } 767 } 768 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1)); 769 ep->dma_channel = channel; 770 771 if (is_in) { 772 if (cpu_is_omap24xx()) 773 dma_channel = OMAP24XX_DMA(USB_W2FC_TX0, channel); 774 else 775 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel; 776 status = omap_request_dma(dma_channel, 777 ep->ep.name, dma_error, ep, &ep->lch); 778 if (status == 0) { 779 omap_writew(reg, UDC_TXDMA_CFG); 780 /* EMIFF or SDRC */ 781 omap_set_dma_src_burst_mode(ep->lch, 782 OMAP_DMA_DATA_BURST_4); 783 omap_set_dma_src_data_pack(ep->lch, 1); 784 /* TIPB */ 785 omap_set_dma_dest_params(ep->lch, 786 OMAP_DMA_PORT_TIPB, 787 OMAP_DMA_AMODE_CONSTANT, 788 UDC_DATA_DMA, 789 0, 0); 790 } 791 } else { 792 if (cpu_is_omap24xx()) 793 dma_channel = OMAP24XX_DMA(USB_W2FC_RX0, channel); 794 else 795 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel; 796 797 status = omap_request_dma(dma_channel, 798 ep->ep.name, dma_error, ep, &ep->lch); 799 if (status == 0) { 800 omap_writew(reg, UDC_RXDMA_CFG); 801 /* TIPB */ 802 omap_set_dma_src_params(ep->lch, 803 OMAP_DMA_PORT_TIPB, 804 OMAP_DMA_AMODE_CONSTANT, 805 UDC_DATA_DMA, 806 0, 0); 807 /* EMIFF or SDRC */ 808 omap_set_dma_dest_burst_mode(ep->lch, 809 OMAP_DMA_DATA_BURST_4); 810 omap_set_dma_dest_data_pack(ep->lch, 1); 811 } 812 } 813 if (status) 814 ep->dma_channel = 0; 815 else { 816 ep->has_dma = 1; 817 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ); 818 819 /* channel type P: hw synch (fifo) */ 820 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) 821 omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P); 822 } 823 824just_restart: 825 /* restart any queue, even if the claim failed */ 826 restart = !ep->stopped && !list_empty(&ep->queue); 827 828 if (status) 829 DBG("%s no dma channel: %d%s\n", ep->ep.name, status, 830 restart ? " (restart)" : ""); 831 else 832 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name, 833 is_in ? 't' : 'r', 834 ep->dma_channel - 1, ep->lch, 835 restart ? " (restart)" : ""); 836 837 if (restart) { 838 struct omap_req *req; 839 req = container_of(ep->queue.next, struct omap_req, queue); 840 if (ep->has_dma) 841 (is_in ? next_in_dma : next_out_dma)(ep, req); 842 else { 843 use_ep(ep, UDC_EP_SEL); 844 (is_in ? write_fifo : read_fifo)(ep, req); 845 deselect_ep(); 846 if (!is_in) { 847 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 848 ep->ackwait = 1 + ep->double_buf; 849 } 850 /* IN: 6 wait states before it'll tx */ 851 } 852 } 853} 854 855static void dma_channel_release(struct omap_ep *ep) 856{ 857 int shift = 4 * (ep->dma_channel - 1); 858 u16 mask = 0x0f << shift; 859 struct omap_req *req; 860 int active; 861 862 /* abort any active usb transfer request */ 863 if (!list_empty(&ep->queue)) 864 req = container_of(ep->queue.next, struct omap_req, queue); 865 else 866 req = NULL; 867 868 active = omap_get_dma_active_status(ep->lch); 869 870 DBG("%s release %s %cxdma%d %p\n", ep->ep.name, 871 active ? "active" : "idle", 872 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r', 873 ep->dma_channel - 1, req); 874 875 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before 876 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them. 877 */ 878 879 /* wait till current packet DMA finishes, and fifo empties */ 880 if (ep->bEndpointAddress & USB_DIR_IN) { 881 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ, 882 UDC_TXDMA_CFG); 883 884 if (req) { 885 finish_in_dma(ep, req, -ECONNRESET); 886 887 /* clear FIFO; hosts probably won't empty it */ 888 use_ep(ep, UDC_EP_SEL); 889 omap_writew(UDC_CLR_EP, UDC_CTRL); 890 deselect_ep(); 891 } 892 while (omap_readw(UDC_TXDMA_CFG) & mask) 893 udelay(10); 894 } else { 895 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ, 896 UDC_RXDMA_CFG); 897 898 /* dma empties the fifo */ 899 while (omap_readw(UDC_RXDMA_CFG) & mask) 900 udelay(10); 901 if (req) 902 finish_out_dma(ep, req, -ECONNRESET, 0); 903 } 904 omap_free_dma(ep->lch); 905 ep->dma_channel = 0; 906 ep->lch = -1; 907 /* has_dma still set, till endpoint is fully quiesced */ 908} 909 910 911/*-------------------------------------------------------------------------*/ 912 913static int 914omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) 915{ 916 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); 917 struct omap_req *req = container_of(_req, struct omap_req, req); 918 struct omap_udc *udc; 919 unsigned long flags; 920 int is_iso = 0; 921 922 /* catch various bogus parameters */ 923 if (!_req || !req->req.complete || !req->req.buf 924 || !list_empty(&req->queue)) { 925 DBG("%s, bad params\n", __func__); 926 return -EINVAL; 927 } 928 if (!_ep || (!ep->desc && ep->bEndpointAddress)) { 929 DBG("%s, bad ep\n", __func__); 930 return -EINVAL; 931 } 932 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { 933 if (req->req.length > ep->ep.maxpacket) 934 return -EMSGSIZE; 935 is_iso = 1; 936 } 937 938 /* this isn't bogus, but OMAP DMA isn't the only hardware to 939 * have a hard time with partial packet reads... reject it. 940 * Except OMAP2 can handle the small packets. 941 */ 942 if (use_dma 943 && ep->has_dma 944 && ep->bEndpointAddress != 0 945 && (ep->bEndpointAddress & USB_DIR_IN) == 0 946 && !cpu_class_is_omap2() 947 && (req->req.length % ep->ep.maxpacket) != 0) { 948 DBG("%s, no partial packet OUT reads\n", __func__); 949 return -EMSGSIZE; 950 } 951 952 udc = ep->udc; 953 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) 954 return -ESHUTDOWN; 955 956 if (use_dma && ep->has_dma) { 957 if (req->req.dma == DMA_ADDR_INVALID) { 958 req->req.dma = dma_map_single( 959 ep->udc->gadget.dev.parent, 960 req->req.buf, 961 req->req.length, 962 (ep->bEndpointAddress & USB_DIR_IN) 963 ? DMA_TO_DEVICE 964 : DMA_FROM_DEVICE); 965 req->mapped = 1; 966 } else { 967 dma_sync_single_for_device( 968 ep->udc->gadget.dev.parent, 969 req->req.dma, req->req.length, 970 (ep->bEndpointAddress & USB_DIR_IN) 971 ? DMA_TO_DEVICE 972 : DMA_FROM_DEVICE); 973 req->mapped = 0; 974 } 975 } 976 977 VDBG("%s queue req %p, len %d buf %p\n", 978 ep->ep.name, _req, _req->length, _req->buf); 979 980 spin_lock_irqsave(&udc->lock, flags); 981 982 req->req.status = -EINPROGRESS; 983 req->req.actual = 0; 984 985 /* maybe kickstart non-iso i/o queues */ 986 if (is_iso) { 987 u16 w; 988 989 w = omap_readw(UDC_IRQ_EN); 990 w |= UDC_SOF_IE; 991 omap_writew(w, UDC_IRQ_EN); 992 } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) { 993 int is_in; 994 995 if (ep->bEndpointAddress == 0) { 996 if (!udc->ep0_pending || !list_empty (&ep->queue)) { 997 spin_unlock_irqrestore(&udc->lock, flags); 998 return -EL2HLT; 999 } 1000 1001 /* empty DATA stage? */ 1002 is_in = udc->ep0_in; 1003 if (!req->req.length) { 1004 1005 /* chip became CONFIGURED or ADDRESSED 1006 * earlier; drivers may already have queued 1007 * requests to non-control endpoints 1008 */ 1009 if (udc->ep0_set_config) { 1010 u16 irq_en = omap_readw(UDC_IRQ_EN); 1011 1012 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE; 1013 if (!udc->ep0_reset_config) 1014 irq_en |= UDC_EPN_RX_IE 1015 | UDC_EPN_TX_IE; 1016 omap_writew(irq_en, UDC_IRQ_EN); 1017 } 1018 1019 /* STATUS for zero length DATA stages is 1020 * always an IN ... even for IN transfers, 1021 * a weird case which seem to stall OMAP. 1022 */ 1023 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM); 1024 omap_writew(UDC_CLR_EP, UDC_CTRL); 1025 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1026 omap_writew(UDC_EP_DIR, UDC_EP_NUM); 1027 1028 /* cleanup */ 1029 udc->ep0_pending = 0; 1030 done(ep, req, 0); 1031 req = NULL; 1032 1033 /* non-empty DATA stage */ 1034 } else if (is_in) { 1035 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM); 1036 } else { 1037 if (udc->ep0_setup) 1038 goto irq_wait; 1039 omap_writew(UDC_EP_SEL, UDC_EP_NUM); 1040 } 1041 } else { 1042 is_in = ep->bEndpointAddress & USB_DIR_IN; 1043 if (!ep->has_dma) 1044 use_ep(ep, UDC_EP_SEL); 1045 /* if ISO: SOF IRQs must be enabled/disabled! */ 1046 } 1047 1048 if (ep->has_dma) 1049 (is_in ? next_in_dma : next_out_dma)(ep, req); 1050 else if (req) { 1051 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1) 1052 req = NULL; 1053 deselect_ep(); 1054 if (!is_in) { 1055 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1056 ep->ackwait = 1 + ep->double_buf; 1057 } 1058 /* IN: 6 wait states before it'll tx */ 1059 } 1060 } 1061 1062irq_wait: 1063 /* irq handler advances the queue */ 1064 if (req != NULL) 1065 list_add_tail(&req->queue, &ep->queue); 1066 spin_unlock_irqrestore(&udc->lock, flags); 1067 1068 return 0; 1069} 1070 1071static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 1072{ 1073 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); 1074 struct omap_req *req; 1075 unsigned long flags; 1076 1077 if (!_ep || !_req) 1078 return -EINVAL; 1079 1080 spin_lock_irqsave(&ep->udc->lock, flags); 1081 1082 /* make sure it's actually queued on this endpoint */ 1083 list_for_each_entry (req, &ep->queue, queue) { 1084 if (&req->req == _req) 1085 break; 1086 } 1087 if (&req->req != _req) { 1088 spin_unlock_irqrestore(&ep->udc->lock, flags); 1089 return -EINVAL; 1090 } 1091 1092 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) { 1093 int channel = ep->dma_channel; 1094 1095 /* releasing the channel cancels the request, 1096 * reclaiming the channel restarts the queue 1097 */ 1098 dma_channel_release(ep); 1099 dma_channel_claim(ep, channel); 1100 } else 1101 done(ep, req, -ECONNRESET); 1102 spin_unlock_irqrestore(&ep->udc->lock, flags); 1103 return 0; 1104} 1105 1106/*-------------------------------------------------------------------------*/ 1107 1108static int omap_ep_set_halt(struct usb_ep *_ep, int value) 1109{ 1110 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); 1111 unsigned long flags; 1112 int status = -EOPNOTSUPP; 1113 1114 spin_lock_irqsave(&ep->udc->lock, flags); 1115 1116 /* just use protocol stalls for ep0; real halts are annoying */ 1117 if (ep->bEndpointAddress == 0) { 1118 if (!ep->udc->ep0_pending) 1119 status = -EINVAL; 1120 else if (value) { 1121 if (ep->udc->ep0_set_config) { 1122 WARNING("error changing config?\n"); 1123 omap_writew(UDC_CLR_CFG, UDC_SYSCON2); 1124 } 1125 omap_writew(UDC_STALL_CMD, UDC_SYSCON2); 1126 ep->udc->ep0_pending = 0; 1127 status = 0; 1128 } else /* NOP */ 1129 status = 0; 1130 1131 /* otherwise, all active non-ISO endpoints can halt */ 1132 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) { 1133 1134 /* IN endpoints must already be idle */ 1135 if ((ep->bEndpointAddress & USB_DIR_IN) 1136 && !list_empty(&ep->queue)) { 1137 status = -EAGAIN; 1138 goto done; 1139 } 1140 1141 if (value) { 1142 int channel; 1143 1144 if (use_dma && ep->dma_channel 1145 && !list_empty(&ep->queue)) { 1146 channel = ep->dma_channel; 1147 dma_channel_release(ep); 1148 } else 1149 channel = 0; 1150 1151 use_ep(ep, UDC_EP_SEL); 1152 if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) { 1153 omap_writew(UDC_SET_HALT, UDC_CTRL); 1154 status = 0; 1155 } else 1156 status = -EAGAIN; 1157 deselect_ep(); 1158 1159 if (channel) 1160 dma_channel_claim(ep, channel); 1161 } else { 1162 use_ep(ep, 0); 1163 omap_writew(ep->udc->clr_halt, UDC_CTRL); 1164 ep->ackwait = 0; 1165 if (!(ep->bEndpointAddress & USB_DIR_IN)) { 1166 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1167 ep->ackwait = 1 + ep->double_buf; 1168 } 1169 } 1170 } 1171done: 1172 VDBG("%s %s halt stat %d\n", ep->ep.name, 1173 value ? "set" : "clear", status); 1174 1175 spin_unlock_irqrestore(&ep->udc->lock, flags); 1176 return status; 1177} 1178 1179static struct usb_ep_ops omap_ep_ops = { 1180 .enable = omap_ep_enable, 1181 .disable = omap_ep_disable, 1182 1183 .alloc_request = omap_alloc_request, 1184 .free_request = omap_free_request, 1185 1186 .queue = omap_ep_queue, 1187 .dequeue = omap_ep_dequeue, 1188 1189 .set_halt = omap_ep_set_halt, 1190 // fifo_status ... report bytes in fifo 1191 // fifo_flush ... flush fifo 1192}; 1193 1194/*-------------------------------------------------------------------------*/ 1195 1196static int omap_get_frame(struct usb_gadget *gadget) 1197{ 1198 u16 sof = omap_readw(UDC_SOF); 1199 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC; 1200} 1201 1202static int omap_wakeup(struct usb_gadget *gadget) 1203{ 1204 struct omap_udc *udc; 1205 unsigned long flags; 1206 int retval = -EHOSTUNREACH; 1207 1208 udc = container_of(gadget, struct omap_udc, gadget); 1209 1210 spin_lock_irqsave(&udc->lock, flags); 1211 if (udc->devstat & UDC_SUS) { 1212 /* NOTE: OTG spec erratum says that OTG devices may 1213 * issue wakeups without host enable. 1214 */ 1215 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) { 1216 DBG("remote wakeup...\n"); 1217 omap_writew(UDC_RMT_WKP, UDC_SYSCON2); 1218 retval = 0; 1219 } 1220 1221 /* NOTE: non-OTG systems may use SRP TOO... */ 1222 } else if (!(udc->devstat & UDC_ATT)) { 1223 if (udc->transceiver) 1224 retval = otg_start_srp(udc->transceiver); 1225 } 1226 spin_unlock_irqrestore(&udc->lock, flags); 1227 1228 return retval; 1229} 1230 1231static int 1232omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered) 1233{ 1234 struct omap_udc *udc; 1235 unsigned long flags; 1236 u16 syscon1; 1237 1238 udc = container_of(gadget, struct omap_udc, gadget); 1239 spin_lock_irqsave(&udc->lock, flags); 1240 syscon1 = omap_readw(UDC_SYSCON1); 1241 if (is_selfpowered) 1242 syscon1 |= UDC_SELF_PWR; 1243 else 1244 syscon1 &= ~UDC_SELF_PWR; 1245 omap_writew(syscon1, UDC_SYSCON1); 1246 spin_unlock_irqrestore(&udc->lock, flags); 1247 1248 return 0; 1249} 1250 1251static int can_pullup(struct omap_udc *udc) 1252{ 1253 return udc->driver && udc->softconnect && udc->vbus_active; 1254} 1255 1256static void pullup_enable(struct omap_udc *udc) 1257{ 1258 u16 w; 1259 1260 w = omap_readw(UDC_SYSCON1); 1261 w |= UDC_PULLUP_EN; 1262 omap_writew(w, UDC_SYSCON1); 1263 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) { 1264 u32 l; 1265 1266 l = omap_readl(OTG_CTRL); 1267 l |= OTG_BSESSVLD; 1268 omap_writel(l, OTG_CTRL); 1269 } 1270 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN); 1271} 1272 1273static void pullup_disable(struct omap_udc *udc) 1274{ 1275 u16 w; 1276 1277 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) { 1278 u32 l; 1279 1280 l = omap_readl(OTG_CTRL); 1281 l &= ~OTG_BSESSVLD; 1282 omap_writel(l, OTG_CTRL); 1283 } 1284 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN); 1285 w = omap_readw(UDC_SYSCON1); 1286 w &= ~UDC_PULLUP_EN; 1287 omap_writew(w, UDC_SYSCON1); 1288} 1289 1290static struct omap_udc *udc; 1291 1292static void omap_udc_enable_clock(int enable) 1293{ 1294 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL) 1295 return; 1296 1297 if (enable) { 1298 clk_enable(udc->dc_clk); 1299 clk_enable(udc->hhc_clk); 1300 udelay(100); 1301 } else { 1302 clk_disable(udc->hhc_clk); 1303 clk_disable(udc->dc_clk); 1304 } 1305} 1306 1307/* 1308 * Called by whatever detects VBUS sessions: external transceiver 1309 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock. 1310 */ 1311static int omap_vbus_session(struct usb_gadget *gadget, int is_active) 1312{ 1313 struct omap_udc *udc; 1314 unsigned long flags; 1315 u32 l; 1316 1317 udc = container_of(gadget, struct omap_udc, gadget); 1318 spin_lock_irqsave(&udc->lock, flags); 1319 VDBG("VBUS %s\n", is_active ? "on" : "off"); 1320 udc->vbus_active = (is_active != 0); 1321 if (cpu_is_omap15xx()) { 1322 /* "software" detect, ignored if !VBUS_MODE_1510 */ 1323 l = omap_readl(FUNC_MUX_CTRL_0); 1324 if (is_active) 1325 l |= VBUS_CTRL_1510; 1326 else 1327 l &= ~VBUS_CTRL_1510; 1328 omap_writel(l, FUNC_MUX_CTRL_0); 1329 } 1330 if (udc->dc_clk != NULL && is_active) { 1331 if (!udc->clk_requested) { 1332 omap_udc_enable_clock(1); 1333 udc->clk_requested = 1; 1334 } 1335 } 1336 if (can_pullup(udc)) 1337 pullup_enable(udc); 1338 else 1339 pullup_disable(udc); 1340 if (udc->dc_clk != NULL && !is_active) { 1341 if (udc->clk_requested) { 1342 omap_udc_enable_clock(0); 1343 udc->clk_requested = 0; 1344 } 1345 } 1346 spin_unlock_irqrestore(&udc->lock, flags); 1347 return 0; 1348} 1349 1350static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA) 1351{ 1352 struct omap_udc *udc; 1353 1354 udc = container_of(gadget, struct omap_udc, gadget); 1355 if (udc->transceiver) 1356 return otg_set_power(udc->transceiver, mA); 1357 return -EOPNOTSUPP; 1358} 1359 1360static int omap_pullup(struct usb_gadget *gadget, int is_on) 1361{ 1362 struct omap_udc *udc; 1363 unsigned long flags; 1364 1365 udc = container_of(gadget, struct omap_udc, gadget); 1366 spin_lock_irqsave(&udc->lock, flags); 1367 udc->softconnect = (is_on != 0); 1368 if (can_pullup(udc)) 1369 pullup_enable(udc); 1370 else 1371 pullup_disable(udc); 1372 spin_unlock_irqrestore(&udc->lock, flags); 1373 return 0; 1374} 1375 1376static struct usb_gadget_ops omap_gadget_ops = { 1377 .get_frame = omap_get_frame, 1378 .wakeup = omap_wakeup, 1379 .set_selfpowered = omap_set_selfpowered, 1380 .vbus_session = omap_vbus_session, 1381 .vbus_draw = omap_vbus_draw, 1382 .pullup = omap_pullup, 1383}; 1384 1385/*-------------------------------------------------------------------------*/ 1386 1387/* dequeue ALL requests; caller holds udc->lock */ 1388static void nuke(struct omap_ep *ep, int status) 1389{ 1390 struct omap_req *req; 1391 1392 ep->stopped = 1; 1393 1394 if (use_dma && ep->dma_channel) 1395 dma_channel_release(ep); 1396 1397 use_ep(ep, 0); 1398 omap_writew(UDC_CLR_EP, UDC_CTRL); 1399 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC) 1400 omap_writew(UDC_SET_HALT, UDC_CTRL); 1401 1402 while (!list_empty(&ep->queue)) { 1403 req = list_entry(ep->queue.next, struct omap_req, queue); 1404 done(ep, req, status); 1405 } 1406} 1407 1408/* caller holds udc->lock */ 1409static void udc_quiesce(struct omap_udc *udc) 1410{ 1411 struct omap_ep *ep; 1412 1413 udc->gadget.speed = USB_SPEED_UNKNOWN; 1414 nuke(&udc->ep[0], -ESHUTDOWN); 1415 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) 1416 nuke(ep, -ESHUTDOWN); 1417} 1418 1419/*-------------------------------------------------------------------------*/ 1420 1421static void update_otg(struct omap_udc *udc) 1422{ 1423 u16 devstat; 1424 1425 if (!gadget_is_otg(&udc->gadget)) 1426 return; 1427 1428 if (omap_readl(OTG_CTRL) & OTG_ID) 1429 devstat = omap_readw(UDC_DEVSTAT); 1430 else 1431 devstat = 0; 1432 1433 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE); 1434 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT); 1435 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT); 1436 1437 /* Enable HNP early, avoiding races on suspend irq path. 1438 * ASSUMES OTG state machine B_BUS_REQ input is true. 1439 */ 1440 if (udc->gadget.b_hnp_enable) { 1441 u32 l; 1442 1443 l = omap_readl(OTG_CTRL); 1444 l |= OTG_B_HNPEN | OTG_B_BUSREQ; 1445 l &= ~OTG_PULLUP; 1446 omap_writel(l, OTG_CTRL); 1447 } 1448} 1449 1450static void ep0_irq(struct omap_udc *udc, u16 irq_src) 1451{ 1452 struct omap_ep *ep0 = &udc->ep[0]; 1453 struct omap_req *req = NULL; 1454 1455 ep0->irqs++; 1456 1457 /* Clear any pending requests and then scrub any rx/tx state 1458 * before starting to handle the SETUP request. 1459 */ 1460 if (irq_src & UDC_SETUP) { 1461 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX); 1462 1463 nuke(ep0, 0); 1464 if (ack) { 1465 omap_writew(ack, UDC_IRQ_SRC); 1466 irq_src = UDC_SETUP; 1467 } 1468 } 1469 1470 /* IN/OUT packets mean we're in the DATA or STATUS stage. 1471 * This driver uses only uses protocol stalls (ep0 never halts), 1472 * and if we got this far the gadget driver already had a 1473 * chance to stall. Tries to be forgiving of host oddities. 1474 * 1475 * NOTE: the last chance gadget drivers have to stall control 1476 * requests is during their request completion callback. 1477 */ 1478 if (!list_empty(&ep0->queue)) 1479 req = container_of(ep0->queue.next, struct omap_req, queue); 1480 1481 /* IN == TX to host */ 1482 if (irq_src & UDC_EP0_TX) { 1483 int stat; 1484 1485 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC); 1486 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); 1487 stat = omap_readw(UDC_STAT_FLG); 1488 if (stat & UDC_ACK) { 1489 if (udc->ep0_in) { 1490 /* write next IN packet from response, 1491 * or set up the status stage. 1492 */ 1493 if (req) 1494 stat = write_fifo(ep0, req); 1495 omap_writew(UDC_EP_DIR, UDC_EP_NUM); 1496 if (!req && udc->ep0_pending) { 1497 omap_writew(UDC_EP_SEL, UDC_EP_NUM); 1498 omap_writew(UDC_CLR_EP, UDC_CTRL); 1499 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1500 omap_writew(0, UDC_EP_NUM); 1501 udc->ep0_pending = 0; 1502 } /* else: 6 wait states before it'll tx */ 1503 } else { 1504 /* ack status stage of OUT transfer */ 1505 omap_writew(UDC_EP_DIR, UDC_EP_NUM); 1506 if (req) 1507 done(ep0, req, 0); 1508 } 1509 req = NULL; 1510 } else if (stat & UDC_STALL) { 1511 omap_writew(UDC_CLR_HALT, UDC_CTRL); 1512 omap_writew(UDC_EP_DIR, UDC_EP_NUM); 1513 } else { 1514 omap_writew(UDC_EP_DIR, UDC_EP_NUM); 1515 } 1516 } 1517 1518 /* OUT == RX from host */ 1519 if (irq_src & UDC_EP0_RX) { 1520 int stat; 1521 1522 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC); 1523 omap_writew(UDC_EP_SEL, UDC_EP_NUM); 1524 stat = omap_readw(UDC_STAT_FLG); 1525 if (stat & UDC_ACK) { 1526 if (!udc->ep0_in) { 1527 stat = 0; 1528 /* read next OUT packet of request, maybe 1529 * reactiviting the fifo; stall on errors. 1530 */ 1531 if (!req || (stat = read_fifo(ep0, req)) < 0) { 1532 omap_writew(UDC_STALL_CMD, UDC_SYSCON2); 1533 udc->ep0_pending = 0; 1534 stat = 0; 1535 } else if (stat == 0) 1536 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1537 omap_writew(0, UDC_EP_NUM); 1538 1539 /* activate status stage */ 1540 if (stat == 1) { 1541 done(ep0, req, 0); 1542 /* that may have STALLed ep0... */ 1543 omap_writew(UDC_EP_SEL | UDC_EP_DIR, 1544 UDC_EP_NUM); 1545 omap_writew(UDC_CLR_EP, UDC_CTRL); 1546 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1547 omap_writew(UDC_EP_DIR, UDC_EP_NUM); 1548 udc->ep0_pending = 0; 1549 } 1550 } else { 1551 /* ack status stage of IN transfer */ 1552 omap_writew(0, UDC_EP_NUM); 1553 if (req) 1554 done(ep0, req, 0); 1555 } 1556 } else if (stat & UDC_STALL) { 1557 omap_writew(UDC_CLR_HALT, UDC_CTRL); 1558 omap_writew(0, UDC_EP_NUM); 1559 } else { 1560 omap_writew(0, UDC_EP_NUM); 1561 } 1562 } 1563 1564 /* SETUP starts all control transfers */ 1565 if (irq_src & UDC_SETUP) { 1566 union u { 1567 u16 word[4]; 1568 struct usb_ctrlrequest r; 1569 } u; 1570 int status = -EINVAL; 1571 struct omap_ep *ep; 1572 1573 /* read the (latest) SETUP message */ 1574 do { 1575 omap_writew(UDC_SETUP_SEL, UDC_EP_NUM); 1576 /* two bytes at a time */ 1577 u.word[0] = omap_readw(UDC_DATA); 1578 u.word[1] = omap_readw(UDC_DATA); 1579 u.word[2] = omap_readw(UDC_DATA); 1580 u.word[3] = omap_readw(UDC_DATA); 1581 omap_writew(0, UDC_EP_NUM); 1582 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP); 1583 1584#define w_value le16_to_cpu(u.r.wValue) 1585#define w_index le16_to_cpu(u.r.wIndex) 1586#define w_length le16_to_cpu(u.r.wLength) 1587 1588 /* Delegate almost all control requests to the gadget driver, 1589 * except for a handful of ch9 status/feature requests that 1590 * hardware doesn't autodecode _and_ the gadget API hides. 1591 */ 1592 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0; 1593 udc->ep0_set_config = 0; 1594 udc->ep0_pending = 1; 1595 ep0->stopped = 0; 1596 ep0->ackwait = 0; 1597 switch (u.r.bRequest) { 1598 case USB_REQ_SET_CONFIGURATION: 1599 /* udc needs to know when ep != 0 is valid */ 1600 if (u.r.bRequestType != USB_RECIP_DEVICE) 1601 goto delegate; 1602 if (w_length != 0) 1603 goto do_stall; 1604 udc->ep0_set_config = 1; 1605 udc->ep0_reset_config = (w_value == 0); 1606 VDBG("set config %d\n", w_value); 1607 1608 /* update udc NOW since gadget driver may start 1609 * queueing requests immediately; clear config 1610 * later if it fails the request. 1611 */ 1612 if (udc->ep0_reset_config) 1613 omap_writew(UDC_CLR_CFG, UDC_SYSCON2); 1614 else 1615 omap_writew(UDC_DEV_CFG, UDC_SYSCON2); 1616 update_otg(udc); 1617 goto delegate; 1618 case USB_REQ_CLEAR_FEATURE: 1619 /* clear endpoint halt */ 1620 if (u.r.bRequestType != USB_RECIP_ENDPOINT) 1621 goto delegate; 1622 if (w_value != USB_ENDPOINT_HALT 1623 || w_length != 0) 1624 goto do_stall; 1625 ep = &udc->ep[w_index & 0xf]; 1626 if (ep != ep0) { 1627 if (w_index & USB_DIR_IN) 1628 ep += 16; 1629 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC 1630 || !ep->desc) 1631 goto do_stall; 1632 use_ep(ep, 0); 1633 omap_writew(udc->clr_halt, UDC_CTRL); 1634 ep->ackwait = 0; 1635 if (!(ep->bEndpointAddress & USB_DIR_IN)) { 1636 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1637 ep->ackwait = 1 + ep->double_buf; 1638 } 1639 /* NOTE: assumes the host behaves sanely, 1640 * only clearing real halts. Else we may 1641 * need to kill pending transfers and then 1642 * restart the queue... very messy for DMA! 1643 */ 1644 } 1645 VDBG("%s halt cleared by host\n", ep->name); 1646 goto ep0out_status_stage; 1647 case USB_REQ_SET_FEATURE: 1648 /* set endpoint halt */ 1649 if (u.r.bRequestType != USB_RECIP_ENDPOINT) 1650 goto delegate; 1651 if (w_value != USB_ENDPOINT_HALT 1652 || w_length != 0) 1653 goto do_stall; 1654 ep = &udc->ep[w_index & 0xf]; 1655 if (w_index & USB_DIR_IN) 1656 ep += 16; 1657 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC 1658 || ep == ep0 || !ep->desc) 1659 goto do_stall; 1660 if (use_dma && ep->has_dma) { 1661 /* this has rude side-effects (aborts) and 1662 * can't really work if DMA-IN is active 1663 */ 1664 DBG("%s host set_halt, NYET \n", ep->name); 1665 goto do_stall; 1666 } 1667 use_ep(ep, 0); 1668 /* can't halt if fifo isn't empty... */ 1669 omap_writew(UDC_CLR_EP, UDC_CTRL); 1670 omap_writew(UDC_SET_HALT, UDC_CTRL); 1671 VDBG("%s halted by host\n", ep->name); 1672ep0out_status_stage: 1673 status = 0; 1674 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); 1675 omap_writew(UDC_CLR_EP, UDC_CTRL); 1676 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1677 omap_writew(UDC_EP_DIR, UDC_EP_NUM); 1678 udc->ep0_pending = 0; 1679 break; 1680 case USB_REQ_GET_STATUS: 1681 /* USB_ENDPOINT_HALT status? */ 1682 if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT)) 1683 goto intf_status; 1684 1685 /* ep0 never stalls */ 1686 if (!(w_index & 0xf)) 1687 goto zero_status; 1688 1689 /* only active endpoints count */ 1690 ep = &udc->ep[w_index & 0xf]; 1691 if (w_index & USB_DIR_IN) 1692 ep += 16; 1693 if (!ep->desc) 1694 goto do_stall; 1695 1696 /* iso never stalls */ 1697 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) 1698 goto zero_status; 1699 1700 ERR("%s status, can't report\n", ep->ep.name); 1701 goto do_stall; 1702 1703intf_status: 1704 /* return interface status. if we were pedantic, 1705 * we'd detect non-existent interfaces, and stall. 1706 */ 1707 if (u.r.bRequestType 1708 != (USB_DIR_IN|USB_RECIP_INTERFACE)) 1709 goto delegate; 1710 1711zero_status: 1712 /* return two zero bytes */ 1713 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); 1714 omap_writew(0, UDC_DATA); 1715 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1716 omap_writew(UDC_EP_DIR, UDC_EP_NUM); 1717 status = 0; 1718 VDBG("GET_STATUS, interface %d\n", w_index); 1719 /* next, status stage */ 1720 break; 1721 default: 1722delegate: 1723 /* activate the ep0out fifo right away */ 1724 if (!udc->ep0_in && w_length) { 1725 omap_writew(0, UDC_EP_NUM); 1726 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1727 } 1728 1729 /* gadget drivers see class/vendor specific requests, 1730 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION}, 1731 * and more 1732 */ 1733 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n", 1734 u.r.bRequestType, u.r.bRequest, 1735 w_value, w_index, w_length); 1736 1737#undef w_value 1738#undef w_index 1739#undef w_length 1740 1741 /* The gadget driver may return an error here, 1742 * causing an immediate protocol stall. 1743 * 1744 * Else it must issue a response, either queueing a 1745 * response buffer for the DATA stage, or halting ep0 1746 * (causing a protocol stall, not a real halt). A 1747 * zero length buffer means no DATA stage. 1748 * 1749 * It's fine to issue that response after the setup() 1750 * call returns, and this IRQ was handled. 1751 */ 1752 udc->ep0_setup = 1; 1753 spin_unlock(&udc->lock); 1754 status = udc->driver->setup (&udc->gadget, &u.r); 1755 spin_lock(&udc->lock); 1756 udc->ep0_setup = 0; 1757 } 1758 1759 if (status < 0) { 1760do_stall: 1761 VDBG("req %02x.%02x protocol STALL; stat %d\n", 1762 u.r.bRequestType, u.r.bRequest, status); 1763 if (udc->ep0_set_config) { 1764 if (udc->ep0_reset_config) 1765 WARNING("error resetting config?\n"); 1766 else 1767 omap_writew(UDC_CLR_CFG, UDC_SYSCON2); 1768 } 1769 omap_writew(UDC_STALL_CMD, UDC_SYSCON2); 1770 udc->ep0_pending = 0; 1771 } 1772 } 1773} 1774 1775/*-------------------------------------------------------------------------*/ 1776 1777#define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT) 1778 1779static void devstate_irq(struct omap_udc *udc, u16 irq_src) 1780{ 1781 u16 devstat, change; 1782 1783 devstat = omap_readw(UDC_DEVSTAT); 1784 change = devstat ^ udc->devstat; 1785 udc->devstat = devstat; 1786 1787 if (change & (UDC_USB_RESET|UDC_ATT)) { 1788 udc_quiesce(udc); 1789 1790 if (change & UDC_ATT) { 1791 /* driver for any external transceiver will 1792 * have called omap_vbus_session() already 1793 */ 1794 if (devstat & UDC_ATT) { 1795 udc->gadget.speed = USB_SPEED_FULL; 1796 VDBG("connect\n"); 1797 if (!udc->transceiver) 1798 pullup_enable(udc); 1799 // if (driver->connect) call it 1800 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) { 1801 udc->gadget.speed = USB_SPEED_UNKNOWN; 1802 if (!udc->transceiver) 1803 pullup_disable(udc); 1804 DBG("disconnect, gadget %s\n", 1805 udc->driver->driver.name); 1806 if (udc->driver->disconnect) { 1807 spin_unlock(&udc->lock); 1808 udc->driver->disconnect(&udc->gadget); 1809 spin_lock(&udc->lock); 1810 } 1811 } 1812 change &= ~UDC_ATT; 1813 } 1814 1815 if (change & UDC_USB_RESET) { 1816 if (devstat & UDC_USB_RESET) { 1817 VDBG("RESET=1\n"); 1818 } else { 1819 udc->gadget.speed = USB_SPEED_FULL; 1820 INFO("USB reset done, gadget %s\n", 1821 udc->driver->driver.name); 1822 /* ep0 traffic is legal from now on */ 1823 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE, 1824 UDC_IRQ_EN); 1825 } 1826 change &= ~UDC_USB_RESET; 1827 } 1828 } 1829 if (change & UDC_SUS) { 1830 if (udc->gadget.speed != USB_SPEED_UNKNOWN) { 1831 if (devstat & UDC_SUS) { 1832 VDBG("suspend\n"); 1833 update_otg(udc); 1834 /* HNP could be under way already */ 1835 if (udc->gadget.speed == USB_SPEED_FULL 1836 && udc->driver->suspend) { 1837 spin_unlock(&udc->lock); 1838 udc->driver->suspend(&udc->gadget); 1839 spin_lock(&udc->lock); 1840 } 1841 if (udc->transceiver) 1842 otg_set_suspend(udc->transceiver, 1); 1843 } else { 1844 VDBG("resume\n"); 1845 if (udc->transceiver) 1846 otg_set_suspend(udc->transceiver, 0); 1847 if (udc->gadget.speed == USB_SPEED_FULL 1848 && udc->driver->resume) { 1849 spin_unlock(&udc->lock); 1850 udc->driver->resume(&udc->gadget); 1851 spin_lock(&udc->lock); 1852 } 1853 } 1854 } 1855 change &= ~UDC_SUS; 1856 } 1857 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) { 1858 update_otg(udc); 1859 change &= ~OTG_FLAGS; 1860 } 1861 1862 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD); 1863 if (change) 1864 VDBG("devstat %03x, ignore change %03x\n", 1865 devstat, change); 1866 1867 omap_writew(UDC_DS_CHG, UDC_IRQ_SRC); 1868} 1869 1870static irqreturn_t omap_udc_irq(int irq, void *_udc) 1871{ 1872 struct omap_udc *udc = _udc; 1873 u16 irq_src; 1874 irqreturn_t status = IRQ_NONE; 1875 unsigned long flags; 1876 1877 spin_lock_irqsave(&udc->lock, flags); 1878 irq_src = omap_readw(UDC_IRQ_SRC); 1879 1880 /* Device state change (usb ch9 stuff) */ 1881 if (irq_src & UDC_DS_CHG) { 1882 devstate_irq(_udc, irq_src); 1883 status = IRQ_HANDLED; 1884 irq_src &= ~UDC_DS_CHG; 1885 } 1886 1887 /* EP0 control transfers */ 1888 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) { 1889 ep0_irq(_udc, irq_src); 1890 status = IRQ_HANDLED; 1891 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX); 1892 } 1893 1894 /* DMA transfer completion */ 1895 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) { 1896 dma_irq(_udc, irq_src); 1897 status = IRQ_HANDLED; 1898 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT); 1899 } 1900 1901 irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX); 1902 if (irq_src) 1903 DBG("udc_irq, unhandled %03x\n", irq_src); 1904 spin_unlock_irqrestore(&udc->lock, flags); 1905 1906 return status; 1907} 1908 1909#define PIO_OUT_TIMEOUT (jiffies + HZ/3) 1910#define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY))) 1911 1912static void pio_out_timer(unsigned long _ep) 1913{ 1914 struct omap_ep *ep = (void *) _ep; 1915 unsigned long flags; 1916 u16 stat_flg; 1917 1918 spin_lock_irqsave(&ep->udc->lock, flags); 1919 if (!list_empty(&ep->queue) && ep->ackwait) { 1920 use_ep(ep, UDC_EP_SEL); 1921 stat_flg = omap_readw(UDC_STAT_FLG); 1922 1923 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN) 1924 || (ep->double_buf && HALF_FULL(stat_flg)))) { 1925 struct omap_req *req; 1926 1927 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg); 1928 req = container_of(ep->queue.next, 1929 struct omap_req, queue); 1930 (void) read_fifo(ep, req); 1931 omap_writew(ep->bEndpointAddress, UDC_EP_NUM); 1932 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1933 ep->ackwait = 1 + ep->double_buf; 1934 } else 1935 deselect_ep(); 1936 } 1937 mod_timer(&ep->timer, PIO_OUT_TIMEOUT); 1938 spin_unlock_irqrestore(&ep->udc->lock, flags); 1939} 1940 1941static irqreturn_t omap_udc_pio_irq(int irq, void *_dev) 1942{ 1943 u16 epn_stat, irq_src; 1944 irqreturn_t status = IRQ_NONE; 1945 struct omap_ep *ep; 1946 int epnum; 1947 struct omap_udc *udc = _dev; 1948 struct omap_req *req; 1949 unsigned long flags; 1950 1951 spin_lock_irqsave(&udc->lock, flags); 1952 epn_stat = omap_readw(UDC_EPN_STAT); 1953 irq_src = omap_readw(UDC_IRQ_SRC); 1954 1955 /* handle OUT first, to avoid some wasteful NAKs */ 1956 if (irq_src & UDC_EPN_RX) { 1957 epnum = (epn_stat >> 8) & 0x0f; 1958 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC); 1959 status = IRQ_HANDLED; 1960 ep = &udc->ep[epnum]; 1961 ep->irqs++; 1962 1963 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM); 1964 ep->fnf = 0; 1965 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) { 1966 ep->ackwait--; 1967 if (!list_empty(&ep->queue)) { 1968 int stat; 1969 req = container_of(ep->queue.next, 1970 struct omap_req, queue); 1971 stat = read_fifo(ep, req); 1972 if (!ep->double_buf) 1973 ep->fnf = 1; 1974 } 1975 } 1976 /* min 6 clock delay before clearing EP_SEL ... */ 1977 epn_stat = omap_readw(UDC_EPN_STAT); 1978 epn_stat = omap_readw(UDC_EPN_STAT); 1979 omap_writew(epnum, UDC_EP_NUM); 1980 1981 /* enabling fifo _after_ clearing ACK, contrary to docs, 1982 * reduces lossage; timer still needed though (sigh). 1983 */ 1984 if (ep->fnf) { 1985 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); 1986 ep->ackwait = 1 + ep->double_buf; 1987 } 1988 mod_timer(&ep->timer, PIO_OUT_TIMEOUT); 1989 } 1990 1991 /* then IN transfers */ 1992 else if (irq_src & UDC_EPN_TX) { 1993 epnum = epn_stat & 0x0f; 1994 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC); 1995 status = IRQ_HANDLED; 1996 ep = &udc->ep[16 + epnum]; 1997 ep->irqs++; 1998 1999 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM); 2000 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) { 2001 ep->ackwait = 0; 2002 if (!list_empty(&ep->queue)) { 2003 req = container_of(ep->queue.next, 2004 struct omap_req, queue); 2005 (void) write_fifo(ep, req); 2006 } 2007 } 2008 /* min 6 clock delay before clearing EP_SEL ... */ 2009 epn_stat = omap_readw(UDC_EPN_STAT); 2010 epn_stat = omap_readw(UDC_EPN_STAT); 2011 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM); 2012 /* then 6 clocks before it'd tx */ 2013 } 2014 2015 spin_unlock_irqrestore(&udc->lock, flags); 2016 return status; 2017} 2018 2019#ifdef USE_ISO 2020static irqreturn_t omap_udc_iso_irq(int irq, void *_dev) 2021{ 2022 struct omap_udc *udc = _dev; 2023 struct omap_ep *ep; 2024 int pending = 0; 2025 unsigned long flags; 2026 2027 spin_lock_irqsave(&udc->lock, flags); 2028 2029 /* handle all non-DMA ISO transfers */ 2030 list_for_each_entry (ep, &udc->iso, iso) { 2031 u16 stat; 2032 struct omap_req *req; 2033 2034 if (ep->has_dma || list_empty(&ep->queue)) 2035 continue; 2036 req = list_entry(ep->queue.next, struct omap_req, queue); 2037 2038 use_ep(ep, UDC_EP_SEL); 2039 stat = omap_readw(UDC_STAT_FLG); 2040 2041 /* NOTE: like the other controller drivers, this isn't 2042 * currently reporting lost or damaged frames. 2043 */ 2044 if (ep->bEndpointAddress & USB_DIR_IN) { 2045 if (stat & UDC_MISS_IN) 2046 /* done(ep, req, -EPROTO) */; 2047 else 2048 write_fifo(ep, req); 2049 } else { 2050 int status = 0; 2051 2052 if (stat & UDC_NO_RXPACKET) 2053 status = -EREMOTEIO; 2054 else if (stat & UDC_ISO_ERR) 2055 status = -EILSEQ; 2056 else if (stat & UDC_DATA_FLUSH) 2057 status = -ENOSR; 2058 2059 if (status) 2060 /* done(ep, req, status) */; 2061 else 2062 read_fifo(ep, req); 2063 } 2064 deselect_ep(); 2065 /* 6 wait states before next EP */ 2066 2067 ep->irqs++; 2068 if (!list_empty(&ep->queue)) 2069 pending = 1; 2070 } 2071 if (!pending) { 2072 u16 w; 2073 2074 w = omap_readw(UDC_IRQ_EN); 2075 w &= ~UDC_SOF_IE; 2076 omap_writew(w, UDC_IRQ_EN); 2077 } 2078 omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC); 2079 2080 spin_unlock_irqrestore(&udc->lock, flags); 2081 return IRQ_HANDLED; 2082} 2083#endif 2084 2085/*-------------------------------------------------------------------------*/ 2086 2087static inline int machine_without_vbus_sense(void) 2088{ 2089 return (machine_is_omap_innovator() 2090 || machine_is_omap_osk() 2091 || machine_is_omap_apollon() 2092#ifndef CONFIG_MACH_OMAP_H4_OTG 2093 || machine_is_omap_h4() 2094#endif 2095 || machine_is_sx1() 2096 || cpu_is_omap7xx() /* No known omap7xx boards with vbus sense */ 2097 ); 2098} 2099 2100int usb_gadget_register_driver (struct usb_gadget_driver *driver) 2101{ 2102 int status = -ENODEV; 2103 struct omap_ep *ep; 2104 unsigned long flags; 2105 2106 /* basic sanity tests */ 2107 if (!udc) 2108 return -ENODEV; 2109 if (!driver 2110 || driver->speed < USB_SPEED_FULL 2111 || !driver->bind 2112 || !driver->setup) 2113 return -EINVAL; 2114 2115 spin_lock_irqsave(&udc->lock, flags); 2116 if (udc->driver) { 2117 spin_unlock_irqrestore(&udc->lock, flags); 2118 return -EBUSY; 2119 } 2120 2121 /* reset state */ 2122 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) { 2123 ep->irqs = 0; 2124 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) 2125 continue; 2126 use_ep(ep, 0); 2127 omap_writew(UDC_SET_HALT, UDC_CTRL); 2128 } 2129 udc->ep0_pending = 0; 2130 udc->ep[0].irqs = 0; 2131 udc->softconnect = 1; 2132 2133 /* hook up the driver */ 2134 driver->driver.bus = NULL; 2135 udc->driver = driver; 2136 udc->gadget.dev.driver = &driver->driver; 2137 spin_unlock_irqrestore(&udc->lock, flags); 2138 2139 if (udc->dc_clk != NULL) 2140 omap_udc_enable_clock(1); 2141 2142 status = driver->bind (&udc->gadget); 2143 if (status) { 2144 DBG("bind to %s --> %d\n", driver->driver.name, status); 2145 udc->gadget.dev.driver = NULL; 2146 udc->driver = NULL; 2147 goto done; 2148 } 2149 DBG("bound to driver %s\n", driver->driver.name); 2150 2151 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC); 2152 2153 /* connect to bus through transceiver */ 2154 if (udc->transceiver) { 2155 status = otg_set_peripheral(udc->transceiver, &udc->gadget); 2156 if (status < 0) { 2157 ERR("can't bind to transceiver\n"); 2158 if (driver->unbind) { 2159 driver->unbind (&udc->gadget); 2160 udc->gadget.dev.driver = NULL; 2161 udc->driver = NULL; 2162 } 2163 goto done; 2164 } 2165 } else { 2166 if (can_pullup(udc)) 2167 pullup_enable (udc); 2168 else 2169 pullup_disable (udc); 2170 } 2171 2172 /* boards that don't have VBUS sensing can't autogate 48MHz; 2173 * can't enter deep sleep while a gadget driver is active. 2174 */ 2175 if (machine_without_vbus_sense()) 2176 omap_vbus_session(&udc->gadget, 1); 2177 2178done: 2179 if (udc->dc_clk != NULL) 2180 omap_udc_enable_clock(0); 2181 return status; 2182} 2183EXPORT_SYMBOL(usb_gadget_register_driver); 2184 2185int usb_gadget_unregister_driver (struct usb_gadget_driver *driver) 2186{ 2187 unsigned long flags; 2188 int status = -ENODEV; 2189 2190 if (!udc) 2191 return -ENODEV; 2192 if (!driver || driver != udc->driver || !driver->unbind) 2193 return -EINVAL; 2194 2195 if (udc->dc_clk != NULL) 2196 omap_udc_enable_clock(1); 2197 2198 if (machine_without_vbus_sense()) 2199 omap_vbus_session(&udc->gadget, 0); 2200 2201 if (udc->transceiver) 2202 (void) otg_set_peripheral(udc->transceiver, NULL); 2203 else 2204 pullup_disable(udc); 2205 2206 spin_lock_irqsave(&udc->lock, flags); 2207 udc_quiesce(udc); 2208 spin_unlock_irqrestore(&udc->lock, flags); 2209 2210 driver->unbind(&udc->gadget); 2211 udc->gadget.dev.driver = NULL; 2212 udc->driver = NULL; 2213 2214 if (udc->dc_clk != NULL) 2215 omap_udc_enable_clock(0); 2216 DBG("unregistered driver '%s'\n", driver->driver.name); 2217 return status; 2218} 2219EXPORT_SYMBOL(usb_gadget_unregister_driver); 2220 2221 2222/*-------------------------------------------------------------------------*/ 2223 2224#ifdef CONFIG_USB_GADGET_DEBUG_FILES 2225 2226#include <linux/seq_file.h> 2227 2228static const char proc_filename[] = "driver/udc"; 2229 2230#define FOURBITS "%s%s%s%s" 2231#define EIGHTBITS FOURBITS FOURBITS 2232 2233static void proc_ep_show(struct seq_file *s, struct omap_ep *ep) 2234{ 2235 u16 stat_flg; 2236 struct omap_req *req; 2237 char buf[20]; 2238 2239 use_ep(ep, 0); 2240 2241 if (use_dma && ep->has_dma) 2242 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ", 2243 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r', 2244 ep->dma_channel - 1, ep->lch); 2245 else 2246 buf[0] = 0; 2247 2248 stat_flg = omap_readw(UDC_STAT_FLG); 2249 seq_printf(s, 2250 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n", 2251 ep->name, buf, 2252 ep->double_buf ? "dbuf " : "", 2253 ({char *s; switch(ep->ackwait){ 2254 case 0: s = ""; break; 2255 case 1: s = "(ackw) "; break; 2256 case 2: s = "(ackw2) "; break; 2257 default: s = "(?) "; break; 2258 } s;}), 2259 ep->irqs, stat_flg, 2260 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "", 2261 (stat_flg & UDC_MISS_IN) ? "miss_in " : "", 2262 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "", 2263 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "", 2264 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "", 2265 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "", 2266 (stat_flg & UDC_EP_HALTED) ? "HALT " : "", 2267 (stat_flg & UDC_STALL) ? "STALL " : "", 2268 (stat_flg & UDC_NAK) ? "NAK " : "", 2269 (stat_flg & UDC_ACK) ? "ACK " : "", 2270 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "", 2271 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "", 2272 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : ""); 2273 2274 if (list_empty (&ep->queue)) 2275 seq_printf(s, "\t(queue empty)\n"); 2276 else 2277 list_for_each_entry (req, &ep->queue, queue) { 2278 unsigned length = req->req.actual; 2279 2280 if (use_dma && buf[0]) { 2281 length += ((ep->bEndpointAddress & USB_DIR_IN) 2282 ? dma_src_len : dma_dest_len) 2283 (ep, req->req.dma + length); 2284 buf[0] = 0; 2285 } 2286 seq_printf(s, "\treq %p len %d/%d buf %p\n", 2287 &req->req, length, 2288 req->req.length, req->req.buf); 2289 } 2290} 2291 2292static char *trx_mode(unsigned m, int enabled) 2293{ 2294 switch (m) { 2295 case 0: return enabled ? "*6wire" : "unused"; 2296 case 1: return "4wire"; 2297 case 2: return "3wire"; 2298 case 3: return "6wire"; 2299 default: return "unknown"; 2300 } 2301} 2302 2303static int proc_otg_show(struct seq_file *s) 2304{ 2305 u32 tmp; 2306 u32 trans; 2307 char *ctrl_name; 2308 2309 tmp = omap_readl(OTG_REV); 2310 if (cpu_is_omap24xx()) { 2311 /* 2312 * REVISIT: Not clear how this works on OMAP2. trans 2313 * is ANDed to produce bits 7 and 8, which might make 2314 * sense for USB_TRANSCEIVER_CTRL on OMAP1, 2315 * but with CONTROL_DEVCONF, these bits have something to 2316 * do with the frame adjustment counter and McBSP2. 2317 */ 2318 ctrl_name = "control_devconf"; 2319 trans = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); 2320 } else { 2321 ctrl_name = "tranceiver_ctrl"; 2322 trans = omap_readw(USB_TRANSCEIVER_CTRL); 2323 } 2324 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n", 2325 tmp >> 4, tmp & 0xf, ctrl_name, trans); 2326 tmp = omap_readw(OTG_SYSCON_1); 2327 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s," 2328 FOURBITS "\n", tmp, 2329 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R), 2330 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R), 2331 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710()) 2332 ? "internal" 2333 : trx_mode(USB0_TRX_MODE(tmp), 1), 2334 (tmp & OTG_IDLE_EN) ? " !otg" : "", 2335 (tmp & HST_IDLE_EN) ? " !host" : "", 2336 (tmp & DEV_IDLE_EN) ? " !dev" : "", 2337 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active"); 2338 tmp = omap_readl(OTG_SYSCON_2); 2339 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS 2340 " b_ase_brst=%d hmc=%d\n", tmp, 2341 (tmp & OTG_EN) ? " otg_en" : "", 2342 (tmp & USBX_SYNCHRO) ? " synchro" : "", 2343 // much more SRP stuff 2344 (tmp & SRP_DATA) ? " srp_data" : "", 2345 (tmp & SRP_VBUS) ? " srp_vbus" : "", 2346 (tmp & OTG_PADEN) ? " otg_paden" : "", 2347 (tmp & HMC_PADEN) ? " hmc_paden" : "", 2348 (tmp & UHOST_EN) ? " uhost_en" : "", 2349 (tmp & HMC_TLLSPEED) ? " tllspeed" : "", 2350 (tmp & HMC_TLLATTACH) ? " tllattach" : "", 2351 B_ASE_BRST(tmp), 2352 OTG_HMC(tmp)); 2353 tmp = omap_readl(OTG_CTRL); 2354 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp, 2355 (tmp & OTG_ASESSVLD) ? " asess" : "", 2356 (tmp & OTG_BSESSEND) ? " bsess_end" : "", 2357 (tmp & OTG_BSESSVLD) ? " bsess" : "", 2358 (tmp & OTG_VBUSVLD) ? " vbus" : "", 2359 (tmp & OTG_ID) ? " id" : "", 2360 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST", 2361 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "", 2362 (tmp & OTG_A_BUSREQ) ? " a_bus" : "", 2363 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "", 2364 (tmp & OTG_B_BUSREQ) ? " b_bus" : "", 2365 (tmp & OTG_BUSDROP) ? " busdrop" : "", 2366 (tmp & OTG_PULLDOWN) ? " down" : "", 2367 (tmp & OTG_PULLUP) ? " up" : "", 2368 (tmp & OTG_DRV_VBUS) ? " drv" : "", 2369 (tmp & OTG_PD_VBUS) ? " pd_vb" : "", 2370 (tmp & OTG_PU_VBUS) ? " pu_vb" : "", 2371 (tmp & OTG_PU_ID) ? " pu_id" : "" 2372 ); 2373 tmp = omap_readw(OTG_IRQ_EN); 2374 seq_printf(s, "otg_irq_en %04x" "\n", tmp); 2375 tmp = omap_readw(OTG_IRQ_SRC); 2376 seq_printf(s, "otg_irq_src %04x" "\n", tmp); 2377 tmp = omap_readw(OTG_OUTCTRL); 2378 seq_printf(s, "otg_outctrl %04x" "\n", tmp); 2379 tmp = omap_readw(OTG_TEST); 2380 seq_printf(s, "otg_test %04x" "\n", tmp); 2381 return 0; 2382} 2383 2384static int proc_udc_show(struct seq_file *s, void *_) 2385{ 2386 u32 tmp; 2387 struct omap_ep *ep; 2388 unsigned long flags; 2389 2390 spin_lock_irqsave(&udc->lock, flags); 2391 2392 seq_printf(s, "%s, version: " DRIVER_VERSION 2393#ifdef USE_ISO 2394 " (iso)" 2395#endif 2396 "%s\n", 2397 driver_desc, 2398 use_dma ? " (dma)" : ""); 2399 2400 tmp = omap_readw(UDC_REV) & 0xff; 2401 seq_printf(s, 2402 "UDC rev %d.%d, fifo mode %d, gadget %s\n" 2403 "hmc %d, transceiver %s\n", 2404 tmp >> 4, tmp & 0xf, 2405 fifo_mode, 2406 udc->driver ? udc->driver->driver.name : "(none)", 2407 HMC, 2408 udc->transceiver 2409 ? udc->transceiver->label 2410 : ((cpu_is_omap1710() || cpu_is_omap24xx()) 2411 ? "external" : "(none)")); 2412 if (cpu_class_is_omap1()) { 2413 seq_printf(s, "ULPD control %04x req %04x status %04x\n", 2414 omap_readw(ULPD_CLOCK_CTRL), 2415 omap_readw(ULPD_SOFT_REQ), 2416 omap_readw(ULPD_STATUS_REQ)); 2417 } 2418 2419 /* OTG controller registers */ 2420 if (!cpu_is_omap15xx()) 2421 proc_otg_show(s); 2422 2423 tmp = omap_readw(UDC_SYSCON1); 2424 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp, 2425 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "", 2426 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "", 2427 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "", 2428 (tmp & UDC_NAK_EN) ? " nak" : "", 2429 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "", 2430 (tmp & UDC_SELF_PWR) ? " self_pwr" : "", 2431 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "", 2432 (tmp & UDC_PULLUP_EN) ? " PULLUP" : ""); 2433 // syscon2 is write-only 2434 2435 /* UDC controller registers */ 2436 if (!(tmp & UDC_PULLUP_EN)) { 2437 seq_printf(s, "(suspended)\n"); 2438 spin_unlock_irqrestore(&udc->lock, flags); 2439 return 0; 2440 } 2441 2442 tmp = omap_readw(UDC_DEVSTAT); 2443 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp, 2444 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "", 2445 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "", 2446 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "", 2447 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "", 2448 (tmp & UDC_USB_RESET) ? " usb_reset" : "", 2449 (tmp & UDC_SUS) ? " SUS" : "", 2450 (tmp & UDC_CFG) ? " CFG" : "", 2451 (tmp & UDC_ADD) ? " ADD" : "", 2452 (tmp & UDC_DEF) ? " DEF" : "", 2453 (tmp & UDC_ATT) ? " ATT" : ""); 2454 seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF)); 2455 tmp = omap_readw(UDC_IRQ_EN); 2456 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp, 2457 (tmp & UDC_SOF_IE) ? " sof" : "", 2458 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "", 2459 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "", 2460 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "", 2461 (tmp & UDC_EP0_IE) ? " ep0" : ""); 2462 tmp = omap_readw(UDC_IRQ_SRC); 2463 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp, 2464 (tmp & UDC_TXN_DONE) ? " txn_done" : "", 2465 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "", 2466 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "", 2467 (tmp & UDC_IRQ_SOF) ? " sof" : "", 2468 (tmp & UDC_EPN_RX) ? " epn_rx" : "", 2469 (tmp & UDC_EPN_TX) ? " epn_tx" : "", 2470 (tmp & UDC_DS_CHG) ? " ds_chg" : "", 2471 (tmp & UDC_SETUP) ? " setup" : "", 2472 (tmp & UDC_EP0_RX) ? " ep0out" : "", 2473 (tmp & UDC_EP0_TX) ? " ep0in" : ""); 2474 if (use_dma) { 2475 unsigned i; 2476 2477 tmp = omap_readw(UDC_DMA_IRQ_EN); 2478 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp, 2479 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "", 2480 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "", 2481 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "", 2482 2483 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "", 2484 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "", 2485 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "", 2486 2487 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "", 2488 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "", 2489 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : ""); 2490 2491 tmp = omap_readw(UDC_RXDMA_CFG); 2492 seq_printf(s, "rxdma_cfg %04x\n", tmp); 2493 if (tmp) { 2494 for (i = 0; i < 3; i++) { 2495 if ((tmp & (0x0f << (i * 4))) == 0) 2496 continue; 2497 seq_printf(s, "rxdma[%d] %04x\n", i, 2498 omap_readw(UDC_RXDMA(i + 1))); 2499 } 2500 } 2501 tmp = omap_readw(UDC_TXDMA_CFG); 2502 seq_printf(s, "txdma_cfg %04x\n", tmp); 2503 if (tmp) { 2504 for (i = 0; i < 3; i++) { 2505 if (!(tmp & (0x0f << (i * 4)))) 2506 continue; 2507 seq_printf(s, "txdma[%d] %04x\n", i, 2508 omap_readw(UDC_TXDMA(i + 1))); 2509 } 2510 } 2511 } 2512 2513 tmp = omap_readw(UDC_DEVSTAT); 2514 if (tmp & UDC_ATT) { 2515 proc_ep_show(s, &udc->ep[0]); 2516 if (tmp & UDC_ADD) { 2517 list_for_each_entry (ep, &udc->gadget.ep_list, 2518 ep.ep_list) { 2519 if (ep->desc) 2520 proc_ep_show(s, ep); 2521 } 2522 } 2523 } 2524 spin_unlock_irqrestore(&udc->lock, flags); 2525 return 0; 2526} 2527 2528static int proc_udc_open(struct inode *inode, struct file *file) 2529{ 2530 return single_open(file, proc_udc_show, NULL); 2531} 2532 2533static const struct file_operations proc_ops = { 2534 .owner = THIS_MODULE, 2535 .open = proc_udc_open, 2536 .read = seq_read, 2537 .llseek = seq_lseek, 2538 .release = single_release, 2539}; 2540 2541static void create_proc_file(void) 2542{ 2543 proc_create(proc_filename, 0, NULL, &proc_ops); 2544} 2545 2546static void remove_proc_file(void) 2547{ 2548 remove_proc_entry(proc_filename, NULL); 2549} 2550 2551#else 2552 2553static inline void create_proc_file(void) {} 2554static inline void remove_proc_file(void) {} 2555 2556#endif 2557 2558/*-------------------------------------------------------------------------*/ 2559 2560/* Before this controller can enumerate, we need to pick an endpoint 2561 * configuration, or "fifo_mode" That involves allocating 2KB of packet 2562 * buffer space among the endpoints we'll be operating. 2563 * 2564 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when 2565 * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that 2566 * capability yet though. 2567 */ 2568static unsigned __init 2569omap_ep_setup(char *name, u8 addr, u8 type, 2570 unsigned buf, unsigned maxp, int dbuf) 2571{ 2572 struct omap_ep *ep; 2573 u16 epn_rxtx = 0; 2574 2575 /* OUT endpoints first, then IN */ 2576 ep = &udc->ep[addr & 0xf]; 2577 if (addr & USB_DIR_IN) 2578 ep += 16; 2579 2580 /* in case of ep init table bugs */ 2581 BUG_ON(ep->name[0]); 2582 2583 /* chip setup ... bit values are same for IN, OUT */ 2584 if (type == USB_ENDPOINT_XFER_ISOC) { 2585 switch (maxp) { 2586 case 8: epn_rxtx = 0 << 12; break; 2587 case 16: epn_rxtx = 1 << 12; break; 2588 case 32: epn_rxtx = 2 << 12; break; 2589 case 64: epn_rxtx = 3 << 12; break; 2590 case 128: epn_rxtx = 4 << 12; break; 2591 case 256: epn_rxtx = 5 << 12; break; 2592 case 512: epn_rxtx = 6 << 12; break; 2593 default: BUG(); 2594 } 2595 epn_rxtx |= UDC_EPN_RX_ISO; 2596 dbuf = 1; 2597 } else { 2598 /* double-buffering "not supported" on 15xx, 2599 * and ignored for PIO-IN on newer chips 2600 * (for more reliable behavior) 2601 */ 2602 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx()) 2603 dbuf = 0; 2604 2605 switch (maxp) { 2606 case 8: epn_rxtx = 0 << 12; break; 2607 case 16: epn_rxtx = 1 << 12; break; 2608 case 32: epn_rxtx = 2 << 12; break; 2609 case 64: epn_rxtx = 3 << 12; break; 2610 default: BUG(); 2611 } 2612 if (dbuf && addr) 2613 epn_rxtx |= UDC_EPN_RX_DB; 2614 init_timer(&ep->timer); 2615 ep->timer.function = pio_out_timer; 2616 ep->timer.data = (unsigned long) ep; 2617 } 2618 if (addr) 2619 epn_rxtx |= UDC_EPN_RX_VALID; 2620 BUG_ON(buf & 0x07); 2621 epn_rxtx |= buf >> 3; 2622 2623 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n", 2624 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf); 2625 2626 if (addr & USB_DIR_IN) 2627 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf)); 2628 else 2629 omap_writew(epn_rxtx, UDC_EP_RX(addr)); 2630 2631 /* next endpoint's buffer starts after this one's */ 2632 buf += maxp; 2633 if (dbuf) 2634 buf += maxp; 2635 BUG_ON(buf > 2048); 2636 2637 /* set up driver data structures */ 2638 BUG_ON(strlen(name) >= sizeof ep->name); 2639 strlcpy(ep->name, name, sizeof ep->name); 2640 INIT_LIST_HEAD(&ep->queue); 2641 INIT_LIST_HEAD(&ep->iso); 2642 ep->bEndpointAddress = addr; 2643 ep->bmAttributes = type; 2644 ep->double_buf = dbuf; 2645 ep->udc = udc; 2646 2647 ep->ep.name = ep->name; 2648 ep->ep.ops = &omap_ep_ops; 2649 ep->ep.maxpacket = ep->maxpacket = maxp; 2650 list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list); 2651 2652 return buf; 2653} 2654 2655static void omap_udc_release(struct device *dev) 2656{ 2657 complete(udc->done); 2658 kfree (udc); 2659 udc = NULL; 2660} 2661 2662static int __init 2663omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv) 2664{ 2665 unsigned tmp, buf; 2666 2667 /* abolish any previous hardware state */ 2668 omap_writew(0, UDC_SYSCON1); 2669 omap_writew(0, UDC_IRQ_EN); 2670 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC); 2671 omap_writew(0, UDC_DMA_IRQ_EN); 2672 omap_writew(0, UDC_RXDMA_CFG); 2673 omap_writew(0, UDC_TXDMA_CFG); 2674 2675 /* UDC_PULLUP_EN gates the chip clock */ 2676 // OTG_SYSCON_1 |= DEV_IDLE_EN; 2677 2678 udc = kzalloc(sizeof(*udc), GFP_KERNEL); 2679 if (!udc) 2680 return -ENOMEM; 2681 2682 spin_lock_init (&udc->lock); 2683 2684 udc->gadget.ops = &omap_gadget_ops; 2685 udc->gadget.ep0 = &udc->ep[0].ep; 2686 INIT_LIST_HEAD(&udc->gadget.ep_list); 2687 INIT_LIST_HEAD(&udc->iso); 2688 udc->gadget.speed = USB_SPEED_UNKNOWN; 2689 udc->gadget.name = driver_name; 2690 2691 device_initialize(&udc->gadget.dev); 2692 dev_set_name(&udc->gadget.dev, "gadget"); 2693 udc->gadget.dev.release = omap_udc_release; 2694 udc->gadget.dev.parent = &odev->dev; 2695 if (use_dma) 2696 udc->gadget.dev.dma_mask = odev->dev.dma_mask; 2697 2698 udc->transceiver = xceiv; 2699 2700 /* ep0 is special; put it right after the SETUP buffer */ 2701 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL, 2702 8 /* after SETUP */, 64 /* maxpacket */, 0); 2703 list_del_init(&udc->ep[0].ep.ep_list); 2704 2705 /* initially disable all non-ep0 endpoints */ 2706 for (tmp = 1; tmp < 15; tmp++) { 2707 omap_writew(0, UDC_EP_RX(tmp)); 2708 omap_writew(0, UDC_EP_TX(tmp)); 2709 } 2710 2711#define OMAP_BULK_EP(name,addr) \ 2712 buf = omap_ep_setup(name "-bulk", addr, \ 2713 USB_ENDPOINT_XFER_BULK, buf, 64, 1); 2714#define OMAP_INT_EP(name,addr, maxp) \ 2715 buf = omap_ep_setup(name "-int", addr, \ 2716 USB_ENDPOINT_XFER_INT, buf, maxp, 0); 2717#define OMAP_ISO_EP(name,addr, maxp) \ 2718 buf = omap_ep_setup(name "-iso", addr, \ 2719 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1); 2720 2721 switch (fifo_mode) { 2722 case 0: 2723 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1); 2724 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2); 2725 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16); 2726 break; 2727 case 1: 2728 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1); 2729 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2); 2730 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16); 2731 2732 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3); 2733 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4); 2734 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16); 2735 2736 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5); 2737 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5); 2738 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16); 2739 2740 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6); 2741 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6); 2742 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16); 2743 2744 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7); 2745 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7); 2746 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16); 2747 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16); 2748 2749 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8); 2750 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8); 2751 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16); 2752 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16); 2753 2754 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15); 2755 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15); 2756 2757 break; 2758 2759#ifdef USE_ISO 2760 case 2: /* mixed iso/bulk */ 2761 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256); 2762 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256); 2763 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128); 2764 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128); 2765 2766 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16); 2767 2768 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6); 2769 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7); 2770 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16); 2771 break; 2772 case 3: /* mixed bulk/iso */ 2773 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1); 2774 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2); 2775 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16); 2776 2777 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4); 2778 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5); 2779 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16); 2780 2781 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256); 2782 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256); 2783 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16); 2784 break; 2785#endif 2786 2787 /* add more modes as needed */ 2788 2789 default: 2790 ERR("unsupported fifo_mode #%d\n", fifo_mode); 2791 return -ENODEV; 2792 } 2793 omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1); 2794 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf); 2795 return 0; 2796} 2797 2798static int __init omap_udc_probe(struct platform_device *pdev) 2799{ 2800 int status = -ENODEV; 2801 int hmc; 2802 struct otg_transceiver *xceiv = NULL; 2803 const char *type = NULL; 2804 struct omap_usb_config *config = pdev->dev.platform_data; 2805 struct clk *dc_clk; 2806 struct clk *hhc_clk; 2807 2808 /* NOTE: "knows" the order of the resources! */ 2809 if (!request_mem_region(pdev->resource[0].start, 2810 pdev->resource[0].end - pdev->resource[0].start + 1, 2811 driver_name)) { 2812 DBG("request_mem_region failed\n"); 2813 return -EBUSY; 2814 } 2815 2816 if (cpu_is_omap16xx()) { 2817 dc_clk = clk_get(&pdev->dev, "usb_dc_ck"); 2818 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck"); 2819 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk)); 2820 /* can't use omap_udc_enable_clock yet */ 2821 clk_enable(dc_clk); 2822 clk_enable(hhc_clk); 2823 udelay(100); 2824 } 2825 2826 if (cpu_is_omap24xx()) { 2827 dc_clk = clk_get(&pdev->dev, "usb_fck"); 2828 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick"); 2829 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk)); 2830 /* can't use omap_udc_enable_clock yet */ 2831 clk_enable(dc_clk); 2832 clk_enable(hhc_clk); 2833 udelay(100); 2834 } 2835 2836 if (cpu_is_omap7xx()) { 2837 dc_clk = clk_get(&pdev->dev, "usb_dc_ck"); 2838 hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck"); 2839 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk)); 2840 /* can't use omap_udc_enable_clock yet */ 2841 clk_enable(dc_clk); 2842 clk_enable(hhc_clk); 2843 udelay(100); 2844 } 2845 2846 INFO("OMAP UDC rev %d.%d%s\n", 2847 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf, 2848 config->otg ? ", Mini-AB" : ""); 2849 2850 /* use the mode given to us by board init code */ 2851 if (cpu_is_omap15xx()) { 2852 hmc = HMC_1510; 2853 type = "(unknown)"; 2854 2855 if (machine_without_vbus_sense()) { 2856 u32 tmp = omap_readl(FUNC_MUX_CTRL_0); 2857 tmp &= ~VBUS_CTRL_1510; 2858 omap_writel(tmp, FUNC_MUX_CTRL_0); 2859 tmp |= VBUS_MODE_1510; 2860 tmp &= ~VBUS_CTRL_1510; 2861 omap_writel(tmp, FUNC_MUX_CTRL_0); 2862 } 2863 } else { 2864 /* The transceiver may package some GPIO logic or handle 2865 * loopback and/or transceiverless setup; if we find one, 2866 * use it. Except for OTG, we don't _need_ to talk to one; 2867 * but not having one probably means no VBUS detection. 2868 */ 2869 xceiv = otg_get_transceiver(); 2870 if (xceiv) 2871 type = xceiv->label; 2872 else if (config->otg) { 2873 DBG("OTG requires external transceiver!\n"); 2874 goto cleanup0; 2875 } 2876 2877 hmc = HMC_1610; 2878 2879 if (cpu_is_omap24xx()) { 2880 /* this could be transceiverless in one of the 2881 * "we don't need to know" modes. 2882 */ 2883 type = "external"; 2884 goto known; 2885 } 2886 2887 switch (hmc) { 2888 case 0: /* POWERUP DEFAULT == 0 */ 2889 case 4: 2890 case 12: 2891 case 20: 2892 if (!cpu_is_omap1710()) { 2893 type = "integrated"; 2894 break; 2895 } 2896 /* FALL THROUGH */ 2897 case 3: 2898 case 11: 2899 case 16: 2900 case 19: 2901 case 25: 2902 if (!xceiv) { 2903 DBG("external transceiver not registered!\n"); 2904 type = "unknown"; 2905 } 2906 break; 2907 case 21: /* internal loopback */ 2908 type = "loopback"; 2909 break; 2910 case 14: /* transceiverless */ 2911 if (cpu_is_omap1710()) 2912 goto bad_on_1710; 2913 /* FALL THROUGH */ 2914 case 13: 2915 case 15: 2916 type = "no"; 2917 break; 2918 2919 default: 2920bad_on_1710: 2921 ERR("unrecognized UDC HMC mode %d\n", hmc); 2922 goto cleanup0; 2923 } 2924 } 2925known: 2926 INFO("hmc mode %d, %s transceiver\n", hmc, type); 2927 2928 /* a "gadget" abstracts/virtualizes the controller */ 2929 status = omap_udc_setup(pdev, xceiv); 2930 if (status) { 2931 goto cleanup0; 2932 } 2933 xceiv = NULL; 2934 // "udc" is now valid 2935 pullup_disable(udc); 2936#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 2937 udc->gadget.is_otg = (config->otg != 0); 2938#endif 2939 2940 /* starting with omap1710 es2.0, clear toggle is a separate bit */ 2941 if (omap_readw(UDC_REV) >= 0x61) 2942 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE; 2943 else 2944 udc->clr_halt = UDC_RESET_EP; 2945 2946 /* USB general purpose IRQ: ep0, state changes, dma, etc */ 2947 status = request_irq(pdev->resource[1].start, omap_udc_irq, 2948 IRQF_SAMPLE_RANDOM, driver_name, udc); 2949 if (status != 0) { 2950 ERR("can't get irq %d, err %d\n", 2951 (int) pdev->resource[1].start, status); 2952 goto cleanup1; 2953 } 2954 2955 /* USB "non-iso" IRQ (PIO for all but ep0) */ 2956 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq, 2957 IRQF_SAMPLE_RANDOM, "omap_udc pio", udc); 2958 if (status != 0) { 2959 ERR("can't get irq %d, err %d\n", 2960 (int) pdev->resource[2].start, status); 2961 goto cleanup2; 2962 } 2963#ifdef USE_ISO 2964 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq, 2965 IRQF_DISABLED, "omap_udc iso", udc); 2966 if (status != 0) { 2967 ERR("can't get irq %d, err %d\n", 2968 (int) pdev->resource[3].start, status); 2969 goto cleanup3; 2970 } 2971#endif 2972 if (cpu_is_omap16xx() || cpu_is_omap7xx()) { 2973 udc->dc_clk = dc_clk; 2974 udc->hhc_clk = hhc_clk; 2975 clk_disable(hhc_clk); 2976 clk_disable(dc_clk); 2977 } 2978 2979 if (cpu_is_omap24xx()) { 2980 udc->dc_clk = dc_clk; 2981 udc->hhc_clk = hhc_clk; 2982 } 2983 2984 create_proc_file(); 2985 status = device_add(&udc->gadget.dev); 2986 if (!status) 2987 return status; 2988 /* If fail, fall through */ 2989#ifdef USE_ISO 2990cleanup3: 2991 free_irq(pdev->resource[2].start, udc); 2992#endif 2993 2994cleanup2: 2995 free_irq(pdev->resource[1].start, udc); 2996 2997cleanup1: 2998 kfree (udc); 2999 udc = NULL; 3000 3001cleanup0: 3002 if (xceiv) 3003 otg_put_transceiver(xceiv); 3004 3005 if (cpu_is_omap16xx() || cpu_is_omap24xx() || cpu_is_omap7xx()) { 3006 clk_disable(hhc_clk); 3007 clk_disable(dc_clk); 3008 clk_put(hhc_clk); 3009 clk_put(dc_clk); 3010 } 3011 3012 release_mem_region(pdev->resource[0].start, 3013 pdev->resource[0].end - pdev->resource[0].start + 1); 3014 3015 return status; 3016} 3017 3018static int __exit omap_udc_remove(struct platform_device *pdev) 3019{ 3020 DECLARE_COMPLETION_ONSTACK(done); 3021 3022 if (!udc) 3023 return -ENODEV; 3024 if (udc->driver) 3025 return -EBUSY; 3026 3027 udc->done = &done; 3028 3029 pullup_disable(udc); 3030 if (udc->transceiver) { 3031 otg_put_transceiver(udc->transceiver); 3032 udc->transceiver = NULL; 3033 } 3034 omap_writew(0, UDC_SYSCON1); 3035 3036 remove_proc_file(); 3037 3038#ifdef USE_ISO 3039 free_irq(pdev->resource[3].start, udc); 3040#endif 3041 free_irq(pdev->resource[2].start, udc); 3042 free_irq(pdev->resource[1].start, udc); 3043 3044 if (udc->dc_clk) { 3045 if (udc->clk_requested) 3046 omap_udc_enable_clock(0); 3047 clk_put(udc->hhc_clk); 3048 clk_put(udc->dc_clk); 3049 } 3050 3051 release_mem_region(pdev->resource[0].start, 3052 pdev->resource[0].end - pdev->resource[0].start + 1); 3053 3054 device_unregister(&udc->gadget.dev); 3055 wait_for_completion(&done); 3056 3057 return 0; 3058} 3059 3060/* suspend/resume/wakeup from sysfs (echo > power/state) or when the 3061 * system is forced into deep sleep 3062 * 3063 * REVISIT we should probably reject suspend requests when there's a host 3064 * session active, rather than disconnecting, at least on boards that can 3065 * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to 3066 * make host resumes and VBUS detection trigger OMAP wakeup events; that 3067 * may involve talking to an external transceiver (e.g. isp1301). 3068 */ 3069 3070static int omap_udc_suspend(struct platform_device *dev, pm_message_t message) 3071{ 3072 u32 devstat; 3073 3074 devstat = omap_readw(UDC_DEVSTAT); 3075 3076 /* we're requesting 48 MHz clock if the pullup is enabled 3077 * (== we're attached to the host) and we're not suspended, 3078 * which would prevent entry to deep sleep... 3079 */ 3080 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) { 3081 WARNING("session active; suspend requires disconnect\n"); 3082 omap_pullup(&udc->gadget, 0); 3083 } 3084 3085 return 0; 3086} 3087 3088static int omap_udc_resume(struct platform_device *dev) 3089{ 3090 DBG("resume + wakeup/SRP\n"); 3091 omap_pullup(&udc->gadget, 1); 3092 3093 /* maybe the host would enumerate us if we nudged it */ 3094 msleep(100); 3095 return omap_wakeup(&udc->gadget); 3096} 3097 3098/*-------------------------------------------------------------------------*/ 3099 3100static struct platform_driver udc_driver = { 3101 .remove = __exit_p(omap_udc_remove), 3102 .suspend = omap_udc_suspend, 3103 .resume = omap_udc_resume, 3104 .driver = { 3105 .owner = THIS_MODULE, 3106 .name = (char *) driver_name, 3107 }, 3108}; 3109 3110static int __init udc_init(void) 3111{ 3112 /* Disable DMA for omap7xx -- it doesn't work right. */ 3113 if (cpu_is_omap7xx()) 3114 use_dma = 0; 3115 3116 INFO("%s, version: " DRIVER_VERSION 3117#ifdef USE_ISO 3118 " (iso)" 3119#endif 3120 "%s\n", driver_desc, 3121 use_dma ? " (dma)" : ""); 3122 return platform_driver_probe(&udc_driver, omap_udc_probe); 3123} 3124module_init(udc_init); 3125 3126static void __exit udc_exit(void) 3127{ 3128 platform_driver_unregister(&udc_driver); 3129} 3130module_exit(udc_exit); 3131 3132MODULE_DESCRIPTION(DRIVER_DESC); 3133MODULE_LICENSE("GPL"); 3134MODULE_ALIAS("platform:omap_udc"); 3135