1/* 2 ************************************************************************* 3 * Ralink Tech Inc. 4 * 5F., No.36, Taiyuan St., Jhubei City, 5 * Hsinchu County 302, 6 * Taiwan, R.O.C. 7 * 8 * (c) Copyright 2002-2007, Ralink Technology, Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify * 11 * it under the terms of the GNU General Public License as published by * 12 * the Free Software Foundation; either version 2 of the License, or * 13 * (at your option) any later version. * 14 * * 15 * This program is distributed in the hope that it will be useful, * 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of * 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * 18 * GNU General Public License for more details. * 19 * * 20 * You should have received a copy of the GNU General Public License * 21 * along with this program; if not, write to the * 22 * Free Software Foundation, Inc., * 23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * 24 * * 25 ************************************************************************* 26 27 Module Name: 28 rtmp_mac.h 29 30 Abstract: 31 Ralink Wireless Chip MAC related definition & structures 32 33 Revision History: 34 Who When What 35 -------- ---------- ---------------------------------------------- 36*/ 37 38#ifndef __RTMP_MAC_H__ 39#define __RTMP_MAC_H__ 40 41/* ================================================================================= */ 42/* TX / RX ring descriptor format */ 43/* ================================================================================= */ 44 45/* the first 24-byte in TXD is called TXINFO and will be DMAed to MAC block through TXFIFO. */ 46/* MAC block use this TXINFO to control the transmission behavior of this frame. */ 47#define FIFO_MGMT 0 48#define FIFO_HCCA 1 49#define FIFO_EDCA 2 50 51/* */ 52/* TXD Wireless Information format for Tx ring and Mgmt Ring */ 53/* */ 54/*txop : for txop mode */ 55/* 0:txop for the MPDU frame will be handles by ASIC by register */ 56/* 1/2/3:the MPDU frame is send after PIFS/backoff/SIFS */ 57struct PACKED rt_txwi { 58 /* Word 0 */ 59 /* ex: 00 03 00 40 means txop = 3, PHYMODE = 1 */ 60 u32 FRAG:1; /* 1 to inform TKIP engine this is a fragment. */ 61 u32 MIMOps:1; /* the remote peer is in dynamic MIMO-PS mode */ 62 u32 CFACK:1; 63 u32 TS:1; 64 65 u32 AMPDU:1; 66 u32 MpduDensity:3; 67 u32 txop:2; /*FOR "THIS" frame. 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful. */ 68 u32 rsv:6; 69 70 u32 MCS:7; 71 u32 BW:1; /*channel bandwidth 20MHz or 40 MHz */ 72 u32 ShortGI:1; 73 u32 STBC:2; /* 1: STBC support MCS =0-7, 2,3 : RESERVE */ 74 u32 Ifs:1; /* */ 75/* u32 rsv2:2; //channel bandwidth 20MHz or 40 MHz */ 76 u32 rsv2:1; 77 u32 TxBF:1; /* 3*3 */ 78 u32 PHYMODE:2; 79 /* Word1 */ 80 /* ex: 1c ff 38 00 means ACK=0, BAWinSize=7, MPDUtotalByteCount = 0x38 */ 81 u32 ACK:1; 82 u32 NSEQ:1; 83 u32 BAWinSize:6; 84 u32 WirelessCliID:8; 85 u32 MPDUtotalByteCount:12; 86 u32 PacketId:4; 87 /*Word2 */ 88 u32 IV; 89 /*Word3 */ 90 u32 EIV; 91}; 92 93/* */ 94/* RXWI wireless information format, in PBF. invisible in driver. */ 95/* */ 96struct PACKED rt_rxwi { 97 /* Word 0 */ 98 u32 WirelessCliID:8; 99 u32 KeyIndex:2; 100 u32 BSSID:3; 101 u32 UDF:3; 102 u32 MPDUtotalByteCount:12; 103 u32 TID:4; 104 /* Word 1 */ 105 u32 FRAG:4; 106 u32 SEQUENCE:12; 107 u32 MCS:7; 108 u32 BW:1; 109 u32 ShortGI:1; 110 u32 STBC:2; 111 u32 rsv:3; 112 u32 PHYMODE:2; /* 1: this RX frame is unicast to me */ 113 /*Word2 */ 114 u32 RSSI0:8; 115 u32 RSSI1:8; 116 u32 RSSI2:8; 117 u32 rsv1:8; 118 /*Word3 */ 119 u32 SNR0:8; 120 u32 SNR1:8; 121 u32 FOFFSET:8; /* RT35xx */ 122 u32 rsv2:8; 123 /*u32 rsv2:16; */ 124}; 125 126/* ================================================================================= */ 127/* Register format */ 128/* ================================================================================= */ 129 130/* */ 131/* SCH/DMA registers - base address 0x0200 */ 132/* */ 133/* INT_SOURCE_CSR: Interrupt source register. Write one to clear corresponding bit */ 134/* */ 135#define DMA_CSR0 0x200 136#define INT_SOURCE_CSR 0x200 137typedef union _INT_SOURCE_CSR_STRUC { 138 struct { 139 u32 RxDelayINT:1; 140 u32 TxDelayINT:1; 141 u32 RxDone:1; 142 u32 Ac0DmaDone:1; /*4 */ 143 u32 Ac1DmaDone:1; 144 u32 Ac2DmaDone:1; 145 u32 Ac3DmaDone:1; 146 u32 HccaDmaDone:1; /* bit7 */ 147 u32 MgmtDmaDone:1; 148 u32 MCUCommandINT:1; /*bit 9 */ 149 u32 RxTxCoherent:1; 150 u32 TBTTInt:1; 151 u32 PreTBTT:1; 152 u32 TXFifoStatusInt:1; /*FIFO Statistics is full, sw should read 0x171c */ 153 u32 AutoWakeup:1; /*bit14 */ 154 u32 GPTimer:1; 155 u32 RxCoherent:1; /*bit16 */ 156 u32 TxCoherent:1; 157 u32: 14; 158 } field; 159 u32 word; 160} INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC; 161 162/* */ 163/* INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF */ 164/* */ 165#define INT_MASK_CSR 0x204 166typedef union _INT_MASK_CSR_STRUC { 167 struct { 168 u32 RXDelay_INT_MSK:1; 169 u32 TxDelay:1; 170 u32 RxDone:1; 171 u32 Ac0DmaDone:1; 172 u32 Ac1DmaDone:1; 173 u32 Ac2DmaDone:1; 174 u32 Ac3DmaDone:1; 175 u32 HccaDmaDone:1; 176 u32 MgmtDmaDone:1; 177 u32 MCUCommandINT:1; 178 u32: 20; 179 u32 RxCoherent:1; 180 u32 TxCoherent:1; 181 } field; 182 u32 word; 183} INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC; 184 185#define WPDMA_GLO_CFG 0x208 186typedef union _WPDMA_GLO_CFG_STRUC { 187 struct { 188 u32 EnableTxDMA:1; 189 u32 TxDMABusy:1; 190 u32 EnableRxDMA:1; 191 u32 RxDMABusy:1; 192 u32 WPDMABurstSIZE:2; 193 u32 EnTXWriteBackDDONE:1; 194 u32 BigEndian:1; 195 u32 RXHdrScater:8; 196 u32 HDR_SEG_LEN:16; 197 } field; 198 u32 word; 199} WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC; 200 201#define WPDMA_RST_IDX 0x20c 202typedef union _WPDMA_RST_IDX_STRUC { 203 struct { 204 u32 RST_DTX_IDX0:1; 205 u32 RST_DTX_IDX1:1; 206 u32 RST_DTX_IDX2:1; 207 u32 RST_DTX_IDX3:1; 208 u32 RST_DTX_IDX4:1; 209 u32 RST_DTX_IDX5:1; 210 u32 rsv:10; 211 u32 RST_DRX_IDX0:1; 212 u32: 15; 213 } field; 214 u32 word; 215} WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC; 216#define DELAY_INT_CFG 0x0210 217typedef union _DELAY_INT_CFG_STRUC { 218 struct { 219 u32 RXMAX_PTIME:8; 220 u32 RXMAX_PINT:7; 221 u32 RXDLY_INT_EN:1; 222 u32 TXMAX_PTIME:8; 223 u32 TXMAX_PINT:7; 224 u32 TXDLY_INT_EN:1; 225 } field; 226 u32 word; 227} DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC; 228#define WMM_AIFSN_CFG 0x0214 229typedef union _AIFSN_CSR_STRUC { 230 struct { 231 u32 Aifsn0:4; /* for AC_BE */ 232 u32 Aifsn1:4; /* for AC_BK */ 233 u32 Aifsn2:4; /* for AC_VI */ 234 u32 Aifsn3:4; /* for AC_VO */ 235 u32 Rsv:16; 236 } field; 237 u32 word; 238} AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC; 239/* */ 240/* CWMIN_CSR: CWmin for each EDCA AC */ 241/* */ 242#define WMM_CWMIN_CFG 0x0218 243typedef union _CWMIN_CSR_STRUC { 244 struct { 245 u32 Cwmin0:4; /* for AC_BE */ 246 u32 Cwmin1:4; /* for AC_BK */ 247 u32 Cwmin2:4; /* for AC_VI */ 248 u32 Cwmin3:4; /* for AC_VO */ 249 u32 Rsv:16; 250 } field; 251 u32 word; 252} CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC; 253 254/* */ 255/* CWMAX_CSR: CWmin for each EDCA AC */ 256/* */ 257#define WMM_CWMAX_CFG 0x021c 258typedef union _CWMAX_CSR_STRUC { 259 struct { 260 u32 Cwmax0:4; /* for AC_BE */ 261 u32 Cwmax1:4; /* for AC_BK */ 262 u32 Cwmax2:4; /* for AC_VI */ 263 u32 Cwmax3:4; /* for AC_VO */ 264 u32 Rsv:16; 265 } field; 266 u32 word; 267} CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC; 268 269/* */ 270/* AC_TXOP_CSR0: AC_BK/AC_BE TXOP register */ 271/* */ 272#define WMM_TXOP0_CFG 0x0220 273typedef union _AC_TXOP_CSR0_STRUC { 274 struct { 275 u16 Ac0Txop; /* for AC_BK, in unit of 32us */ 276 u16 Ac1Txop; /* for AC_BE, in unit of 32us */ 277 } field; 278 u32 word; 279} AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC; 280 281/* */ 282/* AC_TXOP_CSR1: AC_VO/AC_VI TXOP register */ 283/* */ 284#define WMM_TXOP1_CFG 0x0224 285typedef union _AC_TXOP_CSR1_STRUC { 286 struct { 287 u16 Ac2Txop; /* for AC_VI, in unit of 32us */ 288 u16 Ac3Txop; /* for AC_VO, in unit of 32us */ 289 } field; 290 u32 word; 291} AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC; 292 293#define RINGREG_DIFF 0x10 294#define GPIO_CTRL_CFG 0x0228 /*MAC_CSR13 */ 295#define MCU_CMD_CFG 0x022c 296#define TX_BASE_PTR0 0x0230 /*AC_BK base address */ 297#define TX_MAX_CNT0 0x0234 298#define TX_CTX_IDX0 0x0238 299#define TX_DTX_IDX0 0x023c 300#define TX_BASE_PTR1 0x0240 /*AC_BE base address */ 301#define TX_MAX_CNT1 0x0244 302#define TX_CTX_IDX1 0x0248 303#define TX_DTX_IDX1 0x024c 304#define TX_BASE_PTR2 0x0250 /*AC_VI base address */ 305#define TX_MAX_CNT2 0x0254 306#define TX_CTX_IDX2 0x0258 307#define TX_DTX_IDX2 0x025c 308#define TX_BASE_PTR3 0x0260 /*AC_VO base address */ 309#define TX_MAX_CNT3 0x0264 310#define TX_CTX_IDX3 0x0268 311#define TX_DTX_IDX3 0x026c 312#define TX_BASE_PTR4 0x0270 /*HCCA base address */ 313#define TX_MAX_CNT4 0x0274 314#define TX_CTX_IDX4 0x0278 315#define TX_DTX_IDX4 0x027c 316#define TX_BASE_PTR5 0x0280 /*MGMT base address */ 317#define TX_MAX_CNT5 0x0284 318#define TX_CTX_IDX5 0x0288 319#define TX_DTX_IDX5 0x028c 320#define TX_MGMTMAX_CNT TX_MAX_CNT5 321#define TX_MGMTCTX_IDX TX_CTX_IDX5 322#define TX_MGMTDTX_IDX TX_DTX_IDX5 323#define RX_BASE_PTR 0x0290 /*RX base address */ 324#define RX_MAX_CNT 0x0294 325#define RX_CRX_IDX 0x0298 326#define RX_DRX_IDX 0x029c 327 328#define USB_DMA_CFG 0x02a0 329typedef union _USB_DMA_CFG_STRUC { 330 struct { 331 u32 RxBulkAggTOut:8; /*Rx Bulk Aggregation TimeOut in unit of 33ns */ 332 u32 RxBulkAggLmt:8; /*Rx Bulk Aggregation Limit in unit of 256 bytes */ 333 u32 phyclear:1; /*phy watch dog enable. write 1 */ 334 u32 rsv:2; 335 u32 TxClear:1; /*Clear USB DMA TX path */ 336 u32 TxopHalt:1; /*Halt TXOP count down when TX buffer is full. */ 337 u32 RxBulkAggEn:1; /*Enable Rx Bulk Aggregation */ 338 u32 RxBulkEn:1; /*Enable USB DMA Rx */ 339 u32 TxBulkEn:1; /*Enable USB DMA Tx */ 340 u32 EpoutValid:6; /*OUT endpoint data valid */ 341 u32 RxBusy:1; /*USB DMA RX FSM busy */ 342 u32 TxBusy:1; /*USB DMA TX FSM busy */ 343 } field; 344 u32 word; 345} USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC; 346 347/* */ 348/* 3 PBF registers */ 349/* */ 350/* */ 351/* Most are for debug. Driver doesn't touch PBF register. */ 352#define PBF_SYS_CTRL 0x0400 353#define PBF_CFG 0x0408 354#define PBF_MAX_PCNT 0x040C 355#define PBF_CTRL 0x0410 356#define PBF_INT_STA 0x0414 357#define PBF_INT_ENA 0x0418 358#define TXRXQ_PCNT 0x0438 359#define PBF_DBG 0x043c 360#define PBF_CAP_CTRL 0x0440 361 362#ifdef RT30xx 363#ifdef RTMP_EFUSE_SUPPORT 364/* eFuse registers */ 365#define EFUSE_CTRL 0x0580 366#define EFUSE_DATA0 0x0590 367#define EFUSE_DATA1 0x0594 368#define EFUSE_DATA2 0x0598 369#define EFUSE_DATA3 0x059c 370#endif /* RTMP_EFUSE_SUPPORT // */ 371#endif /* RT30xx // */ 372 373#define OSC_CTRL 0x5a4 374#define PCIE_PHY_TX_ATTENUATION_CTRL 0x05C8 375#define LDO_CFG0 0x05d4 376#define GPIO_SWITCH 0x05dc 377 378/* */ 379/* 4 MAC registers */ 380/* */ 381/* */ 382/* 4.1 MAC SYSTEM configuration registers (offset:0x1000) */ 383/* */ 384#define MAC_CSR0 0x1000 385typedef union _ASIC_VER_ID_STRUC { 386 struct { 387 u16 ASICRev; /* reversion : 0 */ 388 u16 ASICVer; /* version : 2860 */ 389 } field; 390 u32 word; 391} ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC; 392#define MAC_SYS_CTRL 0x1004 /*MAC_CSR1 */ 393#define MAC_ADDR_DW0 0x1008 /* MAC ADDR DW0 */ 394#define MAC_ADDR_DW1 0x100c /* MAC ADDR DW1 */ 395/* */ 396/* MAC_CSR2: STA MAC register 0 */ 397/* */ 398typedef union _MAC_DW0_STRUC { 399 struct { 400 u8 Byte0; /* MAC address byte 0 */ 401 u8 Byte1; /* MAC address byte 1 */ 402 u8 Byte2; /* MAC address byte 2 */ 403 u8 Byte3; /* MAC address byte 3 */ 404 } field; 405 u32 word; 406} MAC_DW0_STRUC, *PMAC_DW0_STRUC; 407 408/* */ 409/* MAC_CSR3: STA MAC register 1 */ 410/* */ 411typedef union _MAC_DW1_STRUC { 412 struct { 413 u8 Byte4; /* MAC address byte 4 */ 414 u8 Byte5; /* MAC address byte 5 */ 415 u8 U2MeMask; 416 u8 Rsvd1; 417 } field; 418 u32 word; 419} MAC_DW1_STRUC, *PMAC_DW1_STRUC; 420 421#define MAC_BSSID_DW0 0x1010 /* MAC BSSID DW0 */ 422#define MAC_BSSID_DW1 0x1014 /* MAC BSSID DW1 */ 423 424/* */ 425/* MAC_CSR5: BSSID register 1 */ 426/* */ 427typedef union _MAC_CSR5_STRUC { 428 struct { 429 u8 Byte4; /* BSSID byte 4 */ 430 u8 Byte5; /* BSSID byte 5 */ 431 u16 BssIdMask:2; /* 0: one BSSID, 10: 4 BSSID, 01: 2 BSSID , 11: 8BSSID */ 432 u16 MBssBcnNum:3; 433 u16 Rsvd:11; 434 } field; 435 u32 word; 436} MAC_CSR5_STRUC, *PMAC_CSR5_STRUC; 437 438#define MAX_LEN_CFG 0x1018 /* rt2860b max 16k bytes. bit12:13 Maximum PSDU length (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16 */ 439#define BBP_CSR_CFG 0x101c /* */ 440/* */ 441/* BBP_CSR_CFG: BBP serial control register */ 442/* */ 443typedef union _BBP_CSR_CFG_STRUC { 444 struct { 445 u32 Value:8; /* Register value to program into BBP */ 446 u32 RegNum:8; /* Selected BBP register */ 447 u32 fRead:1; /* 0: Write BBP, 1: Read BBP */ 448 u32 Busy:1; /* 1: ASIC is busy execute BBP programming. */ 449 u32 BBP_PAR_DUR:1; /* 0: 4 MAC clock cycles 1: 8 MAC clock cycles */ 450 u32 BBP_RW_MODE:1; /* 0: use serial mode 1:parallel */ 451 u32: 12; 452 } field; 453 u32 word; 454} BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC; 455#define RF_CSR_CFG0 0x1020 456/* */ 457/* RF_CSR_CFG: RF control register */ 458/* */ 459typedef union _RF_CSR_CFG0_STRUC { 460 struct { 461 u32 RegIdAndContent:24; /* Register value to program into BBP */ 462 u32 bitwidth:5; /* Selected BBP register */ 463 u32 StandbyMode:1; /* 0: high when stand by 1: low when standby */ 464 u32 Sel:1; /* 0:RF_LE0 activate 1:RF_LE1 activate */ 465 u32 Busy:1; /* 0: idle 1: 8busy */ 466 } field; 467 u32 word; 468} RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC; 469#define RF_CSR_CFG1 0x1024 470typedef union _RF_CSR_CFG1_STRUC { 471 struct { 472 u32 RegIdAndContent:24; /* Register value to program into BBP */ 473 u32 RFGap:5; /* Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec) */ 474 u32 rsv:7; /* 0: idle 1: 8busy */ 475 } field; 476 u32 word; 477} RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC; 478#define RF_CSR_CFG2 0x1028 /* */ 479typedef union _RF_CSR_CFG2_STRUC { 480 struct { 481 u32 RegIdAndContent:24; /* Register value to program into BBP */ 482 u32 rsv:8; /* 0: idle 1: 8busy */ 483 } field; 484 u32 word; 485} RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC; 486#define LED_CFG 0x102c /* MAC_CSR14 */ 487typedef union _LED_CFG_STRUC { 488 struct { 489 u32 OnPeriod:8; /* blinking on period unit 1ms */ 490 u32 OffPeriod:8; /* blinking off period unit 1ms */ 491 u32 SlowBlinkPeriod:6; /* slow blinking period. unit:1ms */ 492 u32 rsv:2; 493 u32 RLedMode:2; /* red Led Mode 0: off1: blinking upon TX2: periodic slow blinking3: always on */ 494 u32 GLedMode:2; /* green Led Mode */ 495 u32 YLedMode:2; /* yellow Led Mode */ 496 u32 LedPolar:1; /* Led Polarity. 0: active low1: active high */ 497 u32: 1; 498 } field; 499 u32 word; 500} LED_CFG_STRUC, *PLED_CFG_STRUC; 501/* */ 502/* 4.2 MAC TIMING configuration registers (offset:0x1100) */ 503/* */ 504#define XIFS_TIME_CFG 0x1100 /* MAC_CSR8 MAC_CSR9 */ 505typedef union _IFS_SLOT_CFG_STRUC { 506 struct { 507 u32 CckmSifsTime:8; /* unit 1us. Applied after CCK RX/TX */ 508 u32 OfdmSifsTime:8; /* unit 1us. Applied after OFDM RX/TX */ 509 u32 OfdmXifsTime:4; /*OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND */ 510 u32 EIFS:9; /* unit 1us */ 511 u32 BBRxendEnable:1; /* reference RXEND signal to begin XIFS defer */ 512 u32 rsv:2; 513 } field; 514 u32 word; 515} IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC; 516 517#define BKOFF_SLOT_CFG 0x1104 /* mac_csr9 last 8 bits */ 518#define NAV_TIME_CFG 0x1108 /* NAV (MAC_CSR15) */ 519#define CH_TIME_CFG 0x110C /* Count as channel busy */ 520#define PBF_LIFE_TIMER 0x1110 /*TX/RX MPDU timestamp timer (free run)Unit: 1us */ 521#define BCN_TIME_CFG 0x1114 /* TXRX_CSR9 */ 522 523#define BCN_OFFSET0 0x042C 524#define BCN_OFFSET1 0x0430 525 526/* */ 527/* BCN_TIME_CFG : Synchronization control register */ 528/* */ 529typedef union _BCN_TIME_CFG_STRUC { 530 struct { 531 u32 BeaconInterval:16; /* in unit of 1/16 TU */ 532 u32 bTsfTicking:1; /* Enable TSF auto counting */ 533 u32 TsfSyncMode:2; /* Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode */ 534 u32 bTBTTEnable:1; 535 u32 bBeaconGen:1; /* Enable beacon generator */ 536 u32: 3; 537 u32 TxTimestampCompensate:8; 538 } field; 539 u32 word; 540} BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC; 541#define TBTT_SYNC_CFG 0x1118 /* txrx_csr10 */ 542#define TSF_TIMER_DW0 0x111C /* Local TSF timer lsb 32 bits. Read-only */ 543#define TSF_TIMER_DW1 0x1120 /* msb 32 bits. Read-only. */ 544#define TBTT_TIMER 0x1124 /* TImer remains till next TBTT. Read-only. TXRX_CSR14 */ 545#define INT_TIMER_CFG 0x1128 /* */ 546#define INT_TIMER_EN 0x112c /* GP-timer and pre-tbtt Int enable */ 547#define CH_IDLE_STA 0x1130 /* channel idle time */ 548#define CH_BUSY_STA 0x1134 /* channle busy time */ 549/* */ 550/* 4.2 MAC POWER configuration registers (offset:0x1200) */ 551/* */ 552#define MAC_STATUS_CFG 0x1200 /* old MAC_CSR12 */ 553#define PWR_PIN_CFG 0x1204 /* old MAC_CSR12 */ 554#define AUTO_WAKEUP_CFG 0x1208 /* old MAC_CSR10 */ 555/* */ 556/* AUTO_WAKEUP_CFG: Manual power control / status register */ 557/* */ 558typedef union _AUTO_WAKEUP_STRUC { 559 struct { 560 u32 AutoLeadTime:8; 561 u32 NumofSleepingTbtt:7; /* ForceWake has high privilege than PutToSleep when both set */ 562 u32 EnableAutoWakeup:1; /* 0:sleep, 1:awake */ 563 u32: 16; 564 } field; 565 u32 word; 566} AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC; 567/* */ 568/* 4.3 MAC TX configuration registers (offset:0x1300) */ 569/* */ 570 571#define EDCA_AC0_CFG 0x1300 /*AC_TXOP_CSR0 0x3474 */ 572#define EDCA_AC1_CFG 0x1304 573#define EDCA_AC2_CFG 0x1308 574#define EDCA_AC3_CFG 0x130c 575typedef union _EDCA_AC_CFG_STRUC { 576 struct { 577 u32 AcTxop:8; /* in unit of 32us */ 578 u32 Aifsn:4; /* # of slot time */ 579 u32 Cwmin:4; /* */ 580 u32 Cwmax:4; /*unit power of 2 */ 581 u32: 12; /* */ 582 } field; 583 u32 word; 584} EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC; 585 586#define EDCA_TID_AC_MAP 0x1310 587#define TX_PWR_CFG_0 0x1314 588#define TX_PWR_CFG_1 0x1318 589#define TX_PWR_CFG_2 0x131C 590#define TX_PWR_CFG_3 0x1320 591#define TX_PWR_CFG_4 0x1324 592#define TX_PIN_CFG 0x1328 593#define TX_BAND_CFG 0x132c /* 0x1 use upper 20MHz. 0 juse lower 20MHz */ 594#define TX_SW_CFG0 0x1330 595#define TX_SW_CFG1 0x1334 596#define TX_SW_CFG2 0x1338 597#define TXOP_THRES_CFG 0x133c 598#define TXOP_CTRL_CFG 0x1340 599#define TX_RTS_CFG 0x1344 600 601typedef union _TX_RTS_CFG_STRUC { 602 struct { 603 u32 AutoRtsRetryLimit:8; 604 u32 RtsThres:16; /* unit:byte */ 605 u32 RtsFbkEn:1; /* enable rts rate fallback */ 606 u32 rsv:7; /* 1: HT non-STBC control frame enable */ 607 } field; 608 u32 word; 609} TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC; 610#define TX_TIMEOUT_CFG 0x1348 611typedef union _TX_TIMEOUT_CFG_STRUC { 612 struct { 613 u32 rsv:4; 614 u32 MpduLifeTime:4; /* expiration time = 2^(9+MPDU LIFE TIME) us */ 615 u32 RxAckTimeout:8; /* unit:slot. Used for TX precedure */ 616 u32 TxopTimeout:8; /*TXOP timeout value for TXOP truncation. It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT) */ 617 u32 rsv2:8; /* 1: HT non-STBC control frame enable */ 618 } field; 619 u32 word; 620} TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC; 621#define TX_RTY_CFG 0x134c 622typedef union PACKED _TX_RTY_CFG_STRUC { 623 struct { 624 u32 ShortRtyLimit:8; /* short retry limit */ 625 u32 LongRtyLimit:8; /*long retry limit */ 626 u32 LongRtyThre:12; /* Long retry threshoold */ 627 u32 NonAggRtyMode:1; /* Non-Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer */ 628 u32 AggRtyMode:1; /* Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer */ 629 u32 TxautoFBEnable:1; /* Tx retry PHY rate auto fallback enable */ 630 u32 rsv:1; /* 1: HT non-STBC control frame enable */ 631 } field; 632 u32 word; 633} TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC; 634#define TX_LINK_CFG 0x1350 635typedef union PACKED _TX_LINK_CFG_STRUC { 636 struct PACKED { 637 u32 RemoteMFBLifeTime:8; /*remote MFB life time. unit : 32us */ 638 u32 MFBEnable:1; /* TX apply remote MFB 1:enable */ 639 u32 RemoteUMFSEnable:1; /* remote unsolicit MFB enable. 0: not apply remote remote unsolicit (MFS=7) */ 640 u32 TxMRQEn:1; /* MCS request TX enable */ 641 u32 TxRDGEn:1; /* RDG TX enable */ 642 u32 TxCFAckEn:1; /* Piggyback CF-ACK enable */ 643 u32 rsv:3; /* */ 644 u32 RemotMFB:8; /* remote MCS feedback */ 645 u32 RemotMFS:8; /*remote MCS feedback sequence number */ 646 } field; 647 u32 word; 648} TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC; 649#define HT_FBK_CFG0 0x1354 650typedef union PACKED _HT_FBK_CFG0_STRUC { 651 struct { 652 u32 HTMCS0FBK:4; 653 u32 HTMCS1FBK:4; 654 u32 HTMCS2FBK:4; 655 u32 HTMCS3FBK:4; 656 u32 HTMCS4FBK:4; 657 u32 HTMCS5FBK:4; 658 u32 HTMCS6FBK:4; 659 u32 HTMCS7FBK:4; 660 } field; 661 u32 word; 662} HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC; 663#define HT_FBK_CFG1 0x1358 664typedef union _HT_FBK_CFG1_STRUC { 665 struct { 666 u32 HTMCS8FBK:4; 667 u32 HTMCS9FBK:4; 668 u32 HTMCS10FBK:4; 669 u32 HTMCS11FBK:4; 670 u32 HTMCS12FBK:4; 671 u32 HTMCS13FBK:4; 672 u32 HTMCS14FBK:4; 673 u32 HTMCS15FBK:4; 674 } field; 675 u32 word; 676} HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC; 677#define LG_FBK_CFG0 0x135c 678typedef union _LG_FBK_CFG0_STRUC { 679 struct { 680 u32 OFDMMCS0FBK:4; /*initial value is 0 */ 681 u32 OFDMMCS1FBK:4; /*initial value is 0 */ 682 u32 OFDMMCS2FBK:4; /*initial value is 1 */ 683 u32 OFDMMCS3FBK:4; /*initial value is 2 */ 684 u32 OFDMMCS4FBK:4; /*initial value is 3 */ 685 u32 OFDMMCS5FBK:4; /*initial value is 4 */ 686 u32 OFDMMCS6FBK:4; /*initial value is 5 */ 687 u32 OFDMMCS7FBK:4; /*initial value is 6 */ 688 } field; 689 u32 word; 690} LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC; 691#define LG_FBK_CFG1 0x1360 692typedef union _LG_FBK_CFG1_STRUC { 693 struct { 694 u32 CCKMCS0FBK:4; /*initial value is 0 */ 695 u32 CCKMCS1FBK:4; /*initial value is 0 */ 696 u32 CCKMCS2FBK:4; /*initial value is 1 */ 697 u32 CCKMCS3FBK:4; /*initial value is 2 */ 698 u32 rsv:16; 699 } field; 700 u32 word; 701} LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC; 702 703/*======================================================= */ 704/*================ Protection Paramater================================ */ 705/*======================================================= */ 706#define CCK_PROT_CFG 0x1364 /*CCK Protection */ 707#define ASIC_SHORTNAV 1 708#define ASIC_longNAV 2 709#define ASIC_RTS 1 710#define ASIC_CTS 2 711typedef union _PROT_CFG_STRUC { 712 struct { 713 u32 ProtectRate:16; /*Protection control frame rate for CCK TX(RTS/CTS/CFEnd). */ 714 u32 ProtectCtrl:2; /*Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv */ 715 u32 ProtectNav:2; /*TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect, 2:LongNAVProtect, 3:rsv */ 716 u32 TxopAllowCck:1; /*CCK TXOP allowance.0:disallow. */ 717 u32 TxopAllowOfdm:1; /*CCK TXOP allowance.0:disallow. */ 718 u32 TxopAllowMM20:1; /*CCK TXOP allowance. 0:disallow. */ 719 u32 TxopAllowMM40:1; /*CCK TXOP allowance.0:disallow. */ 720 u32 TxopAllowGF20:1; /*CCK TXOP allowance.0:disallow. */ 721 u32 TxopAllowGF40:1; /*CCK TXOP allowance.0:disallow. */ 722 u32 RTSThEn:1; /*RTS threshold enable on CCK TX */ 723 u32 rsv:5; 724 } field; 725 u32 word; 726} PROT_CFG_STRUC, *PPROT_CFG_STRUC; 727 728#define OFDM_PROT_CFG 0x1368 /*OFDM Protection */ 729#define MM20_PROT_CFG 0x136C /*MM20 Protection */ 730#define MM40_PROT_CFG 0x1370 /*MM40 Protection */ 731#define GF20_PROT_CFG 0x1374 /*GF20 Protection */ 732#define GF40_PROT_CFG 0x1378 /*GR40 Protection */ 733#define EXP_CTS_TIME 0x137C /* */ 734#define EXP_ACK_TIME 0x1380 /* */ 735 736/* */ 737/* 4.4 MAC RX configuration registers (offset:0x1400) */ 738/* */ 739#define RX_FILTR_CFG 0x1400 /*TXRX_CSR0 */ 740#define AUTO_RSP_CFG 0x1404 /*TXRX_CSR4 */ 741/* */ 742/* TXRX_CSR4: Auto-Responder/ */ 743/* */ 744typedef union _AUTO_RSP_CFG_STRUC { 745 struct { 746 u32 AutoResponderEnable:1; 747 u32 BACAckPolicyEnable:1; /* 0:long, 1:short preamble */ 748 u32 CTS40MMode:1; /* Response CTS 40MHz duplicate mode */ 749 u32 CTS40MRef:1; /* Response CTS 40MHz duplicate mode */ 750 u32 AutoResponderPreamble:1; /* 0:long, 1:short preamble */ 751 u32 rsv:1; /* Power bit value in conrtrol frame */ 752 u32 DualCTSEn:1; /* Power bit value in conrtrol frame */ 753 u32 AckCtsPsmBit:1; /* Power bit value in conrtrol frame */ 754 u32: 24; 755 } field; 756 u32 word; 757} AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC; 758 759#define LEGACY_BASIC_RATE 0x1408 /* TXRX_CSR5 0x3054 */ 760#define HT_BASIC_RATE 0x140c 761#define HT_CTRL_CFG 0x1410 762#define SIFS_COST_CFG 0x1414 763#define RX_PARSER_CFG 0x1418 /*Set NAV for all received frames */ 764 765/* */ 766/* 4.5 MAC Security configuration (offset:0x1500) */ 767/* */ 768#define TX_SEC_CNT0 0x1500 /* */ 769#define RX_SEC_CNT0 0x1504 /* */ 770#define CCMP_FC_MUTE 0x1508 /* */ 771/* */ 772/* 4.6 HCCA/PSMP (offset:0x1600) */ 773/* */ 774#define TXOP_HLDR_ADDR0 0x1600 775#define TXOP_HLDR_ADDR1 0x1604 776#define TXOP_HLDR_ET 0x1608 777#define QOS_CFPOLL_RA_DW0 0x160c 778#define QOS_CFPOLL_A1_DW1 0x1610 779#define QOS_CFPOLL_QC 0x1614 780/* */ 781/* 4.7 MAC Statistis registers (offset:0x1700) */ 782/* */ 783#define RX_STA_CNT0 0x1700 /* */ 784#define RX_STA_CNT1 0x1704 /* */ 785#define RX_STA_CNT2 0x1708 /* */ 786 787/* */ 788/* RX_STA_CNT0_STRUC: RX PLCP error count & RX CRC error count */ 789/* */ 790typedef union _RX_STA_CNT0_STRUC { 791 struct { 792 u16 CrcErr; 793 u16 PhyErr; 794 } field; 795 u32 word; 796} RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC; 797 798/* */ 799/* RX_STA_CNT1_STRUC: RX False CCA count & RX long frame count */ 800/* */ 801typedef union _RX_STA_CNT1_STRUC { 802 struct { 803 u16 FalseCca; 804 u16 PlcpErr; 805 } field; 806 u32 word; 807} RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC; 808 809/* */ 810/* RX_STA_CNT2_STRUC: */ 811/* */ 812typedef union _RX_STA_CNT2_STRUC { 813 struct { 814 u16 RxDupliCount; 815 u16 RxFifoOverflowCount; 816 } field; 817 u32 word; 818} RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC; 819#define TX_STA_CNT0 0x170C /* */ 820/* */ 821/* STA_CSR3: TX Beacon count */ 822/* */ 823typedef union _TX_STA_CNT0_STRUC { 824 struct { 825 u16 TxFailCount; 826 u16 TxBeaconCount; 827 } field; 828 u32 word; 829} TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC; 830#define TX_STA_CNT1 0x1710 /* */ 831/* */ 832/* TX_STA_CNT1: TX tx count */ 833/* */ 834typedef union _TX_STA_CNT1_STRUC { 835 struct { 836 u16 TxSuccess; 837 u16 TxRetransmit; 838 } field; 839 u32 word; 840} TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC; 841#define TX_STA_CNT2 0x1714 /* */ 842/* */ 843/* TX_STA_CNT2: TX tx count */ 844/* */ 845typedef union _TX_STA_CNT2_STRUC { 846 struct { 847 u16 TxZeroLenCount; 848 u16 TxUnderFlowCount; 849 } field; 850 u32 word; 851} TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC; 852#define TX_STA_FIFO 0x1718 /* */ 853/* */ 854/* TX_STA_FIFO_STRUC: TX Result for specific PID status fifo register */ 855/* */ 856typedef union PACKED _TX_STA_FIFO_STRUC { 857 struct { 858 u32 bValid:1; /* 1:This register contains a valid TX result */ 859 u32 PidType:4; 860 u32 TxSuccess:1; /* Tx No retry success */ 861 u32 TxAggre:1; /* Tx Retry Success */ 862 u32 TxAckRequired:1; /* Tx fail */ 863 u32 wcid:8; /*wireless client index */ 864/* u32 SuccessRate:16; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16. */ 865 u32 SuccessRate:13; /*include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16. */ 866 u32 TxBF:1; 867 u32 Reserve:2; 868 } field; 869 u32 word; 870} TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC; 871/* Debug counter */ 872#define TX_AGG_CNT 0x171c 873typedef union _TX_AGG_CNT_STRUC { 874 struct { 875 u16 NonAggTxCount; 876 u16 AggTxCount; 877 } field; 878 u32 word; 879} TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC; 880/* Debug counter */ 881#define TX_AGG_CNT0 0x1720 882typedef union _TX_AGG_CNT0_STRUC { 883 struct { 884 u16 AggSize1Count; 885 u16 AggSize2Count; 886 } field; 887 u32 word; 888} TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC; 889/* Debug counter */ 890#define TX_AGG_CNT1 0x1724 891typedef union _TX_AGG_CNT1_STRUC { 892 struct { 893 u16 AggSize3Count; 894 u16 AggSize4Count; 895 } field; 896 u32 word; 897} TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC; 898#define TX_AGG_CNT2 0x1728 899typedef union _TX_AGG_CNT2_STRUC { 900 struct { 901 u16 AggSize5Count; 902 u16 AggSize6Count; 903 } field; 904 u32 word; 905} TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC; 906/* Debug counter */ 907#define TX_AGG_CNT3 0x172c 908typedef union _TX_AGG_CNT3_STRUC { 909 struct { 910 u16 AggSize7Count; 911 u16 AggSize8Count; 912 } field; 913 u32 word; 914} TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC; 915/* Debug counter */ 916#define TX_AGG_CNT4 0x1730 917typedef union _TX_AGG_CNT4_STRUC { 918 struct { 919 u16 AggSize9Count; 920 u16 AggSize10Count; 921 } field; 922 u32 word; 923} TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC; 924#define TX_AGG_CNT5 0x1734 925typedef union _TX_AGG_CNT5_STRUC { 926 struct { 927 u16 AggSize11Count; 928 u16 AggSize12Count; 929 } field; 930 u32 word; 931} TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC; 932#define TX_AGG_CNT6 0x1738 933typedef union _TX_AGG_CNT6_STRUC { 934 struct { 935 u16 AggSize13Count; 936 u16 AggSize14Count; 937 } field; 938 u32 word; 939} TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC; 940#define TX_AGG_CNT7 0x173c 941typedef union _TX_AGG_CNT7_STRUC { 942 struct { 943 u16 AggSize15Count; 944 u16 AggSize16Count; 945 } field; 946 u32 word; 947} TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC; 948#define MPDU_DENSITY_CNT 0x1740 949typedef union _MPDU_DEN_CNT_STRUC { 950 struct { 951 u16 TXZeroDelCount; /*TX zero length delimiter count */ 952 u16 RXZeroDelCount; /*RX zero length delimiter count */ 953 } field; 954 u32 word; 955} MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC; 956/* */ 957/* TXRX control registers - base address 0x3000 */ 958/* */ 959/* rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first.. */ 960#define TXRX_CSR1 0x77d0 961 962/* */ 963/* Security key table memory, base address = 0x1000 */ 964/* */ 965#define MAC_WCID_BASE 0x1800 /*8-bytes(use only 6-bytes) * 256 entry = */ 966#define HW_WCID_ENTRY_SIZE 8 967#define PAIRWISE_KEY_TABLE_BASE 0x4000 /* 32-byte * 256-entry = -byte */ 968#define HW_KEY_ENTRY_SIZE 0x20 969#define PAIRWISE_IVEIV_TABLE_BASE 0x6000 /* 8-byte * 256-entry = -byte */ 970#define MAC_IVEIV_TABLE_BASE 0x6000 /* 8-byte * 256-entry = -byte */ 971#define HW_IVEIV_ENTRY_SIZE 8 972#define MAC_WCID_ATTRIBUTE_BASE 0x6800 /* 4-byte * 256-entry = -byte */ 973#define HW_WCID_ATTRI_SIZE 4 974#define WCID_RESERVED 0x6bfc 975#define SHARED_KEY_TABLE_BASE 0x6c00 /* 32-byte * 16-entry = 512-byte */ 976#define SHARED_KEY_MODE_BASE 0x7000 /* 32-byte * 16-entry = 512-byte */ 977#define HW_SHARED_KEY_MODE_SIZE 4 978#define SHAREDKEYTABLE 0 979#define PAIRWISEKEYTABLE 1 980 981typedef union _SHAREDKEY_MODE_STRUC { 982 struct { 983 u32 Bss0Key0CipherAlg:3; 984 u32: 1; 985 u32 Bss0Key1CipherAlg:3; 986 u32: 1; 987 u32 Bss0Key2CipherAlg:3; 988 u32: 1; 989 u32 Bss0Key3CipherAlg:3; 990 u32: 1; 991 u32 Bss1Key0CipherAlg:3; 992 u32: 1; 993 u32 Bss1Key1CipherAlg:3; 994 u32: 1; 995 u32 Bss1Key2CipherAlg:3; 996 u32: 1; 997 u32 Bss1Key3CipherAlg:3; 998 u32: 1; 999 } field; 1000 u32 word; 1001} SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC; 1002 1003/* 8-byte per entry, 64-entry for pairwise key table */ 1004struct rt_hw_wcid_entry { 1005 u8 Address[6]; 1006 u8 Rsv[2]; 1007}; 1008 1009/* ================================================================================= */ 1010/* WCID format */ 1011/* ================================================================================= */ 1012/*7.1 WCID ENTRY format : 8bytes */ 1013struct rt_wcid_entry { 1014 u8 RXBABitmap7; /* bit0 for TID8, bit7 for TID 15 */ 1015 u8 RXBABitmap0; /* bit0 for TID0, bit7 for TID 7 */ 1016 u8 MAC[6]; /* 0 for shared key table. 1 for pairwise key table */ 1017}; 1018 1019/*8.1.1 SECURITY KEY format : 8DW */ 1020/* 32-byte per entry, total 16-entry for shared key table, 64-entry for pairwise key table */ 1021struct rt_hw_key_entry { 1022 u8 Key[16]; 1023 u8 TxMic[8]; 1024 u8 RxMic[8]; 1025}; 1026 1027/*8.1.2 IV/EIV format : 2DW */ 1028 1029/*8.1.3 RX attribute entry format : 1DW */ 1030struct rt_mac_attribute { 1031 u32 KeyTab:1; /* 0 for shared key table. 1 for pairwise key table */ 1032 u32 PairKeyMode:3; 1033 u32 BSSIDIdx:3; /*multipleBSS index for the WCID */ 1034 u32 RXWIUDF:3; 1035 u32 rsv:22; 1036}; 1037 1038/* ================================================================================= */ 1039/* HOST-MCU communication data structure */ 1040/* ================================================================================= */ 1041 1042/* */ 1043/* H2M_MAILBOX_CSR: Host-to-MCU Mailbox */ 1044/* */ 1045typedef union _H2M_MAILBOX_STRUC { 1046 struct { 1047 u32 LowByte:8; 1048 u32 HighByte:8; 1049 u32 CmdToken:8; 1050 u32 Owner:8; 1051 } field; 1052 u32 word; 1053} H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC; 1054 1055/* */ 1056/* M2H_CMD_DONE_CSR: MCU-to-Host command complete indication */ 1057/* */ 1058typedef union _M2H_CMD_DONE_STRUC { 1059 struct { 1060 u32 CmdToken0; 1061 u32 CmdToken1; 1062 u32 CmdToken2; 1063 u32 CmdToken3; 1064 } field; 1065 u32 word; 1066} M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC; 1067 1068/*NAV_TIME_CFG :NAV */ 1069typedef union _NAV_TIME_CFG_STRUC { 1070 struct { 1071 u8 Sifs; /* in unit of 1-us */ 1072 u8 SlotTime; /* in unit of 1-us */ 1073 u16 Eifs:9; /* in unit of 1-us */ 1074 u16 ZeroSifs:1; /* Applied zero SIFS timer after OFDM RX 0: disable */ 1075 u16 rsv:6; 1076 } field; 1077 u32 word; 1078} NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC; 1079 1080/* */ 1081/* RX_FILTR_CFG: /RX configuration register */ 1082/* */ 1083typedef union _RX_FILTR_CFG_STRUC { 1084 struct { 1085 u32 DropCRCErr:1; /* Drop CRC error */ 1086 u32 DropPhyErr:1; /* Drop physical error */ 1087 u32 DropNotToMe:1; /* Drop not to me unicast frame */ 1088 u32 DropNotMyBSSID:1; /* Drop fram ToDs bit is true */ 1089 1090 u32 DropVerErr:1; /* Drop version error frame */ 1091 u32 DropMcast:1; /* Drop multicast frames */ 1092 u32 DropBcast:1; /* Drop broadcast frames */ 1093 u32 DropDuplicate:1; /* Drop duplicate frame */ 1094 1095 u32 DropCFEndAck:1; /* Drop Ps-Poll */ 1096 u32 DropCFEnd:1; /* Drop Ps-Poll */ 1097 u32 DropAck:1; /* Drop Ps-Poll */ 1098 u32 DropCts:1; /* Drop Ps-Poll */ 1099 1100 u32 DropRts:1; /* Drop Ps-Poll */ 1101 u32 DropPsPoll:1; /* Drop Ps-Poll */ 1102 u32 DropBA:1; /* */ 1103 u32 DropBAR:1; /* */ 1104 1105 u32 DropRsvCntlType:1; 1106 u32: 15; 1107 } field; 1108 u32 word; 1109} RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC; 1110 1111/* */ 1112/* PHY_CSR4: RF serial control register */ 1113/* */ 1114typedef union _PHY_CSR4_STRUC { 1115 struct { 1116 u32 RFRegValue:24; /* Register value (include register id) serial out to RF/IF chip. */ 1117 u32 NumberOfBits:5; /* Number of bits used in RFRegValue (I:20, RFMD:22) */ 1118 u32 IFSelect:1; /* 1: select IF to program, 0: select RF to program */ 1119 u32 PLL_LD:1; /* RF PLL_LD status */ 1120 u32 Busy:1; /* 1: ASIC is busy execute RF programming. */ 1121 } field; 1122 u32 word; 1123} PHY_CSR4_STRUC, *PPHY_CSR4_STRUC; 1124 1125/* */ 1126/* SEC_CSR5: shared key table security mode register */ 1127/* */ 1128typedef union _SEC_CSR5_STRUC { 1129 struct { 1130 u32 Bss2Key0CipherAlg:3; 1131 u32: 1; 1132 u32 Bss2Key1CipherAlg:3; 1133 u32: 1; 1134 u32 Bss2Key2CipherAlg:3; 1135 u32: 1; 1136 u32 Bss2Key3CipherAlg:3; 1137 u32: 1; 1138 u32 Bss3Key0CipherAlg:3; 1139 u32: 1; 1140 u32 Bss3Key1CipherAlg:3; 1141 u32: 1; 1142 u32 Bss3Key2CipherAlg:3; 1143 u32: 1; 1144 u32 Bss3Key3CipherAlg:3; 1145 u32: 1; 1146 } field; 1147 u32 word; 1148} SEC_CSR5_STRUC, *PSEC_CSR5_STRUC; 1149 1150/* */ 1151/* HOST_CMD_CSR: For HOST to interrupt embedded processor */ 1152/* */ 1153typedef union _HOST_CMD_CSR_STRUC { 1154 struct { 1155 u32 HostCommand:8; 1156 u32 Rsv:24; 1157 } field; 1158 u32 word; 1159} HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC; 1160 1161/* */ 1162/* AIFSN_CSR: AIFSN for each EDCA AC */ 1163/* */ 1164 1165/* */ 1166/* E2PROM_CSR: EEPROM control register */ 1167/* */ 1168typedef union _E2PROM_CSR_STRUC { 1169 struct { 1170 u32 Reload:1; /* Reload EEPROM content, write one to reload, self-cleared. */ 1171 u32 EepromSK:1; 1172 u32 EepromCS:1; 1173 u32 EepromDI:1; 1174 u32 EepromDO:1; 1175 u32 Type:1; /* 1: 93C46, 0:93C66 */ 1176 u32 LoadStatus:1; /* 1:loading, 0:done */ 1177 u32 Rsvd:25; 1178 } field; 1179 u32 word; 1180} E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC; 1181 1182/* */ 1183/* QOS_CSR0: TXOP holder address0 register */ 1184/* */ 1185typedef union _QOS_CSR0_STRUC { 1186 struct { 1187 u8 Byte0; /* MAC address byte 0 */ 1188 u8 Byte1; /* MAC address byte 1 */ 1189 u8 Byte2; /* MAC address byte 2 */ 1190 u8 Byte3; /* MAC address byte 3 */ 1191 } field; 1192 u32 word; 1193} QOS_CSR0_STRUC, *PQOS_CSR0_STRUC; 1194 1195/* */ 1196/* QOS_CSR1: TXOP holder address1 register */ 1197/* */ 1198typedef union _QOS_CSR1_STRUC { 1199 struct { 1200 u8 Byte4; /* MAC address byte 4 */ 1201 u8 Byte5; /* MAC address byte 5 */ 1202 u8 Rsvd0; 1203 u8 Rsvd1; 1204 } field; 1205 u32 word; 1206} QOS_CSR1_STRUC, *PQOS_CSR1_STRUC; 1207 1208#define RF_CSR_CFG 0x500 1209typedef union _RF_CSR_CFG_STRUC { 1210 struct { 1211 u32 RF_CSR_DATA:8; /* DATA */ 1212 u32 TESTCSR_RFACC_REGNUM:5; /* RF register ID */ 1213 u32 Rsvd2:3; /* Reserved */ 1214 u32 RF_CSR_WR:1; /* 0: read 1: write */ 1215 u32 RF_CSR_KICK:1; /* kick RF register read/write */ 1216 u32 Rsvd1:14; /* Reserved */ 1217 } field; 1218 u32 word; 1219} RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC; 1220 1221/* */ 1222/* Other on-chip shared memory space, base = 0x2000 */ 1223/* */ 1224 1225/* CIS space - base address = 0x2000 */ 1226#define HW_CIS_BASE 0x2000 1227 1228/* Carrier-sense CTS frame base address. It's where mac stores carrier-sense frame for carrier-sense function. */ 1229#define HW_CS_CTS_BASE 0x7700 1230/* DFS CTS frame base address. It's where mac stores CTS frame for DFS. */ 1231#define HW_DFS_CTS_BASE 0x7780 1232#define HW_CTS_FRAME_SIZE 0x80 1233 1234/* 2004-11-08 john - since NULL frame won't be that long (256 byte). We steal 16 tail bytes */ 1235/* to save debugging settings */ 1236#define HW_DEBUG_SETTING_BASE 0x77f0 /* 0x77f0~0x77ff total 16 bytes */ 1237#define HW_DEBUG_SETTING_BASE2 0x7770 /* 0x77f0~0x77ff total 16 bytes */ 1238 1239/* In order to support maximum 8 MBSS and its maximum length is 512 for each beacon */ 1240/* Three section discontinue memory segments will be used. */ 1241/* 1. The original region for BCN 0~3 */ 1242/* 2. Extract memory from FCE table for BCN 4~5 */ 1243/* 3. Extract memory from Pair-wise key table for BCN 6~7 */ 1244/* It occupied those memory of wcid 238~253 for BCN 6 */ 1245/* and wcid 222~237 for BCN 7 */ 1246#define HW_BEACON_MAX_SIZE 0x1000 /* unit: byte */ 1247#define HW_BEACON_BASE0 0x7800 1248#define HW_BEACON_BASE1 0x7A00 1249#define HW_BEACON_BASE2 0x7C00 1250#define HW_BEACON_BASE3 0x7E00 1251#define HW_BEACON_BASE4 0x7200 1252#define HW_BEACON_BASE5 0x7400 1253#define HW_BEACON_BASE6 0x5DC0 1254#define HW_BEACON_BASE7 0x5BC0 1255 1256#define HW_BEACON_MAX_COUNT 8 1257#define HW_BEACON_OFFSET 0x0200 1258#define HW_BEACON_CONTENT_LEN (HW_BEACON_OFFSET - TXWI_SIZE) 1259 1260/* HOST-MCU shared memory - base address = 0x2100 */ 1261#define HOST_CMD_CSR 0x404 1262#define H2M_MAILBOX_CSR 0x7010 1263#define H2M_MAILBOX_CID 0x7014 1264#define H2M_MAILBOX_STATUS 0x701c 1265#define H2M_INT_SRC 0x7024 1266#define H2M_BBP_AGENT 0x7028 1267#define M2H_CMD_DONE_CSR 0x000c 1268#define MCU_TXOP_ARRAY_BASE 0x000c /* TODO: to be provided by Albert */ 1269#define MCU_TXOP_ENTRY_SIZE 32 /* TODO: to be provided by Albert */ 1270#define MAX_NUM_OF_TXOP_ENTRY 16 /* TODO: must be same with 8051 firmware */ 1271#define MCU_MBOX_VERSION 0x01 /* TODO: to be confirmed by Albert */ 1272#define MCU_MBOX_VERSION_OFFSET 5 /* TODO: to be provided by Albert */ 1273 1274/* */ 1275/* Host DMA registers - base address 0x200 . TX0-3=EDCAQid0-3, TX4=HCCA, TX5=MGMT, */ 1276/* */ 1277/* */ 1278/* DMA RING DESCRIPTOR */ 1279/* */ 1280#define E2PROM_CSR 0x0004 1281#define IO_CNTL_CSR 0x77d0 1282 1283/* ================================================================ */ 1284/* Tx / Rx / Mgmt ring descriptor definition */ 1285/* ================================================================ */ 1286 1287/* the following PID values are used to mark outgoing frame type in TXD->PID so that */ 1288/* proper TX statistics can be collected based on these categories */ 1289/* b3-2 of PID field - */ 1290#define PID_MGMT 0x05 1291#define PID_BEACON 0x0c 1292#define PID_DATA_NORMALUCAST 0x02 1293#define PID_DATA_AMPDU 0x04 1294#define PID_DATA_NO_ACK 0x08 1295#define PID_DATA_NOT_NORM_ACK 0x03 1296/* value domain of pTxD->HostQId (4-bit: 0~15) */ 1297#define QID_AC_BK 1 /* meet ACI definition in 802.11e */ 1298#define QID_AC_BE 0 /* meet ACI definition in 802.11e */ 1299#define QID_AC_VI 2 1300#define QID_AC_VO 3 1301#define QID_HCCA 4 1302#define NUM_OF_TX_RING 4 1303#define QID_MGMT 13 1304#define QID_RX 14 1305#define QID_OTHER 15 1306 1307#endif /* __RTMP_MAC_H__ // */ 1308