1/* 2 * Copyright (c) 2000-2005 ZyDAS Technology Corporation 3 * Copyright (c) 2007-2008 Atheros Communications Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17/* Module Name : ud_defs.h */ 18/* */ 19/* Abstract */ 20/* This module contains USB data structure definitions. */ 21/* */ 22/* NOTES */ 23/* None */ 24/* */ 25/************************************************************************/ 26 27#ifndef _HPUSB_H 28#define _HPUSB_H 29 30#define ZM_OTUS_ENABLE_RETRY_FREQ_CHANGE 31#define ZM_BEACON_BUFFER_ADDRESS 0x117900 32 33#define ZM_MAX_CMD_SIZE 64 34#define ZM_HAL_MAX_EEPROM_REQ 510 35#define ZM_HAL_MAX_EEPROM_PRQ 2 36 37/* For USB STREAM mode */ 38#ifdef ZM_DISABLE_AMSDU8K_SUPPORT 39#define ZM_MAX_USB_IN_TRANSFER_SIZE 4096 40#else 41#define ZM_MAX_USB_IN_TRANSFER_SIZE 8192 42#endif 43#define ZM_USB_STREAM_MODE_TAG_LEN 4 44#define ZM_USB_STREAM_MODE_TAG 0x4e00 45#define ZM_USB_MAX_EPINT_BUFFER 64 46 47struct zsCmdQ 48{ 49 u16_t src; 50 u16_t cmdLen; 51 u8_t* buf; 52 u32_t cmd[ZM_MAX_CMD_SIZE/4]; 53}; 54 55struct zsCommand 56{ 57 u16_t delayWcmdCount; 58 u32_t delayWcmdAddr[(ZM_CMD_QUEUE_SIZE-4)/4]; 59 u32_t delayWcmdVal[(ZM_CMD_QUEUE_SIZE-4)/4]; 60}; 61 62struct zsHalRxInfo 63{ 64 u32_t currentRSSI[7]; /* RSSI combined */ 65 u32_t currentRxEVM[14]; 66 u32_t currentRxDataMT; 67 u32_t currentRxDataMCS; 68 u32_t currentRxDataBW; 69 u32_t currentRxDataSG; 70}; 71 72struct zsHpPriv 73{ 74 u16_t hwFrequency; 75 u8_t hwBw40; 76 u8_t hwExtOffset; 77 78 u8_t disableDfsCh; 79 80 u32_t halCapability; 81 82 /* Fortunately the second loop can be disabled with a bit */ 83 /* called en_pd_dc_offset_thr */ 84 u8_t hwNotFirstInit; 85 86 /* command queue */ 87 u16_t cmdHead; 88 u16_t cmdTail; 89#ifdef ZM_XP_USB_MULTCMD 90 u16_t cmdSend; // Used for Mult send USB cmd 91#endif 92 struct zsCmdQ cmdQ[ZM_CMD_QUEUE_SIZE]; 93 u16_t cmdPending; 94 struct zsCommand cmd; /* buffer for delayed commands */ 95 u8_t ledMode[2]; 96 u32_t ctlBusy; 97 u32_t extBusy; 98 99 /* 100 * ANI & Radar support. 101 */ 102 u32_t procPhyErr; /* Process Phy errs */ 103 u8_t hasHwPhyCounters; /* Hardware has phy counters */ 104 u32_t aniPeriod; /* ani update list period */ 105 struct zsAniStats stats; /* various statistics */ 106 struct zsAniState *curani; /* cached last reference */ 107 struct zsAniState ani[50]; /* per-channel state */ 108 109 s32_t totalSizeDesired[5]; 110 s32_t coarseHigh[5]; 111 s32_t coarseLow[5]; 112 s32_t firpwr[5]; 113 114 /* 115 * ANI related PHY register value. 116 */ 117 u32_t regPHYDesiredSZ; 118 u32_t regPHYFindSig; 119 u32_t regPHYAgcCtl1; 120 u32_t regPHYSfcorr; 121 u32_t regPHYSfcorrLow; 122 u32_t regPHYTiming5; 123 u32_t regPHYCckDetect; 124 125 u32_t eepromImage[1024]; 126 u32_t eepromImageIndex; 127 u32_t eepromImageRdReq; 128 129 u8_t halReInit; 130 131 u8_t OpFlags; 132 133 u8_t tPow2xCck[4]; 134 u8_t tPow2x2g[4]; 135 u8_t tPow2x2g24HeavyClipOffset; 136 u8_t tPow2x2gHt20[8]; 137 u8_t tPow2x2gHt40[8]; 138 u8_t tPow2x5g[4]; 139 u8_t tPow2x5gHt20[8]; 140 u8_t tPow2x5gHt40[8]; 141 142 /* hwBBHeavyClip : used compatibility */ 143 /* 0 : dongle not support. */ 144 /* !0: support heavy clip. */ 145 u8_t hwBBHeavyClip; 146 u8_t enableBBHeavyClip; /* 0=>force disable 1=>enable */ 147 u8_t doBBHeavyClip; /* set 1 if heavy clip need by each frequency switch */ 148 u32_t setValueHeavyClip; /* save setting value for heavy clip when completed routine */ 149 150 /* 151 * Rxdata RSSI, EVM, Rate etc... 152 */ 153 struct zsHalRxInfo halRxInfo; 154 155 u32_t usbSendBytes; 156 u32_t usbAcSendBytes[4]; 157 158 u16_t aggMaxDurationBE; 159 u32_t aggPktNum; 160 161 u16_t txop[4]; 162 u16_t cwmin[4]; 163 u16_t cwmax[4]; 164 u8_t strongRSSI; 165 u8_t rxStrongRSSI; 166 167 u8_t slotType; //0->20us, 1=>9us 168 169#ifdef ZM_OTUS_RX_STREAM_MODE 170 u16_t usbRxRemainLen; 171 u16_t usbRxPktLen; 172 u16_t usbRxPadLen; 173 u16_t usbRxTransferLen; 174 zbuf_t *remainBuf; 175#endif 176 177 u8_t dot11Mode; 178 179 u8_t ibssBcnEnabled; 180 u32_t ibssBcnInterval; 181 182 // For re-issue the frequency change command 183 u32_t latestFrequency; 184 u8_t latestBw40; 185 u8_t latestExtOffset; 186 u8_t freqRetryCounter; 187 188 u8_t recordFreqRetryCounter; 189 u8_t isSiteSurvey; 190 u8_t coldResetNeedFreq; 191 192 u64_t camRollCallTable; 193 u8_t currentAckRtsTpc; 194 195 /* #1 Save the initial value of the related RIFS register settings */ 196 //u32_t isInitialPhy; 197 u32_t initDesiredSigSize; 198 u32_t initAGC; 199 u32_t initAgcControl; 200 u32_t initSearchStartDelay; 201 u32_t initRIFSSearchParams; 202 u32_t initFastChannelChangeControl; 203 204 /* Dynamic SIFS for retransmission event */ 205 u8_t retransmissionEvent; 206 u8_t latestSIFS; 207}; 208 209extern u32_t zfHpLoadEEPROMFromFW(zdev_t* dev); 210 211 212typedef u8_t A_UINT8; 213typedef s8_t A_INT8; 214typedef u16_t A_UINT16; 215typedef u32_t A_UINT32; 216#define __ATTRIB_PACK 217 218#pragma pack (push, 1) 219 220#define AR5416_EEP_VER 0xE 221#define AR5416_EEP_VER_MINOR_MASK 0xFFF 222#define AR5416_EEP_NO_BACK_VER 0x1 223#define AR5416_EEP_MINOR_VER_2 0x2 // Adds modal params txFrameToPaOn, txFrametoDataStart, ht40PowerInc 224#define AR5416_EEP_MINOR_VER_3 0x3 // Adds modal params bswAtten, bswMargin, swSettle and base OpFlags for HT20/40 Disable 225 226// 16-bit offset location start of calibration struct 227#define AR5416_EEP_START_LOC 256 228#define AR5416_NUM_5G_CAL_PIERS 8 229#define AR5416_NUM_2G_CAL_PIERS 4 230#define AR5416_NUM_5G_20_TARGET_POWERS 8 231#define AR5416_NUM_5G_40_TARGET_POWERS 8 232#define AR5416_NUM_2G_CCK_TARGET_POWERS 3 233#define AR5416_NUM_2G_20_TARGET_POWERS 4 234#define AR5416_NUM_2G_40_TARGET_POWERS 4 235#define AR5416_NUM_CTLS 24 236#define AR5416_NUM_BAND_EDGES 8 237#define AR5416_NUM_PD_GAINS 4 238#define AR5416_PD_GAINS_IN_MASK 4 239#define AR5416_PD_GAIN_ICEPTS 5 240#define AR5416_EEPROM_MODAL_SPURS 5 241#define AR5416_MAX_RATE_POWER 63 242#define AR5416_NUM_PDADC_VALUES 128 243#define AR5416_NUM_RATES 16 244#define AR5416_BCHAN_UNUSED 0xFF 245#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 246#define AR5416_OPFLAGS_11A 0x01 247#define AR5416_OPFLAGS_11G 0x02 248#define AR5416_OPFLAGS_5G_HT40 0x04 249#define AR5416_OPFLAGS_2G_HT40 0x08 250#define AR5416_OPFLAGS_5G_HT20 0x10 251#define AR5416_OPFLAGS_2G_HT20 0x20 252#define AR5416_EEPMISC_BIG_ENDIAN 0x01 253#define FREQ2FBIN(x,y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) 254#define AR5416_MAX_CHAINS 2 255#define AR5416_ANT_16S 25 256 257#define AR5416_NUM_ANT_CHAIN_FIELDS 7 258#define AR5416_NUM_ANT_COMMON_FIELDS 4 259#define AR5416_SIZE_ANT_CHAIN_FIELD 3 260#define AR5416_SIZE_ANT_COMMON_FIELD 4 261#define AR5416_ANT_CHAIN_MASK 0x7 262#define AR5416_ANT_COMMON_MASK 0xf 263#define AR5416_CHAIN_0_IDX 0 264#define AR5416_CHAIN_1_IDX 1 265#define AR5416_CHAIN_2_IDX 2 266 267 268/* Capabilities Enum */ 269typedef enum { 270 EEPCAP_COMPRESS_DIS = 0x0001, 271 EEPCAP_AES_DIS = 0x0002, 272 EEPCAP_FASTFRAME_DIS = 0x0004, 273 EEPCAP_BURST_DIS = 0x0008, 274 EEPCAP_MAXQCU_M = 0x01F0, 275 EEPCAP_MAXQCU_S = 4, 276 EEPCAP_HEAVY_CLIP_EN = 0x0200, 277 EEPCAP_KC_ENTRIES_M = 0xF000, 278 EEPCAP_KC_ENTRIES_S = 12, 279} EEPROM_CAPABILITIES; 280 281typedef enum Ar5416_Rates { 282 rate6mb, rate9mb, rate12mb, rate18mb, 283 rate24mb, rate36mb, rate48mb, rate54mb, 284 rate1l, rate2l, rate2s, rate5_5l, 285 rate5_5s, rate11l, rate11s, rateXr, 286 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, 287 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, 288 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, 289 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, 290 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, 291 Ar5416RateSize 292} AR5416_RATES; 293 294typedef struct eepFlags { 295 A_UINT8 opFlags; 296 A_UINT8 eepMisc; 297} __ATTRIB_PACK EEP_FLAGS; 298 299#define AR5416_CHECKSUM_LOCATION (AR5416_EEP_START_LOC + 1) 300typedef struct BaseEepHeader { 301 A_UINT16 length; 302 A_UINT16 checksum; 303 A_UINT16 version; 304 EEP_FLAGS opCapFlags; 305 A_UINT16 regDmn[2]; 306 A_UINT8 macAddr[6]; 307 A_UINT8 rxMask; 308 A_UINT8 txMask; 309 A_UINT16 rfSilent; 310 A_UINT16 blueToothOptions; 311 A_UINT16 deviceCap; 312 A_UINT32 binBuildNumber; 313 A_UINT8 deviceType; 314 A_UINT8 futureBase[33]; 315} __ATTRIB_PACK BASE_EEP_HEADER; // 64 B 316 317typedef struct spurChanStruct { 318 A_UINT16 spurChan; 319 A_UINT8 spurRangeLow; 320 A_UINT8 spurRangeHigh; 321} __ATTRIB_PACK SPUR_CHAN; 322 323typedef struct ModalEepHeader { 324 A_UINT32 antCtrlChain[AR5416_MAX_CHAINS]; // 12 325 A_UINT32 antCtrlCommon; // 4 326 A_INT8 antennaGainCh[AR5416_MAX_CHAINS]; // 3 327 A_UINT8 switchSettling; // 1 328 A_UINT8 txRxAttenCh[AR5416_MAX_CHAINS]; // 3 329 A_UINT8 rxTxMarginCh[AR5416_MAX_CHAINS]; // 3 330 A_INT8 adcDesiredSize; // 1 331 A_INT8 pgaDesiredSize; // 1 332 A_UINT8 xlnaGainCh[AR5416_MAX_CHAINS]; // 3 333 A_UINT8 txEndToXpaOff; // 1 334 A_UINT8 txEndToRxOn; // 1 335 A_UINT8 txFrameToXpaOn; // 1 336 A_UINT8 thresh62; // 1 337 A_INT8 noiseFloorThreshCh[AR5416_MAX_CHAINS]; // 3 338 A_UINT8 xpdGain; // 1 339 A_UINT8 xpd; // 1 340 A_INT8 iqCalICh[AR5416_MAX_CHAINS]; // 1 341 A_INT8 iqCalQCh[AR5416_MAX_CHAINS]; // 1 342 A_UINT8 pdGainOverlap; // 1 343 A_UINT8 ob; // 1 344 A_UINT8 db; // 1 345 A_UINT8 xpaBiasLvl; // 1 346 A_UINT8 pwrDecreaseFor2Chain; // 1 347 A_UINT8 pwrDecreaseFor3Chain; // 1 -> 48 B 348 A_UINT8 txFrameToDataStart; // 1 349 A_UINT8 txFrameToPaOn; // 1 350 A_UINT8 ht40PowerIncForPdadc; // 1 351 A_UINT8 bswAtten[AR5416_MAX_CHAINS]; // 3 352 A_UINT8 bswMargin[AR5416_MAX_CHAINS]; // 3 353 A_UINT8 swSettleHt40; // 1 354 A_UINT8 futureModal[22]; // 355 SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; // 20 B 356} __ATTRIB_PACK MODAL_EEP_HEADER; // == 100 B 357 358typedef struct calDataPerFreq { 359 A_UINT8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 360 A_UINT8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 361} __ATTRIB_PACK CAL_DATA_PER_FREQ; 362 363typedef struct CalTargetPowerLegacy { 364 A_UINT8 bChannel; 365 A_UINT8 tPow2x[4]; 366} __ATTRIB_PACK CAL_TARGET_POWER_LEG; 367 368typedef struct CalTargetPowerHt { 369 A_UINT8 bChannel; 370 A_UINT8 tPow2x[8]; 371} __ATTRIB_PACK CAL_TARGET_POWER_HT; 372 373#if defined(ARCH_BIG_ENDIAN) || defined(BIG_ENDIAN) 374typedef struct CalCtlEdges { 375 A_UINT8 bChannel; 376 A_UINT8 flag :2, 377 tPower :6; 378} __ATTRIB_PACK CAL_CTL_EDGES; 379#else 380typedef struct CalCtlEdges { 381 A_UINT8 bChannel; 382 A_UINT8 tPower :6, 383 flag :2; 384} __ATTRIB_PACK CAL_CTL_EDGES; 385#endif 386 387typedef struct CalCtlData { 388 CAL_CTL_EDGES ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; 389} __ATTRIB_PACK CAL_CTL_DATA; 390 391typedef struct ar5416Eeprom { 392 BASE_EEP_HEADER baseEepHeader; // 64 B 393 A_UINT8 custData[64]; // 64 B 394 MODAL_EEP_HEADER modalHeader[2]; // 200 B 395 A_UINT8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; 396 A_UINT8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; 397 CAL_DATA_PER_FREQ calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; 398 CAL_DATA_PER_FREQ calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; 399 CAL_TARGET_POWER_LEG calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; 400 CAL_TARGET_POWER_HT calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; 401 CAL_TARGET_POWER_HT calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; 402 CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; 403 CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; 404 CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; 405 CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; 406 A_UINT8 ctlIndex[AR5416_NUM_CTLS]; 407 CAL_CTL_DATA ctlData[AR5416_NUM_CTLS]; 408 A_UINT8 padding; 409} __ATTRIB_PACK AR5416_EEPROM; 410 411#pragma pack (pop) 412 413typedef enum ConformanceTestLimits { 414 FCC = 0x10, 415 MKK = 0x40, 416 ETSI = 0x30, 417 SD_NO_CTL = 0xE0, 418 NO_CTL = 0xFF, 419 CTL_MODE_M = 0xF, 420 CTL_11A = 0, 421 CTL_11B = 1, 422 CTL_11G = 2, 423 CTL_TURBO = 3, 424 CTL_108G = 4, 425 CTL_2GHT20 = 5, 426 CTL_5GHT20 = 6, 427 CTL_2GHT40 = 7, 428 CTL_5GHT40 = 8, 429} ATH_CTLS; 430 431#endif /* #ifndef _HPUSB_H */ 432