1/* Copyright (c) 2009, Code Aurora Forum. All rights reserved. 2 * 3 * Redistribution and use in source and binary forms, with or without 4 * modification, are permitted provided that the following conditions are met: 5 * * Redistributions of source code must retain the above copyright 6 * notice, this list of conditions and the following disclaimer. 7 * * Redistributions in binary form must reproduce the above copyright 8 * notice, this list of conditions and the following disclaimer in the 9 * documentation and/or other materials provided with the distribution. 10 * * Neither the name of Code Aurora nor 11 * the names of its contributors may be used to endorse or promote 12 * products derived from this software without specific prior written 13 * permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 18 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 19 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 20 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29#ifndef MDDI_TOSHIBA_H 30#define MDDI_TOSHIBA_H 31 32#define TOSHIBA_VGA_PRIM 1 33#define TOSHIBA_VGA_SECD 2 34 35#define LCD_TOSHIBA_2P4_VGA 0 36#define LCD_TOSHIBA_2P4_WVGA 1 37#define LCD_TOSHIBA_2P4_WVGA_PT 2 38#define LCD_SHARP_2P4_VGA 3 39 40#define GPIO_BLOCK_BASE 0x150000 41#define SYSTEM_BLOCK2_BASE 0x170000 42 43#define GPIODIR (GPIO_BLOCK_BASE|0x04) 44#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00) 45#define GPIOPC (GPIO_BLOCK_BASE|0x28) 46#define GPIODATA (GPIO_BLOCK_BASE|0x00) 47 48#define write_client_reg(__X, __Y, __Z) {\ 49 mddi_queue_register_write(__X, __Y, TRUE, 0);\ 50} 51 52#endif /* MDDI_TOSHIBA_H */ 53