1/* 2 * omap_uwire.c -- MicroWire interface driver for OMAP 3 * 4 * Copyright 2003 MontaVista Software Inc. <source@mvista.com> 5 * 6 * Ported to 2.6 OMAP uwire interface. 7 * Copyright (C) 2004 Texas Instruments. 8 * 9 * Generalization patches by Juha Yrjola <juha.yrjola@nokia.com> 10 * 11 * Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface) 12 * Copyright (C) 2006 Nokia 13 * 14 * Many updates by Imre Deak <imre.deak@nokia.com> 15 * 16 * This program is free software; you can redistribute it and/or modify it 17 * under the terms of the GNU General Public License as published by the 18 * Free Software Foundation; either version 2 of the License, or (at your 19 * option) any later version. 20 * 21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * You should have received a copy of the GNU General Public License along 33 * with this program; if not, write to the Free Software Foundation, Inc., 34 * 675 Mass Ave, Cambridge, MA 02139, USA. 35 */ 36#include <linux/kernel.h> 37#include <linux/init.h> 38#include <linux/delay.h> 39#include <linux/platform_device.h> 40#include <linux/workqueue.h> 41#include <linux/interrupt.h> 42#include <linux/err.h> 43#include <linux/clk.h> 44#include <linux/slab.h> 45 46#include <linux/spi/spi.h> 47#include <linux/spi/spi_bitbang.h> 48 49#include <asm/system.h> 50#include <asm/irq.h> 51#include <mach/hardware.h> 52#include <asm/io.h> 53#include <asm/mach-types.h> 54 55#include <plat/mux.h> 56#include <plat/omap7xx.h> /* OMAP7XX_IO_CONF registers */ 57 58 59#define UWIRE_BASE_PHYS 0xFFFB3000 60 61/* uWire Registers: */ 62#define UWIRE_IO_SIZE 0x20 63#define UWIRE_TDR 0x00 64#define UWIRE_RDR 0x00 65#define UWIRE_CSR 0x01 66#define UWIRE_SR1 0x02 67#define UWIRE_SR2 0x03 68#define UWIRE_SR3 0x04 69#define UWIRE_SR4 0x05 70#define UWIRE_SR5 0x06 71 72/* CSR bits */ 73#define RDRB (1 << 15) 74#define CSRB (1 << 14) 75#define START (1 << 13) 76#define CS_CMD (1 << 12) 77 78/* SR1 or SR2 bits */ 79#define UWIRE_READ_FALLING_EDGE 0x0001 80#define UWIRE_READ_RISING_EDGE 0x0000 81#define UWIRE_WRITE_FALLING_EDGE 0x0000 82#define UWIRE_WRITE_RISING_EDGE 0x0002 83#define UWIRE_CS_ACTIVE_LOW 0x0000 84#define UWIRE_CS_ACTIVE_HIGH 0x0004 85#define UWIRE_FREQ_DIV_2 0x0000 86#define UWIRE_FREQ_DIV_4 0x0008 87#define UWIRE_FREQ_DIV_8 0x0010 88#define UWIRE_CHK_READY 0x0020 89#define UWIRE_CLK_INVERTED 0x0040 90 91 92struct uwire_spi { 93 struct spi_bitbang bitbang; 94 struct clk *ck; 95}; 96 97struct uwire_state { 98 unsigned bits_per_word; 99 unsigned div1_idx; 100}; 101 102/* REVISIT compile time constant for idx_shift? */ 103/* 104 * Or, put it in a structure which is used throughout the driver; 105 * that avoids having to issue two loads for each bit of static data. 106 */ 107static unsigned int uwire_idx_shift; 108static void __iomem *uwire_base; 109 110static inline void uwire_write_reg(int idx, u16 val) 111{ 112 __raw_writew(val, uwire_base + (idx << uwire_idx_shift)); 113} 114 115static inline u16 uwire_read_reg(int idx) 116{ 117 return __raw_readw(uwire_base + (idx << uwire_idx_shift)); 118} 119 120static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags) 121{ 122 u16 w, val = 0; 123 int shift, reg; 124 125 if (flags & UWIRE_CLK_INVERTED) 126 val ^= 0x03; 127 val = flags & 0x3f; 128 if (cs & 1) 129 shift = 6; 130 else 131 shift = 0; 132 if (cs <= 1) 133 reg = UWIRE_SR1; 134 else 135 reg = UWIRE_SR2; 136 137 w = uwire_read_reg(reg); 138 w &= ~(0x3f << shift); 139 w |= val << shift; 140 uwire_write_reg(reg, w); 141} 142 143static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch) 144{ 145 u16 w; 146 int c = 0; 147 unsigned long max_jiffies = jiffies + HZ; 148 149 for (;;) { 150 w = uwire_read_reg(UWIRE_CSR); 151 if ((w & mask) == val) 152 break; 153 if (time_after(jiffies, max_jiffies)) { 154 printk(KERN_ERR "%s: timeout. reg=%#06x " 155 "mask=%#06x val=%#06x\n", 156 __func__, w, mask, val); 157 return -1; 158 } 159 c++; 160 if (might_not_catch && c > 64) 161 break; 162 } 163 return 0; 164} 165 166static void uwire_set_clk1_div(int div1_idx) 167{ 168 u16 w; 169 170 w = uwire_read_reg(UWIRE_SR3); 171 w &= ~(0x03 << 1); 172 w |= div1_idx << 1; 173 uwire_write_reg(UWIRE_SR3, w); 174} 175 176static void uwire_chipselect(struct spi_device *spi, int value) 177{ 178 struct uwire_state *ust = spi->controller_state; 179 u16 w; 180 int old_cs; 181 182 183 BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0)); 184 185 w = uwire_read_reg(UWIRE_CSR); 186 old_cs = (w >> 10) & 0x03; 187 if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) { 188 /* Deselect this CS, or the previous CS */ 189 w &= ~CS_CMD; 190 uwire_write_reg(UWIRE_CSR, w); 191 } 192 /* activate specfied chipselect */ 193 if (value == BITBANG_CS_ACTIVE) { 194 uwire_set_clk1_div(ust->div1_idx); 195 /* invert clock? */ 196 if (spi->mode & SPI_CPOL) 197 uwire_write_reg(UWIRE_SR4, 1); 198 else 199 uwire_write_reg(UWIRE_SR4, 0); 200 201 w = spi->chip_select << 10; 202 w |= CS_CMD; 203 uwire_write_reg(UWIRE_CSR, w); 204 } 205} 206 207static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t) 208{ 209 struct uwire_state *ust = spi->controller_state; 210 unsigned len = t->len; 211 unsigned bits = ust->bits_per_word; 212 unsigned bytes; 213 u16 val, w; 214 int status = 0; 215 216 if (!t->tx_buf && !t->rx_buf) 217 return 0; 218 219 /* Microwire doesn't read and write concurrently */ 220 if (t->tx_buf && t->rx_buf) 221 return -EPERM; 222 223 w = spi->chip_select << 10; 224 w |= CS_CMD; 225 226 if (t->tx_buf) { 227 const u8 *buf = t->tx_buf; 228 229 /* NOTE: DMA could be used for TX transfers */ 230 231 /* write one or two bytes at a time */ 232 while (len >= 1) { 233 /* tx bit 15 is first sent; we byteswap multibyte words 234 * (msb-first) on the way out from memory. 235 */ 236 val = *buf++; 237 if (bits > 8) { 238 bytes = 2; 239 val |= *buf++ << 8; 240 } else 241 bytes = 1; 242 val <<= 16 - bits; 243 244#ifdef VERBOSE 245 pr_debug("%s: write-%d =%04x\n", 246 dev_name(&spi->dev), bits, val); 247#endif 248 if (wait_uwire_csr_flag(CSRB, 0, 0)) 249 goto eio; 250 251 uwire_write_reg(UWIRE_TDR, val); 252 253 /* start write */ 254 val = START | w | (bits << 5); 255 256 uwire_write_reg(UWIRE_CSR, val); 257 len -= bytes; 258 259 /* Wait till write actually starts. 260 * This is needed with MPU clock 60+ MHz. 261 * REVISIT: we may not have time to catch it... 262 */ 263 if (wait_uwire_csr_flag(CSRB, CSRB, 1)) 264 goto eio; 265 266 status += bytes; 267 } 268 269 /* REVISIT: save this for later to get more i/o overlap */ 270 if (wait_uwire_csr_flag(CSRB, 0, 0)) 271 goto eio; 272 273 } else if (t->rx_buf) { 274 u8 *buf = t->rx_buf; 275 276 /* read one or two bytes at a time */ 277 while (len) { 278 if (bits > 8) { 279 bytes = 2; 280 } else 281 bytes = 1; 282 283 /* start read */ 284 val = START | w | (bits << 0); 285 uwire_write_reg(UWIRE_CSR, val); 286 len -= bytes; 287 288 /* Wait till read actually starts */ 289 (void) wait_uwire_csr_flag(CSRB, CSRB, 1); 290 291 if (wait_uwire_csr_flag(RDRB | CSRB, 292 RDRB, 0)) 293 goto eio; 294 295 /* rx bit 0 is last received; multibyte words will 296 * be properly byteswapped on the way to memory. 297 */ 298 val = uwire_read_reg(UWIRE_RDR); 299 val &= (1 << bits) - 1; 300 *buf++ = (u8) val; 301 if (bytes == 2) 302 *buf++ = val >> 8; 303 status += bytes; 304#ifdef VERBOSE 305 pr_debug("%s: read-%d =%04x\n", 306 dev_name(&spi->dev), bits, val); 307#endif 308 309 } 310 } 311 return status; 312eio: 313 return -EIO; 314} 315 316static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t) 317{ 318 struct uwire_state *ust = spi->controller_state; 319 struct uwire_spi *uwire; 320 unsigned flags = 0; 321 unsigned bits; 322 unsigned hz; 323 unsigned long rate; 324 int div1_idx; 325 int div1; 326 int div2; 327 int status; 328 329 uwire = spi_master_get_devdata(spi->master); 330 331 if (spi->chip_select > 3) { 332 pr_debug("%s: cs%d?\n", dev_name(&spi->dev), spi->chip_select); 333 status = -ENODEV; 334 goto done; 335 } 336 337 bits = spi->bits_per_word; 338 if (t != NULL && t->bits_per_word) 339 bits = t->bits_per_word; 340 341 if (bits > 16) { 342 pr_debug("%s: wordsize %d?\n", dev_name(&spi->dev), bits); 343 status = -ENODEV; 344 goto done; 345 } 346 ust->bits_per_word = bits; 347 348 /* mode 0..3, clock inverted separately; 349 * standard nCS signaling; 350 * don't treat DI=high as "not ready" 351 */ 352 if (spi->mode & SPI_CS_HIGH) 353 flags |= UWIRE_CS_ACTIVE_HIGH; 354 355 if (spi->mode & SPI_CPOL) 356 flags |= UWIRE_CLK_INVERTED; 357 358 switch (spi->mode & (SPI_CPOL | SPI_CPHA)) { 359 case SPI_MODE_0: 360 case SPI_MODE_3: 361 flags |= UWIRE_WRITE_FALLING_EDGE | UWIRE_READ_RISING_EDGE; 362 break; 363 case SPI_MODE_1: 364 case SPI_MODE_2: 365 flags |= UWIRE_WRITE_RISING_EDGE | UWIRE_READ_FALLING_EDGE; 366 break; 367 } 368 369 /* assume it's already enabled */ 370 rate = clk_get_rate(uwire->ck); 371 372 hz = spi->max_speed_hz; 373 if (t != NULL && t->speed_hz) 374 hz = t->speed_hz; 375 376 if (!hz) { 377 pr_debug("%s: zero speed?\n", dev_name(&spi->dev)); 378 status = -EINVAL; 379 goto done; 380 } 381 382 /* F_INT = mpu_xor_clk / DIV1 */ 383 for (div1_idx = 0; div1_idx < 4; div1_idx++) { 384 switch (div1_idx) { 385 case 0: 386 div1 = 2; 387 break; 388 case 1: 389 div1 = 4; 390 break; 391 case 2: 392 div1 = 7; 393 break; 394 default: 395 case 3: 396 div1 = 10; 397 break; 398 } 399 div2 = (rate / div1 + hz - 1) / hz; 400 if (div2 <= 8) 401 break; 402 } 403 if (div1_idx == 4) { 404 pr_debug("%s: lowest clock %ld, need %d\n", 405 dev_name(&spi->dev), rate / 10 / 8, hz); 406 status = -EDOM; 407 goto done; 408 } 409 410 /* we have to cache this and reset in uwire_chipselect as this is a 411 * global parameter and another uwire device can change it under 412 * us */ 413 ust->div1_idx = div1_idx; 414 uwire_set_clk1_div(div1_idx); 415 416 rate /= div1; 417 418 switch (div2) { 419 case 0: 420 case 1: 421 case 2: 422 flags |= UWIRE_FREQ_DIV_2; 423 rate /= 2; 424 break; 425 case 3: 426 case 4: 427 flags |= UWIRE_FREQ_DIV_4; 428 rate /= 4; 429 break; 430 case 5: 431 case 6: 432 case 7: 433 case 8: 434 flags |= UWIRE_FREQ_DIV_8; 435 rate /= 8; 436 break; 437 } 438 omap_uwire_configure_mode(spi->chip_select, flags); 439 pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n", 440 __func__, flags, 441 clk_get_rate(uwire->ck) / 1000, 442 rate / 1000); 443 status = 0; 444done: 445 return status; 446} 447 448static int uwire_setup(struct spi_device *spi) 449{ 450 struct uwire_state *ust = spi->controller_state; 451 452 if (ust == NULL) { 453 ust = kzalloc(sizeof(*ust), GFP_KERNEL); 454 if (ust == NULL) 455 return -ENOMEM; 456 spi->controller_state = ust; 457 } 458 459 return uwire_setup_transfer(spi, NULL); 460} 461 462static void uwire_cleanup(struct spi_device *spi) 463{ 464 kfree(spi->controller_state); 465} 466 467static void uwire_off(struct uwire_spi *uwire) 468{ 469 uwire_write_reg(UWIRE_SR3, 0); 470 clk_disable(uwire->ck); 471 clk_put(uwire->ck); 472 spi_master_put(uwire->bitbang.master); 473} 474 475static int __init uwire_probe(struct platform_device *pdev) 476{ 477 struct spi_master *master; 478 struct uwire_spi *uwire; 479 int status; 480 481 master = spi_alloc_master(&pdev->dev, sizeof *uwire); 482 if (!master) 483 return -ENODEV; 484 485 uwire = spi_master_get_devdata(master); 486 487 uwire_base = ioremap(UWIRE_BASE_PHYS, UWIRE_IO_SIZE); 488 if (!uwire_base) { 489 dev_dbg(&pdev->dev, "can't ioremap UWIRE\n"); 490 spi_master_put(master); 491 return -ENOMEM; 492 } 493 494 dev_set_drvdata(&pdev->dev, uwire); 495 496 uwire->ck = clk_get(&pdev->dev, "fck"); 497 if (IS_ERR(uwire->ck)) { 498 status = PTR_ERR(uwire->ck); 499 dev_dbg(&pdev->dev, "no functional clock?\n"); 500 spi_master_put(master); 501 return status; 502 } 503 clk_enable(uwire->ck); 504 505 if (cpu_is_omap7xx()) 506 uwire_idx_shift = 1; 507 else 508 uwire_idx_shift = 2; 509 510 uwire_write_reg(UWIRE_SR3, 1); 511 512 /* the spi->mode bits understood by this driver: */ 513 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 514 515 master->flags = SPI_MASTER_HALF_DUPLEX; 516 517 master->bus_num = 2; /* "official" */ 518 master->num_chipselect = 4; 519 master->setup = uwire_setup; 520 master->cleanup = uwire_cleanup; 521 522 uwire->bitbang.master = master; 523 uwire->bitbang.chipselect = uwire_chipselect; 524 uwire->bitbang.setup_transfer = uwire_setup_transfer; 525 uwire->bitbang.txrx_bufs = uwire_txrx; 526 527 status = spi_bitbang_start(&uwire->bitbang); 528 if (status < 0) { 529 uwire_off(uwire); 530 iounmap(uwire_base); 531 } 532 return status; 533} 534 535static int __exit uwire_remove(struct platform_device *pdev) 536{ 537 struct uwire_spi *uwire = dev_get_drvdata(&pdev->dev); 538 int status; 539 540 541 status = spi_bitbang_stop(&uwire->bitbang); 542 uwire_off(uwire); 543 iounmap(uwire_base); 544 return status; 545} 546 547/* work with hotplug and coldplug */ 548MODULE_ALIAS("platform:omap_uwire"); 549 550static struct platform_driver uwire_driver = { 551 .driver = { 552 .name = "omap_uwire", 553 .owner = THIS_MODULE, 554 }, 555 .remove = __exit_p(uwire_remove), 556 // suspend ... unuse ck 557 // resume ... use ck 558}; 559 560static int __init omap_uwire_init(void) 561{ 562 563 if (machine_is_omap_h2()) { 564 /* defaults: W21 SDO, U18 SDI, V19 SCL */ 565 omap_cfg_reg(N14_1610_UWIRE_CS0); 566 omap_cfg_reg(N15_1610_UWIRE_CS1); 567 } 568 if (machine_is_omap_perseus2()) { 569 /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */ 570 int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000; 571 omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9); 572 } 573 574 return platform_driver_probe(&uwire_driver, uwire_probe); 575} 576 577static void __exit omap_uwire_exit(void) 578{ 579 platform_driver_unregister(&uwire_driver); 580} 581 582subsys_initcall(omap_uwire_init); 583module_exit(omap_uwire_exit); 584 585MODULE_LICENSE("GPL"); 586