1/* 2 * mfd.c: driver for High Speed UART device of Intel Medfield platform 3 * 4 * Refer pxa.c, 8250.c and some other drivers in drivers/serial/ 5 * 6 * (C) Copyright 2010 Intel Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; version 2 11 * of the License. 12 */ 13 14/* Notes: 15 * 1. DMA channel allocation: 0/1 channel are assigned to port 0, 16 * 2/3 chan to port 1, 4/5 chan to port 3. Even number chans 17 * are used for RX, odd chans for TX 18 * 19 * 2. In A0 stepping, UART will not support TX half empty flag 20 * 21 * 3. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always 22 * asserted, only when the HW is reset the DDCD and DDSR will 23 * be triggered 24 */ 25 26#include <linux/module.h> 27#include <linux/init.h> 28#include <linux/console.h> 29#include <linux/sysrq.h> 30#include <linux/slab.h> 31#include <linux/serial_reg.h> 32#include <linux/circ_buf.h> 33#include <linux/delay.h> 34#include <linux/interrupt.h> 35#include <linux/tty.h> 36#include <linux/tty_flip.h> 37#include <linux/serial_core.h> 38#include <linux/serial_mfd.h> 39#include <linux/dma-mapping.h> 40#include <linux/pci.h> 41#include <linux/io.h> 42#include <linux/debugfs.h> 43 44#define MFD_HSU_A0_STEPPING 1 45 46#define HSU_DMA_BUF_SIZE 2048 47 48#define chan_readl(chan, offset) readl(chan->reg + offset) 49#define chan_writel(chan, offset, val) writel(val, chan->reg + offset) 50 51#define mfd_readl(obj, offset) readl(obj->reg + offset) 52#define mfd_writel(obj, offset, val) writel(val, obj->reg + offset) 53 54#define HSU_DMA_TIMEOUT_CHECK_FREQ (HZ/10) 55 56struct hsu_dma_buffer { 57 u8 *buf; 58 dma_addr_t dma_addr; 59 u32 dma_size; 60 u32 ofs; 61}; 62 63struct hsu_dma_chan { 64 u32 id; 65 enum dma_data_direction dirt; 66 struct uart_hsu_port *uport; 67 void __iomem *reg; 68 struct timer_list rx_timer; /* only needed by RX channel */ 69}; 70 71struct uart_hsu_port { 72 struct uart_port port; 73 unsigned char ier; 74 unsigned char lcr; 75 unsigned char mcr; 76 unsigned int lsr_break_flag; 77 char name[12]; 78 int index; 79 struct device *dev; 80 81 struct hsu_dma_chan *txc; 82 struct hsu_dma_chan *rxc; 83 struct hsu_dma_buffer txbuf; 84 struct hsu_dma_buffer rxbuf; 85 int use_dma; /* flag for DMA/PIO */ 86 int running; 87 int dma_tx_on; 88}; 89 90/* Top level data structure of HSU */ 91struct hsu_port { 92 void __iomem *reg; 93 unsigned long paddr; 94 unsigned long iolen; 95 u32 irq; 96 97 struct uart_hsu_port port[3]; 98 struct hsu_dma_chan chans[10]; 99 100 struct dentry *debugfs; 101}; 102 103static inline unsigned int serial_in(struct uart_hsu_port *up, int offset) 104{ 105 unsigned int val; 106 107 if (offset > UART_MSR) { 108 offset <<= 2; 109 val = readl(up->port.membase + offset); 110 } else 111 val = (unsigned int)readb(up->port.membase + offset); 112 113 return val; 114} 115 116static inline void serial_out(struct uart_hsu_port *up, int offset, int value) 117{ 118 if (offset > UART_MSR) { 119 offset <<= 2; 120 writel(value, up->port.membase + offset); 121 } else { 122 unsigned char val = value & 0xff; 123 writeb(val, up->port.membase + offset); 124 } 125} 126 127#ifdef CONFIG_DEBUG_FS 128 129#define HSU_REGS_BUFSIZE 1024 130 131static int hsu_show_regs_open(struct inode *inode, struct file *file) 132{ 133 file->private_data = inode->i_private; 134 return 0; 135} 136 137static ssize_t port_show_regs(struct file *file, char __user *user_buf, 138 size_t count, loff_t *ppos) 139{ 140 struct uart_hsu_port *up = file->private_data; 141 char *buf; 142 u32 len = 0; 143 ssize_t ret; 144 145 buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL); 146 if (!buf) 147 return 0; 148 149 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 150 "MFD HSU port[%d] regs:\n", up->index); 151 152 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 153 "=================================\n"); 154 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 155 "IER: \t\t0x%08x\n", serial_in(up, UART_IER)); 156 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 157 "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR)); 158 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 159 "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR)); 160 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 161 "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR)); 162 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 163 "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR)); 164 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 165 "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR)); 166 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 167 "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR)); 168 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 169 "PS: \t\t0x%08x\n", serial_in(up, UART_PS)); 170 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 171 "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL)); 172 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 173 "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV)); 174 175 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 176 kfree(buf); 177 return ret; 178} 179 180static ssize_t dma_show_regs(struct file *file, char __user *user_buf, 181 size_t count, loff_t *ppos) 182{ 183 struct hsu_dma_chan *chan = file->private_data; 184 char *buf; 185 u32 len = 0; 186 ssize_t ret; 187 188 buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL); 189 if (!buf) 190 return 0; 191 192 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 193 "MFD HSU DMA channel [%d] regs:\n", chan->id); 194 195 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 196 "=================================\n"); 197 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 198 "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR)); 199 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 200 "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR)); 201 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 202 "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR)); 203 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 204 "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR)); 205 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 206 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR)); 207 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 208 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR)); 209 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 210 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR)); 211 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 212 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR)); 213 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 214 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR)); 215 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 216 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR)); 217 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 218 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR)); 219 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len, 220 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR)); 221 222 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 223 kfree(buf); 224 return ret; 225} 226 227static const struct file_operations port_regs_ops = { 228 .owner = THIS_MODULE, 229 .open = hsu_show_regs_open, 230 .read = port_show_regs, 231}; 232 233static const struct file_operations dma_regs_ops = { 234 .owner = THIS_MODULE, 235 .open = hsu_show_regs_open, 236 .read = dma_show_regs, 237}; 238 239static int hsu_debugfs_init(struct hsu_port *hsu) 240{ 241 int i; 242 char name[32]; 243 244 hsu->debugfs = debugfs_create_dir("hsu", NULL); 245 if (!hsu->debugfs) 246 return -ENOMEM; 247 248 for (i = 0; i < 3; i++) { 249 snprintf(name, sizeof(name), "port_%d_regs", i); 250 debugfs_create_file(name, S_IFREG | S_IRUGO, 251 hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops); 252 } 253 254 for (i = 0; i < 6; i++) { 255 snprintf(name, sizeof(name), "dma_chan_%d_regs", i); 256 debugfs_create_file(name, S_IFREG | S_IRUGO, 257 hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops); 258 } 259 260 return 0; 261} 262 263static void hsu_debugfs_remove(struct hsu_port *hsu) 264{ 265 if (hsu->debugfs) 266 debugfs_remove_recursive(hsu->debugfs); 267} 268 269#else 270static inline int hsu_debugfs_init(struct hsu_port *hsu) 271{ 272 return 0; 273} 274 275static inline void hsu_debugfs_remove(struct hsu_port *hsu) 276{ 277} 278#endif /* CONFIG_DEBUG_FS */ 279 280static void serial_hsu_enable_ms(struct uart_port *port) 281{ 282 struct uart_hsu_port *up = 283 container_of(port, struct uart_hsu_port, port); 284 285 up->ier |= UART_IER_MSI; 286 serial_out(up, UART_IER, up->ier); 287} 288 289void hsu_dma_tx(struct uart_hsu_port *up) 290{ 291 struct circ_buf *xmit = &up->port.state->xmit; 292 struct hsu_dma_buffer *dbuf = &up->txbuf; 293 int count; 294 295 /* test_and_set_bit may be better, but anyway it's in lock protected mode */ 296 if (up->dma_tx_on) 297 return; 298 299 /* Update the circ buf info */ 300 xmit->tail += dbuf->ofs; 301 xmit->tail &= UART_XMIT_SIZE - 1; 302 303 up->port.icount.tx += dbuf->ofs; 304 dbuf->ofs = 0; 305 306 /* Disable the channel */ 307 chan_writel(up->txc, HSU_CH_CR, 0x0); 308 309 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) { 310 dma_sync_single_for_device(up->port.dev, 311 dbuf->dma_addr, 312 dbuf->dma_size, 313 DMA_TO_DEVICE); 314 315 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 316 dbuf->ofs = count; 317 318 /* Reprogram the channel */ 319 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail); 320 chan_writel(up->txc, HSU_CH_D0TSR, count); 321 322 /* Reenable the channel */ 323 chan_writel(up->txc, HSU_CH_DCR, 0x1 324 | (0x1 << 8) 325 | (0x1 << 16) 326 | (0x1 << 24)); 327 up->dma_tx_on = 1; 328 chan_writel(up->txc, HSU_CH_CR, 0x1); 329 } 330 331 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 332 uart_write_wakeup(&up->port); 333} 334 335/* The buffer is already cache coherent */ 336void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf) 337{ 338 dbuf->ofs = 0; 339 340 chan_writel(rxc, HSU_CH_BSR, 32); 341 chan_writel(rxc, HSU_CH_MOTSR, 4); 342 343 chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr); 344 chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size); 345 chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8) 346 | (0x1 << 16) 347 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */ 348 ); 349 chan_writel(rxc, HSU_CH_CR, 0x3); 350 351 mod_timer(&rxc->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ); 352} 353 354/* Protected by spin_lock_irqsave(port->lock) */ 355static void serial_hsu_start_tx(struct uart_port *port) 356{ 357 struct uart_hsu_port *up = 358 container_of(port, struct uart_hsu_port, port); 359 360 if (up->use_dma) { 361 hsu_dma_tx(up); 362 } else if (!(up->ier & UART_IER_THRI)) { 363 up->ier |= UART_IER_THRI; 364 serial_out(up, UART_IER, up->ier); 365 } 366} 367 368static void serial_hsu_stop_tx(struct uart_port *port) 369{ 370 struct uart_hsu_port *up = 371 container_of(port, struct uart_hsu_port, port); 372 struct hsu_dma_chan *txc = up->txc; 373 374 if (up->use_dma) 375 chan_writel(txc, HSU_CH_CR, 0x0); 376 else if (up->ier & UART_IER_THRI) { 377 up->ier &= ~UART_IER_THRI; 378 serial_out(up, UART_IER, up->ier); 379 } 380} 381 382/* This is always called in spinlock protected mode, so 383 * modify timeout timer is safe here */ 384void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts) 385{ 386 struct hsu_dma_buffer *dbuf = &up->rxbuf; 387 struct hsu_dma_chan *chan = up->rxc; 388 struct uart_port *port = &up->port; 389 struct tty_struct *tty = port->state->port.tty; 390 int count; 391 392 if (!tty) 393 return; 394 395 /* 396 * First need to know how many is already transferred, 397 * then check if its a timeout DMA irq, and return 398 * the trail bytes out, push them up and reenable the 399 * channel 400 */ 401 402 /* Timeout IRQ, need wait some time, see Errata 2 */ 403 if (int_sts & 0xf00) 404 udelay(2); 405 406 /* Stop the channel */ 407 chan_writel(chan, HSU_CH_CR, 0x0); 408 409 count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr; 410 if (!count) { 411 /* Restart the channel before we leave */ 412 chan_writel(chan, HSU_CH_CR, 0x3); 413 return; 414 } 415 del_timer(&chan->rx_timer); 416 417 dma_sync_single_for_cpu(port->dev, dbuf->dma_addr, 418 dbuf->dma_size, DMA_FROM_DEVICE); 419 420 /* 421 * Head will only wrap around when we recycle 422 * the DMA buffer, and when that happens, we 423 * explicitly set tail to 0. So head will 424 * always be greater than tail. 425 */ 426 tty_insert_flip_string(tty, dbuf->buf, count); 427 port->icount.rx += count; 428 429 dma_sync_single_for_device(up->port.dev, dbuf->dma_addr, 430 dbuf->dma_size, DMA_FROM_DEVICE); 431 432 /* Reprogram the channel */ 433 chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr); 434 chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size); 435 chan_writel(chan, HSU_CH_DCR, 0x1 436 | (0x1 << 8) 437 | (0x1 << 16) 438 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */ 439 ); 440 tty_flip_buffer_push(tty); 441 442 chan_writel(chan, HSU_CH_CR, 0x3); 443 chan->rx_timer.expires = jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ; 444 add_timer(&chan->rx_timer); 445 446} 447 448static void serial_hsu_stop_rx(struct uart_port *port) 449{ 450 struct uart_hsu_port *up = 451 container_of(port, struct uart_hsu_port, port); 452 struct hsu_dma_chan *chan = up->rxc; 453 454 if (up->use_dma) 455 chan_writel(chan, HSU_CH_CR, 0x2); 456 else { 457 up->ier &= ~UART_IER_RLSI; 458 up->port.read_status_mask &= ~UART_LSR_DR; 459 serial_out(up, UART_IER, up->ier); 460 } 461} 462 463static inline void receive_chars(struct uart_hsu_port *up, int *status) 464{ 465 struct tty_struct *tty = up->port.state->port.tty; 466 unsigned int ch, flag; 467 unsigned int max_count = 256; 468 469 if (!tty) 470 return; 471 472 do { 473 ch = serial_in(up, UART_RX); 474 flag = TTY_NORMAL; 475 up->port.icount.rx++; 476 477 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | 478 UART_LSR_FE | UART_LSR_OE))) { 479 480 dev_warn(up->dev, "We really rush into ERR/BI case" 481 "status = 0x%02x", *status); 482 /* For statistics only */ 483 if (*status & UART_LSR_BI) { 484 *status &= ~(UART_LSR_FE | UART_LSR_PE); 485 up->port.icount.brk++; 486 /* 487 * We do the SysRQ and SAK checking 488 * here because otherwise the break 489 * may get masked by ignore_status_mask 490 * or read_status_mask. 491 */ 492 if (uart_handle_break(&up->port)) 493 goto ignore_char; 494 } else if (*status & UART_LSR_PE) 495 up->port.icount.parity++; 496 else if (*status & UART_LSR_FE) 497 up->port.icount.frame++; 498 if (*status & UART_LSR_OE) 499 up->port.icount.overrun++; 500 501 /* Mask off conditions which should be ignored. */ 502 *status &= up->port.read_status_mask; 503 504#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE 505 if (up->port.cons && 506 up->port.cons->index == up->port.line) { 507 /* Recover the break flag from console xmit */ 508 *status |= up->lsr_break_flag; 509 up->lsr_break_flag = 0; 510 } 511#endif 512 if (*status & UART_LSR_BI) { 513 flag = TTY_BREAK; 514 } else if (*status & UART_LSR_PE) 515 flag = TTY_PARITY; 516 else if (*status & UART_LSR_FE) 517 flag = TTY_FRAME; 518 } 519 520 if (uart_handle_sysrq_char(&up->port, ch)) 521 goto ignore_char; 522 523 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag); 524 ignore_char: 525 *status = serial_in(up, UART_LSR); 526 } while ((*status & UART_LSR_DR) && max_count--); 527 tty_flip_buffer_push(tty); 528} 529 530static void transmit_chars(struct uart_hsu_port *up) 531{ 532 struct circ_buf *xmit = &up->port.state->xmit; 533 int count; 534 535 if (up->port.x_char) { 536 serial_out(up, UART_TX, up->port.x_char); 537 up->port.icount.tx++; 538 up->port.x_char = 0; 539 return; 540 } 541 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 542 serial_hsu_stop_tx(&up->port); 543 return; 544 } 545 546#ifndef MFD_HSU_A0_STEPPING 547 count = up->port.fifosize / 2; 548#else 549 /* 550 * A0 only supports fully empty IRQ, and the first char written 551 * into it won't clear the EMPT bit, so we may need be cautious 552 * by useing a shorter buffer 553 */ 554 count = up->port.fifosize - 4; 555#endif 556 do { 557 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 558 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 559 560 up->port.icount.tx++; 561 if (uart_circ_empty(xmit)) 562 break; 563 } while (--count > 0); 564 565 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 566 uart_write_wakeup(&up->port); 567 568 if (uart_circ_empty(xmit)) 569 serial_hsu_stop_tx(&up->port); 570} 571 572static inline void check_modem_status(struct uart_hsu_port *up) 573{ 574 int status; 575 576 status = serial_in(up, UART_MSR); 577 578 if ((status & UART_MSR_ANY_DELTA) == 0) 579 return; 580 581 if (status & UART_MSR_TERI) 582 up->port.icount.rng++; 583 if (status & UART_MSR_DDSR) 584 up->port.icount.dsr++; 585 /* We may only get DDCD when HW init and reset */ 586 if (status & UART_MSR_DDCD) 587 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); 588 /* Will start/stop_tx accordingly */ 589 if (status & UART_MSR_DCTS) 590 uart_handle_cts_change(&up->port, status & UART_MSR_CTS); 591 592 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 593} 594 595/* 596 * This handles the interrupt from one port. 597 */ 598static irqreturn_t port_irq(int irq, void *dev_id) 599{ 600 struct uart_hsu_port *up = dev_id; 601 unsigned int iir, lsr; 602 unsigned long flags; 603 604 if (unlikely(!up->running)) 605 return IRQ_NONE; 606 607 spin_lock_irqsave(&up->port.lock, flags); 608 if (up->use_dma) { 609 lsr = serial_in(up, UART_LSR); 610 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE | 611 UART_LSR_FE | UART_LSR_OE))) 612 dev_warn(up->dev, 613 "Got lsr irq while using DMA, lsr = 0x%2x\n", 614 lsr); 615 check_modem_status(up); 616 spin_unlock_irqrestore(&up->port.lock, flags); 617 return IRQ_HANDLED; 618 } 619 620 iir = serial_in(up, UART_IIR); 621 if (iir & UART_IIR_NO_INT) { 622 spin_unlock_irqrestore(&up->port.lock, flags); 623 return IRQ_NONE; 624 } 625 626 lsr = serial_in(up, UART_LSR); 627 if (lsr & UART_LSR_DR) 628 receive_chars(up, &lsr); 629 check_modem_status(up); 630 631 /* lsr will be renewed during the receive_chars */ 632 if (lsr & UART_LSR_THRE) 633 transmit_chars(up); 634 635 spin_unlock_irqrestore(&up->port.lock, flags); 636 return IRQ_HANDLED; 637} 638 639static inline void dma_chan_irq(struct hsu_dma_chan *chan) 640{ 641 struct uart_hsu_port *up = chan->uport; 642 unsigned long flags; 643 u32 int_sts; 644 645 spin_lock_irqsave(&up->port.lock, flags); 646 647 if (!up->use_dma || !up->running) 648 goto exit; 649 650 /* 651 * No matter what situation, need read clear the IRQ status 652 * There is a bug, see Errata 5, HSD 2900918 653 */ 654 int_sts = chan_readl(chan, HSU_CH_SR); 655 656 /* Rx channel */ 657 if (chan->dirt == DMA_FROM_DEVICE) 658 hsu_dma_rx(up, int_sts); 659 660 /* Tx channel */ 661 if (chan->dirt == DMA_TO_DEVICE) { 662 chan_writel(chan, HSU_CH_CR, 0x0); 663 up->dma_tx_on = 0; 664 hsu_dma_tx(up); 665 } 666 667exit: 668 spin_unlock_irqrestore(&up->port.lock, flags); 669 return; 670} 671 672static irqreturn_t dma_irq(int irq, void *dev_id) 673{ 674 struct hsu_port *hsu = dev_id; 675 u32 int_sts, i; 676 677 int_sts = mfd_readl(hsu, HSU_GBL_DMAISR); 678 679 /* Currently we only have 6 channels may be used */ 680 for (i = 0; i < 6; i++) { 681 if (int_sts & 0x1) 682 dma_chan_irq(&hsu->chans[i]); 683 int_sts >>= 1; 684 } 685 686 return IRQ_HANDLED; 687} 688 689static unsigned int serial_hsu_tx_empty(struct uart_port *port) 690{ 691 struct uart_hsu_port *up = 692 container_of(port, struct uart_hsu_port, port); 693 unsigned long flags; 694 unsigned int ret; 695 696 spin_lock_irqsave(&up->port.lock, flags); 697 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 698 spin_unlock_irqrestore(&up->port.lock, flags); 699 700 return ret; 701} 702 703static unsigned int serial_hsu_get_mctrl(struct uart_port *port) 704{ 705 struct uart_hsu_port *up = 706 container_of(port, struct uart_hsu_port, port); 707 unsigned char status; 708 unsigned int ret; 709 710 status = serial_in(up, UART_MSR); 711 712 ret = 0; 713 if (status & UART_MSR_DCD) 714 ret |= TIOCM_CAR; 715 if (status & UART_MSR_RI) 716 ret |= TIOCM_RNG; 717 if (status & UART_MSR_DSR) 718 ret |= TIOCM_DSR; 719 if (status & UART_MSR_CTS) 720 ret |= TIOCM_CTS; 721 return ret; 722} 723 724static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl) 725{ 726 struct uart_hsu_port *up = 727 container_of(port, struct uart_hsu_port, port); 728 unsigned char mcr = 0; 729 730 if (mctrl & TIOCM_RTS) 731 mcr |= UART_MCR_RTS; 732 if (mctrl & TIOCM_DTR) 733 mcr |= UART_MCR_DTR; 734 if (mctrl & TIOCM_OUT1) 735 mcr |= UART_MCR_OUT1; 736 if (mctrl & TIOCM_OUT2) 737 mcr |= UART_MCR_OUT2; 738 if (mctrl & TIOCM_LOOP) 739 mcr |= UART_MCR_LOOP; 740 741 mcr |= up->mcr; 742 743 serial_out(up, UART_MCR, mcr); 744} 745 746static void serial_hsu_break_ctl(struct uart_port *port, int break_state) 747{ 748 struct uart_hsu_port *up = 749 container_of(port, struct uart_hsu_port, port); 750 unsigned long flags; 751 752 spin_lock_irqsave(&up->port.lock, flags); 753 if (break_state == -1) 754 up->lcr |= UART_LCR_SBC; 755 else 756 up->lcr &= ~UART_LCR_SBC; 757 serial_out(up, UART_LCR, up->lcr); 758 spin_unlock_irqrestore(&up->port.lock, flags); 759} 760 761/* 762 * What special to do: 763 * 1. chose the 64B fifo mode 764 * 2. make sure not to select half empty mode for A0 stepping 765 * 3. start dma or pio depends on configuration 766 * 4. we only allocate dma memory when needed 767 */ 768static int serial_hsu_startup(struct uart_port *port) 769{ 770 struct uart_hsu_port *up = 771 container_of(port, struct uart_hsu_port, port); 772 unsigned long flags; 773 774 /* 775 * Clear the FIFO buffers and disable them. 776 * (they will be reenabled in set_termios()) 777 */ 778 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 779 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 780 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 781 serial_out(up, UART_FCR, 0); 782 783 /* Clear the interrupt registers. */ 784 (void) serial_in(up, UART_LSR); 785 (void) serial_in(up, UART_RX); 786 (void) serial_in(up, UART_IIR); 787 (void) serial_in(up, UART_MSR); 788 789 /* Now, initialize the UART, default is 8n1 */ 790 serial_out(up, UART_LCR, UART_LCR_WLEN8); 791 792 spin_lock_irqsave(&up->port.lock, flags); 793 794 up->port.mctrl |= TIOCM_OUT2; 795 serial_hsu_set_mctrl(&up->port, up->port.mctrl); 796 797 /* 798 * Finally, enable interrupts. Note: Modem status interrupts 799 * are set via set_termios(), which will be occurring imminently 800 * anyway, so we don't enable them here. 801 */ 802 if (!up->use_dma) 803 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE; 804 else 805 up->ier = 0; 806 serial_out(up, UART_IER, up->ier); 807 808 spin_unlock_irqrestore(&up->port.lock, flags); 809 810 /* DMA init */ 811 if (up->use_dma) { 812 struct hsu_dma_buffer *dbuf; 813 struct circ_buf *xmit = &port->state->xmit; 814 815 up->dma_tx_on = 0; 816 817 /* First allocate the RX buffer */ 818 dbuf = &up->rxbuf; 819 dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL); 820 if (!dbuf->buf) { 821 up->use_dma = 0; 822 goto exit; 823 } 824 dbuf->dma_addr = dma_map_single(port->dev, 825 dbuf->buf, 826 HSU_DMA_BUF_SIZE, 827 DMA_FROM_DEVICE); 828 dbuf->dma_size = HSU_DMA_BUF_SIZE; 829 830 /* Start the RX channel right now */ 831 hsu_dma_start_rx_chan(up->rxc, dbuf); 832 833 /* Next init the TX DMA */ 834 dbuf = &up->txbuf; 835 dbuf->buf = xmit->buf; 836 dbuf->dma_addr = dma_map_single(port->dev, 837 dbuf->buf, 838 UART_XMIT_SIZE, 839 DMA_TO_DEVICE); 840 dbuf->dma_size = UART_XMIT_SIZE; 841 842 /* This should not be changed all around */ 843 chan_writel(up->txc, HSU_CH_BSR, 32); 844 chan_writel(up->txc, HSU_CH_MOTSR, 4); 845 dbuf->ofs = 0; 846 } 847 848exit: 849 /* And clear the interrupt registers again for luck. */ 850 (void) serial_in(up, UART_LSR); 851 (void) serial_in(up, UART_RX); 852 (void) serial_in(up, UART_IIR); 853 (void) serial_in(up, UART_MSR); 854 855 up->running = 1; 856 return 0; 857} 858 859static void serial_hsu_shutdown(struct uart_port *port) 860{ 861 struct uart_hsu_port *up = 862 container_of(port, struct uart_hsu_port, port); 863 unsigned long flags; 864 865 del_timer_sync(&up->rxc->rx_timer); 866 867 /* Disable interrupts from this port */ 868 up->ier = 0; 869 serial_out(up, UART_IER, 0); 870 up->running = 0; 871 872 spin_lock_irqsave(&up->port.lock, flags); 873 up->port.mctrl &= ~TIOCM_OUT2; 874 serial_hsu_set_mctrl(&up->port, up->port.mctrl); 875 spin_unlock_irqrestore(&up->port.lock, flags); 876 877 /* Disable break condition and FIFOs */ 878 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); 879 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 880 UART_FCR_CLEAR_RCVR | 881 UART_FCR_CLEAR_XMIT); 882 serial_out(up, UART_FCR, 0); 883} 884 885static void 886serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios, 887 struct ktermios *old) 888{ 889 struct uart_hsu_port *up = 890 container_of(port, struct uart_hsu_port, port); 891 struct tty_struct *tty = port->state->port.tty; 892 unsigned char cval, fcr = 0; 893 unsigned long flags; 894 unsigned int baud, quot; 895 u32 ps, mul; 896 897 switch (termios->c_cflag & CSIZE) { 898 case CS5: 899 cval = UART_LCR_WLEN5; 900 break; 901 case CS6: 902 cval = UART_LCR_WLEN6; 903 break; 904 case CS7: 905 cval = UART_LCR_WLEN7; 906 break; 907 default: 908 case CS8: 909 cval = UART_LCR_WLEN8; 910 break; 911 } 912 913 /* CMSPAR isn't supported by this driver */ 914 if (tty) 915 tty->termios->c_cflag &= ~CMSPAR; 916 917 if (termios->c_cflag & CSTOPB) 918 cval |= UART_LCR_STOP; 919 if (termios->c_cflag & PARENB) 920 cval |= UART_LCR_PARITY; 921 if (!(termios->c_cflag & PARODD)) 922 cval |= UART_LCR_EPAR; 923 924 /* 925 * For those basic low baud rate we can get the direct 926 * scalar from 2746800, like 115200 = 2746800/24, for those 927 * higher baud rate, we have to handle them case by case, 928 * but DIV reg is never touched as its default value 0x3d09 929 */ 930 baud = uart_get_baud_rate(port, termios, old, 0, 4000000); 931 quot = uart_get_divisor(port, baud); 932 933 switch (baud) { 934 case 3500000: 935 mul = 0x3345; 936 ps = 0xC; 937 quot = 1; 938 break; 939 case 18432000: 940 mul = 0x2400; 941 ps = 0x10; 942 quot = 1; 943 break; 944 case 3000000: 945 case 2500000: 946 case 2000000: 947 case 1500000: 948 case 1000000: 949 case 500000: 950 /* mul/ps/quot = 0x9C4/0x10/0x1 will make a 500000 bps */ 951 mul = baud / 500000 * 0x9C4; 952 break; 953 default: 954 ; 955 } 956 957 if ((up->port.uartclk / quot) < (2400 * 16)) 958 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B; 959 else if ((up->port.uartclk / quot) < (230400 * 16)) 960 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B; 961 else 962 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B; 963 964 fcr |= UART_FCR_HSU_64B_FIFO; 965#ifdef MFD_HSU_A0_STEPPING 966 /* A0 doesn't support half empty IRQ */ 967 fcr |= UART_FCR_FULL_EMPT_TXI; 968#endif 969 970 /* 971 * Ok, we're now changing the port state. Do it with 972 * interrupts disabled. 973 */ 974 spin_lock_irqsave(&up->port.lock, flags); 975 976 /* Update the per-port timeout */ 977 uart_update_timeout(port, termios->c_cflag, baud); 978 979 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 980 if (termios->c_iflag & INPCK) 981 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 982 if (termios->c_iflag & (BRKINT | PARMRK)) 983 up->port.read_status_mask |= UART_LSR_BI; 984 985 /* Characters to ignore */ 986 up->port.ignore_status_mask = 0; 987 if (termios->c_iflag & IGNPAR) 988 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 989 if (termios->c_iflag & IGNBRK) { 990 up->port.ignore_status_mask |= UART_LSR_BI; 991 /* 992 * If we're ignoring parity and break indicators, 993 * ignore overruns too (for real raw support). 994 */ 995 if (termios->c_iflag & IGNPAR) 996 up->port.ignore_status_mask |= UART_LSR_OE; 997 } 998 999 /* Ignore all characters if CREAD is not set */ 1000 if ((termios->c_cflag & CREAD) == 0) 1001 up->port.ignore_status_mask |= UART_LSR_DR; 1002 1003 /* 1004 * CTS flow control flag and modem status interrupts, disable 1005 * MSI by default 1006 */ 1007 up->ier &= ~UART_IER_MSI; 1008 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 1009 up->ier |= UART_IER_MSI; 1010 1011 serial_out(up, UART_IER, up->ier); 1012 1013 if (termios->c_cflag & CRTSCTS) 1014 up->mcr |= UART_MCR_AFE | UART_MCR_RTS; 1015 else 1016 up->mcr &= ~UART_MCR_AFE; 1017 1018 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */ 1019 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ 1020 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ 1021 serial_out(up, UART_LCR, cval); /* reset DLAB */ 1022 serial_out(up, UART_MUL, mul); /* set MUL */ 1023 serial_out(up, UART_PS, ps); /* set PS */ 1024 up->lcr = cval; /* Save LCR */ 1025 serial_hsu_set_mctrl(&up->port, up->port.mctrl); 1026 serial_out(up, UART_FCR, fcr); 1027 spin_unlock_irqrestore(&up->port.lock, flags); 1028} 1029 1030static void 1031serial_hsu_pm(struct uart_port *port, unsigned int state, 1032 unsigned int oldstate) 1033{ 1034} 1035 1036static void serial_hsu_release_port(struct uart_port *port) 1037{ 1038} 1039 1040static int serial_hsu_request_port(struct uart_port *port) 1041{ 1042 return 0; 1043} 1044 1045static void serial_hsu_config_port(struct uart_port *port, int flags) 1046{ 1047 struct uart_hsu_port *up = 1048 container_of(port, struct uart_hsu_port, port); 1049 up->port.type = PORT_MFD; 1050} 1051 1052static int 1053serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser) 1054{ 1055 /* We don't want the core code to modify any port params */ 1056 return -EINVAL; 1057} 1058 1059static const char * 1060serial_hsu_type(struct uart_port *port) 1061{ 1062 struct uart_hsu_port *up = 1063 container_of(port, struct uart_hsu_port, port); 1064 return up->name; 1065} 1066 1067/* Mainly for uart console use */ 1068static struct uart_hsu_port *serial_hsu_ports[3]; 1069static struct uart_driver serial_hsu_reg; 1070 1071#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE 1072 1073#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 1074 1075/* Wait for transmitter & holding register to empty */ 1076static inline void wait_for_xmitr(struct uart_hsu_port *up) 1077{ 1078 unsigned int status, tmout = 1000; 1079 1080 /* Wait up to 1ms for the character to be sent. */ 1081 do { 1082 status = serial_in(up, UART_LSR); 1083 1084 if (status & UART_LSR_BI) 1085 up->lsr_break_flag = UART_LSR_BI; 1086 1087 if (--tmout == 0) 1088 break; 1089 udelay(1); 1090 } while (!(status & BOTH_EMPTY)); 1091 1092 /* Wait up to 1s for flow control if necessary */ 1093 if (up->port.flags & UPF_CONS_FLOW) { 1094 tmout = 1000000; 1095 while (--tmout && 1096 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0)) 1097 udelay(1); 1098 } 1099} 1100 1101static void serial_hsu_console_putchar(struct uart_port *port, int ch) 1102{ 1103 struct uart_hsu_port *up = 1104 container_of(port, struct uart_hsu_port, port); 1105 1106 wait_for_xmitr(up); 1107 serial_out(up, UART_TX, ch); 1108} 1109 1110/* 1111 * Print a string to the serial port trying not to disturb 1112 * any possible real use of the port... 1113 * 1114 * The console_lock must be held when we get here. 1115 */ 1116static void 1117serial_hsu_console_write(struct console *co, const char *s, unsigned int count) 1118{ 1119 struct uart_hsu_port *up = serial_hsu_ports[co->index]; 1120 unsigned long flags; 1121 unsigned int ier; 1122 int locked = 1; 1123 1124 local_irq_save(flags); 1125 if (up->port.sysrq) 1126 locked = 0; 1127 else if (oops_in_progress) { 1128 locked = spin_trylock(&up->port.lock); 1129 } else 1130 spin_lock(&up->port.lock); 1131 1132 /* First save the IER then disable the interrupts */ 1133 ier = serial_in(up, UART_IER); 1134 serial_out(up, UART_IER, 0); 1135 1136 uart_console_write(&up->port, s, count, serial_hsu_console_putchar); 1137 1138 /* 1139 * Finally, wait for transmitter to become empty 1140 * and restore the IER 1141 */ 1142 wait_for_xmitr(up); 1143 serial_out(up, UART_IER, ier); 1144 1145 if (locked) 1146 spin_unlock(&up->port.lock); 1147 local_irq_restore(flags); 1148} 1149 1150static struct console serial_hsu_console; 1151 1152static int __init 1153serial_hsu_console_setup(struct console *co, char *options) 1154{ 1155 struct uart_hsu_port *up; 1156 int baud = 115200; 1157 int bits = 8; 1158 int parity = 'n'; 1159 int flow = 'n'; 1160 int ret; 1161 1162 if (co->index == -1 || co->index >= serial_hsu_reg.nr) 1163 co->index = 0; 1164 up = serial_hsu_ports[co->index]; 1165 if (!up) 1166 return -ENODEV; 1167 1168 if (options) 1169 uart_parse_options(options, &baud, &parity, &bits, &flow); 1170 1171 ret = uart_set_options(&up->port, co, baud, parity, bits, flow); 1172 1173 return ret; 1174} 1175 1176static struct console serial_hsu_console = { 1177 .name = "ttyMFD", 1178 .write = serial_hsu_console_write, 1179 .device = uart_console_device, 1180 .setup = serial_hsu_console_setup, 1181 .flags = CON_PRINTBUFFER, 1182 .index = 2, 1183 .data = &serial_hsu_reg, 1184}; 1185#endif 1186 1187struct uart_ops serial_hsu_pops = { 1188 .tx_empty = serial_hsu_tx_empty, 1189 .set_mctrl = serial_hsu_set_mctrl, 1190 .get_mctrl = serial_hsu_get_mctrl, 1191 .stop_tx = serial_hsu_stop_tx, 1192 .start_tx = serial_hsu_start_tx, 1193 .stop_rx = serial_hsu_stop_rx, 1194 .enable_ms = serial_hsu_enable_ms, 1195 .break_ctl = serial_hsu_break_ctl, 1196 .startup = serial_hsu_startup, 1197 .shutdown = serial_hsu_shutdown, 1198 .set_termios = serial_hsu_set_termios, 1199 .pm = serial_hsu_pm, 1200 .type = serial_hsu_type, 1201 .release_port = serial_hsu_release_port, 1202 .request_port = serial_hsu_request_port, 1203 .config_port = serial_hsu_config_port, 1204 .verify_port = serial_hsu_verify_port, 1205}; 1206 1207static struct uart_driver serial_hsu_reg = { 1208 .owner = THIS_MODULE, 1209 .driver_name = "MFD serial", 1210 .dev_name = "ttyMFD", 1211 .major = TTY_MAJOR, 1212 .minor = 128, 1213 .nr = 3, 1214}; 1215 1216#ifdef CONFIG_PM 1217static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state) 1218{ 1219 void *priv = pci_get_drvdata(pdev); 1220 struct uart_hsu_port *up; 1221 1222 /* Make sure this is not the internal dma controller */ 1223 if (priv && (pdev->device != 0x081E)) { 1224 up = priv; 1225 uart_suspend_port(&serial_hsu_reg, &up->port); 1226 } 1227 1228 pci_save_state(pdev); 1229 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1230 return 0; 1231} 1232 1233static int serial_hsu_resume(struct pci_dev *pdev) 1234{ 1235 void *priv = pci_get_drvdata(pdev); 1236 struct uart_hsu_port *up; 1237 int ret; 1238 1239 pci_set_power_state(pdev, PCI_D0); 1240 pci_restore_state(pdev); 1241 1242 ret = pci_enable_device(pdev); 1243 if (ret) 1244 dev_warn(&pdev->dev, 1245 "HSU: can't re-enable device, try to continue\n"); 1246 1247 if (priv && (pdev->device != 0x081E)) { 1248 up = priv; 1249 uart_resume_port(&serial_hsu_reg, &up->port); 1250 } 1251 return 0; 1252} 1253#else 1254#define serial_hsu_suspend NULL 1255#define serial_hsu_resume NULL 1256#endif 1257 1258/* temp global pointer before we settle down on using one or four PCI dev */ 1259static struct hsu_port *phsu; 1260 1261static int serial_hsu_probe(struct pci_dev *pdev, 1262 const struct pci_device_id *ent) 1263{ 1264 struct uart_hsu_port *uport; 1265 int index, ret; 1266 1267 printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n", 1268 pdev->vendor, pdev->device); 1269 1270 switch (pdev->device) { 1271 case 0x081B: 1272 index = 0; 1273 break; 1274 case 0x081C: 1275 index = 1; 1276 break; 1277 case 0x081D: 1278 index = 2; 1279 break; 1280 case 0x081E: 1281 /* internal DMA controller */ 1282 index = 3; 1283 break; 1284 default: 1285 dev_err(&pdev->dev, "HSU: out of index!"); 1286 return -ENODEV; 1287 } 1288 1289 ret = pci_enable_device(pdev); 1290 if (ret) 1291 return ret; 1292 1293 if (index == 3) { 1294 /* DMA controller */ 1295 ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu); 1296 if (ret) { 1297 dev_err(&pdev->dev, "can not get IRQ\n"); 1298 goto err_disable; 1299 } 1300 pci_set_drvdata(pdev, phsu); 1301 } else { 1302 /* UART port 0~2 */ 1303 uport = &phsu->port[index]; 1304 uport->port.irq = pdev->irq; 1305 uport->port.dev = &pdev->dev; 1306 uport->dev = &pdev->dev; 1307 1308 ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport); 1309 if (ret) { 1310 dev_err(&pdev->dev, "can not get IRQ\n"); 1311 goto err_disable; 1312 } 1313 uart_add_one_port(&serial_hsu_reg, &uport->port); 1314 1315#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE 1316 if (index == 2) { 1317 register_console(&serial_hsu_console); 1318 uport->port.cons = &serial_hsu_console; 1319 } 1320#endif 1321 pci_set_drvdata(pdev, uport); 1322 } 1323 1324 return 0; 1325 1326err_disable: 1327 pci_disable_device(pdev); 1328 return ret; 1329} 1330 1331static void hsu_dma_rx_timeout(unsigned long data) 1332{ 1333 struct hsu_dma_chan *chan = (void *)data; 1334 struct uart_hsu_port *up = chan->uport; 1335 struct hsu_dma_buffer *dbuf = &up->rxbuf; 1336 int count = 0; 1337 unsigned long flags; 1338 1339 spin_lock_irqsave(&up->port.lock, flags); 1340 1341 count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr; 1342 1343 if (!count) { 1344 mod_timer(&chan->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ); 1345 goto exit; 1346 } 1347 1348 hsu_dma_rx(up, 0); 1349exit: 1350 spin_unlock_irqrestore(&up->port.lock, flags); 1351} 1352 1353static void hsu_global_init(void) 1354{ 1355 struct hsu_port *hsu; 1356 struct uart_hsu_port *uport; 1357 struct hsu_dma_chan *dchan; 1358 int i, ret; 1359 1360 hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL); 1361 if (!hsu) 1362 return; 1363 1364 /* Get basic io resource and map it */ 1365 hsu->paddr = 0xffa28000; 1366 hsu->iolen = 0x1000; 1367 1368 if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global"))) 1369 pr_warning("HSU: error in request mem region\n"); 1370 1371 hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen); 1372 if (!hsu->reg) { 1373 pr_err("HSU: error in ioremap\n"); 1374 ret = -ENOMEM; 1375 goto err_free_region; 1376 } 1377 1378 /* Initialise the 3 UART ports */ 1379 uport = hsu->port; 1380 for (i = 0; i < 3; i++) { 1381 uport->port.type = PORT_MFD; 1382 uport->port.iotype = UPIO_MEM; 1383 uport->port.mapbase = (resource_size_t)hsu->paddr 1384 + HSU_PORT_REG_OFFSET 1385 + i * HSU_PORT_REG_LENGTH; 1386 uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET 1387 + i * HSU_PORT_REG_LENGTH; 1388 1389 sprintf(uport->name, "hsu_port%d", i); 1390 uport->port.fifosize = 64; 1391 uport->port.ops = &serial_hsu_pops; 1392 uport->port.line = i; 1393 uport->port.flags = UPF_IOREMAP; 1394 /* set the scalable maxim support rate to 2746800 bps */ 1395 uport->port.uartclk = 115200 * 24 * 16; 1396 1397 uport->running = 0; 1398 uport->txc = &hsu->chans[i * 2]; 1399 uport->rxc = &hsu->chans[i * 2 + 1]; 1400 1401 serial_hsu_ports[i] = uport; 1402 uport->index = i; 1403 uport++; 1404 } 1405 1406 /* Initialise 6 dma channels */ 1407 dchan = hsu->chans; 1408 for (i = 0; i < 6; i++) { 1409 dchan->id = i; 1410 dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 1411 dchan->uport = &hsu->port[i/2]; 1412 dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET + 1413 i * HSU_DMA_CHANS_REG_LENGTH; 1414 1415 if (dchan->dirt == DMA_FROM_DEVICE) { 1416 init_timer(&dchan->rx_timer); 1417 dchan->rx_timer.function = hsu_dma_rx_timeout; 1418 dchan->rx_timer.data = (unsigned long)dchan; 1419 } 1420 dchan++; 1421 } 1422 1423 phsu = hsu; 1424 hsu_debugfs_init(hsu); 1425 return; 1426 1427err_free_region: 1428 release_mem_region(hsu->paddr, hsu->iolen); 1429 kfree(hsu); 1430 return; 1431} 1432 1433static void serial_hsu_remove(struct pci_dev *pdev) 1434{ 1435 void *priv = pci_get_drvdata(pdev); 1436 struct uart_hsu_port *up; 1437 1438 if (!priv) 1439 return; 1440 1441 /* For port 0/1/2, priv is the address of uart_hsu_port */ 1442 if (pdev->device != 0x081E) { 1443 up = priv; 1444 uart_remove_one_port(&serial_hsu_reg, &up->port); 1445 } 1446 1447 pci_set_drvdata(pdev, NULL); 1448 free_irq(pdev->irq, priv); 1449 pci_disable_device(pdev); 1450} 1451 1452/* First 3 are UART ports, and the 4th is the DMA */ 1453static const struct pci_device_id pci_ids[] __devinitdata = { 1454 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) }, 1455 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) }, 1456 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) }, 1457 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) }, 1458 {}, 1459}; 1460 1461static struct pci_driver hsu_pci_driver = { 1462 .name = "HSU serial", 1463 .id_table = pci_ids, 1464 .probe = serial_hsu_probe, 1465 .remove = __devexit_p(serial_hsu_remove), 1466 .suspend = serial_hsu_suspend, 1467 .resume = serial_hsu_resume, 1468}; 1469 1470static int __init hsu_pci_init(void) 1471{ 1472 int ret; 1473 1474 hsu_global_init(); 1475 1476 ret = uart_register_driver(&serial_hsu_reg); 1477 if (ret) 1478 return ret; 1479 1480 return pci_register_driver(&hsu_pci_driver); 1481} 1482 1483static void __exit hsu_pci_exit(void) 1484{ 1485 pci_unregister_driver(&hsu_pci_driver); 1486 uart_unregister_driver(&serial_hsu_reg); 1487 1488 hsu_debugfs_remove(phsu); 1489 1490 kfree(phsu); 1491} 1492 1493module_init(hsu_pci_init); 1494module_exit(hsu_pci_exit); 1495 1496MODULE_LICENSE("GPL v2"); 1497MODULE_ALIAS("platform:medfield-hsu"); 1498