1/* 2 * linux/drivers/char/8250.c 3 * 4 * Driver for 8250/16550-type serial ports 5 * 6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 7 * 8 * Copyright (C) 2001 Russell King. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * A note about mapbase / membase 16 * 17 * mapbase is the physical address of the IO port. 18 * membase is an 'ioremapped' cookie. 19 */ 20 21#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 22#define SUPPORT_SYSRQ 23#endif 24 25#include <linux/module.h> 26#include <linux/moduleparam.h> 27#include <linux/ioport.h> 28#include <linux/init.h> 29#include <linux/console.h> 30#include <linux/sysrq.h> 31#include <linux/delay.h> 32#include <linux/platform_device.h> 33#include <linux/tty.h> 34#include <linux/tty_flip.h> 35#include <linux/serial_reg.h> 36#include <linux/serial_core.h> 37#include <linux/serial.h> 38#include <linux/serial_8250.h> 39#include <linux/nmi.h> 40#include <linux/mutex.h> 41#include <linux/slab.h> 42 43#include <asm/io.h> 44#include <asm/irq.h> 45 46#include "8250.h" 47 48#ifdef CONFIG_SPARC 49#include "suncore.h" 50#endif 51 52/* 53 * Configuration: 54 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option 55 * is unsafe when used on edge-triggered interrupts. 56 */ 57static unsigned int share_irqs = SERIAL8250_SHARE_IRQS; 58 59static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS; 60 61static struct uart_driver serial8250_reg; 62 63static int serial_index(struct uart_port *port) 64{ 65 return (serial8250_reg.minor - 64) + port->line; 66} 67 68static unsigned int skip_txen_test; /* force skip of txen test at init time */ 69 70/* 71 * Debugging. 72 */ 73#define DEBUG_AUTOCONF(fmt...) do { } while (0) 74 75#define DEBUG_INTR(fmt...) do { } while (0) 76 77#define PASS_LIMIT 256 78 79#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 80 81 82/* 83 * We default to IRQ0 for the "no irq" hack. Some 84 * machine types want others as well - they're free 85 * to redefine this in their header file. 86 */ 87#define is_real_interrupt(irq) ((irq) != 0) 88 89#ifdef CONFIG_SERIAL_8250_DETECT_IRQ 90#define CONFIG_SERIAL_DETECT_IRQ 1 91#endif 92#ifdef CONFIG_SERIAL_8250_MANY_PORTS 93#define CONFIG_SERIAL_MANY_PORTS 1 94#endif 95 96/* 97 * HUB6 is always on. This will be removed once the header 98 * files have been cleaned. 99 */ 100#define CONFIG_HUB6 1 101 102#include <asm/serial.h> 103/* 104 * SERIAL_PORT_DFNS tells us about built-in ports that have no 105 * standard enumeration mechanism. Platforms that can find all 106 * serial ports via mechanisms like ACPI or PCI need not supply it. 107 */ 108#ifndef SERIAL_PORT_DFNS 109#define SERIAL_PORT_DFNS 110#endif 111 112static const struct old_serial_port old_serial_port[] = { 113 SERIAL_PORT_DFNS /* defined in asm/serial.h */ 114}; 115 116#define UART_NR CONFIG_SERIAL_8250_NR_UARTS 117 118#ifdef CONFIG_SERIAL_8250_RSA 119 120#define PORT_RSA_MAX 4 121static unsigned long probe_rsa[PORT_RSA_MAX]; 122static unsigned int probe_rsa_count; 123#endif /* CONFIG_SERIAL_8250_RSA */ 124 125struct uart_8250_port { 126 struct uart_port port; 127 struct timer_list timer; /* "no irq" timer */ 128 struct list_head list; /* ports on this IRQ */ 129 unsigned short capabilities; /* port capabilities */ 130 unsigned short bugs; /* port bugs */ 131 unsigned int tx_loadsz; /* transmit fifo load size */ 132 unsigned char acr; 133 unsigned char ier; 134 unsigned char lcr; 135 unsigned char mcr; 136 unsigned char mcr_mask; /* mask of user bits */ 137 unsigned char mcr_force; /* mask of forced bits */ 138 unsigned char cur_iotype; /* Running I/O type */ 139 140 /* 141 * Some bits in registers are cleared on a read, so they must 142 * be saved whenever the register is read but the bits will not 143 * be immediately processed. 144 */ 145#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS 146 unsigned char lsr_saved_flags; 147#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA 148 unsigned char msr_saved_flags; 149 150 /* 151 * We provide a per-port pm hook. 152 */ 153 void (*pm)(struct uart_port *port, 154 unsigned int state, unsigned int old); 155}; 156 157struct irq_info { 158 struct hlist_node node; 159 int irq; 160 spinlock_t lock; /* Protects list not the hash */ 161 struct list_head *head; 162}; 163 164#define NR_IRQ_HASH 32 /* Can be adjusted later */ 165static struct hlist_head irq_lists[NR_IRQ_HASH]; 166static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */ 167 168/* 169 * Here we define the default xmit fifo size used for each type of UART. 170 */ 171static const struct serial8250_config uart_config[] = { 172 [PORT_UNKNOWN] = { 173 .name = "unknown", 174 .fifo_size = 1, 175 .tx_loadsz = 1, 176 }, 177 [PORT_8250] = { 178 .name = "8250", 179 .fifo_size = 1, 180 .tx_loadsz = 1, 181 }, 182 [PORT_16450] = { 183 .name = "16450", 184 .fifo_size = 1, 185 .tx_loadsz = 1, 186 }, 187 [PORT_16550] = { 188 .name = "16550", 189 .fifo_size = 1, 190 .tx_loadsz = 1, 191 }, 192 [PORT_16550A] = { 193 .name = "16550A", 194 .fifo_size = 16, 195 .tx_loadsz = 16, 196 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 197 .flags = UART_CAP_FIFO, 198 }, 199 [PORT_CIRRUS] = { 200 .name = "Cirrus", 201 .fifo_size = 1, 202 .tx_loadsz = 1, 203 }, 204 [PORT_16650] = { 205 .name = "ST16650", 206 .fifo_size = 1, 207 .tx_loadsz = 1, 208 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 209 }, 210 [PORT_16650V2] = { 211 .name = "ST16650V2", 212 .fifo_size = 32, 213 .tx_loadsz = 16, 214 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | 215 UART_FCR_T_TRIG_00, 216 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 217 }, 218 [PORT_16750] = { 219 .name = "TI16750", 220 .fifo_size = 64, 221 .tx_loadsz = 64, 222 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | 223 UART_FCR7_64BYTE, 224 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, 225 }, 226 [PORT_STARTECH] = { 227 .name = "Startech", 228 .fifo_size = 1, 229 .tx_loadsz = 1, 230 }, 231 [PORT_16C950] = { 232 .name = "16C950/954", 233 .fifo_size = 128, 234 .tx_loadsz = 128, 235 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 236 /* UART_CAP_EFR breaks billionon CF bluetooth card. */ 237 .flags = UART_CAP_FIFO | UART_CAP_SLEEP, 238 }, 239 [PORT_16654] = { 240 .name = "ST16654", 241 .fifo_size = 64, 242 .tx_loadsz = 32, 243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | 244 UART_FCR_T_TRIG_10, 245 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 246 }, 247 [PORT_16850] = { 248 .name = "XR16850", 249 .fifo_size = 128, 250 .tx_loadsz = 128, 251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 252 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 253 }, 254 [PORT_RSA] = { 255 .name = "RSA", 256 .fifo_size = 2048, 257 .tx_loadsz = 2048, 258 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11, 259 .flags = UART_CAP_FIFO, 260 }, 261 [PORT_NS16550A] = { 262 .name = "NS16550A", 263 .fifo_size = 16, 264 .tx_loadsz = 16, 265 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 266 .flags = UART_CAP_FIFO | UART_NATSEMI, 267 }, 268 [PORT_XSCALE] = { 269 .name = "XScale", 270 .fifo_size = 32, 271 .tx_loadsz = 32, 272 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 273 .flags = UART_CAP_FIFO | UART_CAP_UUE, 274 }, 275 [PORT_RM9000] = { 276 .name = "RM9000", 277 .fifo_size = 16, 278 .tx_loadsz = 16, 279 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 280 .flags = UART_CAP_FIFO, 281 }, 282 [PORT_OCTEON] = { 283 .name = "OCTEON", 284 .fifo_size = 64, 285 .tx_loadsz = 64, 286 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 287 .flags = UART_CAP_FIFO, 288 }, 289 [PORT_AR7] = { 290 .name = "AR7", 291 .fifo_size = 16, 292 .tx_loadsz = 16, 293 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, 294 .flags = UART_CAP_FIFO | UART_CAP_AFE, 295 }, 296 [PORT_U6_16550A] = { 297 .name = "U6_16550A", 298 .fifo_size = 64, 299 .tx_loadsz = 64, 300 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 301 .flags = UART_CAP_FIFO | UART_CAP_AFE, 302 }, 303}; 304 305#if defined(CONFIG_MIPS_ALCHEMY) 306 307/* Au1x00 UART hardware has a weird register layout */ 308static const u8 au_io_in_map[] = { 309 [UART_RX] = 0, 310 [UART_IER] = 2, 311 [UART_IIR] = 3, 312 [UART_LCR] = 5, 313 [UART_MCR] = 6, 314 [UART_LSR] = 7, 315 [UART_MSR] = 8, 316}; 317 318static const u8 au_io_out_map[] = { 319 [UART_TX] = 1, 320 [UART_IER] = 2, 321 [UART_FCR] = 4, 322 [UART_LCR] = 5, 323 [UART_MCR] = 6, 324}; 325 326/* sane hardware needs no mapping */ 327static inline int map_8250_in_reg(struct uart_port *p, int offset) 328{ 329 if (p->iotype != UPIO_AU) 330 return offset; 331 return au_io_in_map[offset]; 332} 333 334static inline int map_8250_out_reg(struct uart_port *p, int offset) 335{ 336 if (p->iotype != UPIO_AU) 337 return offset; 338 return au_io_out_map[offset]; 339} 340 341#elif defined(CONFIG_SERIAL_8250_RM9K) 342 343static const u8 344 regmap_in[8] = { 345 [UART_RX] = 0x00, 346 [UART_IER] = 0x0c, 347 [UART_IIR] = 0x14, 348 [UART_LCR] = 0x1c, 349 [UART_MCR] = 0x20, 350 [UART_LSR] = 0x24, 351 [UART_MSR] = 0x28, 352 [UART_SCR] = 0x2c 353 }, 354 regmap_out[8] = { 355 [UART_TX] = 0x04, 356 [UART_IER] = 0x0c, 357 [UART_FCR] = 0x18, 358 [UART_LCR] = 0x1c, 359 [UART_MCR] = 0x20, 360 [UART_LSR] = 0x24, 361 [UART_MSR] = 0x28, 362 [UART_SCR] = 0x2c 363 }; 364 365static inline int map_8250_in_reg(struct uart_port *p, int offset) 366{ 367 if (p->iotype != UPIO_RM9000) 368 return offset; 369 return regmap_in[offset]; 370} 371 372static inline int map_8250_out_reg(struct uart_port *p, int offset) 373{ 374 if (p->iotype != UPIO_RM9000) 375 return offset; 376 return regmap_out[offset]; 377} 378 379#else 380 381/* sane hardware needs no mapping */ 382#define map_8250_in_reg(up, offset) (offset) 383#define map_8250_out_reg(up, offset) (offset) 384 385#endif 386 387static unsigned int hub6_serial_in(struct uart_port *p, int offset) 388{ 389 offset = map_8250_in_reg(p, offset) << p->regshift; 390 outb(p->hub6 - 1 + offset, p->iobase); 391 return inb(p->iobase + 1); 392} 393 394static void hub6_serial_out(struct uart_port *p, int offset, int value) 395{ 396 offset = map_8250_out_reg(p, offset) << p->regshift; 397 outb(p->hub6 - 1 + offset, p->iobase); 398 outb(value, p->iobase + 1); 399} 400 401static unsigned int mem_serial_in(struct uart_port *p, int offset) 402{ 403 offset = map_8250_in_reg(p, offset) << p->regshift; 404 return readb(p->membase + offset); 405} 406 407static void mem_serial_out(struct uart_port *p, int offset, int value) 408{ 409 offset = map_8250_out_reg(p, offset) << p->regshift; 410 writeb(value, p->membase + offset); 411} 412 413static void mem32_serial_out(struct uart_port *p, int offset, int value) 414{ 415 offset = map_8250_out_reg(p, offset) << p->regshift; 416 writel(value, p->membase + offset); 417} 418 419static unsigned int mem32_serial_in(struct uart_port *p, int offset) 420{ 421 offset = map_8250_in_reg(p, offset) << p->regshift; 422 return readl(p->membase + offset); 423} 424 425static unsigned int au_serial_in(struct uart_port *p, int offset) 426{ 427 offset = map_8250_in_reg(p, offset) << p->regshift; 428 return __raw_readl(p->membase + offset); 429} 430 431static void au_serial_out(struct uart_port *p, int offset, int value) 432{ 433 offset = map_8250_out_reg(p, offset) << p->regshift; 434 __raw_writel(value, p->membase + offset); 435} 436 437static unsigned int tsi_serial_in(struct uart_port *p, int offset) 438{ 439 unsigned int tmp; 440 offset = map_8250_in_reg(p, offset) << p->regshift; 441 if (offset == UART_IIR) { 442 tmp = readl(p->membase + (UART_IIR & ~3)); 443 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */ 444 } else 445 return readb(p->membase + offset); 446} 447 448static void tsi_serial_out(struct uart_port *p, int offset, int value) 449{ 450 offset = map_8250_out_reg(p, offset) << p->regshift; 451 if (!((offset == UART_IER) && (value & UART_IER_UUE))) 452 writeb(value, p->membase + offset); 453} 454 455static void dwapb_serial_out(struct uart_port *p, int offset, int value) 456{ 457 int save_offset = offset; 458 offset = map_8250_out_reg(p, offset) << p->regshift; 459 /* Save the LCR value so it can be re-written when a 460 * Busy Detect interrupt occurs. */ 461 if (save_offset == UART_LCR) { 462 struct uart_8250_port *up = (struct uart_8250_port *)p; 463 up->lcr = value; 464 } 465 writeb(value, p->membase + offset); 466 /* Read the IER to ensure any interrupt is cleared before 467 * returning from ISR. */ 468 if (save_offset == UART_TX || save_offset == UART_IER) 469 value = p->serial_in(p, UART_IER); 470} 471 472static unsigned int io_serial_in(struct uart_port *p, int offset) 473{ 474 offset = map_8250_in_reg(p, offset) << p->regshift; 475 return inb(p->iobase + offset); 476} 477 478static void io_serial_out(struct uart_port *p, int offset, int value) 479{ 480 offset = map_8250_out_reg(p, offset) << p->regshift; 481 outb(value, p->iobase + offset); 482} 483 484static void set_io_from_upio(struct uart_port *p) 485{ 486 struct uart_8250_port *up = (struct uart_8250_port *)p; 487 switch (p->iotype) { 488 case UPIO_HUB6: 489 p->serial_in = hub6_serial_in; 490 p->serial_out = hub6_serial_out; 491 break; 492 493 case UPIO_MEM: 494 p->serial_in = mem_serial_in; 495 p->serial_out = mem_serial_out; 496 break; 497 498 case UPIO_RM9000: 499 case UPIO_MEM32: 500 p->serial_in = mem32_serial_in; 501 p->serial_out = mem32_serial_out; 502 break; 503 504 case UPIO_AU: 505 p->serial_in = au_serial_in; 506 p->serial_out = au_serial_out; 507 break; 508 509 case UPIO_TSI: 510 p->serial_in = tsi_serial_in; 511 p->serial_out = tsi_serial_out; 512 break; 513 514 case UPIO_DWAPB: 515 p->serial_in = mem_serial_in; 516 p->serial_out = dwapb_serial_out; 517 break; 518 519 default: 520 p->serial_in = io_serial_in; 521 p->serial_out = io_serial_out; 522 break; 523 } 524 /* Remember loaded iotype */ 525 up->cur_iotype = p->iotype; 526} 527 528static void 529serial_out_sync(struct uart_8250_port *up, int offset, int value) 530{ 531 struct uart_port *p = &up->port; 532 switch (p->iotype) { 533 case UPIO_MEM: 534 case UPIO_MEM32: 535 case UPIO_AU: 536 case UPIO_DWAPB: 537 p->serial_out(p, offset, value); 538 p->serial_in(p, UART_LCR); /* safe, no side-effects */ 539 break; 540 default: 541 p->serial_out(p, offset, value); 542 } 543} 544 545#define serial_in(up, offset) \ 546 (up->port.serial_in(&(up)->port, (offset))) 547#define serial_out(up, offset, value) \ 548 (up->port.serial_out(&(up)->port, (offset), (value))) 549/* 550 * We used to support using pause I/O for certain machines. We 551 * haven't supported this for a while, but just in case it's badly 552 * needed for certain old 386 machines, I've left these #define's 553 * in.... 554 */ 555#define serial_inp(up, offset) serial_in(up, offset) 556#define serial_outp(up, offset, value) serial_out(up, offset, value) 557 558/* Uart divisor latch read */ 559static inline int _serial_dl_read(struct uart_8250_port *up) 560{ 561 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8; 562} 563 564/* Uart divisor latch write */ 565static inline void _serial_dl_write(struct uart_8250_port *up, int value) 566{ 567 serial_outp(up, UART_DLL, value & 0xff); 568 serial_outp(up, UART_DLM, value >> 8 & 0xff); 569} 570 571#if defined(CONFIG_MIPS_ALCHEMY) 572/* Au1x00 haven't got a standard divisor latch */ 573static int serial_dl_read(struct uart_8250_port *up) 574{ 575 if (up->port.iotype == UPIO_AU) 576 return __raw_readl(up->port.membase + 0x28); 577 else 578 return _serial_dl_read(up); 579} 580 581static void serial_dl_write(struct uart_8250_port *up, int value) 582{ 583 if (up->port.iotype == UPIO_AU) 584 __raw_writel(value, up->port.membase + 0x28); 585 else 586 _serial_dl_write(up, value); 587} 588#elif defined(CONFIG_SERIAL_8250_RM9K) 589static int serial_dl_read(struct uart_8250_port *up) 590{ 591 return (up->port.iotype == UPIO_RM9000) ? 592 (((__raw_readl(up->port.membase + 0x10) << 8) | 593 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) : 594 _serial_dl_read(up); 595} 596 597static void serial_dl_write(struct uart_8250_port *up, int value) 598{ 599 if (up->port.iotype == UPIO_RM9000) { 600 __raw_writel(value, up->port.membase + 0x08); 601 __raw_writel(value >> 8, up->port.membase + 0x10); 602 } else { 603 _serial_dl_write(up, value); 604 } 605} 606#else 607#define serial_dl_read(up) _serial_dl_read(up) 608#define serial_dl_write(up, value) _serial_dl_write(up, value) 609#endif 610 611/* 612 * For the 16C950 613 */ 614static void serial_icr_write(struct uart_8250_port *up, int offset, int value) 615{ 616 serial_out(up, UART_SCR, offset); 617 serial_out(up, UART_ICR, value); 618} 619 620static unsigned int serial_icr_read(struct uart_8250_port *up, int offset) 621{ 622 unsigned int value; 623 624 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); 625 serial_out(up, UART_SCR, offset); 626 value = serial_in(up, UART_ICR); 627 serial_icr_write(up, UART_ACR, up->acr); 628 629 return value; 630} 631 632/* 633 * FIFO support. 634 */ 635static void serial8250_clear_fifos(struct uart_8250_port *p) 636{ 637 if (p->capabilities & UART_CAP_FIFO) { 638 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO); 639 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO | 640 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 641 serial_outp(p, UART_FCR, 0); 642 } 643} 644 645/* 646 * IER sleep support. UARTs which have EFRs need the "extended 647 * capability" bit enabled. Note that on XR16C850s, we need to 648 * reset LCR to write to IER. 649 */ 650static void serial8250_set_sleep(struct uart_8250_port *p, int sleep) 651{ 652 if (p->capabilities & UART_CAP_SLEEP) { 653 if (p->capabilities & UART_CAP_EFR) { 654 serial_outp(p, UART_LCR, 0xBF); 655 serial_outp(p, UART_EFR, UART_EFR_ECB); 656 serial_outp(p, UART_LCR, 0); 657 } 658 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); 659 if (p->capabilities & UART_CAP_EFR) { 660 serial_outp(p, UART_LCR, 0xBF); 661 serial_outp(p, UART_EFR, 0); 662 serial_outp(p, UART_LCR, 0); 663 } 664 } 665} 666 667#ifdef CONFIG_SERIAL_8250_RSA 668/* 669 * Attempts to turn on the RSA FIFO. Returns zero on failure. 670 * We set the port uart clock rate if we succeed. 671 */ 672static int __enable_rsa(struct uart_8250_port *up) 673{ 674 unsigned char mode; 675 int result; 676 677 mode = serial_inp(up, UART_RSA_MSR); 678 result = mode & UART_RSA_MSR_FIFO; 679 680 if (!result) { 681 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); 682 mode = serial_inp(up, UART_RSA_MSR); 683 result = mode & UART_RSA_MSR_FIFO; 684 } 685 686 if (result) 687 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; 688 689 return result; 690} 691 692static void enable_rsa(struct uart_8250_port *up) 693{ 694 if (up->port.type == PORT_RSA) { 695 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { 696 spin_lock_irq(&up->port.lock); 697 __enable_rsa(up); 698 spin_unlock_irq(&up->port.lock); 699 } 700 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) 701 serial_outp(up, UART_RSA_FRR, 0); 702 } 703} 704 705/* 706 * Attempts to turn off the RSA FIFO. Returns zero on failure. 707 * It is unknown why interrupts were disabled in here. However, 708 * the caller is expected to preserve this behaviour by grabbing 709 * the spinlock before calling this function. 710 */ 711static void disable_rsa(struct uart_8250_port *up) 712{ 713 unsigned char mode; 714 int result; 715 716 if (up->port.type == PORT_RSA && 717 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { 718 spin_lock_irq(&up->port.lock); 719 720 mode = serial_inp(up, UART_RSA_MSR); 721 result = !(mode & UART_RSA_MSR_FIFO); 722 723 if (!result) { 724 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); 725 mode = serial_inp(up, UART_RSA_MSR); 726 result = !(mode & UART_RSA_MSR_FIFO); 727 } 728 729 if (result) 730 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; 731 spin_unlock_irq(&up->port.lock); 732 } 733} 734#endif /* CONFIG_SERIAL_8250_RSA */ 735 736/* 737 * This is a quickie test to see how big the FIFO is. 738 * It doesn't work at all the time, more's the pity. 739 */ 740static int size_fifo(struct uart_8250_port *up) 741{ 742 unsigned char old_fcr, old_mcr, old_lcr; 743 unsigned short old_dl; 744 int count; 745 746 old_lcr = serial_inp(up, UART_LCR); 747 serial_outp(up, UART_LCR, 0); 748 old_fcr = serial_inp(up, UART_FCR); 749 old_mcr = serial_inp(up, UART_MCR); 750 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | 751 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 752 serial_outp(up, UART_MCR, UART_MCR_LOOP); 753 serial_outp(up, UART_LCR, UART_LCR_DLAB); 754 old_dl = serial_dl_read(up); 755 serial_dl_write(up, 0x0001); 756 serial_outp(up, UART_LCR, 0x03); 757 for (count = 0; count < 256; count++) 758 serial_outp(up, UART_TX, count); 759 mdelay(20); 760 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) && 761 (count < 256); count++) 762 serial_inp(up, UART_RX); 763 serial_outp(up, UART_FCR, old_fcr); 764 serial_outp(up, UART_MCR, old_mcr); 765 serial_outp(up, UART_LCR, UART_LCR_DLAB); 766 serial_dl_write(up, old_dl); 767 serial_outp(up, UART_LCR, old_lcr); 768 769 return count; 770} 771 772/* 773 * Read UART ID using the divisor method - set DLL and DLM to zero 774 * and the revision will be in DLL and device type in DLM. We 775 * preserve the device state across this. 776 */ 777static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) 778{ 779 unsigned char old_dll, old_dlm, old_lcr; 780 unsigned int id; 781 782 old_lcr = serial_inp(p, UART_LCR); 783 serial_outp(p, UART_LCR, UART_LCR_DLAB); 784 785 old_dll = serial_inp(p, UART_DLL); 786 old_dlm = serial_inp(p, UART_DLM); 787 788 serial_outp(p, UART_DLL, 0); 789 serial_outp(p, UART_DLM, 0); 790 791 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8; 792 793 serial_outp(p, UART_DLL, old_dll); 794 serial_outp(p, UART_DLM, old_dlm); 795 serial_outp(p, UART_LCR, old_lcr); 796 797 return id; 798} 799 800/* 801 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's. 802 * When this function is called we know it is at least a StarTech 803 * 16650 V2, but it might be one of several StarTech UARTs, or one of 804 * its clones. (We treat the broken original StarTech 16650 V1 as a 805 * 16550, and why not? Startech doesn't seem to even acknowledge its 806 * existence.) 807 * 808 * What evil have men's minds wrought... 809 */ 810static void autoconfig_has_efr(struct uart_8250_port *up) 811{ 812 unsigned int id1, id2, id3, rev; 813 814 /* 815 * Everything with an EFR has SLEEP 816 */ 817 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; 818 819 /* 820 * First we check to see if it's an Oxford Semiconductor UART. 821 * 822 * If we have to do this here because some non-National 823 * Semiconductor clone chips lock up if you try writing to the 824 * LSR register (which serial_icr_read does) 825 */ 826 827 /* 828 * Check for Oxford Semiconductor 16C950. 829 * 830 * EFR [4] must be set else this test fails. 831 * 832 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca) 833 * claims that it's needed for 952 dual UART's (which are not 834 * recommended for new designs). 835 */ 836 up->acr = 0; 837 serial_out(up, UART_LCR, 0xBF); 838 serial_out(up, UART_EFR, UART_EFR_ECB); 839 serial_out(up, UART_LCR, 0x00); 840 id1 = serial_icr_read(up, UART_ID1); 841 id2 = serial_icr_read(up, UART_ID2); 842 id3 = serial_icr_read(up, UART_ID3); 843 rev = serial_icr_read(up, UART_REV); 844 845 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev); 846 847 if (id1 == 0x16 && id2 == 0xC9 && 848 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) { 849 up->port.type = PORT_16C950; 850 851 if (id3 == 0x52 && rev == 0x01) 852 up->bugs |= UART_BUG_QUOT; 853 return; 854 } 855 856 /* 857 * We check for a XR16C850 by setting DLL and DLM to 0, and then 858 * reading back DLL and DLM. The chip type depends on the DLM 859 * value read back: 860 * 0x10 - XR16C850 and the DLL contains the chip revision. 861 * 0x12 - XR16C2850. 862 * 0x14 - XR16C854. 863 */ 864 id1 = autoconfig_read_divisor_id(up); 865 DEBUG_AUTOCONF("850id=%04x ", id1); 866 867 id2 = id1 >> 8; 868 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) { 869 up->port.type = PORT_16850; 870 return; 871 } 872 873 /* 874 * It wasn't an XR16C850. 875 * 876 * We distinguish between the '654 and the '650 by counting 877 * how many bytes are in the FIFO. I'm using this for now, 878 * since that's the technique that was sent to me in the 879 * serial driver update, but I'm not convinced this works. 880 * I've had problems doing this in the past. -TYT 881 */ 882 if (size_fifo(up) == 64) 883 up->port.type = PORT_16654; 884 else 885 up->port.type = PORT_16650V2; 886} 887 888/* 889 * We detected a chip without a FIFO. Only two fall into 890 * this category - the original 8250 and the 16450. The 891 * 16450 has a scratch register (accessible with LCR=0) 892 */ 893static void autoconfig_8250(struct uart_8250_port *up) 894{ 895 unsigned char scratch, status1, status2; 896 897 up->port.type = PORT_8250; 898 899 scratch = serial_in(up, UART_SCR); 900 serial_outp(up, UART_SCR, 0xa5); 901 status1 = serial_in(up, UART_SCR); 902 serial_outp(up, UART_SCR, 0x5a); 903 status2 = serial_in(up, UART_SCR); 904 serial_outp(up, UART_SCR, scratch); 905 906 if (status1 == 0xa5 && status2 == 0x5a) 907 up->port.type = PORT_16450; 908} 909 910static int broken_efr(struct uart_8250_port *up) 911{ 912 /* 913 * Exar ST16C2550 "A2" devices incorrectly detect as 914 * having an EFR, and report an ID of 0x0201. See 915 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf 916 */ 917 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) 918 return 1; 919 920 return 0; 921} 922 923/* 924 * We know that the chip has FIFOs. Does it have an EFR? The 925 * EFR is located in the same register position as the IIR and 926 * we know the top two bits of the IIR are currently set. The 927 * EFR should contain zero. Try to read the EFR. 928 */ 929static void autoconfig_16550a(struct uart_8250_port *up) 930{ 931 unsigned char status1, status2; 932 unsigned int iersave; 933 934 up->port.type = PORT_16550A; 935 up->capabilities |= UART_CAP_FIFO; 936 937 /* 938 * Check for presence of the EFR when DLAB is set. 939 * Only ST16C650V1 UARTs pass this test. 940 */ 941 serial_outp(up, UART_LCR, UART_LCR_DLAB); 942 if (serial_in(up, UART_EFR) == 0) { 943 serial_outp(up, UART_EFR, 0xA8); 944 if (serial_in(up, UART_EFR) != 0) { 945 DEBUG_AUTOCONF("EFRv1 "); 946 up->port.type = PORT_16650; 947 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; 948 } else { 949 DEBUG_AUTOCONF("Motorola 8xxx DUART "); 950 } 951 serial_outp(up, UART_EFR, 0); 952 return; 953 } 954 955 /* 956 * Maybe it requires 0xbf to be written to the LCR. 957 * (other ST16C650V2 UARTs, TI16C752A, etc) 958 */ 959 serial_outp(up, UART_LCR, 0xBF); 960 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) { 961 DEBUG_AUTOCONF("EFRv2 "); 962 autoconfig_has_efr(up); 963 return; 964 } 965 966 /* 967 * Check for a National Semiconductor SuperIO chip. 968 * Attempt to switch to bank 2, read the value of the LOOP bit 969 * from EXCR1. Switch back to bank 0, change it in MCR. Then 970 * switch back to bank 2, read it from EXCR1 again and check 971 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2 972 */ 973 serial_outp(up, UART_LCR, 0); 974 status1 = serial_in(up, UART_MCR); 975 serial_outp(up, UART_LCR, 0xE0); 976 status2 = serial_in(up, 0x02); /* EXCR1 */ 977 978 if (!((status2 ^ status1) & UART_MCR_LOOP)) { 979 serial_outp(up, UART_LCR, 0); 980 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP); 981 serial_outp(up, UART_LCR, 0xE0); 982 status2 = serial_in(up, 0x02); /* EXCR1 */ 983 serial_outp(up, UART_LCR, 0); 984 serial_outp(up, UART_MCR, status1); 985 986 if ((status2 ^ status1) & UART_MCR_LOOP) { 987 unsigned short quot; 988 989 serial_outp(up, UART_LCR, 0xE0); 990 991 quot = serial_dl_read(up); 992 quot <<= 3; 993 994 status1 = serial_in(up, 0x04); /* EXCR2 */ 995 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ 996 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ 997 serial_outp(up, 0x04, status1); 998 999 serial_dl_write(up, quot); 1000 1001 serial_outp(up, UART_LCR, 0); 1002 1003 up->port.uartclk = 921600*16; 1004 up->port.type = PORT_NS16550A; 1005 up->capabilities |= UART_NATSEMI; 1006 return; 1007 } 1008 } 1009 1010 /* 1011 * No EFR. Try to detect a TI16750, which only sets bit 5 of 1012 * the IIR when 64 byte FIFO mode is enabled when DLAB is set. 1013 * Try setting it with and without DLAB set. Cheap clones 1014 * set bit 5 without DLAB set. 1015 */ 1016 serial_outp(up, UART_LCR, 0); 1017 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 1018 status1 = serial_in(up, UART_IIR) >> 5; 1019 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1020 serial_outp(up, UART_LCR, UART_LCR_DLAB); 1021 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 1022 status2 = serial_in(up, UART_IIR) >> 5; 1023 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1024 serial_outp(up, UART_LCR, 0); 1025 1026 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2); 1027 1028 if (status1 == 6 && status2 == 7) { 1029 up->port.type = PORT_16750; 1030 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; 1031 return; 1032 } 1033 1034 /* 1035 * Try writing and reading the UART_IER_UUE bit (b6). 1036 * If it works, this is probably one of the Xscale platform's 1037 * internal UARTs. 1038 * We're going to explicitly set the UUE bit to 0 before 1039 * trying to write and read a 1 just to make sure it's not 1040 * already a 1 and maybe locked there before we even start start. 1041 */ 1042 iersave = serial_in(up, UART_IER); 1043 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE); 1044 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) { 1045 /* 1046 * OK it's in a known zero state, try writing and reading 1047 * without disturbing the current state of the other bits. 1048 */ 1049 serial_outp(up, UART_IER, iersave | UART_IER_UUE); 1050 if (serial_in(up, UART_IER) & UART_IER_UUE) { 1051 /* 1052 * It's an Xscale. 1053 * We'll leave the UART_IER_UUE bit set to 1 (enabled). 1054 */ 1055 DEBUG_AUTOCONF("Xscale "); 1056 up->port.type = PORT_XSCALE; 1057 up->capabilities |= UART_CAP_UUE; 1058 return; 1059 } 1060 } else { 1061 /* 1062 * If we got here we couldn't force the IER_UUE bit to 0. 1063 * Log it and continue. 1064 */ 1065 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 "); 1066 } 1067 serial_outp(up, UART_IER, iersave); 1068 1069 /* 1070 * We distinguish between 16550A and U6 16550A by counting 1071 * how many bytes are in the FIFO. 1072 */ 1073 if (up->port.type == PORT_16550A && size_fifo(up) == 64) { 1074 up->port.type = PORT_U6_16550A; 1075 up->capabilities |= UART_CAP_AFE; 1076 } 1077} 1078 1079/* 1080 * This routine is called by rs_init() to initialize a specific serial 1081 * port. It determines what type of UART chip this serial port is 1082 * using: 8250, 16450, 16550, 16550A. The important question is 1083 * whether or not this UART is a 16550A or not, since this will 1084 * determine whether or not we can use its FIFO features or not. 1085 */ 1086static void autoconfig(struct uart_8250_port *up, unsigned int probeflags) 1087{ 1088 unsigned char status1, scratch, scratch2, scratch3; 1089 unsigned char save_lcr, save_mcr; 1090 unsigned long flags; 1091 1092 if (!up->port.iobase && !up->port.mapbase && !up->port.membase) 1093 return; 1094 1095 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ", 1096 serial_index(&up->port), up->port.iobase, up->port.membase); 1097 1098 /* 1099 * We really do need global IRQs disabled here - we're going to 1100 * be frobbing the chips IRQ enable register to see if it exists. 1101 */ 1102 spin_lock_irqsave(&up->port.lock, flags); 1103 1104 up->capabilities = 0; 1105 up->bugs = 0; 1106 1107 if (!(up->port.flags & UPF_BUGGY_UART)) { 1108 /* 1109 * Do a simple existence test first; if we fail this, 1110 * there's no point trying anything else. 1111 * 1112 * 0x80 is used as a nonsense port to prevent against 1113 * false positives due to ISA bus float. The 1114 * assumption is that 0x80 is a non-existent port; 1115 * which should be safe since include/asm/io.h also 1116 * makes this assumption. 1117 * 1118 * Note: this is safe as long as MCR bit 4 is clear 1119 * and the device is in "PC" mode. 1120 */ 1121 scratch = serial_inp(up, UART_IER); 1122 serial_outp(up, UART_IER, 0); 1123#ifdef __i386__ 1124 outb(0xff, 0x080); 1125#endif 1126 /* 1127 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL 1128 * 16C754B) allow only to modify them if an EFR bit is set. 1129 */ 1130 scratch2 = serial_inp(up, UART_IER) & 0x0f; 1131 serial_outp(up, UART_IER, 0x0F); 1132#ifdef __i386__ 1133 outb(0, 0x080); 1134#endif 1135 scratch3 = serial_inp(up, UART_IER) & 0x0f; 1136 serial_outp(up, UART_IER, scratch); 1137 if (scratch2 != 0 || scratch3 != 0x0F) { 1138 /* 1139 * We failed; there's nothing here 1140 */ 1141 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ", 1142 scratch2, scratch3); 1143 goto out; 1144 } 1145 } 1146 1147 save_mcr = serial_in(up, UART_MCR); 1148 save_lcr = serial_in(up, UART_LCR); 1149 1150 /* 1151 * Check to see if a UART is really there. Certain broken 1152 * internal modems based on the Rockwell chipset fail this 1153 * test, because they apparently don't implement the loopback 1154 * test mode. So this test is skipped on the COM 1 through 1155 * COM 4 ports. This *should* be safe, since no board 1156 * manufacturer would be stupid enough to design a board 1157 * that conflicts with COM 1-4 --- we hope! 1158 */ 1159 if (!(up->port.flags & UPF_SKIP_TEST)) { 1160 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A); 1161 status1 = serial_inp(up, UART_MSR) & 0xF0; 1162 serial_outp(up, UART_MCR, save_mcr); 1163 if (status1 != 0x90) { 1164 DEBUG_AUTOCONF("LOOP test failed (%02x) ", 1165 status1); 1166 goto out; 1167 } 1168 } 1169 1170 /* 1171 * We're pretty sure there's a port here. Lets find out what 1172 * type of port it is. The IIR top two bits allows us to find 1173 * out if it's 8250 or 16450, 16550, 16550A or later. This 1174 * determines what we test for next. 1175 * 1176 * We also initialise the EFR (if any) to zero for later. The 1177 * EFR occupies the same register location as the FCR and IIR. 1178 */ 1179 serial_outp(up, UART_LCR, 0xBF); 1180 serial_outp(up, UART_EFR, 0); 1181 serial_outp(up, UART_LCR, 0); 1182 1183 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1184 scratch = serial_in(up, UART_IIR) >> 6; 1185 1186 DEBUG_AUTOCONF("iir=%d ", scratch); 1187 1188 switch (scratch) { 1189 case 0: 1190 autoconfig_8250(up); 1191 break; 1192 case 1: 1193 up->port.type = PORT_UNKNOWN; 1194 break; 1195 case 2: 1196 up->port.type = PORT_16550; 1197 break; 1198 case 3: 1199 autoconfig_16550a(up); 1200 break; 1201 } 1202 1203#ifdef CONFIG_SERIAL_8250_RSA 1204 /* 1205 * Only probe for RSA ports if we got the region. 1206 */ 1207 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) { 1208 int i; 1209 1210 for (i = 0 ; i < probe_rsa_count; ++i) { 1211 if (probe_rsa[i] == up->port.iobase && 1212 __enable_rsa(up)) { 1213 up->port.type = PORT_RSA; 1214 break; 1215 } 1216 } 1217 } 1218#endif 1219 1220 serial_outp(up, UART_LCR, save_lcr); 1221 1222 if (up->capabilities != uart_config[up->port.type].flags) { 1223 printk(KERN_WARNING 1224 "ttyS%d: detected caps %08x should be %08x\n", 1225 serial_index(&up->port), up->capabilities, 1226 uart_config[up->port.type].flags); 1227 } 1228 1229 up->port.fifosize = uart_config[up->port.type].fifo_size; 1230 up->capabilities = uart_config[up->port.type].flags; 1231 up->tx_loadsz = uart_config[up->port.type].tx_loadsz; 1232 1233 if (up->port.type == PORT_UNKNOWN) 1234 goto out; 1235 1236 /* 1237 * Reset the UART. 1238 */ 1239#ifdef CONFIG_SERIAL_8250_RSA 1240 if (up->port.type == PORT_RSA) 1241 serial_outp(up, UART_RSA_FRR, 0); 1242#endif 1243 serial_outp(up, UART_MCR, save_mcr); 1244 serial8250_clear_fifos(up); 1245 serial_in(up, UART_RX); 1246 if (up->capabilities & UART_CAP_UUE) 1247 serial_outp(up, UART_IER, UART_IER_UUE); 1248 else 1249 serial_outp(up, UART_IER, 0); 1250 1251 out: 1252 spin_unlock_irqrestore(&up->port.lock, flags); 1253 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name); 1254} 1255 1256static void autoconfig_irq(struct uart_8250_port *up) 1257{ 1258 unsigned char save_mcr, save_ier; 1259 unsigned char save_ICP = 0; 1260 unsigned int ICP = 0; 1261 unsigned long irqs; 1262 int irq; 1263 1264 if (up->port.flags & UPF_FOURPORT) { 1265 ICP = (up->port.iobase & 0xfe0) | 0x1f; 1266 save_ICP = inb_p(ICP); 1267 outb_p(0x80, ICP); 1268 (void) inb_p(ICP); 1269 } 1270 1271 /* forget possible initially masked and pending IRQ */ 1272 probe_irq_off(probe_irq_on()); 1273 save_mcr = serial_inp(up, UART_MCR); 1274 save_ier = serial_inp(up, UART_IER); 1275 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2); 1276 1277 irqs = probe_irq_on(); 1278 serial_outp(up, UART_MCR, 0); 1279 udelay(10); 1280 if (up->port.flags & UPF_FOURPORT) { 1281 serial_outp(up, UART_MCR, 1282 UART_MCR_DTR | UART_MCR_RTS); 1283 } else { 1284 serial_outp(up, UART_MCR, 1285 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); 1286 } 1287 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */ 1288 (void)serial_inp(up, UART_LSR); 1289 (void)serial_inp(up, UART_RX); 1290 (void)serial_inp(up, UART_IIR); 1291 (void)serial_inp(up, UART_MSR); 1292 serial_outp(up, UART_TX, 0xFF); 1293 udelay(20); 1294 irq = probe_irq_off(irqs); 1295 1296 serial_outp(up, UART_MCR, save_mcr); 1297 serial_outp(up, UART_IER, save_ier); 1298 1299 if (up->port.flags & UPF_FOURPORT) 1300 outb_p(save_ICP, ICP); 1301 1302 up->port.irq = (irq > 0) ? irq : 0; 1303} 1304 1305static inline void __stop_tx(struct uart_8250_port *p) 1306{ 1307 if (p->ier & UART_IER_THRI) { 1308 p->ier &= ~UART_IER_THRI; 1309 serial_out(p, UART_IER, p->ier); 1310 } 1311} 1312 1313static void serial8250_stop_tx(struct uart_port *port) 1314{ 1315 struct uart_8250_port *up = (struct uart_8250_port *)port; 1316 1317 __stop_tx(up); 1318 1319 /* 1320 * We really want to stop the transmitter from sending. 1321 */ 1322 if (up->port.type == PORT_16C950) { 1323 up->acr |= UART_ACR_TXDIS; 1324 serial_icr_write(up, UART_ACR, up->acr); 1325 } 1326} 1327 1328static void transmit_chars(struct uart_8250_port *up); 1329 1330static void serial8250_start_tx(struct uart_port *port) 1331{ 1332 struct uart_8250_port *up = (struct uart_8250_port *)port; 1333 1334 if (!(up->ier & UART_IER_THRI)) { 1335 up->ier |= UART_IER_THRI; 1336 serial_out(up, UART_IER, up->ier); 1337 1338 if (up->bugs & UART_BUG_TXEN) { 1339 unsigned char lsr; 1340 lsr = serial_in(up, UART_LSR); 1341 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; 1342 if ((up->port.type == PORT_RM9000) ? 1343 (lsr & UART_LSR_THRE) : 1344 (lsr & UART_LSR_TEMT)) 1345 transmit_chars(up); 1346 } 1347 } 1348 1349 /* 1350 * Re-enable the transmitter if we disabled it. 1351 */ 1352 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { 1353 up->acr &= ~UART_ACR_TXDIS; 1354 serial_icr_write(up, UART_ACR, up->acr); 1355 } 1356} 1357 1358static void serial8250_stop_rx(struct uart_port *port) 1359{ 1360 struct uart_8250_port *up = (struct uart_8250_port *)port; 1361 1362 up->ier &= ~UART_IER_RLSI; 1363 up->port.read_status_mask &= ~UART_LSR_DR; 1364 serial_out(up, UART_IER, up->ier); 1365} 1366 1367static void serial8250_enable_ms(struct uart_port *port) 1368{ 1369 struct uart_8250_port *up = (struct uart_8250_port *)port; 1370 1371 /* no MSR capabilities */ 1372 if (up->bugs & UART_BUG_NOMSR) 1373 return; 1374 1375 up->ier |= UART_IER_MSI; 1376 serial_out(up, UART_IER, up->ier); 1377} 1378 1379static void 1380receive_chars(struct uart_8250_port *up, unsigned int *status) 1381{ 1382 struct tty_struct *tty = up->port.state->port.tty; 1383 unsigned char ch, lsr = *status; 1384 int max_count = 256; 1385 char flag; 1386 1387 do { 1388 if (likely(lsr & UART_LSR_DR)) 1389 ch = serial_inp(up, UART_RX); 1390 else 1391 /* 1392 * Intel 82571 has a Serial Over Lan device that will 1393 * set UART_LSR_BI without setting UART_LSR_DR when 1394 * it receives a break. To avoid reading from the 1395 * receive buffer without UART_LSR_DR bit set, we 1396 * just force the read character to be 0 1397 */ 1398 ch = 0; 1399 1400 flag = TTY_NORMAL; 1401 up->port.icount.rx++; 1402 1403 lsr |= up->lsr_saved_flags; 1404 up->lsr_saved_flags = 0; 1405 1406 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { 1407 /* 1408 * For statistics only 1409 */ 1410 if (lsr & UART_LSR_BI) { 1411 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 1412 up->port.icount.brk++; 1413 /* 1414 * We do the SysRQ and SAK checking 1415 * here because otherwise the break 1416 * may get masked by ignore_status_mask 1417 * or read_status_mask. 1418 */ 1419 if (uart_handle_break(&up->port)) 1420 goto ignore_char; 1421 } else if (lsr & UART_LSR_PE) 1422 up->port.icount.parity++; 1423 else if (lsr & UART_LSR_FE) 1424 up->port.icount.frame++; 1425 if (lsr & UART_LSR_OE) 1426 up->port.icount.overrun++; 1427 1428 /* 1429 * Mask off conditions which should be ignored. 1430 */ 1431 lsr &= up->port.read_status_mask; 1432 1433 if (lsr & UART_LSR_BI) { 1434 DEBUG_INTR("handling break...."); 1435 flag = TTY_BREAK; 1436 } else if (lsr & UART_LSR_PE) 1437 flag = TTY_PARITY; 1438 else if (lsr & UART_LSR_FE) 1439 flag = TTY_FRAME; 1440 } 1441 if (uart_handle_sysrq_char(&up->port, ch)) 1442 goto ignore_char; 1443 1444 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); 1445 1446ignore_char: 1447 lsr = serial_inp(up, UART_LSR); 1448 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0)); 1449 spin_unlock(&up->port.lock); 1450 tty_flip_buffer_push(tty); 1451 spin_lock(&up->port.lock); 1452 *status = lsr; 1453} 1454 1455static void transmit_chars(struct uart_8250_port *up) 1456{ 1457 struct circ_buf *xmit = &up->port.state->xmit; 1458 int count; 1459 1460 if (up->port.x_char) { 1461 serial_outp(up, UART_TX, up->port.x_char); 1462 up->port.icount.tx++; 1463 up->port.x_char = 0; 1464 return; 1465 } 1466 if (uart_tx_stopped(&up->port)) { 1467 serial8250_stop_tx(&up->port); 1468 return; 1469 } 1470 if (uart_circ_empty(xmit)) { 1471 __stop_tx(up); 1472 return; 1473 } 1474 1475 count = up->tx_loadsz; 1476 do { 1477 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 1478 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1479 up->port.icount.tx++; 1480 if (uart_circ_empty(xmit)) 1481 break; 1482 } while (--count > 0); 1483 1484 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1485 uart_write_wakeup(&up->port); 1486 1487 DEBUG_INTR("THRE..."); 1488 1489 if (uart_circ_empty(xmit)) 1490 __stop_tx(up); 1491} 1492 1493static unsigned int check_modem_status(struct uart_8250_port *up) 1494{ 1495 unsigned int status = serial_in(up, UART_MSR); 1496 1497 status |= up->msr_saved_flags; 1498 up->msr_saved_flags = 0; 1499 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 1500 up->port.state != NULL) { 1501 if (status & UART_MSR_TERI) 1502 up->port.icount.rng++; 1503 if (status & UART_MSR_DDSR) 1504 up->port.icount.dsr++; 1505 if (status & UART_MSR_DDCD) 1506 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); 1507 if (status & UART_MSR_DCTS) 1508 uart_handle_cts_change(&up->port, status & UART_MSR_CTS); 1509 1510 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 1511 } 1512 1513 return status; 1514} 1515 1516/* 1517 * This handles the interrupt from one port. 1518 */ 1519static void serial8250_handle_port(struct uart_8250_port *up) 1520{ 1521 unsigned int status; 1522 unsigned long flags; 1523 1524 spin_lock_irqsave(&up->port.lock, flags); 1525 1526 status = serial_inp(up, UART_LSR); 1527 1528 DEBUG_INTR("status = %x...", status); 1529 1530 if (status & (UART_LSR_DR | UART_LSR_BI)) 1531 receive_chars(up, &status); 1532 check_modem_status(up); 1533 if (status & UART_LSR_THRE) 1534 transmit_chars(up); 1535 1536 spin_unlock_irqrestore(&up->port.lock, flags); 1537} 1538 1539/* 1540 * This is the serial driver's interrupt routine. 1541 * 1542 * Arjan thinks the old way was overly complex, so it got simplified. 1543 * Alan disagrees, saying that need the complexity to handle the weird 1544 * nature of ISA shared interrupts. (This is a special exception.) 1545 * 1546 * In order to handle ISA shared interrupts properly, we need to check 1547 * that all ports have been serviced, and therefore the ISA interrupt 1548 * line has been de-asserted. 1549 * 1550 * This means we need to loop through all ports. checking that they 1551 * don't have an interrupt pending. 1552 */ 1553static irqreturn_t serial8250_interrupt(int irq, void *dev_id) 1554{ 1555 struct irq_info *i = dev_id; 1556 struct list_head *l, *end = NULL; 1557 int pass_counter = 0, handled = 0; 1558 1559 DEBUG_INTR("serial8250_interrupt(%d)...", irq); 1560 1561 spin_lock(&i->lock); 1562 1563 l = i->head; 1564 do { 1565 struct uart_8250_port *up; 1566 unsigned int iir; 1567 1568 up = list_entry(l, struct uart_8250_port, list); 1569 1570 iir = serial_in(up, UART_IIR); 1571 if (!(iir & UART_IIR_NO_INT)) { 1572 serial8250_handle_port(up); 1573 1574 handled = 1; 1575 1576 end = NULL; 1577 } else if (up->port.iotype == UPIO_DWAPB && 1578 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 1579 /* The DesignWare APB UART has an Busy Detect (0x07) 1580 * interrupt meaning an LCR write attempt occured while the 1581 * UART was busy. The interrupt must be cleared by reading 1582 * the UART status register (USR) and the LCR re-written. */ 1583 unsigned int status; 1584 status = *(volatile u32 *)up->port.private_data; 1585 serial_out(up, UART_LCR, up->lcr); 1586 1587 handled = 1; 1588 1589 end = NULL; 1590 } else if (end == NULL) 1591 end = l; 1592 1593 l = l->next; 1594 1595 if (l == i->head && pass_counter++ > PASS_LIMIT) { 1596 /* If we hit this, we're dead. */ 1597 printk(KERN_ERR "serial8250: too much work for " 1598 "irq%d\n", irq); 1599 break; 1600 } 1601 } while (l != end); 1602 1603 spin_unlock(&i->lock); 1604 1605 DEBUG_INTR("end.\n"); 1606 1607 return IRQ_RETVAL(handled); 1608} 1609 1610/* 1611 * To support ISA shared interrupts, we need to have one interrupt 1612 * handler that ensures that the IRQ line has been deasserted 1613 * before returning. Failing to do this will result in the IRQ 1614 * line being stuck active, and, since ISA irqs are edge triggered, 1615 * no more IRQs will be seen. 1616 */ 1617static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up) 1618{ 1619 spin_lock_irq(&i->lock); 1620 1621 if (!list_empty(i->head)) { 1622 if (i->head == &up->list) 1623 i->head = i->head->next; 1624 list_del(&up->list); 1625 } else { 1626 BUG_ON(i->head != &up->list); 1627 i->head = NULL; 1628 } 1629 spin_unlock_irq(&i->lock); 1630 /* List empty so throw away the hash node */ 1631 if (i->head == NULL) { 1632 hlist_del(&i->node); 1633 kfree(i); 1634 } 1635} 1636 1637static int serial_link_irq_chain(struct uart_8250_port *up) 1638{ 1639 struct hlist_head *h; 1640 struct hlist_node *n; 1641 struct irq_info *i; 1642 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0; 1643 1644 mutex_lock(&hash_mutex); 1645 1646 h = &irq_lists[up->port.irq % NR_IRQ_HASH]; 1647 1648 hlist_for_each(n, h) { 1649 i = hlist_entry(n, struct irq_info, node); 1650 if (i->irq == up->port.irq) 1651 break; 1652 } 1653 1654 if (n == NULL) { 1655 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL); 1656 if (i == NULL) { 1657 mutex_unlock(&hash_mutex); 1658 return -ENOMEM; 1659 } 1660 spin_lock_init(&i->lock); 1661 i->irq = up->port.irq; 1662 hlist_add_head(&i->node, h); 1663 } 1664 mutex_unlock(&hash_mutex); 1665 1666 spin_lock_irq(&i->lock); 1667 1668 if (i->head) { 1669 list_add(&up->list, i->head); 1670 spin_unlock_irq(&i->lock); 1671 1672 ret = 0; 1673 } else { 1674 INIT_LIST_HEAD(&up->list); 1675 i->head = &up->list; 1676 spin_unlock_irq(&i->lock); 1677 irq_flags |= up->port.irqflags; 1678 ret = request_irq(up->port.irq, serial8250_interrupt, 1679 irq_flags, "serial", i); 1680 if (ret < 0) 1681 serial_do_unlink(i, up); 1682 } 1683 1684 return ret; 1685} 1686 1687static void serial_unlink_irq_chain(struct uart_8250_port *up) 1688{ 1689 struct irq_info *i; 1690 struct hlist_node *n; 1691 struct hlist_head *h; 1692 1693 mutex_lock(&hash_mutex); 1694 1695 h = &irq_lists[up->port.irq % NR_IRQ_HASH]; 1696 1697 hlist_for_each(n, h) { 1698 i = hlist_entry(n, struct irq_info, node); 1699 if (i->irq == up->port.irq) 1700 break; 1701 } 1702 1703 BUG_ON(n == NULL); 1704 BUG_ON(i->head == NULL); 1705 1706 if (list_empty(i->head)) 1707 free_irq(up->port.irq, i); 1708 1709 serial_do_unlink(i, up); 1710 mutex_unlock(&hash_mutex); 1711} 1712 1713/* Base timer interval for polling */ 1714static inline int poll_timeout(int timeout) 1715{ 1716 return timeout > 6 ? (timeout / 2 - 2) : 1; 1717} 1718 1719/* 1720 * This function is used to handle ports that do not have an 1721 * interrupt. This doesn't work very well for 16450's, but gives 1722 * barely passable results for a 16550A. (Although at the expense 1723 * of much CPU overhead). 1724 */ 1725static void serial8250_timeout(unsigned long data) 1726{ 1727 struct uart_8250_port *up = (struct uart_8250_port *)data; 1728 unsigned int iir; 1729 1730 iir = serial_in(up, UART_IIR); 1731 if (!(iir & UART_IIR_NO_INT)) 1732 serial8250_handle_port(up); 1733 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout)); 1734} 1735 1736static void serial8250_backup_timeout(unsigned long data) 1737{ 1738 struct uart_8250_port *up = (struct uart_8250_port *)data; 1739 unsigned int iir, ier = 0, lsr; 1740 unsigned long flags; 1741 1742 /* 1743 * Must disable interrupts or else we risk racing with the interrupt 1744 * based handler. 1745 */ 1746 if (is_real_interrupt(up->port.irq)) { 1747 ier = serial_in(up, UART_IER); 1748 serial_out(up, UART_IER, 0); 1749 } 1750 1751 iir = serial_in(up, UART_IIR); 1752 1753 /* 1754 * This should be a safe test for anyone who doesn't trust the 1755 * IIR bits on their UART, but it's specifically designed for 1756 * the "Diva" UART used on the management processor on many HP 1757 * ia64 and parisc boxes. 1758 */ 1759 spin_lock_irqsave(&up->port.lock, flags); 1760 lsr = serial_in(up, UART_LSR); 1761 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; 1762 spin_unlock_irqrestore(&up->port.lock, flags); 1763 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) && 1764 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) && 1765 (lsr & UART_LSR_THRE)) { 1766 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT); 1767 iir |= UART_IIR_THRI; 1768 } 1769 1770 if (!(iir & UART_IIR_NO_INT)) 1771 serial8250_handle_port(up); 1772 1773 if (is_real_interrupt(up->port.irq)) 1774 serial_out(up, UART_IER, ier); 1775 1776 /* Standard timer interval plus 0.2s to keep the port running */ 1777 mod_timer(&up->timer, 1778 jiffies + poll_timeout(up->port.timeout) + HZ / 5); 1779} 1780 1781static unsigned int serial8250_tx_empty(struct uart_port *port) 1782{ 1783 struct uart_8250_port *up = (struct uart_8250_port *)port; 1784 unsigned long flags; 1785 unsigned int lsr; 1786 1787 spin_lock_irqsave(&up->port.lock, flags); 1788 lsr = serial_in(up, UART_LSR); 1789 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; 1790 spin_unlock_irqrestore(&up->port.lock, flags); 1791 1792 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0; 1793} 1794 1795static unsigned int serial8250_get_mctrl(struct uart_port *port) 1796{ 1797 struct uart_8250_port *up = (struct uart_8250_port *)port; 1798 unsigned int status; 1799 unsigned int ret; 1800 1801 status = check_modem_status(up); 1802 1803 ret = 0; 1804 if (status & UART_MSR_DCD) 1805 ret |= TIOCM_CAR; 1806 if (status & UART_MSR_RI) 1807 ret |= TIOCM_RNG; 1808 if (status & UART_MSR_DSR) 1809 ret |= TIOCM_DSR; 1810 if (status & UART_MSR_CTS) 1811 ret |= TIOCM_CTS; 1812 return ret; 1813} 1814 1815static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 1816{ 1817 struct uart_8250_port *up = (struct uart_8250_port *)port; 1818 unsigned char mcr = 0; 1819 1820 if (mctrl & TIOCM_RTS) 1821 mcr |= UART_MCR_RTS; 1822 if (mctrl & TIOCM_DTR) 1823 mcr |= UART_MCR_DTR; 1824 if (mctrl & TIOCM_OUT1) 1825 mcr |= UART_MCR_OUT1; 1826 if (mctrl & TIOCM_OUT2) 1827 mcr |= UART_MCR_OUT2; 1828 if (mctrl & TIOCM_LOOP) 1829 mcr |= UART_MCR_LOOP; 1830 1831 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr; 1832 1833 serial_out(up, UART_MCR, mcr); 1834} 1835 1836static void serial8250_break_ctl(struct uart_port *port, int break_state) 1837{ 1838 struct uart_8250_port *up = (struct uart_8250_port *)port; 1839 unsigned long flags; 1840 1841 spin_lock_irqsave(&up->port.lock, flags); 1842 if (break_state == -1) 1843 up->lcr |= UART_LCR_SBC; 1844 else 1845 up->lcr &= ~UART_LCR_SBC; 1846 serial_out(up, UART_LCR, up->lcr); 1847 spin_unlock_irqrestore(&up->port.lock, flags); 1848} 1849 1850/* 1851 * Wait for transmitter & holding register to empty 1852 */ 1853static void wait_for_xmitr(struct uart_8250_port *up, int bits) 1854{ 1855 unsigned int status, tmout = 10000; 1856 1857 /* Wait up to 10ms for the character(s) to be sent. */ 1858 do { 1859 status = serial_in(up, UART_LSR); 1860 1861 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS; 1862 1863 if (--tmout == 0) 1864 break; 1865 udelay(1); 1866 } while ((status & bits) != bits); 1867 1868 /* Wait up to 1s for flow control if necessary */ 1869 if (up->port.flags & UPF_CONS_FLOW) { 1870 unsigned int tmout; 1871 for (tmout = 1000000; tmout; tmout--) { 1872 unsigned int msr = serial_in(up, UART_MSR); 1873 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 1874 if (msr & UART_MSR_CTS) 1875 break; 1876 udelay(1); 1877 touch_nmi_watchdog(); 1878 } 1879 } 1880} 1881 1882#ifdef CONFIG_CONSOLE_POLL 1883/* 1884 * Console polling routines for writing and reading from the uart while 1885 * in an interrupt or debug context. 1886 */ 1887 1888static int serial8250_get_poll_char(struct uart_port *port) 1889{ 1890 struct uart_8250_port *up = (struct uart_8250_port *)port; 1891 unsigned char lsr = serial_inp(up, UART_LSR); 1892 1893 if (!(lsr & UART_LSR_DR)) 1894 return NO_POLL_CHAR; 1895 1896 return serial_inp(up, UART_RX); 1897} 1898 1899 1900static void serial8250_put_poll_char(struct uart_port *port, 1901 unsigned char c) 1902{ 1903 unsigned int ier; 1904 struct uart_8250_port *up = (struct uart_8250_port *)port; 1905 1906 /* 1907 * First save the IER then disable the interrupts 1908 */ 1909 ier = serial_in(up, UART_IER); 1910 if (up->capabilities & UART_CAP_UUE) 1911 serial_out(up, UART_IER, UART_IER_UUE); 1912 else 1913 serial_out(up, UART_IER, 0); 1914 1915 wait_for_xmitr(up, BOTH_EMPTY); 1916 /* 1917 * Send the character out. 1918 * If a LF, also do CR... 1919 */ 1920 serial_out(up, UART_TX, c); 1921 if (c == 10) { 1922 wait_for_xmitr(up, BOTH_EMPTY); 1923 serial_out(up, UART_TX, 13); 1924 } 1925 1926 /* 1927 * Finally, wait for transmitter to become empty 1928 * and restore the IER 1929 */ 1930 wait_for_xmitr(up, BOTH_EMPTY); 1931 serial_out(up, UART_IER, ier); 1932} 1933 1934#endif /* CONFIG_CONSOLE_POLL */ 1935 1936static int serial8250_startup(struct uart_port *port) 1937{ 1938 struct uart_8250_port *up = (struct uart_8250_port *)port; 1939 unsigned long flags; 1940 unsigned char lsr, iir; 1941 int retval; 1942 1943 up->capabilities = uart_config[up->port.type].flags; 1944 up->mcr = 0; 1945 1946 if (up->port.iotype != up->cur_iotype) 1947 set_io_from_upio(port); 1948 1949 if (up->port.type == PORT_16C950) { 1950 /* Wake up and initialize UART */ 1951 up->acr = 0; 1952 serial_outp(up, UART_LCR, 0xBF); 1953 serial_outp(up, UART_EFR, UART_EFR_ECB); 1954 serial_outp(up, UART_IER, 0); 1955 serial_outp(up, UART_LCR, 0); 1956 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ 1957 serial_outp(up, UART_LCR, 0xBF); 1958 serial_outp(up, UART_EFR, UART_EFR_ECB); 1959 serial_outp(up, UART_LCR, 0); 1960 } 1961 1962#ifdef CONFIG_SERIAL_8250_RSA 1963 /* 1964 * If this is an RSA port, see if we can kick it up to the 1965 * higher speed clock. 1966 */ 1967 enable_rsa(up); 1968#endif 1969 1970 /* 1971 * Clear the FIFO buffers and disable them. 1972 * (they will be reenabled in set_termios()) 1973 */ 1974 serial8250_clear_fifos(up); 1975 1976 /* 1977 * Clear the interrupt registers. 1978 */ 1979 (void) serial_inp(up, UART_LSR); 1980 (void) serial_inp(up, UART_RX); 1981 (void) serial_inp(up, UART_IIR); 1982 (void) serial_inp(up, UART_MSR); 1983 1984 /* 1985 * At this point, there's no way the LSR could still be 0xff; 1986 * if it is, then bail out, because there's likely no UART 1987 * here. 1988 */ 1989 if (!(up->port.flags & UPF_BUGGY_UART) && 1990 (serial_inp(up, UART_LSR) == 0xff)) { 1991 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n", 1992 serial_index(&up->port)); 1993 return -ENODEV; 1994 } 1995 1996 /* 1997 * For a XR16C850, we need to set the trigger levels 1998 */ 1999 if (up->port.type == PORT_16850) { 2000 unsigned char fctr; 2001 2002 serial_outp(up, UART_LCR, 0xbf); 2003 2004 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX); 2005 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX); 2006 serial_outp(up, UART_TRG, UART_TRG_96); 2007 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX); 2008 serial_outp(up, UART_TRG, UART_TRG_96); 2009 2010 serial_outp(up, UART_LCR, 0); 2011 } 2012 2013 if (is_real_interrupt(up->port.irq)) { 2014 unsigned char iir1; 2015 /* 2016 * Test for UARTs that do not reassert THRE when the 2017 * transmitter is idle and the interrupt has already 2018 * been cleared. Real 16550s should always reassert 2019 * this interrupt whenever the transmitter is idle and 2020 * the interrupt is enabled. Delays are necessary to 2021 * allow register changes to become visible. 2022 */ 2023 spin_lock_irqsave(&up->port.lock, flags); 2024 if (up->port.irqflags & IRQF_SHARED) 2025 disable_irq_nosync(up->port.irq); 2026 2027 wait_for_xmitr(up, UART_LSR_THRE); 2028 serial_out_sync(up, UART_IER, UART_IER_THRI); 2029 udelay(1); /* allow THRE to set */ 2030 iir1 = serial_in(up, UART_IIR); 2031 serial_out(up, UART_IER, 0); 2032 serial_out_sync(up, UART_IER, UART_IER_THRI); 2033 udelay(1); /* allow a working UART time to re-assert THRE */ 2034 iir = serial_in(up, UART_IIR); 2035 serial_out(up, UART_IER, 0); 2036 2037 if (up->port.irqflags & IRQF_SHARED) 2038 enable_irq(up->port.irq); 2039 spin_unlock_irqrestore(&up->port.lock, flags); 2040 2041 /* 2042 * If the interrupt is not reasserted, setup a timer to 2043 * kick the UART on a regular basis. 2044 */ 2045 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) { 2046 up->bugs |= UART_BUG_THRE; 2047 pr_debug("ttyS%d - using backup timer\n", 2048 serial_index(port)); 2049 } 2050 } 2051 2052 /* 2053 * The above check will only give an accurate result the first time 2054 * the port is opened so this value needs to be preserved. 2055 */ 2056 if (up->bugs & UART_BUG_THRE) { 2057 up->timer.function = serial8250_backup_timeout; 2058 up->timer.data = (unsigned long)up; 2059 mod_timer(&up->timer, jiffies + 2060 poll_timeout(up->port.timeout) + HZ / 5); 2061 } 2062 2063 /* 2064 * If the "interrupt" for this port doesn't correspond with any 2065 * hardware interrupt, we use a timer-based system. The original 2066 * driver used to do this with IRQ0. 2067 */ 2068 if (!is_real_interrupt(up->port.irq)) { 2069 up->timer.data = (unsigned long)up; 2070 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout)); 2071 } else { 2072 retval = serial_link_irq_chain(up); 2073 if (retval) 2074 return retval; 2075 } 2076 2077 /* 2078 * Now, initialize the UART 2079 */ 2080 serial_outp(up, UART_LCR, UART_LCR_WLEN8); 2081 2082 spin_lock_irqsave(&up->port.lock, flags); 2083 if (up->port.flags & UPF_FOURPORT) { 2084 if (!is_real_interrupt(up->port.irq)) 2085 up->port.mctrl |= TIOCM_OUT1; 2086 } else 2087 /* 2088 * Most PC uarts need OUT2 raised to enable interrupts. 2089 */ 2090 if (is_real_interrupt(up->port.irq)) 2091 up->port.mctrl |= TIOCM_OUT2; 2092 2093 serial8250_set_mctrl(&up->port, up->port.mctrl); 2094 2095 /* Serial over Lan (SoL) hack: 2096 Intel 8257x Gigabit ethernet chips have a 2097 16550 emulation, to be used for Serial Over Lan. 2098 Those chips take a longer time than a normal 2099 serial device to signalize that a transmission 2100 data was queued. Due to that, the above test generally 2101 fails. One solution would be to delay the reading of 2102 iir. However, this is not reliable, since the timeout 2103 is variable. So, let's just don't test if we receive 2104 TX irq. This way, we'll never enable UART_BUG_TXEN. 2105 */ 2106 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST) 2107 goto dont_test_tx_en; 2108 2109 /* 2110 * Do a quick test to see if we receive an 2111 * interrupt when we enable the TX irq. 2112 */ 2113 serial_outp(up, UART_IER, UART_IER_THRI); 2114 lsr = serial_in(up, UART_LSR); 2115 iir = serial_in(up, UART_IIR); 2116 serial_outp(up, UART_IER, 0); 2117 2118 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) { 2119 if (!(up->bugs & UART_BUG_TXEN)) { 2120 up->bugs |= UART_BUG_TXEN; 2121 pr_debug("ttyS%d - enabling bad tx status workarounds\n", 2122 serial_index(port)); 2123 } 2124 } else { 2125 up->bugs &= ~UART_BUG_TXEN; 2126 } 2127 2128dont_test_tx_en: 2129 spin_unlock_irqrestore(&up->port.lock, flags); 2130 2131 /* 2132 * Clear the interrupt registers again for luck, and clear the 2133 * saved flags to avoid getting false values from polling 2134 * routines or the previous session. 2135 */ 2136 serial_inp(up, UART_LSR); 2137 serial_inp(up, UART_RX); 2138 serial_inp(up, UART_IIR); 2139 serial_inp(up, UART_MSR); 2140 up->lsr_saved_flags = 0; 2141 up->msr_saved_flags = 0; 2142 2143 /* 2144 * Finally, enable interrupts. Note: Modem status interrupts 2145 * are set via set_termios(), which will be occurring imminently 2146 * anyway, so we don't enable them here. 2147 */ 2148 up->ier = UART_IER_RLSI | UART_IER_RDI; 2149 serial_outp(up, UART_IER, up->ier); 2150 2151 if (up->port.flags & UPF_FOURPORT) { 2152 unsigned int icp; 2153 /* 2154 * Enable interrupts on the AST Fourport board 2155 */ 2156 icp = (up->port.iobase & 0xfe0) | 0x01f; 2157 outb_p(0x80, icp); 2158 (void) inb_p(icp); 2159 } 2160 2161 return 0; 2162} 2163 2164static void serial8250_shutdown(struct uart_port *port) 2165{ 2166 struct uart_8250_port *up = (struct uart_8250_port *)port; 2167 unsigned long flags; 2168 2169 /* 2170 * Disable interrupts from this port 2171 */ 2172 up->ier = 0; 2173 serial_outp(up, UART_IER, 0); 2174 2175 spin_lock_irqsave(&up->port.lock, flags); 2176 if (up->port.flags & UPF_FOURPORT) { 2177 /* reset interrupts on the AST Fourport board */ 2178 inb((up->port.iobase & 0xfe0) | 0x1f); 2179 up->port.mctrl |= TIOCM_OUT1; 2180 } else 2181 up->port.mctrl &= ~TIOCM_OUT2; 2182 2183 serial8250_set_mctrl(&up->port, up->port.mctrl); 2184 spin_unlock_irqrestore(&up->port.lock, flags); 2185 2186 /* 2187 * Disable break condition and FIFOs 2188 */ 2189 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC); 2190 serial8250_clear_fifos(up); 2191 2192#ifdef CONFIG_SERIAL_8250_RSA 2193 /* 2194 * Reset the RSA board back to 115kbps compat mode. 2195 */ 2196 disable_rsa(up); 2197#endif 2198 2199 /* 2200 * Read data port to reset things, and then unlink from 2201 * the IRQ chain. 2202 */ 2203 (void) serial_in(up, UART_RX); 2204 2205 del_timer_sync(&up->timer); 2206 up->timer.function = serial8250_timeout; 2207 if (is_real_interrupt(up->port.irq)) 2208 serial_unlink_irq_chain(up); 2209} 2210 2211static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud) 2212{ 2213 unsigned int quot; 2214 2215 /* 2216 * Handle magic divisors for baud rates above baud_base on 2217 * SMSC SuperIO chips. 2218 */ 2219 if ((port->flags & UPF_MAGIC_MULTIPLIER) && 2220 baud == (port->uartclk/4)) 2221 quot = 0x8001; 2222 else if ((port->flags & UPF_MAGIC_MULTIPLIER) && 2223 baud == (port->uartclk/8)) 2224 quot = 0x8002; 2225 else 2226 quot = uart_get_divisor(port, baud); 2227 2228 return quot; 2229} 2230 2231void 2232serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios, 2233 struct ktermios *old) 2234{ 2235 struct uart_8250_port *up = (struct uart_8250_port *)port; 2236 unsigned char cval, fcr = 0; 2237 unsigned long flags; 2238 unsigned int baud, quot; 2239 2240 switch (termios->c_cflag & CSIZE) { 2241 case CS5: 2242 cval = UART_LCR_WLEN5; 2243 break; 2244 case CS6: 2245 cval = UART_LCR_WLEN6; 2246 break; 2247 case CS7: 2248 cval = UART_LCR_WLEN7; 2249 break; 2250 default: 2251 case CS8: 2252 cval = UART_LCR_WLEN8; 2253 break; 2254 } 2255 2256 if (termios->c_cflag & CSTOPB) 2257 cval |= UART_LCR_STOP; 2258 if (termios->c_cflag & PARENB) 2259 cval |= UART_LCR_PARITY; 2260 if (!(termios->c_cflag & PARODD)) 2261 cval |= UART_LCR_EPAR; 2262#ifdef CMSPAR 2263 if (termios->c_cflag & CMSPAR) 2264 cval |= UART_LCR_SPAR; 2265#endif 2266 2267 /* 2268 * Ask the core to calculate the divisor for us. 2269 */ 2270 baud = uart_get_baud_rate(port, termios, old, 2271 port->uartclk / 16 / 0xffff, 2272 port->uartclk / 16); 2273 quot = serial8250_get_divisor(port, baud); 2274 2275 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0) 2276 quot++; 2277 2278 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) { 2279 if (baud < 2400) 2280 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1; 2281 else 2282 fcr = uart_config[up->port.type].fcr; 2283 } 2284 2285 /* 2286 * MCR-based auto flow control. When AFE is enabled, RTS will be 2287 * deasserted when the receive FIFO contains more characters than 2288 * the trigger, or the MCR RTS bit is cleared. In the case where 2289 * the remote UART is not using CTS auto flow control, we must 2290 * have sufficient FIFO entries for the latency of the remote 2291 * UART to respond. IOW, at least 32 bytes of FIFO. 2292 */ 2293 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) { 2294 up->mcr &= ~UART_MCR_AFE; 2295 if (termios->c_cflag & CRTSCTS) 2296 up->mcr |= UART_MCR_AFE; 2297 } 2298 2299 /* 2300 * Ok, we're now changing the port state. Do it with 2301 * interrupts disabled. 2302 */ 2303 spin_lock_irqsave(&up->port.lock, flags); 2304 2305 /* 2306 * Update the per-port timeout. 2307 */ 2308 uart_update_timeout(port, termios->c_cflag, baud); 2309 2310 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 2311 if (termios->c_iflag & INPCK) 2312 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 2313 if (termios->c_iflag & (BRKINT | PARMRK)) 2314 up->port.read_status_mask |= UART_LSR_BI; 2315 2316 /* 2317 * Characteres to ignore 2318 */ 2319 up->port.ignore_status_mask = 0; 2320 if (termios->c_iflag & IGNPAR) 2321 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 2322 if (termios->c_iflag & IGNBRK) { 2323 up->port.ignore_status_mask |= UART_LSR_BI; 2324 /* 2325 * If we're ignoring parity and break indicators, 2326 * ignore overruns too (for real raw support). 2327 */ 2328 if (termios->c_iflag & IGNPAR) 2329 up->port.ignore_status_mask |= UART_LSR_OE; 2330 } 2331 2332 /* 2333 * ignore all characters if CREAD is not set 2334 */ 2335 if ((termios->c_cflag & CREAD) == 0) 2336 up->port.ignore_status_mask |= UART_LSR_DR; 2337 2338 /* 2339 * CTS flow control flag and modem status interrupts 2340 */ 2341 up->ier &= ~UART_IER_MSI; 2342 if (!(up->bugs & UART_BUG_NOMSR) && 2343 UART_ENABLE_MS(&up->port, termios->c_cflag)) 2344 up->ier |= UART_IER_MSI; 2345 if (up->capabilities & UART_CAP_UUE) 2346 up->ier |= UART_IER_UUE | UART_IER_RTOIE; 2347 2348 serial_out(up, UART_IER, up->ier); 2349 2350 if (up->capabilities & UART_CAP_EFR) { 2351 unsigned char efr = 0; 2352 if (termios->c_cflag & CRTSCTS) 2353 efr |= UART_EFR_CTS; 2354 2355 serial_outp(up, UART_LCR, 0xBF); 2356 serial_outp(up, UART_EFR, efr); 2357 } 2358 2359#ifdef CONFIG_ARCH_OMAP 2360 if (cpu_is_omap1510() && is_omap_port(up)) { 2361 if (baud == 115200) { 2362 quot = 1; 2363 serial_out(up, UART_OMAP_OSC_12M_SEL, 1); 2364 } else 2365 serial_out(up, UART_OMAP_OSC_12M_SEL, 0); 2366 } 2367#endif 2368 2369 if (up->capabilities & UART_NATSEMI) { 2370 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */ 2371 serial_outp(up, UART_LCR, 0xe0); 2372 } else { 2373 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */ 2374 } 2375 2376 serial_dl_write(up, quot); 2377 2378 /* 2379 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR 2380 * is written without DLAB set, this mode will be disabled. 2381 */ 2382 if (up->port.type == PORT_16750) 2383 serial_outp(up, UART_FCR, fcr); 2384 2385 serial_outp(up, UART_LCR, cval); /* reset DLAB */ 2386 up->lcr = cval; /* Save LCR */ 2387 if (up->port.type != PORT_16750) { 2388 if (fcr & UART_FCR_ENABLE_FIFO) { 2389 /* emulated UARTs (Lucent Venus 167x) need two steps */ 2390 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); 2391 } 2392 serial_outp(up, UART_FCR, fcr); /* set fcr */ 2393 } 2394 serial8250_set_mctrl(&up->port, up->port.mctrl); 2395 spin_unlock_irqrestore(&up->port.lock, flags); 2396 /* Don't rewrite B0 */ 2397 if (tty_termios_baud_rate(termios)) 2398 tty_termios_encode_baud_rate(termios, baud, baud); 2399} 2400EXPORT_SYMBOL(serial8250_do_set_termios); 2401 2402static void 2403serial8250_set_termios(struct uart_port *port, struct ktermios *termios, 2404 struct ktermios *old) 2405{ 2406 if (port->set_termios) 2407 port->set_termios(port, termios, old); 2408 else 2409 serial8250_do_set_termios(port, termios, old); 2410} 2411 2412static void 2413serial8250_set_ldisc(struct uart_port *port, int new) 2414{ 2415 if (new == N_PPS) { 2416 port->flags |= UPF_HARDPPS_CD; 2417 serial8250_enable_ms(port); 2418 } else 2419 port->flags &= ~UPF_HARDPPS_CD; 2420} 2421 2422static void 2423serial8250_pm(struct uart_port *port, unsigned int state, 2424 unsigned int oldstate) 2425{ 2426 struct uart_8250_port *p = (struct uart_8250_port *)port; 2427 2428 serial8250_set_sleep(p, state != 0); 2429 2430 if (p->pm) 2431 p->pm(port, state, oldstate); 2432} 2433 2434static unsigned int serial8250_port_size(struct uart_8250_port *pt) 2435{ 2436 if (pt->port.iotype == UPIO_AU) 2437 return 0x1000; 2438#ifdef CONFIG_ARCH_OMAP 2439 if (is_omap_port(pt)) 2440 return 0x16 << pt->port.regshift; 2441#endif 2442 return 8 << pt->port.regshift; 2443} 2444 2445/* 2446 * Resource handling. 2447 */ 2448static int serial8250_request_std_resource(struct uart_8250_port *up) 2449{ 2450 unsigned int size = serial8250_port_size(up); 2451 int ret = 0; 2452 2453 switch (up->port.iotype) { 2454 case UPIO_AU: 2455 case UPIO_TSI: 2456 case UPIO_MEM32: 2457 case UPIO_MEM: 2458 case UPIO_DWAPB: 2459 if (!up->port.mapbase) 2460 break; 2461 2462 if (!request_mem_region(up->port.mapbase, size, "serial")) { 2463 ret = -EBUSY; 2464 break; 2465 } 2466 2467 if (up->port.flags & UPF_IOREMAP) { 2468 up->port.membase = ioremap_nocache(up->port.mapbase, 2469 size); 2470 if (!up->port.membase) { 2471 release_mem_region(up->port.mapbase, size); 2472 ret = -ENOMEM; 2473 } 2474 } 2475 break; 2476 2477 case UPIO_HUB6: 2478 case UPIO_PORT: 2479 if (!request_region(up->port.iobase, size, "serial")) 2480 ret = -EBUSY; 2481 break; 2482 } 2483 return ret; 2484} 2485 2486static void serial8250_release_std_resource(struct uart_8250_port *up) 2487{ 2488 unsigned int size = serial8250_port_size(up); 2489 2490 switch (up->port.iotype) { 2491 case UPIO_AU: 2492 case UPIO_TSI: 2493 case UPIO_MEM32: 2494 case UPIO_MEM: 2495 case UPIO_DWAPB: 2496 if (!up->port.mapbase) 2497 break; 2498 2499 if (up->port.flags & UPF_IOREMAP) { 2500 iounmap(up->port.membase); 2501 up->port.membase = NULL; 2502 } 2503 2504 release_mem_region(up->port.mapbase, size); 2505 break; 2506 2507 case UPIO_HUB6: 2508 case UPIO_PORT: 2509 release_region(up->port.iobase, size); 2510 break; 2511 } 2512} 2513 2514static int serial8250_request_rsa_resource(struct uart_8250_port *up) 2515{ 2516 unsigned long start = UART_RSA_BASE << up->port.regshift; 2517 unsigned int size = 8 << up->port.regshift; 2518 int ret = -EINVAL; 2519 2520 switch (up->port.iotype) { 2521 case UPIO_HUB6: 2522 case UPIO_PORT: 2523 start += up->port.iobase; 2524 if (request_region(start, size, "serial-rsa")) 2525 ret = 0; 2526 else 2527 ret = -EBUSY; 2528 break; 2529 } 2530 2531 return ret; 2532} 2533 2534static void serial8250_release_rsa_resource(struct uart_8250_port *up) 2535{ 2536 unsigned long offset = UART_RSA_BASE << up->port.regshift; 2537 unsigned int size = 8 << up->port.regshift; 2538 2539 switch (up->port.iotype) { 2540 case UPIO_HUB6: 2541 case UPIO_PORT: 2542 release_region(up->port.iobase + offset, size); 2543 break; 2544 } 2545} 2546 2547static void serial8250_release_port(struct uart_port *port) 2548{ 2549 struct uart_8250_port *up = (struct uart_8250_port *)port; 2550 2551 serial8250_release_std_resource(up); 2552 if (up->port.type == PORT_RSA) 2553 serial8250_release_rsa_resource(up); 2554} 2555 2556static int serial8250_request_port(struct uart_port *port) 2557{ 2558 struct uart_8250_port *up = (struct uart_8250_port *)port; 2559 int ret = 0; 2560 2561 ret = serial8250_request_std_resource(up); 2562 if (ret == 0 && up->port.type == PORT_RSA) { 2563 ret = serial8250_request_rsa_resource(up); 2564 if (ret < 0) 2565 serial8250_release_std_resource(up); 2566 } 2567 2568 return ret; 2569} 2570 2571static void serial8250_config_port(struct uart_port *port, int flags) 2572{ 2573 struct uart_8250_port *up = (struct uart_8250_port *)port; 2574 int probeflags = PROBE_ANY; 2575 int ret; 2576 2577 /* 2578 * Find the region that we can probe for. This in turn 2579 * tells us whether we can probe for the type of port. 2580 */ 2581 ret = serial8250_request_std_resource(up); 2582 if (ret < 0) 2583 return; 2584 2585 ret = serial8250_request_rsa_resource(up); 2586 if (ret < 0) 2587 probeflags &= ~PROBE_RSA; 2588 2589 if (up->port.iotype != up->cur_iotype) 2590 set_io_from_upio(port); 2591 2592 if (flags & UART_CONFIG_TYPE) 2593 autoconfig(up, probeflags); 2594 2595 /* if access method is AU, it is a 16550 with a quirk */ 2596 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU) 2597 up->bugs |= UART_BUG_NOMSR; 2598 2599 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) 2600 autoconfig_irq(up); 2601 2602 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA) 2603 serial8250_release_rsa_resource(up); 2604 if (up->port.type == PORT_UNKNOWN) 2605 serial8250_release_std_resource(up); 2606} 2607 2608static int 2609serial8250_verify_port(struct uart_port *port, struct serial_struct *ser) 2610{ 2611 if (ser->irq >= nr_irqs || ser->irq < 0 || 2612 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || 2613 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS || 2614 ser->type == PORT_STARTECH) 2615 return -EINVAL; 2616 return 0; 2617} 2618 2619static const char * 2620serial8250_type(struct uart_port *port) 2621{ 2622 int type = port->type; 2623 2624 if (type >= ARRAY_SIZE(uart_config)) 2625 type = 0; 2626 return uart_config[type].name; 2627} 2628 2629static struct uart_ops serial8250_pops = { 2630 .tx_empty = serial8250_tx_empty, 2631 .set_mctrl = serial8250_set_mctrl, 2632 .get_mctrl = serial8250_get_mctrl, 2633 .stop_tx = serial8250_stop_tx, 2634 .start_tx = serial8250_start_tx, 2635 .stop_rx = serial8250_stop_rx, 2636 .enable_ms = serial8250_enable_ms, 2637 .break_ctl = serial8250_break_ctl, 2638 .startup = serial8250_startup, 2639 .shutdown = serial8250_shutdown, 2640 .set_termios = serial8250_set_termios, 2641 .set_ldisc = serial8250_set_ldisc, 2642 .pm = serial8250_pm, 2643 .type = serial8250_type, 2644 .release_port = serial8250_release_port, 2645 .request_port = serial8250_request_port, 2646 .config_port = serial8250_config_port, 2647 .verify_port = serial8250_verify_port, 2648#ifdef CONFIG_CONSOLE_POLL 2649 .poll_get_char = serial8250_get_poll_char, 2650 .poll_put_char = serial8250_put_poll_char, 2651#endif 2652}; 2653 2654static struct uart_8250_port serial8250_ports[UART_NR]; 2655 2656static void __init serial8250_isa_init_ports(void) 2657{ 2658 struct uart_8250_port *up; 2659 static int first = 1; 2660 int i, irqflag = 0; 2661 2662 if (!first) 2663 return; 2664 first = 0; 2665 2666 for (i = 0; i < nr_uarts; i++) { 2667 struct uart_8250_port *up = &serial8250_ports[i]; 2668 2669 up->port.line = i; 2670 spin_lock_init(&up->port.lock); 2671 2672 init_timer(&up->timer); 2673 up->timer.function = serial8250_timeout; 2674 2675 /* 2676 * ALPHA_KLUDGE_MCR needs to be killed. 2677 */ 2678 up->mcr_mask = ~ALPHA_KLUDGE_MCR; 2679 up->mcr_force = ALPHA_KLUDGE_MCR; 2680 2681 up->port.ops = &serial8250_pops; 2682 } 2683 2684 if (share_irqs) 2685 irqflag = IRQF_SHARED; 2686 2687 for (i = 0, up = serial8250_ports; 2688 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts; 2689 i++, up++) { 2690 up->port.iobase = old_serial_port[i].port; 2691 up->port.irq = irq_canonicalize(old_serial_port[i].irq); 2692 up->port.irqflags = old_serial_port[i].irqflags; 2693 up->port.uartclk = old_serial_port[i].baud_base * 16; 2694 up->port.flags = old_serial_port[i].flags; 2695 up->port.hub6 = old_serial_port[i].hub6; 2696 up->port.membase = old_serial_port[i].iomem_base; 2697 up->port.iotype = old_serial_port[i].io_type; 2698 up->port.regshift = old_serial_port[i].iomem_reg_shift; 2699 set_io_from_upio(&up->port); 2700 up->port.irqflags |= irqflag; 2701 } 2702} 2703 2704static void 2705serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type) 2706{ 2707 up->port.type = type; 2708 up->port.fifosize = uart_config[type].fifo_size; 2709 up->capabilities = uart_config[type].flags; 2710 up->tx_loadsz = uart_config[type].tx_loadsz; 2711} 2712 2713static void __init 2714serial8250_register_ports(struct uart_driver *drv, struct device *dev) 2715{ 2716 int i; 2717 2718 for (i = 0; i < nr_uarts; i++) { 2719 struct uart_8250_port *up = &serial8250_ports[i]; 2720 up->cur_iotype = 0xFF; 2721 } 2722 2723 serial8250_isa_init_ports(); 2724 2725 for (i = 0; i < nr_uarts; i++) { 2726 struct uart_8250_port *up = &serial8250_ports[i]; 2727 2728 up->port.dev = dev; 2729 2730 if (up->port.flags & UPF_FIXED_TYPE) 2731 serial8250_init_fixed_type_port(up, up->port.type); 2732 2733 uart_add_one_port(drv, &up->port); 2734 } 2735} 2736 2737#ifdef CONFIG_SERIAL_8250_CONSOLE 2738 2739static void serial8250_console_putchar(struct uart_port *port, int ch) 2740{ 2741 struct uart_8250_port *up = (struct uart_8250_port *)port; 2742 2743 wait_for_xmitr(up, UART_LSR_THRE); 2744 serial_out(up, UART_TX, ch); 2745} 2746 2747/* 2748 * Print a string to the serial port trying not to disturb 2749 * any possible real use of the port... 2750 * 2751 * The console_lock must be held when we get here. 2752 */ 2753static void 2754serial8250_console_write(struct console *co, const char *s, unsigned int count) 2755{ 2756 struct uart_8250_port *up = &serial8250_ports[co->index]; 2757 unsigned long flags; 2758 unsigned int ier; 2759 int locked = 1; 2760 2761 touch_nmi_watchdog(); 2762 2763 local_irq_save(flags); 2764 if (up->port.sysrq) { 2765 /* serial8250_handle_port() already took the lock */ 2766 locked = 0; 2767 } else if (oops_in_progress) { 2768 locked = spin_trylock(&up->port.lock); 2769 } else 2770 spin_lock(&up->port.lock); 2771 2772 /* 2773 * First save the IER then disable the interrupts 2774 */ 2775 ier = serial_in(up, UART_IER); 2776 2777 if (up->capabilities & UART_CAP_UUE) 2778 serial_out(up, UART_IER, UART_IER_UUE); 2779 else 2780 serial_out(up, UART_IER, 0); 2781 2782 uart_console_write(&up->port, s, count, serial8250_console_putchar); 2783 2784 /* 2785 * Finally, wait for transmitter to become empty 2786 * and restore the IER 2787 */ 2788 wait_for_xmitr(up, BOTH_EMPTY); 2789 serial_out(up, UART_IER, ier); 2790 2791 /* 2792 * The receive handling will happen properly because the 2793 * receive ready bit will still be set; it is not cleared 2794 * on read. However, modem control will not, we must 2795 * call it if we have saved something in the saved flags 2796 * while processing with interrupts off. 2797 */ 2798 if (up->msr_saved_flags) 2799 check_modem_status(up); 2800 2801 if (locked) 2802 spin_unlock(&up->port.lock); 2803 local_irq_restore(flags); 2804} 2805 2806static int __init serial8250_console_setup(struct console *co, char *options) 2807{ 2808 struct uart_port *port; 2809 int baud = 9600; 2810 int bits = 8; 2811 int parity = 'n'; 2812 int flow = 'n'; 2813 2814 /* 2815 * Check whether an invalid uart number has been specified, and 2816 * if so, search for the first available port that does have 2817 * console support. 2818 */ 2819 if (co->index >= nr_uarts) 2820 co->index = 0; 2821 port = &serial8250_ports[co->index].port; 2822 if (!port->iobase && !port->membase) 2823 return -ENODEV; 2824 2825 if (options) 2826 uart_parse_options(options, &baud, &parity, &bits, &flow); 2827 2828 return uart_set_options(port, co, baud, parity, bits, flow); 2829} 2830 2831static int serial8250_console_early_setup(void) 2832{ 2833 return serial8250_find_port_for_earlycon(); 2834} 2835 2836static struct console serial8250_console = { 2837 .name = "ttyS", 2838 .write = serial8250_console_write, 2839 .device = uart_console_device, 2840 .setup = serial8250_console_setup, 2841 .early_setup = serial8250_console_early_setup, 2842 .flags = CON_PRINTBUFFER, 2843 .index = -1, 2844 .data = &serial8250_reg, 2845}; 2846 2847static int __init serial8250_console_init(void) 2848{ 2849 if (nr_uarts > UART_NR) 2850 nr_uarts = UART_NR; 2851 2852 serial8250_isa_init_ports(); 2853 register_console(&serial8250_console); 2854 return 0; 2855} 2856console_initcall(serial8250_console_init); 2857 2858int serial8250_find_port(struct uart_port *p) 2859{ 2860 int line; 2861 struct uart_port *port; 2862 2863 for (line = 0; line < nr_uarts; line++) { 2864 port = &serial8250_ports[line].port; 2865 if (uart_match_port(p, port)) 2866 return line; 2867 } 2868 return -ENODEV; 2869} 2870 2871#define SERIAL8250_CONSOLE &serial8250_console 2872#else 2873#define SERIAL8250_CONSOLE NULL 2874#endif 2875 2876static struct uart_driver serial8250_reg = { 2877 .owner = THIS_MODULE, 2878 .driver_name = "serial", 2879 .dev_name = "ttyS", 2880 .major = TTY_MAJOR, 2881 .minor = 64, 2882 .cons = SERIAL8250_CONSOLE, 2883}; 2884 2885/* 2886 * early_serial_setup - early registration for 8250 ports 2887 * 2888 * Setup an 8250 port structure prior to console initialisation. Use 2889 * after console initialisation will cause undefined behaviour. 2890 */ 2891int __init early_serial_setup(struct uart_port *port) 2892{ 2893 struct uart_port *p; 2894 2895 if (port->line >= ARRAY_SIZE(serial8250_ports)) 2896 return -ENODEV; 2897 2898 serial8250_isa_init_ports(); 2899 p = &serial8250_ports[port->line].port; 2900 p->iobase = port->iobase; 2901 p->membase = port->membase; 2902 p->irq = port->irq; 2903 p->irqflags = port->irqflags; 2904 p->uartclk = port->uartclk; 2905 p->fifosize = port->fifosize; 2906 p->regshift = port->regshift; 2907 p->iotype = port->iotype; 2908 p->flags = port->flags; 2909 p->mapbase = port->mapbase; 2910 p->private_data = port->private_data; 2911 p->type = port->type; 2912 p->line = port->line; 2913 2914 set_io_from_upio(p); 2915 if (port->serial_in) 2916 p->serial_in = port->serial_in; 2917 if (port->serial_out) 2918 p->serial_out = port->serial_out; 2919 2920 return 0; 2921} 2922 2923/** 2924 * serial8250_suspend_port - suspend one serial port 2925 * @line: serial line number 2926 * 2927 * Suspend one serial port. 2928 */ 2929void serial8250_suspend_port(int line) 2930{ 2931 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port); 2932} 2933 2934/** 2935 * serial8250_resume_port - resume one serial port 2936 * @line: serial line number 2937 * 2938 * Resume one serial port. 2939 */ 2940void serial8250_resume_port(int line) 2941{ 2942 struct uart_8250_port *up = &serial8250_ports[line]; 2943 2944 if (up->capabilities & UART_NATSEMI) { 2945 unsigned char tmp; 2946 2947 /* Ensure it's still in high speed mode */ 2948 serial_outp(up, UART_LCR, 0xE0); 2949 2950 tmp = serial_in(up, 0x04); /* EXCR2 */ 2951 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ 2952 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ 2953 serial_outp(up, 0x04, tmp); 2954 2955 serial_outp(up, UART_LCR, 0); 2956 } 2957 uart_resume_port(&serial8250_reg, &up->port); 2958} 2959 2960/* 2961 * Register a set of serial devices attached to a platform device. The 2962 * list is terminated with a zero flags entry, which means we expect 2963 * all entries to have at least UPF_BOOT_AUTOCONF set. 2964 */ 2965static int __devinit serial8250_probe(struct platform_device *dev) 2966{ 2967 struct plat_serial8250_port *p = dev->dev.platform_data; 2968 struct uart_port port; 2969 int ret, i, irqflag = 0; 2970 2971 memset(&port, 0, sizeof(struct uart_port)); 2972 2973 if (share_irqs) 2974 irqflag = IRQF_SHARED; 2975 2976 for (i = 0; p && p->flags != 0; p++, i++) { 2977 port.iobase = p->iobase; 2978 port.membase = p->membase; 2979 port.irq = p->irq; 2980 port.irqflags = p->irqflags; 2981 port.uartclk = p->uartclk; 2982 port.regshift = p->regshift; 2983 port.iotype = p->iotype; 2984 port.flags = p->flags; 2985 port.mapbase = p->mapbase; 2986 port.hub6 = p->hub6; 2987 port.private_data = p->private_data; 2988 port.type = p->type; 2989 port.serial_in = p->serial_in; 2990 port.serial_out = p->serial_out; 2991 port.set_termios = p->set_termios; 2992 port.dev = &dev->dev; 2993 port.irqflags |= irqflag; 2994 ret = serial8250_register_port(&port); 2995 if (ret < 0) { 2996 dev_err(&dev->dev, "unable to register port at index %d " 2997 "(IO%lx MEM%llx IRQ%d): %d\n", i, 2998 p->iobase, (unsigned long long)p->mapbase, 2999 p->irq, ret); 3000 } 3001 } 3002 return 0; 3003} 3004 3005/* 3006 * Remove serial ports registered against a platform device. 3007 */ 3008static int __devexit serial8250_remove(struct platform_device *dev) 3009{ 3010 int i; 3011 3012 for (i = 0; i < nr_uarts; i++) { 3013 struct uart_8250_port *up = &serial8250_ports[i]; 3014 3015 if (up->port.dev == &dev->dev) 3016 serial8250_unregister_port(i); 3017 } 3018 return 0; 3019} 3020 3021static int serial8250_suspend(struct platform_device *dev, pm_message_t state) 3022{ 3023 int i; 3024 3025 for (i = 0; i < UART_NR; i++) { 3026 struct uart_8250_port *up = &serial8250_ports[i]; 3027 3028 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) 3029 uart_suspend_port(&serial8250_reg, &up->port); 3030 } 3031 3032 return 0; 3033} 3034 3035static int serial8250_resume(struct platform_device *dev) 3036{ 3037 int i; 3038 3039 for (i = 0; i < UART_NR; i++) { 3040 struct uart_8250_port *up = &serial8250_ports[i]; 3041 3042 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) 3043 serial8250_resume_port(i); 3044 } 3045 3046 return 0; 3047} 3048 3049static struct platform_driver serial8250_isa_driver = { 3050 .probe = serial8250_probe, 3051 .remove = __devexit_p(serial8250_remove), 3052 .suspend = serial8250_suspend, 3053 .resume = serial8250_resume, 3054 .driver = { 3055 .name = "serial8250", 3056 .owner = THIS_MODULE, 3057 }, 3058}; 3059 3060/* 3061 * This "device" covers _all_ ISA 8250-compatible serial devices listed 3062 * in the table in include/asm/serial.h 3063 */ 3064static struct platform_device *serial8250_isa_devs; 3065 3066/* 3067 * serial8250_register_port and serial8250_unregister_port allows for 3068 * 16x50 serial ports to be configured at run-time, to support PCMCIA 3069 * modems and PCI multiport cards. 3070 */ 3071static DEFINE_MUTEX(serial_mutex); 3072 3073static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port) 3074{ 3075 int i; 3076 3077 /* 3078 * First, find a port entry which matches. 3079 */ 3080 for (i = 0; i < nr_uarts; i++) 3081 if (uart_match_port(&serial8250_ports[i].port, port)) 3082 return &serial8250_ports[i]; 3083 3084 /* 3085 * We didn't find a matching entry, so look for the first 3086 * free entry. We look for one which hasn't been previously 3087 * used (indicated by zero iobase). 3088 */ 3089 for (i = 0; i < nr_uarts; i++) 3090 if (serial8250_ports[i].port.type == PORT_UNKNOWN && 3091 serial8250_ports[i].port.iobase == 0) 3092 return &serial8250_ports[i]; 3093 3094 /* 3095 * That also failed. Last resort is to find any entry which 3096 * doesn't have a real port associated with it. 3097 */ 3098 for (i = 0; i < nr_uarts; i++) 3099 if (serial8250_ports[i].port.type == PORT_UNKNOWN) 3100 return &serial8250_ports[i]; 3101 3102 return NULL; 3103} 3104 3105/** 3106 * serial8250_register_port - register a serial port 3107 * @port: serial port template 3108 * 3109 * Configure the serial port specified by the request. If the 3110 * port exists and is in use, it is hung up and unregistered 3111 * first. 3112 * 3113 * The port is then probed and if necessary the IRQ is autodetected 3114 * If this fails an error is returned. 3115 * 3116 * On success the port is ready to use and the line number is returned. 3117 */ 3118int serial8250_register_port(struct uart_port *port) 3119{ 3120 struct uart_8250_port *uart; 3121 int ret = -ENOSPC; 3122 3123 if (port->uartclk == 0) 3124 return -EINVAL; 3125 3126 mutex_lock(&serial_mutex); 3127 3128 uart = serial8250_find_match_or_unused(port); 3129 if (uart) { 3130 uart_remove_one_port(&serial8250_reg, &uart->port); 3131 3132 uart->port.iobase = port->iobase; 3133 uart->port.membase = port->membase; 3134 uart->port.irq = port->irq; 3135 uart->port.irqflags = port->irqflags; 3136 uart->port.uartclk = port->uartclk; 3137 uart->port.fifosize = port->fifosize; 3138 uart->port.regshift = port->regshift; 3139 uart->port.iotype = port->iotype; 3140 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF; 3141 uart->port.mapbase = port->mapbase; 3142 uart->port.private_data = port->private_data; 3143 if (port->dev) 3144 uart->port.dev = port->dev; 3145 3146 if (port->flags & UPF_FIXED_TYPE) 3147 serial8250_init_fixed_type_port(uart, port->type); 3148 3149 set_io_from_upio(&uart->port); 3150 /* Possibly override default I/O functions. */ 3151 if (port->serial_in) 3152 uart->port.serial_in = port->serial_in; 3153 if (port->serial_out) 3154 uart->port.serial_out = port->serial_out; 3155 /* Possibly override set_termios call */ 3156 if (port->set_termios) 3157 uart->port.set_termios = port->set_termios; 3158 3159 ret = uart_add_one_port(&serial8250_reg, &uart->port); 3160 if (ret == 0) 3161 ret = uart->port.line; 3162 } 3163 mutex_unlock(&serial_mutex); 3164 3165 return ret; 3166} 3167EXPORT_SYMBOL(serial8250_register_port); 3168 3169/** 3170 * serial8250_unregister_port - remove a 16x50 serial port at runtime 3171 * @line: serial line number 3172 * 3173 * Remove one serial port. This may not be called from interrupt 3174 * context. We hand the port back to the our control. 3175 */ 3176void serial8250_unregister_port(int line) 3177{ 3178 struct uart_8250_port *uart = &serial8250_ports[line]; 3179 3180 mutex_lock(&serial_mutex); 3181 uart_remove_one_port(&serial8250_reg, &uart->port); 3182 if (serial8250_isa_devs) { 3183 uart->port.flags &= ~UPF_BOOT_AUTOCONF; 3184 uart->port.type = PORT_UNKNOWN; 3185 uart->port.dev = &serial8250_isa_devs->dev; 3186 uart_add_one_port(&serial8250_reg, &uart->port); 3187 } else { 3188 uart->port.dev = NULL; 3189 } 3190 mutex_unlock(&serial_mutex); 3191} 3192EXPORT_SYMBOL(serial8250_unregister_port); 3193 3194static int __init serial8250_init(void) 3195{ 3196 int ret; 3197 3198 if (nr_uarts > UART_NR) 3199 nr_uarts = UART_NR; 3200 3201 printk(KERN_INFO "Serial: 8250/16550 driver, " 3202 "%d ports, IRQ sharing %sabled\n", nr_uarts, 3203 share_irqs ? "en" : "dis"); 3204 3205#ifdef CONFIG_SPARC 3206 ret = sunserial_register_minors(&serial8250_reg, UART_NR); 3207#else 3208 serial8250_reg.nr = UART_NR; 3209 ret = uart_register_driver(&serial8250_reg); 3210#endif 3211 if (ret) 3212 goto out; 3213 3214 serial8250_isa_devs = platform_device_alloc("serial8250", 3215 PLAT8250_DEV_LEGACY); 3216 if (!serial8250_isa_devs) { 3217 ret = -ENOMEM; 3218 goto unreg_uart_drv; 3219 } 3220 3221 ret = platform_device_add(serial8250_isa_devs); 3222 if (ret) 3223 goto put_dev; 3224 3225 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev); 3226 3227 ret = platform_driver_register(&serial8250_isa_driver); 3228 if (ret == 0) 3229 goto out; 3230 3231 platform_device_del(serial8250_isa_devs); 3232put_dev: 3233 platform_device_put(serial8250_isa_devs); 3234unreg_uart_drv: 3235#ifdef CONFIG_SPARC 3236 sunserial_unregister_minors(&serial8250_reg, UART_NR); 3237#else 3238 uart_unregister_driver(&serial8250_reg); 3239#endif 3240out: 3241 return ret; 3242} 3243 3244static void __exit serial8250_exit(void) 3245{ 3246 struct platform_device *isa_dev = serial8250_isa_devs; 3247 3248 /* 3249 * This tells serial8250_unregister_port() not to re-register 3250 * the ports (thereby making serial8250_isa_driver permanently 3251 * in use.) 3252 */ 3253 serial8250_isa_devs = NULL; 3254 3255 platform_driver_unregister(&serial8250_isa_driver); 3256 platform_device_unregister(isa_dev); 3257 3258#ifdef CONFIG_SPARC 3259 sunserial_unregister_minors(&serial8250_reg, UART_NR); 3260#else 3261 uart_unregister_driver(&serial8250_reg); 3262#endif 3263} 3264 3265module_init(serial8250_init); 3266module_exit(serial8250_exit); 3267 3268EXPORT_SYMBOL(serial8250_suspend_port); 3269EXPORT_SYMBOL(serial8250_resume_port); 3270 3271MODULE_LICENSE("GPL"); 3272MODULE_DESCRIPTION("Generic 8250/16x50 serial driver"); 3273 3274module_param(share_irqs, uint, 0644); 3275MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices" 3276 " (unsafe)"); 3277 3278module_param(nr_uarts, uint, 0644); 3279MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")"); 3280 3281module_param(skip_txen_test, uint, 0644); 3282MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time"); 3283 3284#ifdef CONFIG_SERIAL_8250_RSA 3285module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444); 3286MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA"); 3287#endif 3288MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR); 3289