1/* 2 * Copyright (c) 2005-2009 Brocade Communications Systems, Inc. 3 * All rights reserved 4 * www.brocade.com 5 * 6 * Linux driver for Brocade Fibre Channel Host Bus Adapter. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License (GPL) Version 2 as 10 * published by the Free Software Foundation 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 */ 17 18/* 19 * bfi_cbreg.h crossbow host block register definitions 20 * 21 * !!! Do not edit. Auto generated. !!! 22 */ 23 24#ifndef __BFI_CBREG_H__ 25#define __BFI_CBREG_H__ 26 27 28#define HOSTFN0_INT_STATUS 0x00014000 29#define __HOSTFN0_INT_STATUS_LVL_MK 0x00f00000 30#define __HOSTFN0_INT_STATUS_LVL_SH 20 31#define __HOSTFN0_INT_STATUS_LVL(_v) ((_v) << __HOSTFN0_INT_STATUS_LVL_SH) 32#define __HOSTFN0_INT_STATUS_P 0x000fffff 33#define HOSTFN0_INT_MSK 0x00014004 34#define HOST_PAGE_NUM_FN0 0x00014008 35#define __HOST_PAGE_NUM_FN 0x000001ff 36#define HOSTFN1_INT_STATUS 0x00014100 37#define __HOSTFN1_INT_STAT_LVL_MK 0x00f00000 38#define __HOSTFN1_INT_STAT_LVL_SH 20 39#define __HOSTFN1_INT_STAT_LVL(_v) ((_v) << __HOSTFN1_INT_STAT_LVL_SH) 40#define __HOSTFN1_INT_STAT_P 0x000fffff 41#define HOSTFN1_INT_MSK 0x00014104 42#define HOST_PAGE_NUM_FN1 0x00014108 43#define APP_PLL_400_CTL_REG 0x00014204 44#define __P_400_PLL_LOCK 0x80000000 45#define __APP_PLL_400_SRAM_USE_100MHZ 0x00100000 46#define __APP_PLL_400_RESET_TIMER_MK 0x000e0000 47#define __APP_PLL_400_RESET_TIMER_SH 17 48#define __APP_PLL_400_RESET_TIMER(_v) ((_v) << __APP_PLL_400_RESET_TIMER_SH) 49#define __APP_PLL_400_LOGIC_SOFT_RESET 0x00010000 50#define __APP_PLL_400_CNTLMT0_1_MK 0x0000c000 51#define __APP_PLL_400_CNTLMT0_1_SH 14 52#define __APP_PLL_400_CNTLMT0_1(_v) ((_v) << __APP_PLL_400_CNTLMT0_1_SH) 53#define __APP_PLL_400_JITLMT0_1_MK 0x00003000 54#define __APP_PLL_400_JITLMT0_1_SH 12 55#define __APP_PLL_400_JITLMT0_1(_v) ((_v) << __APP_PLL_400_JITLMT0_1_SH) 56#define __APP_PLL_400_HREF 0x00000800 57#define __APP_PLL_400_HDIV 0x00000400 58#define __APP_PLL_400_P0_1_MK 0x00000300 59#define __APP_PLL_400_P0_1_SH 8 60#define __APP_PLL_400_P0_1(_v) ((_v) << __APP_PLL_400_P0_1_SH) 61#define __APP_PLL_400_Z0_2_MK 0x000000e0 62#define __APP_PLL_400_Z0_2_SH 5 63#define __APP_PLL_400_Z0_2(_v) ((_v) << __APP_PLL_400_Z0_2_SH) 64#define __APP_PLL_400_RSEL200500 0x00000010 65#define __APP_PLL_400_ENARST 0x00000008 66#define __APP_PLL_400_BYPASS 0x00000004 67#define __APP_PLL_400_LRESETN 0x00000002 68#define __APP_PLL_400_ENABLE 0x00000001 69#define APP_PLL_212_CTL_REG 0x00014208 70#define __P_212_PLL_LOCK 0x80000000 71#define __APP_PLL_212_RESET_TIMER_MK 0x000e0000 72#define __APP_PLL_212_RESET_TIMER_SH 17 73#define __APP_PLL_212_RESET_TIMER(_v) ((_v) << __APP_PLL_212_RESET_TIMER_SH) 74#define __APP_PLL_212_LOGIC_SOFT_RESET 0x00010000 75#define __APP_PLL_212_CNTLMT0_1_MK 0x0000c000 76#define __APP_PLL_212_CNTLMT0_1_SH 14 77#define __APP_PLL_212_CNTLMT0_1(_v) ((_v) << __APP_PLL_212_CNTLMT0_1_SH) 78#define __APP_PLL_212_JITLMT0_1_MK 0x00003000 79#define __APP_PLL_212_JITLMT0_1_SH 12 80#define __APP_PLL_212_JITLMT0_1(_v) ((_v) << __APP_PLL_212_JITLMT0_1_SH) 81#define __APP_PLL_212_HREF 0x00000800 82#define __APP_PLL_212_HDIV 0x00000400 83#define __APP_PLL_212_P0_1_MK 0x00000300 84#define __APP_PLL_212_P0_1_SH 8 85#define __APP_PLL_212_P0_1(_v) ((_v) << __APP_PLL_212_P0_1_SH) 86#define __APP_PLL_212_Z0_2_MK 0x000000e0 87#define __APP_PLL_212_Z0_2_SH 5 88#define __APP_PLL_212_Z0_2(_v) ((_v) << __APP_PLL_212_Z0_2_SH) 89#define __APP_PLL_212_RSEL200500 0x00000010 90#define __APP_PLL_212_ENARST 0x00000008 91#define __APP_PLL_212_BYPASS 0x00000004 92#define __APP_PLL_212_LRESETN 0x00000002 93#define __APP_PLL_212_ENABLE 0x00000001 94#define HOST_SEM0_REG 0x00014230 95#define __HOST_SEMAPHORE 0x00000001 96#define HOST_SEM1_REG 0x00014234 97#define HOST_SEM2_REG 0x00014238 98#define HOST_SEM3_REG 0x0001423c 99#define HOST_SEM0_INFO_REG 0x00014240 100#define HOST_SEM1_INFO_REG 0x00014244 101#define HOST_SEM2_INFO_REG 0x00014248 102#define HOST_SEM3_INFO_REG 0x0001424c 103#define HOSTFN0_LPU0_CMD_STAT 0x00019000 104#define __HOSTFN0_LPU0_MBOX_INFO_MK 0xfffffffe 105#define __HOSTFN0_LPU0_MBOX_INFO_SH 1 106#define __HOSTFN0_LPU0_MBOX_INFO(_v) ((_v) << __HOSTFN0_LPU0_MBOX_INFO_SH) 107#define __HOSTFN0_LPU0_MBOX_CMD_STATUS 0x00000001 108#define LPU0_HOSTFN0_CMD_STAT 0x00019008 109#define __LPU0_HOSTFN0_MBOX_INFO_MK 0xfffffffe 110#define __LPU0_HOSTFN0_MBOX_INFO_SH 1 111#define __LPU0_HOSTFN0_MBOX_INFO(_v) ((_v) << __LPU0_HOSTFN0_MBOX_INFO_SH) 112#define __LPU0_HOSTFN0_MBOX_CMD_STATUS 0x00000001 113#define HOSTFN1_LPU1_CMD_STAT 0x00019014 114#define __HOSTFN1_LPU1_MBOX_INFO_MK 0xfffffffe 115#define __HOSTFN1_LPU1_MBOX_INFO_SH 1 116#define __HOSTFN1_LPU1_MBOX_INFO(_v) ((_v) << __HOSTFN1_LPU1_MBOX_INFO_SH) 117#define __HOSTFN1_LPU1_MBOX_CMD_STATUS 0x00000001 118#define LPU1_HOSTFN1_CMD_STAT 0x0001901c 119#define __LPU1_HOSTFN1_MBOX_INFO_MK 0xfffffffe 120#define __LPU1_HOSTFN1_MBOX_INFO_SH 1 121#define __LPU1_HOSTFN1_MBOX_INFO(_v) ((_v) << __LPU1_HOSTFN1_MBOX_INFO_SH) 122#define __LPU1_HOSTFN1_MBOX_CMD_STATUS 0x00000001 123#define CPE_Q0_DEPTH 0x00010014 124#define CPE_Q0_PI 0x0001001c 125#define CPE_Q0_CI 0x00010020 126#define CPE_Q1_DEPTH 0x00010034 127#define CPE_Q1_PI 0x0001003c 128#define CPE_Q1_CI 0x00010040 129#define CPE_Q2_DEPTH 0x00010054 130#define CPE_Q2_PI 0x0001005c 131#define CPE_Q2_CI 0x00010060 132#define CPE_Q3_DEPTH 0x00010074 133#define CPE_Q3_PI 0x0001007c 134#define CPE_Q3_CI 0x00010080 135#define CPE_Q4_DEPTH 0x00010094 136#define CPE_Q4_PI 0x0001009c 137#define CPE_Q4_CI 0x000100a0 138#define CPE_Q5_DEPTH 0x000100b4 139#define CPE_Q5_PI 0x000100bc 140#define CPE_Q5_CI 0x000100c0 141#define CPE_Q6_DEPTH 0x000100d4 142#define CPE_Q6_PI 0x000100dc 143#define CPE_Q6_CI 0x000100e0 144#define CPE_Q7_DEPTH 0x000100f4 145#define CPE_Q7_PI 0x000100fc 146#define CPE_Q7_CI 0x00010100 147#define RME_Q0_DEPTH 0x00011014 148#define RME_Q0_PI 0x0001101c 149#define RME_Q0_CI 0x00011020 150#define RME_Q1_DEPTH 0x00011034 151#define RME_Q1_PI 0x0001103c 152#define RME_Q1_CI 0x00011040 153#define RME_Q2_DEPTH 0x00011054 154#define RME_Q2_PI 0x0001105c 155#define RME_Q2_CI 0x00011060 156#define RME_Q3_DEPTH 0x00011074 157#define RME_Q3_PI 0x0001107c 158#define RME_Q3_CI 0x00011080 159#define RME_Q4_DEPTH 0x00011094 160#define RME_Q4_PI 0x0001109c 161#define RME_Q4_CI 0x000110a0 162#define RME_Q5_DEPTH 0x000110b4 163#define RME_Q5_PI 0x000110bc 164#define RME_Q5_CI 0x000110c0 165#define RME_Q6_DEPTH 0x000110d4 166#define RME_Q6_PI 0x000110dc 167#define RME_Q6_CI 0x000110e0 168#define RME_Q7_DEPTH 0x000110f4 169#define RME_Q7_PI 0x000110fc 170#define RME_Q7_CI 0x00011100 171#define PSS_CTL_REG 0x00018800 172#define __PSS_I2C_CLK_DIV_MK 0x00030000 173#define __PSS_I2C_CLK_DIV_SH 16 174#define __PSS_I2C_CLK_DIV(_v) ((_v) << __PSS_I2C_CLK_DIV_SH) 175#define __PSS_LMEM_INIT_DONE 0x00001000 176#define __PSS_LMEM_RESET 0x00000200 177#define __PSS_LMEM_INIT_EN 0x00000100 178#define __PSS_LPU1_RESET 0x00000002 179#define __PSS_LPU0_RESET 0x00000001 180#define PSS_ERR_STATUS_REG 0x00018810 181#define __PSS_LMEM1_CORR_ERR 0x00000800 182#define __PSS_LMEM0_CORR_ERR 0x00000400 183#define __PSS_LMEM1_UNCORR_ERR 0x00000200 184#define __PSS_LMEM0_UNCORR_ERR 0x00000100 185#define __PSS_BAL_PERR 0x00000080 186#define __PSS_DIP_IF_ERR 0x00000040 187#define __PSS_IOH_IF_ERR 0x00000020 188#define __PSS_TDS_IF_ERR 0x00000010 189#define __PSS_RDS_IF_ERR 0x00000008 190#define __PSS_SGM_IF_ERR 0x00000004 191#define __PSS_LPU1_RAM_ERR 0x00000002 192#define __PSS_LPU0_RAM_ERR 0x00000001 193#define ERR_SET_REG 0x00018818 194#define __PSS_ERR_STATUS_SET 0x00000fff 195 196/* 197 * These definitions are either in error/missing in spec. Its auto-generated 198 * from hard coded values in regparse.pl. 199 */ 200#define __EMPHPOST_AT_4G_MK_FIX 0x0000001c 201#define __EMPHPOST_AT_4G_SH_FIX 0x00000002 202#define __EMPHPRE_AT_4G_FIX 0x00000003 203#define __SFP_TXRATE_EN_FIX 0x00000100 204#define __SFP_RXRATE_EN_FIX 0x00000080 205 206 207/* 208 * These register definitions are auto-generated from hard coded values 209 * in regparse.pl. 210 */ 211#define HOSTFN0_LPU_MBOX0_0 0x00019200 212#define HOSTFN1_LPU_MBOX0_8 0x00019260 213#define LPU_HOSTFN0_MBOX0_0 0x00019280 214#define LPU_HOSTFN1_MBOX0_8 0x000192e0 215 216 217/* 218 * These register mapping definitions are auto-generated from mapping tables 219 * in regparse.pl. 220 */ 221#define BFA_IOC0_HBEAT_REG HOST_SEM0_INFO_REG 222#define BFA_IOC0_STATE_REG HOST_SEM1_INFO_REG 223#define BFA_IOC1_HBEAT_REG HOST_SEM2_INFO_REG 224#define BFA_IOC1_STATE_REG HOST_SEM3_INFO_REG 225#define BFA_FW_USE_COUNT HOST_SEM4_INFO_REG 226 227#define CPE_Q_DEPTH(__n) \ 228 (CPE_Q0_DEPTH + (__n) * (CPE_Q1_DEPTH - CPE_Q0_DEPTH)) 229#define CPE_Q_PI(__n) \ 230 (CPE_Q0_PI + (__n) * (CPE_Q1_PI - CPE_Q0_PI)) 231#define CPE_Q_CI(__n) \ 232 (CPE_Q0_CI + (__n) * (CPE_Q1_CI - CPE_Q0_CI)) 233#define RME_Q_DEPTH(__n) \ 234 (RME_Q0_DEPTH + (__n) * (RME_Q1_DEPTH - RME_Q0_DEPTH)) 235#define RME_Q_PI(__n) \ 236 (RME_Q0_PI + (__n) * (RME_Q1_PI - RME_Q0_PI)) 237#define RME_Q_CI(__n) \ 238 (RME_Q0_CI + (__n) * (RME_Q1_CI - RME_Q0_CI)) 239 240#define CPE_Q_NUM(__fn, __q) (((__fn) << 2) + (__q)) 241#define RME_Q_NUM(__fn, __q) (((__fn) << 2) + (__q)) 242#define CPE_Q_MASK(__q) ((__q) & 0x3) 243#define RME_Q_MASK(__q) ((__q) & 0x3) 244 245 246/* 247 * PCI MSI-X vector defines 248 */ 249enum { 250 BFA_MSIX_CPE_Q0 = 0, 251 BFA_MSIX_CPE_Q1 = 1, 252 BFA_MSIX_CPE_Q2 = 2, 253 BFA_MSIX_CPE_Q3 = 3, 254 BFA_MSIX_CPE_Q4 = 4, 255 BFA_MSIX_CPE_Q5 = 5, 256 BFA_MSIX_CPE_Q6 = 6, 257 BFA_MSIX_CPE_Q7 = 7, 258 BFA_MSIX_RME_Q0 = 8, 259 BFA_MSIX_RME_Q1 = 9, 260 BFA_MSIX_RME_Q2 = 10, 261 BFA_MSIX_RME_Q3 = 11, 262 BFA_MSIX_RME_Q4 = 12, 263 BFA_MSIX_RME_Q5 = 13, 264 BFA_MSIX_RME_Q6 = 14, 265 BFA_MSIX_RME_Q7 = 15, 266 BFA_MSIX_ERR_EMC = 16, 267 BFA_MSIX_ERR_LPU0 = 17, 268 BFA_MSIX_ERR_LPU1 = 18, 269 BFA_MSIX_ERR_PSS = 19, 270 BFA_MSIX_MBOX_LPU0 = 20, 271 BFA_MSIX_MBOX_LPU1 = 21, 272 BFA_MSIX_CB_MAX = 22, 273}; 274 275/* 276 * And corresponding host interrupt status bit field defines 277 */ 278#define __HFN_INT_CPE_Q0 0x00000001U 279#define __HFN_INT_CPE_Q1 0x00000002U 280#define __HFN_INT_CPE_Q2 0x00000004U 281#define __HFN_INT_CPE_Q3 0x00000008U 282#define __HFN_INT_CPE_Q4 0x00000010U 283#define __HFN_INT_CPE_Q5 0x00000020U 284#define __HFN_INT_CPE_Q6 0x00000040U 285#define __HFN_INT_CPE_Q7 0x00000080U 286#define __HFN_INT_RME_Q0 0x00000100U 287#define __HFN_INT_RME_Q1 0x00000200U 288#define __HFN_INT_RME_Q2 0x00000400U 289#define __HFN_INT_RME_Q3 0x00000800U 290#define __HFN_INT_RME_Q4 0x00001000U 291#define __HFN_INT_RME_Q5 0x00002000U 292#define __HFN_INT_RME_Q6 0x00004000U 293#define __HFN_INT_RME_Q7 0x00008000U 294#define __HFN_INT_ERR_EMC 0x00010000U 295#define __HFN_INT_ERR_LPU0 0x00020000U 296#define __HFN_INT_ERR_LPU1 0x00040000U 297#define __HFN_INT_ERR_PSS 0x00080000U 298#define __HFN_INT_MBOX_LPU0 0x00100000U 299#define __HFN_INT_MBOX_LPU1 0x00200000U 300#define __HFN_INT_MBOX1_LPU0 0x00400000U 301#define __HFN_INT_MBOX1_LPU1 0x00800000U 302#define __HFN_INT_CPE_MASK 0x000000ffU 303#define __HFN_INT_RME_MASK 0x0000ff00U 304 305 306/* 307 * crossbow memory map. 308 */ 309#define PSS_SMEM_PAGE_START 0x8000 310#define PSS_SMEM_PGNUM(_pg0, _ma) ((_pg0) + ((_ma) >> 15)) 311#define PSS_SMEM_PGOFF(_ma) ((_ma) & 0x7fff) 312 313/* 314 * End of crossbow memory map 315 */ 316 317 318#endif /* __BFI_CBREG_H__ */ 319