1/* 2 * File: drivers/pci/pcie/aspm.c 3 * Enabling PCIe link L0s/L1 state and Clock Power Management 4 * 5 * Copyright (C) 2007 Intel 6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com) 7 * Copyright (C) Shaohua Li (shaohua.li@intel.com) 8 */ 9 10#include <linux/kernel.h> 11#include <linux/module.h> 12#include <linux/moduleparam.h> 13#include <linux/pci.h> 14#include <linux/pci_regs.h> 15#include <linux/errno.h> 16#include <linux/pm.h> 17#include <linux/init.h> 18#include <linux/slab.h> 19#include <linux/jiffies.h> 20#include <linux/delay.h> 21#include <linux/pci-aspm.h> 22#include "../pci.h" 23 24#ifdef MODULE_PARAM_PREFIX 25#undef MODULE_PARAM_PREFIX 26#endif 27#define MODULE_PARAM_PREFIX "pcie_aspm." 28 29/* Note: those are not register definitions */ 30#define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */ 31#define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */ 32#define ASPM_STATE_L1 (4) /* L1 state */ 33#define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW) 34#define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1) 35 36struct aspm_latency { 37 u32 l0s; /* L0s latency (nsec) */ 38 u32 l1; /* L1 latency (nsec) */ 39}; 40 41struct pcie_link_state { 42 struct pci_dev *pdev; /* Upstream component of the Link */ 43 struct pcie_link_state *root; /* pointer to the root port link */ 44 struct pcie_link_state *parent; /* pointer to the parent Link state */ 45 struct list_head sibling; /* node in link_list */ 46 struct list_head children; /* list of child link states */ 47 struct list_head link; /* node in parent's children list */ 48 49 /* ASPM state */ 50 u32 aspm_support:3; /* Supported ASPM state */ 51 u32 aspm_enabled:3; /* Enabled ASPM state */ 52 u32 aspm_capable:3; /* Capable ASPM state with latency */ 53 u32 aspm_default:3; /* Default ASPM state by BIOS */ 54 u32 aspm_disable:3; /* Disabled ASPM state */ 55 56 /* Clock PM state */ 57 u32 clkpm_capable:1; /* Clock PM capable? */ 58 u32 clkpm_enabled:1; /* Current Clock PM state */ 59 u32 clkpm_default:1; /* Default Clock PM state by BIOS */ 60 61 /* Exit latencies */ 62 struct aspm_latency latency_up; /* Upstream direction exit latency */ 63 struct aspm_latency latency_dw; /* Downstream direction exit latency */ 64 /* 65 * Endpoint acceptable latencies. A pcie downstream port only 66 * has one slot under it, so at most there are 8 functions. 67 */ 68 struct aspm_latency acceptable[8]; 69}; 70 71static int aspm_disabled, aspm_force; 72static DEFINE_MUTEX(aspm_lock); 73static LIST_HEAD(link_list); 74 75#define POLICY_DEFAULT 0 /* BIOS default setting */ 76#define POLICY_PERFORMANCE 1 /* high performance */ 77#define POLICY_POWERSAVE 2 /* high power saving */ 78static int aspm_policy; 79static const char *policy_str[] = { 80 [POLICY_DEFAULT] = "default", 81 [POLICY_PERFORMANCE] = "performance", 82 [POLICY_POWERSAVE] = "powersave" 83}; 84 85#define LINK_RETRAIN_TIMEOUT HZ 86 87static int policy_to_aspm_state(struct pcie_link_state *link) 88{ 89 switch (aspm_policy) { 90 case POLICY_PERFORMANCE: 91 /* Disable ASPM and Clock PM */ 92 return 0; 93 case POLICY_POWERSAVE: 94 /* Enable ASPM L0s/L1 */ 95 return ASPM_STATE_ALL; 96 case POLICY_DEFAULT: 97 return link->aspm_default; 98 } 99 return 0; 100} 101 102static int policy_to_clkpm_state(struct pcie_link_state *link) 103{ 104 switch (aspm_policy) { 105 case POLICY_PERFORMANCE: 106 /* Disable ASPM and Clock PM */ 107 return 0; 108 case POLICY_POWERSAVE: 109 /* Disable Clock PM */ 110 return 1; 111 case POLICY_DEFAULT: 112 return link->clkpm_default; 113 } 114 return 0; 115} 116 117static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable) 118{ 119 int pos; 120 u16 reg16; 121 struct pci_dev *child; 122 struct pci_bus *linkbus = link->pdev->subordinate; 123 124 list_for_each_entry(child, &linkbus->devices, bus_list) { 125 pos = pci_pcie_cap(child); 126 if (!pos) 127 return; 128 pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16); 129 if (enable) 130 reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN; 131 else 132 reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN; 133 pci_write_config_word(child, pos + PCI_EXP_LNKCTL, reg16); 134 } 135 link->clkpm_enabled = !!enable; 136} 137 138static void pcie_set_clkpm(struct pcie_link_state *link, int enable) 139{ 140 /* Don't enable Clock PM if the link is not Clock PM capable */ 141 if (!link->clkpm_capable && enable) 142 return; 143 /* Need nothing if the specified equals to current state */ 144 if (link->clkpm_enabled == enable) 145 return; 146 pcie_set_clkpm_nocheck(link, enable); 147} 148 149static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) 150{ 151 int pos, capable = 1, enabled = 1; 152 u32 reg32; 153 u16 reg16; 154 struct pci_dev *child; 155 struct pci_bus *linkbus = link->pdev->subordinate; 156 157 /* All functions should have the same cap and state, take the worst */ 158 list_for_each_entry(child, &linkbus->devices, bus_list) { 159 pos = pci_pcie_cap(child); 160 if (!pos) 161 return; 162 pci_read_config_dword(child, pos + PCI_EXP_LNKCAP, ®32); 163 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { 164 capable = 0; 165 enabled = 0; 166 break; 167 } 168 pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16); 169 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) 170 enabled = 0; 171 } 172 link->clkpm_enabled = enabled; 173 link->clkpm_default = enabled; 174 link->clkpm_capable = (blacklist) ? 0 : capable; 175} 176 177/* 178 * pcie_aspm_configure_common_clock: check if the 2 ends of a link 179 * could use common clock. If they are, configure them to use the 180 * common clock. That will reduce the ASPM state exit latency. 181 */ 182static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) 183{ 184 int ppos, cpos, same_clock = 1; 185 u16 reg16, parent_reg, child_reg[8]; 186 unsigned long start_jiffies; 187 struct pci_dev *child, *parent = link->pdev; 188 struct pci_bus *linkbus = parent->subordinate; 189 /* 190 * All functions of a slot should have the same Slot Clock 191 * Configuration, so just check one function 192 */ 193 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); 194 BUG_ON(!pci_is_pcie(child)); 195 196 /* Check downstream component if bit Slot Clock Configuration is 1 */ 197 cpos = pci_pcie_cap(child); 198 pci_read_config_word(child, cpos + PCI_EXP_LNKSTA, ®16); 199 if (!(reg16 & PCI_EXP_LNKSTA_SLC)) 200 same_clock = 0; 201 202 /* Check upstream component if bit Slot Clock Configuration is 1 */ 203 ppos = pci_pcie_cap(parent); 204 pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16); 205 if (!(reg16 & PCI_EXP_LNKSTA_SLC)) 206 same_clock = 0; 207 208 /* Configure downstream component, all functions */ 209 list_for_each_entry(child, &linkbus->devices, bus_list) { 210 cpos = pci_pcie_cap(child); 211 pci_read_config_word(child, cpos + PCI_EXP_LNKCTL, ®16); 212 child_reg[PCI_FUNC(child->devfn)] = reg16; 213 if (same_clock) 214 reg16 |= PCI_EXP_LNKCTL_CCC; 215 else 216 reg16 &= ~PCI_EXP_LNKCTL_CCC; 217 pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, reg16); 218 } 219 220 /* Configure upstream component */ 221 pci_read_config_word(parent, ppos + PCI_EXP_LNKCTL, ®16); 222 parent_reg = reg16; 223 if (same_clock) 224 reg16 |= PCI_EXP_LNKCTL_CCC; 225 else 226 reg16 &= ~PCI_EXP_LNKCTL_CCC; 227 pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16); 228 229 /* Retrain link */ 230 reg16 |= PCI_EXP_LNKCTL_RL; 231 pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16); 232 233 /* Wait for link training end. Break out after waiting for timeout */ 234 start_jiffies = jiffies; 235 for (;;) { 236 pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16); 237 if (!(reg16 & PCI_EXP_LNKSTA_LT)) 238 break; 239 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) 240 break; 241 msleep(1); 242 } 243 if (!(reg16 & PCI_EXP_LNKSTA_LT)) 244 return; 245 246 /* Training failed. Restore common clock configurations */ 247 dev_printk(KERN_ERR, &parent->dev, 248 "ASPM: Could not configure common clock\n"); 249 list_for_each_entry(child, &linkbus->devices, bus_list) { 250 cpos = pci_pcie_cap(child); 251 pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, 252 child_reg[PCI_FUNC(child->devfn)]); 253 } 254 pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, parent_reg); 255} 256 257/* Convert L0s latency encoding to ns */ 258static u32 calc_l0s_latency(u32 encoding) 259{ 260 if (encoding == 0x7) 261 return (5 * 1000); /* > 4us */ 262 return (64 << encoding); 263} 264 265/* Convert L0s acceptable latency encoding to ns */ 266static u32 calc_l0s_acceptable(u32 encoding) 267{ 268 if (encoding == 0x7) 269 return -1U; 270 return (64 << encoding); 271} 272 273/* Convert L1 latency encoding to ns */ 274static u32 calc_l1_latency(u32 encoding) 275{ 276 if (encoding == 0x7) 277 return (65 * 1000); /* > 64us */ 278 return (1000 << encoding); 279} 280 281/* Convert L1 acceptable latency encoding to ns */ 282static u32 calc_l1_acceptable(u32 encoding) 283{ 284 if (encoding == 0x7) 285 return -1U; 286 return (1000 << encoding); 287} 288 289struct aspm_register_info { 290 u32 support:2; 291 u32 enabled:2; 292 u32 latency_encoding_l0s; 293 u32 latency_encoding_l1; 294}; 295 296static void pcie_get_aspm_reg(struct pci_dev *pdev, 297 struct aspm_register_info *info) 298{ 299 int pos; 300 u16 reg16; 301 u32 reg32; 302 303 pos = pci_pcie_cap(pdev); 304 pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32); 305 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; 306 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; 307 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; 308 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); 309 info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC; 310} 311 312static void pcie_aspm_check_latency(struct pci_dev *endpoint) 313{ 314 u32 latency, l1_switch_latency = 0; 315 struct aspm_latency *acceptable; 316 struct pcie_link_state *link; 317 318 /* Device not in D0 doesn't need latency check */ 319 if ((endpoint->current_state != PCI_D0) && 320 (endpoint->current_state != PCI_UNKNOWN)) 321 return; 322 323 link = endpoint->bus->self->link_state; 324 acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; 325 326 while (link) { 327 /* Check upstream direction L0s latency */ 328 if ((link->aspm_capable & ASPM_STATE_L0S_UP) && 329 (link->latency_up.l0s > acceptable->l0s)) 330 link->aspm_capable &= ~ASPM_STATE_L0S_UP; 331 332 /* Check downstream direction L0s latency */ 333 if ((link->aspm_capable & ASPM_STATE_L0S_DW) && 334 (link->latency_dw.l0s > acceptable->l0s)) 335 link->aspm_capable &= ~ASPM_STATE_L0S_DW; 336 /* 337 * Check L1 latency. 338 * Every switch on the path to root complex need 1 339 * more microsecond for L1. Spec doesn't mention L0s. 340 */ 341 latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1); 342 if ((link->aspm_capable & ASPM_STATE_L1) && 343 (latency + l1_switch_latency > acceptable->l1)) 344 link->aspm_capable &= ~ASPM_STATE_L1; 345 l1_switch_latency += 1000; 346 347 link = link->parent; 348 } 349} 350 351static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) 352{ 353 struct pci_dev *child, *parent = link->pdev; 354 struct pci_bus *linkbus = parent->subordinate; 355 struct aspm_register_info upreg, dwreg; 356 357 if (blacklist) { 358 /* Set enabled/disable so that we will disable ASPM later */ 359 link->aspm_enabled = ASPM_STATE_ALL; 360 link->aspm_disable = ASPM_STATE_ALL; 361 return; 362 } 363 364 /* Configure common clock before checking latencies */ 365 pcie_aspm_configure_common_clock(link); 366 367 /* Get upstream/downstream components' register state */ 368 pcie_get_aspm_reg(parent, &upreg); 369 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); 370 pcie_get_aspm_reg(child, &dwreg); 371 372 /* 373 * Setup L0s state 374 * 375 * Note that we must not enable L0s in either direction on a 376 * given link unless components on both sides of the link each 377 * support L0s. 378 */ 379 if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S) 380 link->aspm_support |= ASPM_STATE_L0S; 381 if (dwreg.enabled & PCIE_LINK_STATE_L0S) 382 link->aspm_enabled |= ASPM_STATE_L0S_UP; 383 if (upreg.enabled & PCIE_LINK_STATE_L0S) 384 link->aspm_enabled |= ASPM_STATE_L0S_DW; 385 link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s); 386 link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s); 387 388 /* Setup L1 state */ 389 if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1) 390 link->aspm_support |= ASPM_STATE_L1; 391 if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1) 392 link->aspm_enabled |= ASPM_STATE_L1; 393 link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1); 394 link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1); 395 396 /* Save default state */ 397 link->aspm_default = link->aspm_enabled; 398 399 /* Setup initial capable state. Will be updated later */ 400 link->aspm_capable = link->aspm_support; 401 /* 402 * If the downstream component has pci bridge function, don't 403 * do ASPM for now. 404 */ 405 list_for_each_entry(child, &linkbus->devices, bus_list) { 406 if (child->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) { 407 link->aspm_disable = ASPM_STATE_ALL; 408 break; 409 } 410 } 411 412 /* Get and check endpoint acceptable latencies */ 413 list_for_each_entry(child, &linkbus->devices, bus_list) { 414 int pos; 415 u32 reg32, encoding; 416 struct aspm_latency *acceptable = 417 &link->acceptable[PCI_FUNC(child->devfn)]; 418 419 if (child->pcie_type != PCI_EXP_TYPE_ENDPOINT && 420 child->pcie_type != PCI_EXP_TYPE_LEG_END) 421 continue; 422 423 pos = pci_pcie_cap(child); 424 pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32); 425 /* Calculate endpoint L0s acceptable latency */ 426 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; 427 acceptable->l0s = calc_l0s_acceptable(encoding); 428 /* Calculate endpoint L1 acceptable latency */ 429 encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; 430 acceptable->l1 = calc_l1_acceptable(encoding); 431 432 pcie_aspm_check_latency(child); 433 } 434} 435 436static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val) 437{ 438 u16 reg16; 439 int pos = pci_pcie_cap(pdev); 440 441 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); 442 reg16 &= ~0x3; 443 reg16 |= val; 444 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16); 445} 446 447static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state) 448{ 449 u32 upstream = 0, dwstream = 0; 450 struct pci_dev *child, *parent = link->pdev; 451 struct pci_bus *linkbus = parent->subordinate; 452 453 /* Nothing to do if the link is already in the requested state */ 454 state &= (link->aspm_capable & ~link->aspm_disable); 455 if (link->aspm_enabled == state) 456 return; 457 /* Convert ASPM state to upstream/downstream ASPM register state */ 458 if (state & ASPM_STATE_L0S_UP) 459 dwstream |= PCIE_LINK_STATE_L0S; 460 if (state & ASPM_STATE_L0S_DW) 461 upstream |= PCIE_LINK_STATE_L0S; 462 if (state & ASPM_STATE_L1) { 463 upstream |= PCIE_LINK_STATE_L1; 464 dwstream |= PCIE_LINK_STATE_L1; 465 } 466 /* 467 * Spec 2.0 suggests all functions should be configured the 468 * same setting for ASPM. Enabling ASPM L1 should be done in 469 * upstream component first and then downstream, and vice 470 * versa for disabling ASPM L1. Spec doesn't mention L0S. 471 */ 472 if (state & ASPM_STATE_L1) 473 pcie_config_aspm_dev(parent, upstream); 474 list_for_each_entry(child, &linkbus->devices, bus_list) 475 pcie_config_aspm_dev(child, dwstream); 476 if (!(state & ASPM_STATE_L1)) 477 pcie_config_aspm_dev(parent, upstream); 478 479 link->aspm_enabled = state; 480} 481 482static void pcie_config_aspm_path(struct pcie_link_state *link) 483{ 484 while (link) { 485 pcie_config_aspm_link(link, policy_to_aspm_state(link)); 486 link = link->parent; 487 } 488} 489 490static void free_link_state(struct pcie_link_state *link) 491{ 492 link->pdev->link_state = NULL; 493 kfree(link); 494} 495 496static int pcie_aspm_sanity_check(struct pci_dev *pdev) 497{ 498 struct pci_dev *child; 499 int pos; 500 u32 reg32; 501 /* 502 * Some functions in a slot might not all be PCIe functions, 503 * very strange. Disable ASPM for the whole slot 504 */ 505 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { 506 pos = pci_pcie_cap(child); 507 if (!pos) 508 return -EINVAL; 509 /* 510 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use 511 * RBER bit to determine if a function is 1.1 version device 512 */ 513 pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32); 514 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { 515 dev_printk(KERN_INFO, &child->dev, "disabling ASPM" 516 " on pre-1.1 PCIe device. You can enable it" 517 " with 'pcie_aspm=force'\n"); 518 return -EINVAL; 519 } 520 } 521 return 0; 522} 523 524static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev) 525{ 526 struct pcie_link_state *link; 527 528 link = kzalloc(sizeof(*link), GFP_KERNEL); 529 if (!link) 530 return NULL; 531 INIT_LIST_HEAD(&link->sibling); 532 INIT_LIST_HEAD(&link->children); 533 INIT_LIST_HEAD(&link->link); 534 link->pdev = pdev; 535 if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) { 536 struct pcie_link_state *parent; 537 parent = pdev->bus->parent->self->link_state; 538 if (!parent) { 539 kfree(link); 540 return NULL; 541 } 542 link->parent = parent; 543 list_add(&link->link, &parent->children); 544 } 545 /* Setup a pointer to the root port link */ 546 if (!link->parent) 547 link->root = link; 548 else 549 link->root = link->parent->root; 550 551 list_add(&link->sibling, &link_list); 552 pdev->link_state = link; 553 return link; 554} 555 556/* 557 * pcie_aspm_init_link_state: Initiate PCI express link state. 558 * It is called after the pcie and its children devices are scaned. 559 * @pdev: the root port or switch downstream port 560 */ 561void pcie_aspm_init_link_state(struct pci_dev *pdev) 562{ 563 struct pcie_link_state *link; 564 int blacklist = !!pcie_aspm_sanity_check(pdev); 565 566 if (aspm_disabled || !pci_is_pcie(pdev) || pdev->link_state) 567 return; 568 if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && 569 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) 570 return; 571 572 /* VIA has a strange chipset, root port is under a bridge */ 573 if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT && 574 pdev->bus->self) 575 return; 576 577 down_read(&pci_bus_sem); 578 if (list_empty(&pdev->subordinate->devices)) 579 goto out; 580 581 mutex_lock(&aspm_lock); 582 link = alloc_pcie_link_state(pdev); 583 if (!link) 584 goto unlock; 585 /* 586 * Setup initial ASPM state. Note that we need to configure 587 * upstream links also because capable state of them can be 588 * update through pcie_aspm_cap_init(). 589 */ 590 pcie_aspm_cap_init(link, blacklist); 591 592 /* Setup initial Clock PM state */ 593 pcie_clkpm_cap_init(link, blacklist); 594 595 /* 596 * At this stage drivers haven't had an opportunity to change the 597 * link policy setting. Enabling ASPM on broken hardware can cripple 598 * it even before the driver has had a chance to disable ASPM, so 599 * default to a safe level right now. If we're enabling ASPM beyond 600 * the BIOS's expectation, we'll do so once pci_enable_device() is 601 * called. 602 */ 603 if (aspm_policy != POLICY_POWERSAVE) { 604 pcie_config_aspm_path(link); 605 pcie_set_clkpm(link, policy_to_clkpm_state(link)); 606 } 607 608unlock: 609 mutex_unlock(&aspm_lock); 610out: 611 up_read(&pci_bus_sem); 612} 613 614/* Recheck latencies and update aspm_capable for links under the root */ 615static void pcie_update_aspm_capable(struct pcie_link_state *root) 616{ 617 struct pcie_link_state *link; 618 BUG_ON(root->parent); 619 list_for_each_entry(link, &link_list, sibling) { 620 if (link->root != root) 621 continue; 622 link->aspm_capable = link->aspm_support; 623 } 624 list_for_each_entry(link, &link_list, sibling) { 625 struct pci_dev *child; 626 struct pci_bus *linkbus = link->pdev->subordinate; 627 if (link->root != root) 628 continue; 629 list_for_each_entry(child, &linkbus->devices, bus_list) { 630 if ((child->pcie_type != PCI_EXP_TYPE_ENDPOINT) && 631 (child->pcie_type != PCI_EXP_TYPE_LEG_END)) 632 continue; 633 pcie_aspm_check_latency(child); 634 } 635 } 636} 637 638/* @pdev: the endpoint device */ 639void pcie_aspm_exit_link_state(struct pci_dev *pdev) 640{ 641 struct pci_dev *parent = pdev->bus->self; 642 struct pcie_link_state *link, *root, *parent_link; 643 644 if (aspm_disabled || !pci_is_pcie(pdev) || 645 !parent || !parent->link_state) 646 return; 647 if ((parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT) && 648 (parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)) 649 return; 650 651 down_read(&pci_bus_sem); 652 mutex_lock(&aspm_lock); 653 /* 654 * All PCIe functions are in one slot, remove one function will remove 655 * the whole slot, so just wait until we are the last function left. 656 */ 657 if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices)) 658 goto out; 659 660 link = parent->link_state; 661 root = link->root; 662 parent_link = link->parent; 663 664 /* All functions are removed, so just disable ASPM for the link */ 665 pcie_config_aspm_link(link, 0); 666 list_del(&link->sibling); 667 list_del(&link->link); 668 /* Clock PM is for endpoint device */ 669 free_link_state(link); 670 671 /* Recheck latencies and configure upstream links */ 672 if (parent_link) { 673 pcie_update_aspm_capable(root); 674 pcie_config_aspm_path(parent_link); 675 } 676out: 677 mutex_unlock(&aspm_lock); 678 up_read(&pci_bus_sem); 679} 680 681/* @pdev: the root port or switch downstream port */ 682void pcie_aspm_pm_state_change(struct pci_dev *pdev) 683{ 684 struct pcie_link_state *link = pdev->link_state; 685 686 if (aspm_disabled || !pci_is_pcie(pdev) || !link) 687 return; 688 if ((pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) && 689 (pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)) 690 return; 691 /* 692 * Devices changed PM state, we should recheck if latency 693 * meets all functions' requirement 694 */ 695 down_read(&pci_bus_sem); 696 mutex_lock(&aspm_lock); 697 pcie_update_aspm_capable(link->root); 698 pcie_config_aspm_path(link); 699 mutex_unlock(&aspm_lock); 700 up_read(&pci_bus_sem); 701} 702 703/* 704 * pci_disable_link_state - disable pci device's link state, so the link will 705 * never enter specific states 706 */ 707void pci_disable_link_state(struct pci_dev *pdev, int state) 708{ 709 struct pci_dev *parent = pdev->bus->self; 710 struct pcie_link_state *link; 711 712 if (aspm_disabled || !pci_is_pcie(pdev)) 713 return; 714 if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT || 715 pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) 716 parent = pdev; 717 if (!parent || !parent->link_state) 718 return; 719 720 down_read(&pci_bus_sem); 721 mutex_lock(&aspm_lock); 722 link = parent->link_state; 723 if (state & PCIE_LINK_STATE_L0S) 724 link->aspm_disable |= ASPM_STATE_L0S; 725 if (state & PCIE_LINK_STATE_L1) 726 link->aspm_disable |= ASPM_STATE_L1; 727 pcie_config_aspm_link(link, policy_to_aspm_state(link)); 728 729 if (state & PCIE_LINK_STATE_CLKPM) { 730 link->clkpm_capable = 0; 731 pcie_set_clkpm(link, 0); 732 } 733 mutex_unlock(&aspm_lock); 734 up_read(&pci_bus_sem); 735} 736EXPORT_SYMBOL(pci_disable_link_state); 737 738static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp) 739{ 740 int i; 741 struct pcie_link_state *link; 742 743 for (i = 0; i < ARRAY_SIZE(policy_str); i++) 744 if (!strncmp(val, policy_str[i], strlen(policy_str[i]))) 745 break; 746 if (i >= ARRAY_SIZE(policy_str)) 747 return -EINVAL; 748 if (i == aspm_policy) 749 return 0; 750 751 down_read(&pci_bus_sem); 752 mutex_lock(&aspm_lock); 753 aspm_policy = i; 754 list_for_each_entry(link, &link_list, sibling) { 755 pcie_config_aspm_link(link, policy_to_aspm_state(link)); 756 pcie_set_clkpm(link, policy_to_clkpm_state(link)); 757 } 758 mutex_unlock(&aspm_lock); 759 up_read(&pci_bus_sem); 760 return 0; 761} 762 763static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp) 764{ 765 int i, cnt = 0; 766 for (i = 0; i < ARRAY_SIZE(policy_str); i++) 767 if (i == aspm_policy) 768 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]); 769 else 770 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]); 771 return cnt; 772} 773 774module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy, 775 NULL, 0644); 776 777#ifdef CONFIG_PCIEASPM_DEBUG 778static ssize_t link_state_show(struct device *dev, 779 struct device_attribute *attr, 780 char *buf) 781{ 782 struct pci_dev *pci_device = to_pci_dev(dev); 783 struct pcie_link_state *link_state = pci_device->link_state; 784 785 return sprintf(buf, "%d\n", link_state->aspm_enabled); 786} 787 788static ssize_t link_state_store(struct device *dev, 789 struct device_attribute *attr, 790 const char *buf, 791 size_t n) 792{ 793 struct pci_dev *pdev = to_pci_dev(dev); 794 struct pcie_link_state *link, *root = pdev->link_state->root; 795 u32 val = buf[0] - '0', state = 0; 796 797 if (n < 1 || val > 3) 798 return -EINVAL; 799 800 /* Convert requested state to ASPM state */ 801 if (val & PCIE_LINK_STATE_L0S) 802 state |= ASPM_STATE_L0S; 803 if (val & PCIE_LINK_STATE_L1) 804 state |= ASPM_STATE_L1; 805 806 down_read(&pci_bus_sem); 807 mutex_lock(&aspm_lock); 808 list_for_each_entry(link, &link_list, sibling) { 809 if (link->root != root) 810 continue; 811 pcie_config_aspm_link(link, state); 812 } 813 mutex_unlock(&aspm_lock); 814 up_read(&pci_bus_sem); 815 return n; 816} 817 818static ssize_t clk_ctl_show(struct device *dev, 819 struct device_attribute *attr, 820 char *buf) 821{ 822 struct pci_dev *pci_device = to_pci_dev(dev); 823 struct pcie_link_state *link_state = pci_device->link_state; 824 825 return sprintf(buf, "%d\n", link_state->clkpm_enabled); 826} 827 828static ssize_t clk_ctl_store(struct device *dev, 829 struct device_attribute *attr, 830 const char *buf, 831 size_t n) 832{ 833 struct pci_dev *pdev = to_pci_dev(dev); 834 int state; 835 836 if (n < 1) 837 return -EINVAL; 838 state = buf[0]-'0'; 839 840 down_read(&pci_bus_sem); 841 mutex_lock(&aspm_lock); 842 pcie_set_clkpm_nocheck(pdev->link_state, !!state); 843 mutex_unlock(&aspm_lock); 844 up_read(&pci_bus_sem); 845 846 return n; 847} 848 849static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store); 850static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store); 851 852static char power_group[] = "power"; 853void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) 854{ 855 struct pcie_link_state *link_state = pdev->link_state; 856 857 if (!pci_is_pcie(pdev) || 858 (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && 859 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) 860 return; 861 862 if (link_state->aspm_support) 863 sysfs_add_file_to_group(&pdev->dev.kobj, 864 &dev_attr_link_state.attr, power_group); 865 if (link_state->clkpm_capable) 866 sysfs_add_file_to_group(&pdev->dev.kobj, 867 &dev_attr_clk_ctl.attr, power_group); 868} 869 870void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) 871{ 872 struct pcie_link_state *link_state = pdev->link_state; 873 874 if (!pci_is_pcie(pdev) || 875 (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && 876 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) 877 return; 878 879 if (link_state->aspm_support) 880 sysfs_remove_file_from_group(&pdev->dev.kobj, 881 &dev_attr_link_state.attr, power_group); 882 if (link_state->clkpm_capable) 883 sysfs_remove_file_from_group(&pdev->dev.kobj, 884 &dev_attr_clk_ctl.attr, power_group); 885} 886#endif 887 888static int __init pcie_aspm_disable(char *str) 889{ 890 if (!strcmp(str, "off")) { 891 aspm_disabled = 1; 892 printk(KERN_INFO "PCIe ASPM is disabled\n"); 893 } else if (!strcmp(str, "force")) { 894 aspm_force = 1; 895 printk(KERN_INFO "PCIe ASPM is forcedly enabled\n"); 896 } 897 return 1; 898} 899 900__setup("pcie_aspm=", pcie_aspm_disable); 901 902void pcie_no_aspm(void) 903{ 904 if (!aspm_force) 905 aspm_disabled = 1; 906} 907 908/** 909 * pcie_aspm_enabled - is PCIe ASPM enabled? 910 * 911 * Returns true if ASPM has not been disabled by the command-line option 912 * pcie_aspm=off. 913 **/ 914int pcie_aspm_enabled(void) 915{ 916 return !aspm_disabled; 917} 918EXPORT_SYMBOL(pcie_aspm_enabled); 919