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1/* Low-level parallel port routines for built-in port on SGI IP32
2 *
3 * Author: Arnaud Giersch <arnaud.giersch@free.fr>
4 *
5 * Based on parport_pc.c by
6 *	Phil Blundell, Tim Waugh, Jose Renau, David Campbell,
7 *	Andrea Arcangeli, et al.
8 *
9 * Thanks to Ilya A. Volynets-Evenbakh for his help.
10 *
11 * Copyright (C) 2005, 2006 Arnaud Giersch.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the Free
15 * Software Foundation; either version 2 of the License, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
21 * more details.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc., 59
25 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 */
27
28/* Current status:
29 *
30 *	Basic SPP and PS2 modes are supported.
31 *	Support for parallel port IRQ is present.
32 *	Hardware SPP (a.k.a. compatibility), EPP, and ECP modes are
33 *	supported.
34 *	SPP/ECP FIFO can be driven in PIO or DMA mode.  PIO mode can work with
35 *	or without interrupt support.
36 *
37 *	Hardware ECP mode is not fully implemented (ecp_read_data and
38 *	ecp_write_addr are actually missing).
39 *
40 * To do:
41 *
42 *	Fully implement ECP mode.
43 *	EPP and ECP mode need to be tested.  I currently do not own any
44 *	peripheral supporting these extended mode, and cannot test them.
45 *	If DMA mode works well, decide if support for PIO FIFO modes should be
46 *	dropped.
47 *	Use the io{read,write} family functions when they become available in
48 *	the linux-mips.org tree.  Note: the MIPS specific functions readsb()
49 *	and writesb() are to be translated by ioread8_rep() and iowrite8_rep()
50 *	respectively.
51 */
52
53/* The built-in parallel port on the SGI 02 workstation (a.k.a. IP32) is an
54 * IEEE 1284 parallel port driven by a Texas Instrument TL16PIR552PH chip[1].
55 * This chip supports SPP, bidirectional, EPP and ECP modes.  It has a 16 byte
56 * FIFO buffer and supports DMA transfers.
57 *
58 * [1] http://focus.ti.com/docs/prod/folders/print/tl16pir552.html
59 *
60 * Theoretically, we could simply use the parport_pc module.  It is however
61 * not so simple.  The parport_pc code assumes that the parallel port
62 * registers are port-mapped.  On the O2, they are memory-mapped.
63 * Furthermore, each register is replicated on 256 consecutive addresses (as
64 * it is for the built-in serial ports on the same chip).
65 */
66
67/*--- Some configuration defines ---------------------------------------*/
68
69/* DEBUG_PARPORT_IP32
70 *	0	disable debug
71 *	1	standard level: pr_debug1 is enabled
72 *	2	parport_ip32_dump_state is enabled
73 *	>=3	verbose level: pr_debug is enabled
74 */
75#if !defined(DEBUG_PARPORT_IP32)
76#	define DEBUG_PARPORT_IP32  0	/* 0 (disabled) for production */
77#endif
78
79/*----------------------------------------------------------------------*/
80
81/* Setup DEBUG macros.  This is done before any includes, just in case we
82 * activate pr_debug() with DEBUG_PARPORT_IP32 >= 3.
83 */
84#if DEBUG_PARPORT_IP32 == 1
85#	warning DEBUG_PARPORT_IP32 == 1
86#elif DEBUG_PARPORT_IP32 == 2
87#	warning DEBUG_PARPORT_IP32 == 2
88#elif DEBUG_PARPORT_IP32 >= 3
89#	warning DEBUG_PARPORT_IP32 >= 3
90#	if !defined(DEBUG)
91#		define DEBUG /* enable pr_debug() in kernel.h */
92#	endif
93#endif
94
95#include <linux/completion.h>
96#include <linux/delay.h>
97#include <linux/dma-mapping.h>
98#include <linux/err.h>
99#include <linux/init.h>
100#include <linux/interrupt.h>
101#include <linux/jiffies.h>
102#include <linux/kernel.h>
103#include <linux/module.h>
104#include <linux/parport.h>
105#include <linux/sched.h>
106#include <linux/slab.h>
107#include <linux/spinlock.h>
108#include <linux/stddef.h>
109#include <linux/types.h>
110#include <asm/io.h>
111#include <asm/ip32/ip32_ints.h>
112#include <asm/ip32/mace.h>
113
114/*--- Global variables -------------------------------------------------*/
115
116/* Verbose probing on by default for debugging. */
117#if DEBUG_PARPORT_IP32 >= 1
118#	define DEFAULT_VERBOSE_PROBING	1
119#else
120#	define DEFAULT_VERBOSE_PROBING	0
121#endif
122
123/* Default prefix for printk */
124#define PPIP32 "parport_ip32: "
125
126/*
127 * These are the module parameters:
128 * @features:		bit mask of features to enable/disable
129 *			(all enabled by default)
130 * @verbose_probing:	log chit-chat during initialization
131 */
132#define PARPORT_IP32_ENABLE_IRQ	(1U << 0)
133#define PARPORT_IP32_ENABLE_DMA	(1U << 1)
134#define PARPORT_IP32_ENABLE_SPP	(1U << 2)
135#define PARPORT_IP32_ENABLE_EPP	(1U << 3)
136#define PARPORT_IP32_ENABLE_ECP	(1U << 4)
137static unsigned int features =	~0U;
138static int verbose_probing =	DEFAULT_VERBOSE_PROBING;
139
140/* We do not support more than one port. */
141static struct parport *this_port = NULL;
142
143/* Timing constants for FIFO modes.  */
144#define FIFO_NFAULT_TIMEOUT	100	/* milliseconds */
145#define FIFO_POLLING_INTERVAL	50	/* microseconds */
146
147/*--- I/O register definitions -----------------------------------------*/
148
149/**
150 * struct parport_ip32_regs - virtual addresses of parallel port registers
151 * @data:	Data Register
152 * @dsr:	Device Status Register
153 * @dcr:	Device Control Register
154 * @eppAddr:	EPP Address Register
155 * @eppData0:	EPP Data Register 0
156 * @eppData1:	EPP Data Register 1
157 * @eppData2:	EPP Data Register 2
158 * @eppData3:	EPP Data Register 3
159 * @ecpAFifo:	ECP Address FIFO
160 * @fifo:	General FIFO register.  The same address is used for:
161 *		- cFifo, the Parallel Port DATA FIFO
162 *		- ecpDFifo, the ECP Data FIFO
163 *		- tFifo, the ECP Test FIFO
164 * @cnfgA:	Configuration Register A
165 * @cnfgB:	Configuration Register B
166 * @ecr:	Extended Control Register
167 */
168struct parport_ip32_regs {
169	void __iomem *data;
170	void __iomem *dsr;
171	void __iomem *dcr;
172	void __iomem *eppAddr;
173	void __iomem *eppData0;
174	void __iomem *eppData1;
175	void __iomem *eppData2;
176	void __iomem *eppData3;
177	void __iomem *ecpAFifo;
178	void __iomem *fifo;
179	void __iomem *cnfgA;
180	void __iomem *cnfgB;
181	void __iomem *ecr;
182};
183
184/* Device Status Register */
185#define DSR_nBUSY		(1U << 7)	/* PARPORT_STATUS_BUSY */
186#define DSR_nACK		(1U << 6)	/* PARPORT_STATUS_ACK */
187#define DSR_PERROR		(1U << 5)	/* PARPORT_STATUS_PAPEROUT */
188#define DSR_SELECT		(1U << 4)	/* PARPORT_STATUS_SELECT */
189#define DSR_nFAULT		(1U << 3)	/* PARPORT_STATUS_ERROR */
190#define DSR_nPRINT		(1U << 2)	/* specific to TL16PIR552 */
191/* #define DSR_reserved		(1U << 1) */
192#define DSR_TIMEOUT		(1U << 0)	/* EPP timeout */
193
194/* Device Control Register */
195/* #define DCR_reserved		(1U << 7) | (1U <<  6) */
196#define DCR_DIR			(1U << 5)	/* direction */
197#define DCR_IRQ			(1U << 4)	/* interrupt on nAck */
198#define DCR_SELECT		(1U << 3)	/* PARPORT_CONTROL_SELECT */
199#define DCR_nINIT		(1U << 2)	/* PARPORT_CONTROL_INIT */
200#define DCR_AUTOFD		(1U << 1)	/* PARPORT_CONTROL_AUTOFD */
201#define DCR_STROBE		(1U << 0)	/* PARPORT_CONTROL_STROBE */
202
203/* ECP Configuration Register A */
204#define CNFGA_IRQ		(1U << 7)
205#define CNFGA_ID_MASK		((1U << 6) | (1U << 5) | (1U << 4))
206#define CNFGA_ID_SHIFT		4
207#define CNFGA_ID_16		(00U << CNFGA_ID_SHIFT)
208#define CNFGA_ID_8		(01U << CNFGA_ID_SHIFT)
209#define CNFGA_ID_32		(02U << CNFGA_ID_SHIFT)
210/* #define CNFGA_reserved	(1U << 3) */
211#define CNFGA_nBYTEINTRANS	(1U << 2)
212#define CNFGA_PWORDLEFT		((1U << 1) | (1U << 0))
213
214/* ECP Configuration Register B */
215#define CNFGB_COMPRESS		(1U << 7)
216#define CNFGB_INTRVAL		(1U << 6)
217#define CNFGB_IRQ_MASK		((1U << 5) | (1U << 4) | (1U << 3))
218#define CNFGB_IRQ_SHIFT		3
219#define CNFGB_DMA_MASK		((1U << 2) | (1U << 1) | (1U << 0))
220#define CNFGB_DMA_SHIFT		0
221
222/* Extended Control Register */
223#define ECR_MODE_MASK		((1U << 7) | (1U << 6) | (1U << 5))
224#define ECR_MODE_SHIFT		5
225#define ECR_MODE_SPP		(00U << ECR_MODE_SHIFT)
226#define ECR_MODE_PS2		(01U << ECR_MODE_SHIFT)
227#define ECR_MODE_PPF		(02U << ECR_MODE_SHIFT)
228#define ECR_MODE_ECP		(03U << ECR_MODE_SHIFT)
229#define ECR_MODE_EPP		(04U << ECR_MODE_SHIFT)
230/* #define ECR_MODE_reserved	(05U << ECR_MODE_SHIFT) */
231#define ECR_MODE_TST		(06U << ECR_MODE_SHIFT)
232#define ECR_MODE_CFG		(07U << ECR_MODE_SHIFT)
233#define ECR_nERRINTR		(1U << 4)
234#define ECR_DMAEN		(1U << 3)
235#define ECR_SERVINTR		(1U << 2)
236#define ECR_F_FULL		(1U << 1)
237#define ECR_F_EMPTY		(1U << 0)
238
239/*--- Private data -----------------------------------------------------*/
240
241/**
242 * enum parport_ip32_irq_mode - operation mode of interrupt handler
243 * @PARPORT_IP32_IRQ_FWD:	forward interrupt to the upper parport layer
244 * @PARPORT_IP32_IRQ_HERE:	interrupt is handled locally
245 */
246enum parport_ip32_irq_mode { PARPORT_IP32_IRQ_FWD, PARPORT_IP32_IRQ_HERE };
247
248/**
249 * struct parport_ip32_private - private stuff for &struct parport
250 * @regs:		register addresses
251 * @dcr_cache:		cached contents of DCR
252 * @dcr_writable:	bit mask of writable DCR bits
253 * @pword:		number of bytes per PWord
254 * @fifo_depth:		number of PWords that FIFO will hold
255 * @readIntrThreshold:	minimum number of PWords we can read
256 *			if we get an interrupt
257 * @writeIntrThreshold:	minimum number of PWords we can write
258 *			if we get an interrupt
259 * @irq_mode:		operation mode of interrupt handler for this port
260 * @irq_complete:	mutex used to wait for an interrupt to occur
261 */
262struct parport_ip32_private {
263	struct parport_ip32_regs	regs;
264	unsigned int			dcr_cache;
265	unsigned int			dcr_writable;
266	unsigned int			pword;
267	unsigned int			fifo_depth;
268	unsigned int			readIntrThreshold;
269	unsigned int			writeIntrThreshold;
270	enum parport_ip32_irq_mode	irq_mode;
271	struct completion		irq_complete;
272};
273
274/*--- Debug code -------------------------------------------------------*/
275
276/*
277 * pr_debug1 - print debug messages
278 *
279 * This is like pr_debug(), but is defined for %DEBUG_PARPORT_IP32 >= 1
280 */
281#if DEBUG_PARPORT_IP32 >= 1
282#	define pr_debug1(...)	printk(KERN_DEBUG __VA_ARGS__)
283#else /* DEBUG_PARPORT_IP32 < 1 */
284#	define pr_debug1(...)	do { } while (0)
285#endif
286
287/*
288 * pr_trace, pr_trace1 - trace function calls
289 * @p:		pointer to &struct parport
290 * @fmt:	printk format string
291 * @...:	parameters for format string
292 *
293 * Macros used to trace function calls.  The given string is formatted after
294 * function name.  pr_trace() uses pr_debug(), and pr_trace1() uses
295 * pr_debug1().  __pr_trace() is the low-level macro and is not to be used
296 * directly.
297 */
298#define __pr_trace(pr, p, fmt, ...)					\
299	pr("%s: %s" fmt "\n",						\
300	   ({ const struct parport *__p = (p);				\
301		   __p ? __p->name : "parport_ip32"; }),		\
302	   __func__ , ##__VA_ARGS__)
303#define pr_trace(p, fmt, ...)	__pr_trace(pr_debug, p, fmt , ##__VA_ARGS__)
304#define pr_trace1(p, fmt, ...)	__pr_trace(pr_debug1, p, fmt , ##__VA_ARGS__)
305
306/*
307 * __pr_probe, pr_probe - print message if @verbose_probing is true
308 * @p:		pointer to &struct parport
309 * @fmt:	printk format string
310 * @...:	parameters for format string
311 *
312 * For new lines, use pr_probe().  Use __pr_probe() for continued lines.
313 */
314#define __pr_probe(...)							\
315	do { if (verbose_probing) printk(__VA_ARGS__); } while (0)
316#define pr_probe(p, fmt, ...)						\
317	__pr_probe(KERN_INFO PPIP32 "0x%lx: " fmt, (p)->base , ##__VA_ARGS__)
318
319/*
320 * parport_ip32_dump_state - print register status of parport
321 * @p:		pointer to &struct parport
322 * @str:	string to add in message
323 * @show_ecp_config:	shall we dump ECP configuration registers too?
324 *
325 * This function is only here for debugging purpose, and should be used with
326 * care.  Reading the parallel port registers may have undesired side effects.
327 * Especially if @show_ecp_config is true, the parallel port is resetted.
328 * This function is only defined if %DEBUG_PARPORT_IP32 >= 2.
329 */
330#if DEBUG_PARPORT_IP32 >= 2
331static void parport_ip32_dump_state(struct parport *p, char *str,
332				    unsigned int show_ecp_config)
333{
334	struct parport_ip32_private * const priv = p->physport->private_data;
335	unsigned int i;
336
337	printk(KERN_DEBUG PPIP32 "%s: state (%s):\n", p->name, str);
338	{
339		static const char ecr_modes[8][4] = {"SPP", "PS2", "PPF",
340						     "ECP", "EPP", "???",
341						     "TST", "CFG"};
342		unsigned int ecr = readb(priv->regs.ecr);
343		printk(KERN_DEBUG PPIP32 "    ecr=0x%02x", ecr);
344		printk(" %s",
345		       ecr_modes[(ecr & ECR_MODE_MASK) >> ECR_MODE_SHIFT]);
346		if (ecr & ECR_nERRINTR)
347			printk(",nErrIntrEn");
348		if (ecr & ECR_DMAEN)
349			printk(",dmaEn");
350		if (ecr & ECR_SERVINTR)
351			printk(",serviceIntr");
352		if (ecr & ECR_F_FULL)
353			printk(",f_full");
354		if (ecr & ECR_F_EMPTY)
355			printk(",f_empty");
356		printk("\n");
357	}
358	if (show_ecp_config) {
359		unsigned int oecr, cnfgA, cnfgB;
360		oecr = readb(priv->regs.ecr);
361		writeb(ECR_MODE_PS2, priv->regs.ecr);
362		writeb(ECR_MODE_CFG, priv->regs.ecr);
363		cnfgA = readb(priv->regs.cnfgA);
364		cnfgB = readb(priv->regs.cnfgB);
365		writeb(ECR_MODE_PS2, priv->regs.ecr);
366		writeb(oecr, priv->regs.ecr);
367		printk(KERN_DEBUG PPIP32 "    cnfgA=0x%02x", cnfgA);
368		printk(" ISA-%s", (cnfgA & CNFGA_IRQ) ? "Level" : "Pulses");
369		switch (cnfgA & CNFGA_ID_MASK) {
370		case CNFGA_ID_8:
371			printk(",8 bits");
372			break;
373		case CNFGA_ID_16:
374			printk(",16 bits");
375			break;
376		case CNFGA_ID_32:
377			printk(",32 bits");
378			break;
379		default:
380			printk(",unknown ID");
381			break;
382		}
383		if (!(cnfgA & CNFGA_nBYTEINTRANS))
384			printk(",ByteInTrans");
385		if ((cnfgA & CNFGA_ID_MASK) != CNFGA_ID_8)
386			printk(",%d byte%s left", cnfgA & CNFGA_PWORDLEFT,
387			       ((cnfgA & CNFGA_PWORDLEFT) > 1) ? "s" : "");
388		printk("\n");
389		printk(KERN_DEBUG PPIP32 "    cnfgB=0x%02x", cnfgB);
390		printk(" irq=%u,dma=%u",
391		       (cnfgB & CNFGB_IRQ_MASK) >> CNFGB_IRQ_SHIFT,
392		       (cnfgB & CNFGB_DMA_MASK) >> CNFGB_DMA_SHIFT);
393		printk(",intrValue=%d", !!(cnfgB & CNFGB_INTRVAL));
394		if (cnfgB & CNFGB_COMPRESS)
395			printk(",compress");
396		printk("\n");
397	}
398	for (i = 0; i < 2; i++) {
399		unsigned int dcr = i ? priv->dcr_cache : readb(priv->regs.dcr);
400		printk(KERN_DEBUG PPIP32 "    dcr(%s)=0x%02x",
401		       i ? "soft" : "hard", dcr);
402		printk(" %s", (dcr & DCR_DIR) ? "rev" : "fwd");
403		if (dcr & DCR_IRQ)
404			printk(",ackIntEn");
405		if (!(dcr & DCR_SELECT))
406			printk(",nSelectIn");
407		if (dcr & DCR_nINIT)
408			printk(",nInit");
409		if (!(dcr & DCR_AUTOFD))
410			printk(",nAutoFD");
411		if (!(dcr & DCR_STROBE))
412			printk(",nStrobe");
413		printk("\n");
414	}
415#define sep (f++ ? ',' : ' ')
416	{
417		unsigned int f = 0;
418		unsigned int dsr = readb(priv->regs.dsr);
419		printk(KERN_DEBUG PPIP32 "    dsr=0x%02x", dsr);
420		if (!(dsr & DSR_nBUSY))
421			printk("%cBusy", sep);
422		if (dsr & DSR_nACK)
423			printk("%cnAck", sep);
424		if (dsr & DSR_PERROR)
425			printk("%cPError", sep);
426		if (dsr & DSR_SELECT)
427			printk("%cSelect", sep);
428		if (dsr & DSR_nFAULT)
429			printk("%cnFault", sep);
430		if (!(dsr & DSR_nPRINT))
431			printk("%c(Print)", sep);
432		if (dsr & DSR_TIMEOUT)
433			printk("%cTimeout", sep);
434		printk("\n");
435	}
436#undef sep
437}
438#else /* DEBUG_PARPORT_IP32 < 2 */
439#define parport_ip32_dump_state(...)	do { } while (0)
440#endif
441
442/*
443 * CHECK_EXTRA_BITS - track and log extra bits
444 * @p:		pointer to &struct parport
445 * @b:		byte to inspect
446 * @m:		bit mask of authorized bits
447 *
448 * This is used to track and log extra bits that should not be there in
449 * parport_ip32_write_control() and parport_ip32_frob_control().  It is only
450 * defined if %DEBUG_PARPORT_IP32 >= 1.
451 */
452#if DEBUG_PARPORT_IP32 >= 1
453#define CHECK_EXTRA_BITS(p, b, m)					\
454	do {								\
455		unsigned int __b = (b), __m = (m);			\
456		if (__b & ~__m)						\
457			pr_debug1(PPIP32 "%s: extra bits in %s(%s): "	\
458				  "0x%02x/0x%02x\n",			\
459				  (p)->name, __func__, #b, __b, __m);	\
460	} while (0)
461#else /* DEBUG_PARPORT_IP32 < 1 */
462#define CHECK_EXTRA_BITS(...)	do { } while (0)
463#endif
464
465/*--- IP32 parallel port DMA operations --------------------------------*/
466
467/**
468 * struct parport_ip32_dma_data - private data needed for DMA operation
469 * @dir:	DMA direction (from or to device)
470 * @buf:	buffer physical address
471 * @len:	buffer length
472 * @next:	address of next bytes to DMA transfer
473 * @left:	number of bytes remaining
474 * @ctx:	next context to write (0: context_a; 1: context_b)
475 * @irq_on:	are the DMA IRQs currently enabled?
476 * @lock:	spinlock to protect access to the structure
477 */
478struct parport_ip32_dma_data {
479	enum dma_data_direction		dir;
480	dma_addr_t			buf;
481	dma_addr_t			next;
482	size_t				len;
483	size_t				left;
484	unsigned int			ctx;
485	unsigned int			irq_on;
486	spinlock_t			lock;
487};
488static struct parport_ip32_dma_data parport_ip32_dma;
489
490/**
491 * parport_ip32_dma_setup_context - setup next DMA context
492 * @limit:	maximum data size for the context
493 *
494 * The alignment constraints must be verified in caller function, and the
495 * parameter @limit must be set accordingly.
496 */
497static void parport_ip32_dma_setup_context(unsigned int limit)
498{
499	unsigned long flags;
500
501	spin_lock_irqsave(&parport_ip32_dma.lock, flags);
502	if (parport_ip32_dma.left > 0) {
503		/* Note: ctxreg is "volatile" here only because
504		 * mace->perif.ctrl.parport.context_a and context_b are
505		 * "volatile".  */
506		volatile u64 __iomem *ctxreg = (parport_ip32_dma.ctx == 0) ?
507			&mace->perif.ctrl.parport.context_a :
508			&mace->perif.ctrl.parport.context_b;
509		u64 count;
510		u64 ctxval;
511		if (parport_ip32_dma.left <= limit) {
512			count = parport_ip32_dma.left;
513			ctxval = MACEPAR_CONTEXT_LASTFLAG;
514		} else {
515			count = limit;
516			ctxval = 0;
517		}
518
519		pr_trace(NULL,
520			 "(%u): 0x%04x:0x%04x, %u -> %u%s",
521			 limit,
522			 (unsigned int)parport_ip32_dma.buf,
523			 (unsigned int)parport_ip32_dma.next,
524			 (unsigned int)count,
525			 parport_ip32_dma.ctx, ctxval ? "*" : "");
526
527		ctxval |= parport_ip32_dma.next &
528			MACEPAR_CONTEXT_BASEADDR_MASK;
529		ctxval |= ((count - 1) << MACEPAR_CONTEXT_DATALEN_SHIFT) &
530			MACEPAR_CONTEXT_DATALEN_MASK;
531		writeq(ctxval, ctxreg);
532		parport_ip32_dma.next += count;
533		parport_ip32_dma.left -= count;
534		parport_ip32_dma.ctx ^= 1U;
535	}
536	/* If there is nothing more to send, disable IRQs to avoid to
537	 * face an IRQ storm which can lock the machine.  Disable them
538	 * only once. */
539	if (parport_ip32_dma.left == 0 && parport_ip32_dma.irq_on) {
540		pr_debug(PPIP32 "IRQ off (ctx)\n");
541		disable_irq_nosync(MACEISA_PAR_CTXA_IRQ);
542		disable_irq_nosync(MACEISA_PAR_CTXB_IRQ);
543		parport_ip32_dma.irq_on = 0;
544	}
545	spin_unlock_irqrestore(&parport_ip32_dma.lock, flags);
546}
547
548/**
549 * parport_ip32_dma_interrupt - DMA interrupt handler
550 * @irq:	interrupt number
551 * @dev_id:	unused
552 */
553static irqreturn_t parport_ip32_dma_interrupt(int irq, void *dev_id)
554{
555	if (parport_ip32_dma.left)
556		pr_trace(NULL, "(%d): ctx=%d", irq, parport_ip32_dma.ctx);
557	parport_ip32_dma_setup_context(MACEPAR_CONTEXT_DATA_BOUND);
558	return IRQ_HANDLED;
559}
560
561#if DEBUG_PARPORT_IP32
562static irqreturn_t parport_ip32_merr_interrupt(int irq, void *dev_id)
563{
564	pr_trace1(NULL, "(%d)", irq);
565	return IRQ_HANDLED;
566}
567#endif
568
569/**
570 * parport_ip32_dma_start - begins a DMA transfer
571 * @dir:	DMA direction: DMA_TO_DEVICE or DMA_FROM_DEVICE
572 * @addr:	pointer to data buffer
573 * @count:	buffer size
574 *
575 * Calls to parport_ip32_dma_start() and parport_ip32_dma_stop() must be
576 * correctly balanced.
577 */
578static int parport_ip32_dma_start(enum dma_data_direction dir,
579				  void *addr, size_t count)
580{
581	unsigned int limit;
582	u64 ctrl;
583
584	pr_trace(NULL, "(%d, %lu)", dir, (unsigned long)count);
585
586	BUG_ON(dir != DMA_TO_DEVICE);
587
588	/* Reset DMA controller */
589	ctrl = MACEPAR_CTLSTAT_RESET;
590	writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
591
592	/* DMA IRQs should normally be enabled */
593	if (!parport_ip32_dma.irq_on) {
594		WARN_ON(1);
595		enable_irq(MACEISA_PAR_CTXA_IRQ);
596		enable_irq(MACEISA_PAR_CTXB_IRQ);
597		parport_ip32_dma.irq_on = 1;
598	}
599
600	/* Prepare DMA pointers */
601	parport_ip32_dma.dir = dir;
602	parport_ip32_dma.buf = dma_map_single(NULL, addr, count, dir);
603	parport_ip32_dma.len = count;
604	parport_ip32_dma.next = parport_ip32_dma.buf;
605	parport_ip32_dma.left = parport_ip32_dma.len;
606	parport_ip32_dma.ctx = 0;
607
608	/* Setup DMA direction and first two contexts */
609	ctrl = (dir == DMA_TO_DEVICE) ? 0 : MACEPAR_CTLSTAT_DIRECTION;
610	writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
611	/* Single transfer should not cross a 4K page boundary */
612	limit = MACEPAR_CONTEXT_DATA_BOUND -
613		(parport_ip32_dma.next & (MACEPAR_CONTEXT_DATA_BOUND - 1));
614	parport_ip32_dma_setup_context(limit);
615	parport_ip32_dma_setup_context(MACEPAR_CONTEXT_DATA_BOUND);
616
617	/* Real start of DMA transfer */
618	ctrl |= MACEPAR_CTLSTAT_ENABLE;
619	writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
620
621	return 0;
622}
623
624/**
625 * parport_ip32_dma_stop - ends a running DMA transfer
626 *
627 * Calls to parport_ip32_dma_start() and parport_ip32_dma_stop() must be
628 * correctly balanced.
629 */
630static void parport_ip32_dma_stop(void)
631{
632	u64 ctx_a;
633	u64 ctx_b;
634	u64 ctrl;
635	u64 diag;
636	size_t res[2];	/* {[0] = res_a, [1] = res_b} */
637
638	pr_trace(NULL, "()");
639
640	/* Disable IRQs */
641	spin_lock_irq(&parport_ip32_dma.lock);
642	if (parport_ip32_dma.irq_on) {
643		pr_debug(PPIP32 "IRQ off (stop)\n");
644		disable_irq_nosync(MACEISA_PAR_CTXA_IRQ);
645		disable_irq_nosync(MACEISA_PAR_CTXB_IRQ);
646		parport_ip32_dma.irq_on = 0;
647	}
648	spin_unlock_irq(&parport_ip32_dma.lock);
649	/* Force IRQ synchronization, even if the IRQs were disabled
650	 * elsewhere. */
651	synchronize_irq(MACEISA_PAR_CTXA_IRQ);
652	synchronize_irq(MACEISA_PAR_CTXB_IRQ);
653
654	/* Stop DMA transfer */
655	ctrl = readq(&mace->perif.ctrl.parport.cntlstat);
656	ctrl &= ~MACEPAR_CTLSTAT_ENABLE;
657	writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
658
659	/* Adjust residue (parport_ip32_dma.left) */
660	ctx_a = readq(&mace->perif.ctrl.parport.context_a);
661	ctx_b = readq(&mace->perif.ctrl.parport.context_b);
662	ctrl = readq(&mace->perif.ctrl.parport.cntlstat);
663	diag = readq(&mace->perif.ctrl.parport.diagnostic);
664	res[0] = (ctrl & MACEPAR_CTLSTAT_CTXA_VALID) ?
665		1 + ((ctx_a & MACEPAR_CONTEXT_DATALEN_MASK) >>
666		     MACEPAR_CONTEXT_DATALEN_SHIFT) :
667		0;
668	res[1] = (ctrl & MACEPAR_CTLSTAT_CTXB_VALID) ?
669		1 + ((ctx_b & MACEPAR_CONTEXT_DATALEN_MASK) >>
670		     MACEPAR_CONTEXT_DATALEN_SHIFT) :
671		0;
672	if (diag & MACEPAR_DIAG_DMACTIVE)
673		res[(diag & MACEPAR_DIAG_CTXINUSE) != 0] =
674			1 + ((diag & MACEPAR_DIAG_CTRMASK) >>
675			     MACEPAR_DIAG_CTRSHIFT);
676	parport_ip32_dma.left += res[0] + res[1];
677
678	/* Reset DMA controller, and re-enable IRQs */
679	ctrl = MACEPAR_CTLSTAT_RESET;
680	writeq(ctrl, &mace->perif.ctrl.parport.cntlstat);
681	pr_debug(PPIP32 "IRQ on (stop)\n");
682	enable_irq(MACEISA_PAR_CTXA_IRQ);
683	enable_irq(MACEISA_PAR_CTXB_IRQ);
684	parport_ip32_dma.irq_on = 1;
685
686	dma_unmap_single(NULL, parport_ip32_dma.buf, parport_ip32_dma.len,
687			 parport_ip32_dma.dir);
688}
689
690/**
691 * parport_ip32_dma_get_residue - get residue from last DMA transfer
692 *
693 * Returns the number of bytes remaining from last DMA transfer.
694 */
695static inline size_t parport_ip32_dma_get_residue(void)
696{
697	return parport_ip32_dma.left;
698}
699
700/**
701 * parport_ip32_dma_register - initialize DMA engine
702 *
703 * Returns zero for success.
704 */
705static int parport_ip32_dma_register(void)
706{
707	int err;
708
709	spin_lock_init(&parport_ip32_dma.lock);
710	parport_ip32_dma.irq_on = 1;
711
712	/* Reset DMA controller */
713	writeq(MACEPAR_CTLSTAT_RESET, &mace->perif.ctrl.parport.cntlstat);
714
715	/* Request IRQs */
716	err = request_irq(MACEISA_PAR_CTXA_IRQ, parport_ip32_dma_interrupt,
717			  0, "parport_ip32", NULL);
718	if (err)
719		goto fail_a;
720	err = request_irq(MACEISA_PAR_CTXB_IRQ, parport_ip32_dma_interrupt,
721			  0, "parport_ip32", NULL);
722	if (err)
723		goto fail_b;
724#if DEBUG_PARPORT_IP32
725	err = request_irq(MACEISA_PAR_MERR_IRQ, parport_ip32_merr_interrupt,
726			  0, "parport_ip32", NULL);
727	if (err)
728		goto fail_merr;
729#endif
730	return 0;
731
732#if DEBUG_PARPORT_IP32
733fail_merr:
734	free_irq(MACEISA_PAR_CTXB_IRQ, NULL);
735#endif
736fail_b:
737	free_irq(MACEISA_PAR_CTXA_IRQ, NULL);
738fail_a:
739	return err;
740}
741
742/**
743 * parport_ip32_dma_unregister - release and free resources for DMA engine
744 */
745static void parport_ip32_dma_unregister(void)
746{
747#if DEBUG_PARPORT_IP32
748	free_irq(MACEISA_PAR_MERR_IRQ, NULL);
749#endif
750	free_irq(MACEISA_PAR_CTXB_IRQ, NULL);
751	free_irq(MACEISA_PAR_CTXA_IRQ, NULL);
752}
753
754/*--- Interrupt handlers and associates --------------------------------*/
755
756/**
757 * parport_ip32_wakeup - wakes up code waiting for an interrupt
758 * @p:		pointer to &struct parport
759 */
760static inline void parport_ip32_wakeup(struct parport *p)
761{
762	struct parport_ip32_private * const priv = p->physport->private_data;
763	complete(&priv->irq_complete);
764}
765
766/**
767 * parport_ip32_interrupt - interrupt handler
768 * @irq:	interrupt number
769 * @dev_id:	pointer to &struct parport
770 *
771 * Caught interrupts are forwarded to the upper parport layer if IRQ_mode is
772 * %PARPORT_IP32_IRQ_FWD.
773 */
774static irqreturn_t parport_ip32_interrupt(int irq, void *dev_id)
775{
776	struct parport * const p = dev_id;
777	struct parport_ip32_private * const priv = p->physport->private_data;
778	enum parport_ip32_irq_mode irq_mode = priv->irq_mode;
779
780	switch (irq_mode) {
781	case PARPORT_IP32_IRQ_FWD:
782		return parport_irq_handler(irq, dev_id);
783
784	case PARPORT_IP32_IRQ_HERE:
785		parport_ip32_wakeup(p);
786		break;
787	}
788
789	return IRQ_HANDLED;
790}
791
792/*--- Some utility function to manipulate ECR register -----------------*/
793
794/**
795 * parport_ip32_read_econtrol - read contents of the ECR register
796 * @p:		pointer to &struct parport
797 */
798static inline unsigned int parport_ip32_read_econtrol(struct parport *p)
799{
800	struct parport_ip32_private * const priv = p->physport->private_data;
801	return readb(priv->regs.ecr);
802}
803
804/**
805 * parport_ip32_write_econtrol - write new contents to the ECR register
806 * @p:		pointer to &struct parport
807 * @c:		new value to write
808 */
809static inline void parport_ip32_write_econtrol(struct parport *p,
810					       unsigned int c)
811{
812	struct parport_ip32_private * const priv = p->physport->private_data;
813	writeb(c, priv->regs.ecr);
814}
815
816/**
817 * parport_ip32_frob_econtrol - change bits from the ECR register
818 * @p:		pointer to &struct parport
819 * @mask:	bit mask of bits to change
820 * @val:	new value for changed bits
821 *
822 * Read from the ECR, mask out the bits in @mask, exclusive-or with the bits
823 * in @val, and write the result to the ECR.
824 */
825static inline void parport_ip32_frob_econtrol(struct parport *p,
826					      unsigned int mask,
827					      unsigned int val)
828{
829	unsigned int c;
830	c = (parport_ip32_read_econtrol(p) & ~mask) ^ val;
831	parport_ip32_write_econtrol(p, c);
832}
833
834/**
835 * parport_ip32_set_mode - change mode of ECP port
836 * @p:		pointer to &struct parport
837 * @mode:	new mode to write in ECR
838 *
839 * ECR is reset in a sane state (interrupts and DMA disabled), and placed in
840 * mode @mode.  Go through PS2 mode if needed.
841 */
842static void parport_ip32_set_mode(struct parport *p, unsigned int mode)
843{
844	unsigned int omode;
845
846	mode &= ECR_MODE_MASK;
847	omode = parport_ip32_read_econtrol(p) & ECR_MODE_MASK;
848
849	if (!(mode == ECR_MODE_SPP || mode == ECR_MODE_PS2
850	      || omode == ECR_MODE_SPP || omode == ECR_MODE_PS2)) {
851		/* We have to go through PS2 mode */
852		unsigned int ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR;
853		parport_ip32_write_econtrol(p, ecr);
854	}
855	parport_ip32_write_econtrol(p, mode | ECR_nERRINTR | ECR_SERVINTR);
856}
857
858/*--- Basic functions needed for parport -------------------------------*/
859
860/**
861 * parport_ip32_read_data - return current contents of the DATA register
862 * @p:		pointer to &struct parport
863 */
864static inline unsigned char parport_ip32_read_data(struct parport *p)
865{
866	struct parport_ip32_private * const priv = p->physport->private_data;
867	return readb(priv->regs.data);
868}
869
870/**
871 * parport_ip32_write_data - set new contents for the DATA register
872 * @p:		pointer to &struct parport
873 * @d:		new value to write
874 */
875static inline void parport_ip32_write_data(struct parport *p, unsigned char d)
876{
877	struct parport_ip32_private * const priv = p->physport->private_data;
878	writeb(d, priv->regs.data);
879}
880
881/**
882 * parport_ip32_read_status - return current contents of the DSR register
883 * @p:		pointer to &struct parport
884 */
885static inline unsigned char parport_ip32_read_status(struct parport *p)
886{
887	struct parport_ip32_private * const priv = p->physport->private_data;
888	return readb(priv->regs.dsr);
889}
890
891/**
892 * __parport_ip32_read_control - return cached contents of the DCR register
893 * @p:		pointer to &struct parport
894 */
895static inline unsigned int __parport_ip32_read_control(struct parport *p)
896{
897	struct parport_ip32_private * const priv = p->physport->private_data;
898	return priv->dcr_cache; /* use soft copy */
899}
900
901/**
902 * __parport_ip32_write_control - set new contents for the DCR register
903 * @p:		pointer to &struct parport
904 * @c:		new value to write
905 */
906static inline void __parport_ip32_write_control(struct parport *p,
907						unsigned int c)
908{
909	struct parport_ip32_private * const priv = p->physport->private_data;
910	CHECK_EXTRA_BITS(p, c, priv->dcr_writable);
911	c &= priv->dcr_writable; /* only writable bits */
912	writeb(c, priv->regs.dcr);
913	priv->dcr_cache = c;		/* update soft copy */
914}
915
916/**
917 * __parport_ip32_frob_control - change bits from the DCR register
918 * @p:		pointer to &struct parport
919 * @mask:	bit mask of bits to change
920 * @val:	new value for changed bits
921 *
922 * This is equivalent to read from the DCR, mask out the bits in @mask,
923 * exclusive-or with the bits in @val, and write the result to the DCR.
924 * Actually, the cached contents of the DCR is used.
925 */
926static inline void __parport_ip32_frob_control(struct parport *p,
927					       unsigned int mask,
928					       unsigned int val)
929{
930	unsigned int c;
931	c = (__parport_ip32_read_control(p) & ~mask) ^ val;
932	__parport_ip32_write_control(p, c);
933}
934
935/**
936 * parport_ip32_read_control - return cached contents of the DCR register
937 * @p:		pointer to &struct parport
938 *
939 * The return value is masked so as to only return the value of %DCR_STROBE,
940 * %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT.
941 */
942static inline unsigned char parport_ip32_read_control(struct parport *p)
943{
944	const unsigned int rm =
945		DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT;
946	return __parport_ip32_read_control(p) & rm;
947}
948
949/**
950 * parport_ip32_write_control - set new contents for the DCR register
951 * @p:		pointer to &struct parport
952 * @c:		new value to write
953 *
954 * The value is masked so as to only change the value of %DCR_STROBE,
955 * %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT.
956 */
957static inline void parport_ip32_write_control(struct parport *p,
958					      unsigned char c)
959{
960	const unsigned int wm =
961		DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT;
962	CHECK_EXTRA_BITS(p, c, wm);
963	__parport_ip32_frob_control(p, wm, c & wm);
964}
965
966/**
967 * parport_ip32_frob_control - change bits from the DCR register
968 * @p:		pointer to &struct parport
969 * @mask:	bit mask of bits to change
970 * @val:	new value for changed bits
971 *
972 * This differs from __parport_ip32_frob_control() in that it only allows to
973 * change the value of %DCR_STROBE, %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT.
974 */
975static inline unsigned char parport_ip32_frob_control(struct parport *p,
976						      unsigned char mask,
977						      unsigned char val)
978{
979	const unsigned int wm =
980		DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT;
981	CHECK_EXTRA_BITS(p, mask, wm);
982	CHECK_EXTRA_BITS(p, val, wm);
983	__parport_ip32_frob_control(p, mask & wm, val & wm);
984	return parport_ip32_read_control(p);
985}
986
987/**
988 * parport_ip32_disable_irq - disable interrupts on the rising edge of nACK
989 * @p:		pointer to &struct parport
990 */
991static inline void parport_ip32_disable_irq(struct parport *p)
992{
993	__parport_ip32_frob_control(p, DCR_IRQ, 0);
994}
995
996/**
997 * parport_ip32_enable_irq - enable interrupts on the rising edge of nACK
998 * @p:		pointer to &struct parport
999 */
1000static inline void parport_ip32_enable_irq(struct parport *p)
1001{
1002	__parport_ip32_frob_control(p, DCR_IRQ, DCR_IRQ);
1003}
1004
1005/**
1006 * parport_ip32_data_forward - enable host-to-peripheral communications
1007 * @p:		pointer to &struct parport
1008 *
1009 * Enable the data line drivers, for 8-bit host-to-peripheral communications.
1010 */
1011static inline void parport_ip32_data_forward(struct parport *p)
1012{
1013	__parport_ip32_frob_control(p, DCR_DIR, 0);
1014}
1015
1016/**
1017 * parport_ip32_data_reverse - enable peripheral-to-host communications
1018 * @p:		pointer to &struct parport
1019 *
1020 * Place the data bus in a high impedance state, if @p->modes has the
1021 * PARPORT_MODE_TRISTATE bit set.
1022 */
1023static inline void parport_ip32_data_reverse(struct parport *p)
1024{
1025	__parport_ip32_frob_control(p, DCR_DIR, DCR_DIR);
1026}
1027
1028/**
1029 * parport_ip32_init_state - for core parport code
1030 * @dev:	pointer to &struct pardevice
1031 * @s:		pointer to &struct parport_state to initialize
1032 */
1033static void parport_ip32_init_state(struct pardevice *dev,
1034				    struct parport_state *s)
1035{
1036	s->u.ip32.dcr = DCR_SELECT | DCR_nINIT;
1037	s->u.ip32.ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR;
1038}
1039
1040/**
1041 * parport_ip32_save_state - for core parport code
1042 * @p:		pointer to &struct parport
1043 * @s:		pointer to &struct parport_state to save state to
1044 */
1045static void parport_ip32_save_state(struct parport *p,
1046				    struct parport_state *s)
1047{
1048	s->u.ip32.dcr = __parport_ip32_read_control(p);
1049	s->u.ip32.ecr = parport_ip32_read_econtrol(p);
1050}
1051
1052/**
1053 * parport_ip32_restore_state - for core parport code
1054 * @p:		pointer to &struct parport
1055 * @s:		pointer to &struct parport_state to restore state from
1056 */
1057static void parport_ip32_restore_state(struct parport *p,
1058				       struct parport_state *s)
1059{
1060	parport_ip32_set_mode(p, s->u.ip32.ecr & ECR_MODE_MASK);
1061	parport_ip32_write_econtrol(p, s->u.ip32.ecr);
1062	__parport_ip32_write_control(p, s->u.ip32.dcr);
1063}
1064
1065/*--- EPP mode functions -----------------------------------------------*/
1066
1067/**
1068 * parport_ip32_clear_epp_timeout - clear Timeout bit in EPP mode
1069 * @p:		pointer to &struct parport
1070 *
1071 * Returns 1 if the Timeout bit is clear, and 0 otherwise.
1072 */
1073static unsigned int parport_ip32_clear_epp_timeout(struct parport *p)
1074{
1075	struct parport_ip32_private * const priv = p->physport->private_data;
1076	unsigned int cleared;
1077
1078	if (!(parport_ip32_read_status(p) & DSR_TIMEOUT))
1079		cleared = 1;
1080	else {
1081		unsigned int r;
1082		/* To clear timeout some chips require double read */
1083		parport_ip32_read_status(p);
1084		r = parport_ip32_read_status(p);
1085		/* Some reset by writing 1 */
1086		writeb(r | DSR_TIMEOUT, priv->regs.dsr);
1087		/* Others by writing 0 */
1088		writeb(r & ~DSR_TIMEOUT, priv->regs.dsr);
1089
1090		r = parport_ip32_read_status(p);
1091		cleared = !(r & DSR_TIMEOUT);
1092	}
1093
1094	pr_trace(p, "(): %s", cleared ? "cleared" : "failed");
1095	return cleared;
1096}
1097
1098/**
1099 * parport_ip32_epp_read - generic EPP read function
1100 * @eppreg:	I/O register to read from
1101 * @p:		pointer to &struct parport
1102 * @buf:	buffer to store read data
1103 * @len:	length of buffer @buf
1104 * @flags:	may be PARPORT_EPP_FAST
1105 */
1106static size_t parport_ip32_epp_read(void __iomem *eppreg,
1107				    struct parport *p, void *buf,
1108				    size_t len, int flags)
1109{
1110	struct parport_ip32_private * const priv = p->physport->private_data;
1111	size_t got;
1112	parport_ip32_set_mode(p, ECR_MODE_EPP);
1113	parport_ip32_data_reverse(p);
1114	parport_ip32_write_control(p, DCR_nINIT);
1115	if ((flags & PARPORT_EPP_FAST) && (len > 1)) {
1116		readsb(eppreg, buf, len);
1117		if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
1118			parport_ip32_clear_epp_timeout(p);
1119			return -EIO;
1120		}
1121		got = len;
1122	} else {
1123		u8 *bufp = buf;
1124		for (got = 0; got < len; got++) {
1125			*bufp++ = readb(eppreg);
1126			if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
1127				parport_ip32_clear_epp_timeout(p);
1128				break;
1129			}
1130		}
1131	}
1132	parport_ip32_data_forward(p);
1133	parport_ip32_set_mode(p, ECR_MODE_PS2);
1134	return got;
1135}
1136
1137/**
1138 * parport_ip32_epp_write - generic EPP write function
1139 * @eppreg:	I/O register to write to
1140 * @p:		pointer to &struct parport
1141 * @buf:	buffer of data to write
1142 * @len:	length of buffer @buf
1143 * @flags:	may be PARPORT_EPP_FAST
1144 */
1145static size_t parport_ip32_epp_write(void __iomem *eppreg,
1146				     struct parport *p, const void *buf,
1147				     size_t len, int flags)
1148{
1149	struct parport_ip32_private * const priv = p->physport->private_data;
1150	size_t written;
1151	parport_ip32_set_mode(p, ECR_MODE_EPP);
1152	parport_ip32_data_forward(p);
1153	parport_ip32_write_control(p, DCR_nINIT);
1154	if ((flags & PARPORT_EPP_FAST) && (len > 1)) {
1155		writesb(eppreg, buf, len);
1156		if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
1157			parport_ip32_clear_epp_timeout(p);
1158			return -EIO;
1159		}
1160		written = len;
1161	} else {
1162		const u8 *bufp = buf;
1163		for (written = 0; written < len; written++) {
1164			writeb(*bufp++, eppreg);
1165			if (readb(priv->regs.dsr) & DSR_TIMEOUT) {
1166				parport_ip32_clear_epp_timeout(p);
1167				break;
1168			}
1169		}
1170	}
1171	parport_ip32_set_mode(p, ECR_MODE_PS2);
1172	return written;
1173}
1174
1175/**
1176 * parport_ip32_epp_read_data - read a block of data in EPP mode
1177 * @p:		pointer to &struct parport
1178 * @buf:	buffer to store read data
1179 * @len:	length of buffer @buf
1180 * @flags:	may be PARPORT_EPP_FAST
1181 */
1182static size_t parport_ip32_epp_read_data(struct parport *p, void *buf,
1183					 size_t len, int flags)
1184{
1185	struct parport_ip32_private * const priv = p->physport->private_data;
1186	return parport_ip32_epp_read(priv->regs.eppData0, p, buf, len, flags);
1187}
1188
1189/**
1190 * parport_ip32_epp_write_data - write a block of data in EPP mode
1191 * @p:		pointer to &struct parport
1192 * @buf:	buffer of data to write
1193 * @len:	length of buffer @buf
1194 * @flags:	may be PARPORT_EPP_FAST
1195 */
1196static size_t parport_ip32_epp_write_data(struct parport *p, const void *buf,
1197					  size_t len, int flags)
1198{
1199	struct parport_ip32_private * const priv = p->physport->private_data;
1200	return parport_ip32_epp_write(priv->regs.eppData0, p, buf, len, flags);
1201}
1202
1203/**
1204 * parport_ip32_epp_read_addr - read a block of addresses in EPP mode
1205 * @p:		pointer to &struct parport
1206 * @buf:	buffer to store read data
1207 * @len:	length of buffer @buf
1208 * @flags:	may be PARPORT_EPP_FAST
1209 */
1210static size_t parport_ip32_epp_read_addr(struct parport *p, void *buf,
1211					 size_t len, int flags)
1212{
1213	struct parport_ip32_private * const priv = p->physport->private_data;
1214	return parport_ip32_epp_read(priv->regs.eppAddr, p, buf, len, flags);
1215}
1216
1217/**
1218 * parport_ip32_epp_write_addr - write a block of addresses in EPP mode
1219 * @p:		pointer to &struct parport
1220 * @buf:	buffer of data to write
1221 * @len:	length of buffer @buf
1222 * @flags:	may be PARPORT_EPP_FAST
1223 */
1224static size_t parport_ip32_epp_write_addr(struct parport *p, const void *buf,
1225					  size_t len, int flags)
1226{
1227	struct parport_ip32_private * const priv = p->physport->private_data;
1228	return parport_ip32_epp_write(priv->regs.eppAddr, p, buf, len, flags);
1229}
1230
1231/*--- ECP mode functions (FIFO) ----------------------------------------*/
1232
1233/**
1234 * parport_ip32_fifo_wait_break - check if the waiting function should return
1235 * @p:		pointer to &struct parport
1236 * @expire:	timeout expiring date, in jiffies
1237 *
1238 * parport_ip32_fifo_wait_break() checks if the waiting function should return
1239 * immediately or not.  The break conditions are:
1240 *	- expired timeout;
1241 *	- a pending signal;
1242 *	- nFault asserted low.
1243 * This function also calls cond_resched().
1244 */
1245static unsigned int parport_ip32_fifo_wait_break(struct parport *p,
1246						 unsigned long expire)
1247{
1248	cond_resched();
1249	if (time_after(jiffies, expire)) {
1250		pr_debug1(PPIP32 "%s: FIFO write timed out\n", p->name);
1251		return 1;
1252	}
1253	if (signal_pending(current)) {
1254		pr_debug1(PPIP32 "%s: Signal pending\n", p->name);
1255		return 1;
1256	}
1257	if (!(parport_ip32_read_status(p) & DSR_nFAULT)) {
1258		pr_debug1(PPIP32 "%s: nFault asserted low\n", p->name);
1259		return 1;
1260	}
1261	return 0;
1262}
1263
1264/**
1265 * parport_ip32_fwp_wait_polling - wait for FIFO to empty (polling)
1266 * @p:		pointer to &struct parport
1267 *
1268 * Returns the number of bytes that can safely be written in the FIFO.  A
1269 * return value of zero means that the calling function should terminate as
1270 * fast as possible.
1271 */
1272static unsigned int parport_ip32_fwp_wait_polling(struct parport *p)
1273{
1274	struct parport_ip32_private * const priv = p->physport->private_data;
1275	struct parport * const physport = p->physport;
1276	unsigned long expire;
1277	unsigned int count;
1278	unsigned int ecr;
1279
1280	expire = jiffies + physport->cad->timeout;
1281	count = 0;
1282	while (1) {
1283		if (parport_ip32_fifo_wait_break(p, expire))
1284			break;
1285
1286		/* Check FIFO state.  We do nothing when the FIFO is nor full,
1287		 * nor empty.  It appears that the FIFO full bit is not always
1288		 * reliable, the FIFO state is sometimes wrongly reported, and
1289		 * the chip gets confused if we give it another byte. */
1290		ecr = parport_ip32_read_econtrol(p);
1291		if (ecr & ECR_F_EMPTY) {
1292			/* FIFO is empty, fill it up */
1293			count = priv->fifo_depth;
1294			break;
1295		}
1296
1297		/* Wait a moment... */
1298		udelay(FIFO_POLLING_INTERVAL);
1299	} /* while (1) */
1300
1301	return count;
1302}
1303
1304/**
1305 * parport_ip32_fwp_wait_interrupt - wait for FIFO to empty (interrupt-driven)
1306 * @p:		pointer to &struct parport
1307 *
1308 * Returns the number of bytes that can safely be written in the FIFO.  A
1309 * return value of zero means that the calling function should terminate as
1310 * fast as possible.
1311 */
1312static unsigned int parport_ip32_fwp_wait_interrupt(struct parport *p)
1313{
1314	static unsigned int lost_interrupt = 0;
1315	struct parport_ip32_private * const priv = p->physport->private_data;
1316	struct parport * const physport = p->physport;
1317	unsigned long nfault_timeout;
1318	unsigned long expire;
1319	unsigned int count;
1320	unsigned int ecr;
1321
1322	nfault_timeout = min((unsigned long)physport->cad->timeout,
1323			     msecs_to_jiffies(FIFO_NFAULT_TIMEOUT));
1324	expire = jiffies + physport->cad->timeout;
1325	count = 0;
1326	while (1) {
1327		if (parport_ip32_fifo_wait_break(p, expire))
1328			break;
1329
1330		/* Initialize mutex used to take interrupts into account */
1331		INIT_COMPLETION(priv->irq_complete);
1332
1333		/* Enable serviceIntr */
1334		parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0);
1335
1336		/* Enabling serviceIntr while the FIFO is empty does not
1337		 * always generate an interrupt, so check for emptiness
1338		 * now. */
1339		ecr = parport_ip32_read_econtrol(p);
1340		if (!(ecr & ECR_F_EMPTY)) {
1341			/* FIFO is not empty: wait for an interrupt or a
1342			 * timeout to occur */
1343			wait_for_completion_interruptible_timeout(
1344				&priv->irq_complete, nfault_timeout);
1345			ecr = parport_ip32_read_econtrol(p);
1346			if ((ecr & ECR_F_EMPTY) && !(ecr & ECR_SERVINTR)
1347			    && !lost_interrupt) {
1348				printk(KERN_WARNING PPIP32
1349				       "%s: lost interrupt in %s\n",
1350				       p->name, __func__);
1351				lost_interrupt = 1;
1352			}
1353		}
1354
1355		/* Disable serviceIntr */
1356		parport_ip32_frob_econtrol(p, ECR_SERVINTR, ECR_SERVINTR);
1357
1358		/* Check FIFO state */
1359		if (ecr & ECR_F_EMPTY) {
1360			/* FIFO is empty, fill it up */
1361			count = priv->fifo_depth;
1362			break;
1363		} else if (ecr & ECR_SERVINTR) {
1364			/* FIFO is not empty, but we know that can safely push
1365			 * writeIntrThreshold bytes into it */
1366			count = priv->writeIntrThreshold;
1367			break;
1368		}
1369		/* FIFO is not empty, and we did not get any interrupt.
1370		 * Either it's time to check for nFault, or a signal is
1371		 * pending.  This is verified in
1372		 * parport_ip32_fifo_wait_break(), so we continue the loop. */
1373	} /* while (1) */
1374
1375	return count;
1376}
1377
1378/**
1379 * parport_ip32_fifo_write_block_pio - write a block of data (PIO mode)
1380 * @p:		pointer to &struct parport
1381 * @buf:	buffer of data to write
1382 * @len:	length of buffer @buf
1383 *
1384 * Uses PIO to write the contents of the buffer @buf into the parallel port
1385 * FIFO.  Returns the number of bytes that were actually written.  It can work
1386 * with or without the help of interrupts.  The parallel port must be
1387 * correctly initialized before calling parport_ip32_fifo_write_block_pio().
1388 */
1389static size_t parport_ip32_fifo_write_block_pio(struct parport *p,
1390						const void *buf, size_t len)
1391{
1392	struct parport_ip32_private * const priv = p->physport->private_data;
1393	const u8 *bufp = buf;
1394	size_t left = len;
1395
1396	priv->irq_mode = PARPORT_IP32_IRQ_HERE;
1397
1398	while (left > 0) {
1399		unsigned int count;
1400
1401		count = (p->irq == PARPORT_IRQ_NONE) ?
1402			parport_ip32_fwp_wait_polling(p) :
1403			parport_ip32_fwp_wait_interrupt(p);
1404		if (count == 0)
1405			break;	/* Transmission should be stopped */
1406		if (count > left)
1407			count = left;
1408		if (count == 1) {
1409			writeb(*bufp, priv->regs.fifo);
1410			bufp++, left--;
1411		} else {
1412			writesb(priv->regs.fifo, bufp, count);
1413			bufp += count, left -= count;
1414		}
1415	}
1416
1417	priv->irq_mode = PARPORT_IP32_IRQ_FWD;
1418
1419	return len - left;
1420}
1421
1422/**
1423 * parport_ip32_fifo_write_block_dma - write a block of data (DMA mode)
1424 * @p:		pointer to &struct parport
1425 * @buf:	buffer of data to write
1426 * @len:	length of buffer @buf
1427 *
1428 * Uses DMA to write the contents of the buffer @buf into the parallel port
1429 * FIFO.  Returns the number of bytes that were actually written.  The
1430 * parallel port must be correctly initialized before calling
1431 * parport_ip32_fifo_write_block_dma().
1432 */
1433static size_t parport_ip32_fifo_write_block_dma(struct parport *p,
1434						const void *buf, size_t len)
1435{
1436	struct parport_ip32_private * const priv = p->physport->private_data;
1437	struct parport * const physport = p->physport;
1438	unsigned long nfault_timeout;
1439	unsigned long expire;
1440	size_t written;
1441	unsigned int ecr;
1442
1443	priv->irq_mode = PARPORT_IP32_IRQ_HERE;
1444
1445	parport_ip32_dma_start(DMA_TO_DEVICE, (void *)buf, len);
1446	INIT_COMPLETION(priv->irq_complete);
1447	parport_ip32_frob_econtrol(p, ECR_DMAEN | ECR_SERVINTR, ECR_DMAEN);
1448
1449	nfault_timeout = min((unsigned long)physport->cad->timeout,
1450			     msecs_to_jiffies(FIFO_NFAULT_TIMEOUT));
1451	expire = jiffies + physport->cad->timeout;
1452	while (1) {
1453		if (parport_ip32_fifo_wait_break(p, expire))
1454			break;
1455		wait_for_completion_interruptible_timeout(&priv->irq_complete,
1456							  nfault_timeout);
1457		ecr = parport_ip32_read_econtrol(p);
1458		if (ecr & ECR_SERVINTR)
1459			break;	/* DMA transfer just finished */
1460	}
1461	parport_ip32_dma_stop();
1462	written = len - parport_ip32_dma_get_residue();
1463
1464	priv->irq_mode = PARPORT_IP32_IRQ_FWD;
1465
1466	return written;
1467}
1468
1469/**
1470 * parport_ip32_fifo_write_block - write a block of data
1471 * @p:		pointer to &struct parport
1472 * @buf:	buffer of data to write
1473 * @len:	length of buffer @buf
1474 *
1475 * Uses PIO or DMA to write the contents of the buffer @buf into the parallel
1476 * p FIFO.  Returns the number of bytes that were actually written.
1477 */
1478static size_t parport_ip32_fifo_write_block(struct parport *p,
1479					    const void *buf, size_t len)
1480{
1481	size_t written = 0;
1482	if (len)
1483		written = (p->modes & PARPORT_MODE_DMA) ?
1484			parport_ip32_fifo_write_block_dma(p, buf, len) :
1485			parport_ip32_fifo_write_block_pio(p, buf, len);
1486	return written;
1487}
1488
1489/**
1490 * parport_ip32_drain_fifo - wait for FIFO to empty
1491 * @p:		pointer to &struct parport
1492 * @timeout:	timeout, in jiffies
1493 *
1494 * This function waits for FIFO to empty.  It returns 1 when FIFO is empty, or
1495 * 0 if the timeout @timeout is reached before, or if a signal is pending.
1496 */
1497static unsigned int parport_ip32_drain_fifo(struct parport *p,
1498					    unsigned long timeout)
1499{
1500	unsigned long expire = jiffies + timeout;
1501	unsigned int polling_interval;
1502	unsigned int counter;
1503
1504	/* Busy wait for approx. 200us */
1505	for (counter = 0; counter < 40; counter++) {
1506		if (parport_ip32_read_econtrol(p) & ECR_F_EMPTY)
1507			break;
1508		if (time_after(jiffies, expire))
1509			break;
1510		if (signal_pending(current))
1511			break;
1512		udelay(5);
1513	}
1514	/* Poll slowly.  Polling interval starts with 1 millisecond, and is
1515	 * increased exponentially until 128.  */
1516	polling_interval = 1; /* msecs */
1517	while (!(parport_ip32_read_econtrol(p) & ECR_F_EMPTY)) {
1518		if (time_after_eq(jiffies, expire))
1519			break;
1520		msleep_interruptible(polling_interval);
1521		if (signal_pending(current))
1522			break;
1523		if (polling_interval < 128)
1524			polling_interval *= 2;
1525	}
1526
1527	return !!(parport_ip32_read_econtrol(p) & ECR_F_EMPTY);
1528}
1529
1530/**
1531 * parport_ip32_get_fifo_residue - reset FIFO
1532 * @p:		pointer to &struct parport
1533 * @mode:	current operation mode (ECR_MODE_PPF or ECR_MODE_ECP)
1534 *
1535 * This function resets FIFO, and returns the number of bytes remaining in it.
1536 */
1537static unsigned int parport_ip32_get_fifo_residue(struct parport *p,
1538						  unsigned int mode)
1539{
1540	struct parport_ip32_private * const priv = p->physport->private_data;
1541	unsigned int residue;
1542	unsigned int cnfga;
1543
1544	if (parport_ip32_read_econtrol(p) & ECR_F_EMPTY)
1545		residue = 0;
1546	else {
1547		pr_debug1(PPIP32 "%s: FIFO is stuck\n", p->name);
1548
1549		/* Stop all transfers.
1550		 *
1551		 * Microsoft's document instructs to drive DCR_STROBE to 0,
1552		 * but it doesn't work (at least in Compatibility mode, not
1553		 * tested in ECP mode).  Switching directly to Test mode (as
1554		 * in parport_pc) is not an option: it does confuse the port,
1555		 * ECP service interrupts are no more working after that.  A
1556		 * hard reset is then needed to revert to a sane state.
1557		 *
1558		 * Let's hope that the FIFO is really stuck and that the
1559		 * peripheral doesn't wake up now.
1560		 */
1561		parport_ip32_frob_control(p, DCR_STROBE, 0);
1562
1563		/* Fill up FIFO */
1564		for (residue = priv->fifo_depth; residue > 0; residue--) {
1565			if (parport_ip32_read_econtrol(p) & ECR_F_FULL)
1566				break;
1567			writeb(0x00, priv->regs.fifo);
1568		}
1569	}
1570	if (residue)
1571		pr_debug1(PPIP32 "%s: %d PWord%s left in FIFO\n",
1572			  p->name, residue,
1573			  (residue == 1) ? " was" : "s were");
1574
1575	/* Now reset the FIFO */
1576	parport_ip32_set_mode(p, ECR_MODE_PS2);
1577
1578	/* Host recovery for ECP mode */
1579	if (mode == ECR_MODE_ECP) {
1580		parport_ip32_data_reverse(p);
1581		parport_ip32_frob_control(p, DCR_nINIT, 0);
1582		if (parport_wait_peripheral(p, DSR_PERROR, 0))
1583			pr_debug1(PPIP32 "%s: PEerror timeout 1 in %s\n",
1584				  p->name, __func__);
1585		parport_ip32_frob_control(p, DCR_STROBE, DCR_STROBE);
1586		parport_ip32_frob_control(p, DCR_nINIT, DCR_nINIT);
1587		if (parport_wait_peripheral(p, DSR_PERROR, DSR_PERROR))
1588			pr_debug1(PPIP32 "%s: PEerror timeout 2 in %s\n",
1589				  p->name, __func__);
1590	}
1591
1592	/* Adjust residue if needed */
1593	parport_ip32_set_mode(p, ECR_MODE_CFG);
1594	cnfga = readb(priv->regs.cnfgA);
1595	if (!(cnfga & CNFGA_nBYTEINTRANS)) {
1596		pr_debug1(PPIP32 "%s: cnfgA contains 0x%02x\n",
1597			  p->name, cnfga);
1598		pr_debug1(PPIP32 "%s: Accounting for extra byte\n",
1599			  p->name);
1600		residue++;
1601	}
1602
1603	/* Don't care about partial PWords since we do not support
1604	 * PWord != 1 byte. */
1605
1606	/* Back to forward PS2 mode. */
1607	parport_ip32_set_mode(p, ECR_MODE_PS2);
1608	parport_ip32_data_forward(p);
1609
1610	return residue;
1611}
1612
1613/**
1614 * parport_ip32_compat_write_data - write a block of data in SPP mode
1615 * @p:		pointer to &struct parport
1616 * @buf:	buffer of data to write
1617 * @len:	length of buffer @buf
1618 * @flags:	ignored
1619 */
1620static size_t parport_ip32_compat_write_data(struct parport *p,
1621					     const void *buf, size_t len,
1622					     int flags)
1623{
1624	static unsigned int ready_before = 1;
1625	struct parport_ip32_private * const priv = p->physport->private_data;
1626	struct parport * const physport = p->physport;
1627	size_t written = 0;
1628
1629	/* Special case: a timeout of zero means we cannot call schedule().
1630	 * Also if O_NONBLOCK is set then use the default implementation. */
1631	if (physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
1632		return parport_ieee1284_write_compat(p, buf, len, flags);
1633
1634	/* Reset FIFO, go in forward mode, and disable ackIntEn */
1635	parport_ip32_set_mode(p, ECR_MODE_PS2);
1636	parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
1637	parport_ip32_data_forward(p);
1638	parport_ip32_disable_irq(p);
1639	parport_ip32_set_mode(p, ECR_MODE_PPF);
1640	physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
1641
1642	/* Wait for peripheral to become ready */
1643	if (parport_wait_peripheral(p, DSR_nBUSY | DSR_nFAULT,
1644				       DSR_nBUSY | DSR_nFAULT)) {
1645		/* Avoid to flood the logs */
1646		if (ready_before)
1647			printk(KERN_INFO PPIP32 "%s: not ready in %s\n",
1648			       p->name, __func__);
1649		ready_before = 0;
1650		goto stop;
1651	}
1652	ready_before = 1;
1653
1654	written = parport_ip32_fifo_write_block(p, buf, len);
1655
1656	/* Wait FIFO to empty.  Timeout is proportional to FIFO_depth.  */
1657	parport_ip32_drain_fifo(p, physport->cad->timeout * priv->fifo_depth);
1658
1659	/* Check for a potential residue */
1660	written -= parport_ip32_get_fifo_residue(p, ECR_MODE_PPF);
1661
1662	/* Then, wait for BUSY to get low. */
1663	if (parport_wait_peripheral(p, DSR_nBUSY, DSR_nBUSY))
1664		printk(KERN_DEBUG PPIP32 "%s: BUSY timeout in %s\n",
1665		       p->name, __func__);
1666
1667stop:
1668	/* Reset FIFO */
1669	parport_ip32_set_mode(p, ECR_MODE_PS2);
1670	physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1671
1672	return written;
1673}
1674
1675
1676/**
1677 * parport_ip32_ecp_write_data - write a block of data in ECP mode
1678 * @p:		pointer to &struct parport
1679 * @buf:	buffer of data to write
1680 * @len:	length of buffer @buf
1681 * @flags:	ignored
1682 */
1683static size_t parport_ip32_ecp_write_data(struct parport *p,
1684					  const void *buf, size_t len,
1685					  int flags)
1686{
1687	static unsigned int ready_before = 1;
1688	struct parport_ip32_private * const priv = p->physport->private_data;
1689	struct parport * const physport = p->physport;
1690	size_t written = 0;
1691
1692	/* Special case: a timeout of zero means we cannot call schedule().
1693	 * Also if O_NONBLOCK is set then use the default implementation. */
1694	if (physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
1695		return parport_ieee1284_ecp_write_data(p, buf, len, flags);
1696
1697	/* Negotiate to forward mode if necessary. */
1698	if (physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
1699		/* Event 47: Set nInit high. */
1700		parport_ip32_frob_control(p, DCR_nINIT | DCR_AUTOFD,
1701					     DCR_nINIT | DCR_AUTOFD);
1702
1703		/* Event 49: PError goes high. */
1704		if (parport_wait_peripheral(p, DSR_PERROR, DSR_PERROR)) {
1705			printk(KERN_DEBUG PPIP32 "%s: PError timeout in %s",
1706			       p->name, __func__);
1707			physport->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN;
1708			return 0;
1709		}
1710	}
1711
1712	/* Reset FIFO, go in forward mode, and disable ackIntEn */
1713	parport_ip32_set_mode(p, ECR_MODE_PS2);
1714	parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
1715	parport_ip32_data_forward(p);
1716	parport_ip32_disable_irq(p);
1717	parport_ip32_set_mode(p, ECR_MODE_ECP);
1718	physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
1719
1720	/* Wait for peripheral to become ready */
1721	if (parport_wait_peripheral(p, DSR_nBUSY | DSR_nFAULT,
1722				       DSR_nBUSY | DSR_nFAULT)) {
1723		/* Avoid to flood the logs */
1724		if (ready_before)
1725			printk(KERN_INFO PPIP32 "%s: not ready in %s\n",
1726			       p->name, __func__);
1727		ready_before = 0;
1728		goto stop;
1729	}
1730	ready_before = 1;
1731
1732	written = parport_ip32_fifo_write_block(p, buf, len);
1733
1734	/* Wait FIFO to empty.  Timeout is proportional to FIFO_depth.  */
1735	parport_ip32_drain_fifo(p, physport->cad->timeout * priv->fifo_depth);
1736
1737	/* Check for a potential residue */
1738	written -= parport_ip32_get_fifo_residue(p, ECR_MODE_ECP);
1739
1740	/* Then, wait for BUSY to get low. */
1741	if (parport_wait_peripheral(p, DSR_nBUSY, DSR_nBUSY))
1742		printk(KERN_DEBUG PPIP32 "%s: BUSY timeout in %s\n",
1743		       p->name, __func__);
1744
1745stop:
1746	/* Reset FIFO */
1747	parport_ip32_set_mode(p, ECR_MODE_PS2);
1748	physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1749
1750	return written;
1751}
1752
1753
1754/*--- Default parport operations ---------------------------------------*/
1755
1756static __initdata struct parport_operations parport_ip32_ops = {
1757	.write_data		= parport_ip32_write_data,
1758	.read_data		= parport_ip32_read_data,
1759
1760	.write_control		= parport_ip32_write_control,
1761	.read_control		= parport_ip32_read_control,
1762	.frob_control		= parport_ip32_frob_control,
1763
1764	.read_status		= parport_ip32_read_status,
1765
1766	.enable_irq		= parport_ip32_enable_irq,
1767	.disable_irq		= parport_ip32_disable_irq,
1768
1769	.data_forward		= parport_ip32_data_forward,
1770	.data_reverse		= parport_ip32_data_reverse,
1771
1772	.init_state		= parport_ip32_init_state,
1773	.save_state		= parport_ip32_save_state,
1774	.restore_state		= parport_ip32_restore_state,
1775
1776	.epp_write_data		= parport_ieee1284_epp_write_data,
1777	.epp_read_data		= parport_ieee1284_epp_read_data,
1778	.epp_write_addr		= parport_ieee1284_epp_write_addr,
1779	.epp_read_addr		= parport_ieee1284_epp_read_addr,
1780
1781	.ecp_write_data		= parport_ieee1284_ecp_write_data,
1782	.ecp_read_data		= parport_ieee1284_ecp_read_data,
1783	.ecp_write_addr		= parport_ieee1284_ecp_write_addr,
1784
1785	.compat_write_data	= parport_ieee1284_write_compat,
1786	.nibble_read_data	= parport_ieee1284_read_nibble,
1787	.byte_read_data		= parport_ieee1284_read_byte,
1788
1789	.owner			= THIS_MODULE,
1790};
1791
1792/*--- Device detection -------------------------------------------------*/
1793
1794/**
1795 * parport_ip32_ecp_supported - check for an ECP port
1796 * @p:		pointer to the &parport structure
1797 *
1798 * Returns 1 if an ECP port is found, and 0 otherwise.  This function actually
1799 * checks if an Extended Control Register seems to be present.  On successful
1800 * return, the port is placed in SPP mode.
1801 */
1802static __init unsigned int parport_ip32_ecp_supported(struct parport *p)
1803{
1804	struct parport_ip32_private * const priv = p->physport->private_data;
1805	unsigned int ecr;
1806
1807	ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR;
1808	writeb(ecr, priv->regs.ecr);
1809	if (readb(priv->regs.ecr) != (ecr | ECR_F_EMPTY))
1810		goto fail;
1811
1812	pr_probe(p, "Found working ECR register\n");
1813	parport_ip32_set_mode(p, ECR_MODE_SPP);
1814	parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
1815	return 1;
1816
1817fail:
1818	pr_probe(p, "ECR register not found\n");
1819	return 0;
1820}
1821
1822/**
1823 * parport_ip32_fifo_supported - check for FIFO parameters
1824 * @p:		pointer to the &parport structure
1825 *
1826 * Check for FIFO parameters of an Extended Capabilities Port.  Returns 1 on
1827 * success, and 0 otherwise.  Adjust FIFO parameters in the parport structure.
1828 * On return, the port is placed in SPP mode.
1829 */
1830static __init unsigned int parport_ip32_fifo_supported(struct parport *p)
1831{
1832	struct parport_ip32_private * const priv = p->physport->private_data;
1833	unsigned int configa, configb;
1834	unsigned int pword;
1835	unsigned int i;
1836
1837	/* Configuration mode */
1838	parport_ip32_set_mode(p, ECR_MODE_CFG);
1839	configa = readb(priv->regs.cnfgA);
1840	configb = readb(priv->regs.cnfgB);
1841
1842	/* Find out PWord size */
1843	switch (configa & CNFGA_ID_MASK) {
1844	case CNFGA_ID_8:
1845		pword = 1;
1846		break;
1847	case CNFGA_ID_16:
1848		pword = 2;
1849		break;
1850	case CNFGA_ID_32:
1851		pword = 4;
1852		break;
1853	default:
1854		pr_probe(p, "Unknown implementation ID: 0x%0x\n",
1855			 (configa & CNFGA_ID_MASK) >> CNFGA_ID_SHIFT);
1856		goto fail;
1857		break;
1858	}
1859	if (pword != 1) {
1860		pr_probe(p, "Unsupported PWord size: %u\n", pword);
1861		goto fail;
1862	}
1863	priv->pword = pword;
1864	pr_probe(p, "PWord is %u bits\n", 8 * priv->pword);
1865
1866	/* Check for compression support */
1867	writeb(configb | CNFGB_COMPRESS, priv->regs.cnfgB);
1868	if (readb(priv->regs.cnfgB) & CNFGB_COMPRESS)
1869		pr_probe(p, "Hardware compression detected (unsupported)\n");
1870	writeb(configb & ~CNFGB_COMPRESS, priv->regs.cnfgB);
1871
1872	/* Reset FIFO and go in test mode (no interrupt, no DMA) */
1873	parport_ip32_set_mode(p, ECR_MODE_TST);
1874
1875	/* FIFO must be empty now */
1876	if (!(readb(priv->regs.ecr) & ECR_F_EMPTY)) {
1877		pr_probe(p, "FIFO not reset\n");
1878		goto fail;
1879	}
1880
1881	/* Find out FIFO depth. */
1882	priv->fifo_depth = 0;
1883	for (i = 0; i < 1024; i++) {
1884		if (readb(priv->regs.ecr) & ECR_F_FULL) {
1885			/* FIFO full */
1886			priv->fifo_depth = i;
1887			break;
1888		}
1889		writeb((u8)i, priv->regs.fifo);
1890	}
1891	if (i >= 1024) {
1892		pr_probe(p, "Can't fill FIFO\n");
1893		goto fail;
1894	}
1895	if (!priv->fifo_depth) {
1896		pr_probe(p, "Can't get FIFO depth\n");
1897		goto fail;
1898	}
1899	pr_probe(p, "FIFO is %u PWords deep\n", priv->fifo_depth);
1900
1901	/* Enable interrupts */
1902	parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0);
1903
1904	/* Find out writeIntrThreshold: number of PWords we know we can write
1905	 * if we get an interrupt. */
1906	priv->writeIntrThreshold = 0;
1907	for (i = 0; i < priv->fifo_depth; i++) {
1908		if (readb(priv->regs.fifo) != (u8)i) {
1909			pr_probe(p, "Invalid data in FIFO\n");
1910			goto fail;
1911		}
1912		if (!priv->writeIntrThreshold
1913		    && readb(priv->regs.ecr) & ECR_SERVINTR)
1914			/* writeIntrThreshold reached */
1915			priv->writeIntrThreshold = i + 1;
1916		if (i + 1 < priv->fifo_depth
1917		    && readb(priv->regs.ecr) & ECR_F_EMPTY) {
1918			/* FIFO empty before the last byte? */
1919			pr_probe(p, "Data lost in FIFO\n");
1920			goto fail;
1921		}
1922	}
1923	if (!priv->writeIntrThreshold) {
1924		pr_probe(p, "Can't get writeIntrThreshold\n");
1925		goto fail;
1926	}
1927	pr_probe(p, "writeIntrThreshold is %u\n", priv->writeIntrThreshold);
1928
1929	/* FIFO must be empty now */
1930	if (!(readb(priv->regs.ecr) & ECR_F_EMPTY)) {
1931		pr_probe(p, "Can't empty FIFO\n");
1932		goto fail;
1933	}
1934
1935	/* Reset FIFO */
1936	parport_ip32_set_mode(p, ECR_MODE_PS2);
1937	/* Set reverse direction (must be in PS2 mode) */
1938	parport_ip32_data_reverse(p);
1939	/* Test FIFO, no interrupt, no DMA */
1940	parport_ip32_set_mode(p, ECR_MODE_TST);
1941	/* Enable interrupts */
1942	parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0);
1943
1944	/* Find out readIntrThreshold: number of PWords we can read if we get
1945	 * an interrupt. */
1946	priv->readIntrThreshold = 0;
1947	for (i = 0; i < priv->fifo_depth; i++) {
1948		writeb(0xaa, priv->regs.fifo);
1949		if (readb(priv->regs.ecr) & ECR_SERVINTR) {
1950			/* readIntrThreshold reached */
1951			priv->readIntrThreshold = i + 1;
1952			break;
1953		}
1954	}
1955	if (!priv->readIntrThreshold) {
1956		pr_probe(p, "Can't get readIntrThreshold\n");
1957		goto fail;
1958	}
1959	pr_probe(p, "readIntrThreshold is %u\n", priv->readIntrThreshold);
1960
1961	/* Reset ECR */
1962	parport_ip32_set_mode(p, ECR_MODE_PS2);
1963	parport_ip32_data_forward(p);
1964	parport_ip32_set_mode(p, ECR_MODE_SPP);
1965	return 1;
1966
1967fail:
1968	priv->fifo_depth = 0;
1969	parport_ip32_set_mode(p, ECR_MODE_SPP);
1970	return 0;
1971}
1972
1973/*--- Initialization code ----------------------------------------------*/
1974
1975/**
1976 * parport_ip32_make_isa_registers - compute (ISA) register addresses
1977 * @regs:	pointer to &struct parport_ip32_regs to fill
1978 * @base:	base address of standard and EPP registers
1979 * @base_hi:	base address of ECP registers
1980 * @regshift:	how much to shift register offset by
1981 *
1982 * Compute register addresses, according to the ISA standard.  The addresses
1983 * of the standard and EPP registers are computed from address @base.  The
1984 * addresses of the ECP registers are computed from address @base_hi.
1985 */
1986static void __init
1987parport_ip32_make_isa_registers(struct parport_ip32_regs *regs,
1988				void __iomem *base, void __iomem *base_hi,
1989				unsigned int regshift)
1990{
1991#define r_base(offset)    ((u8 __iomem *)base    + ((offset) << regshift))
1992#define r_base_hi(offset) ((u8 __iomem *)base_hi + ((offset) << regshift))
1993	*regs = (struct parport_ip32_regs){
1994		.data		= r_base(0),
1995		.dsr		= r_base(1),
1996		.dcr		= r_base(2),
1997		.eppAddr	= r_base(3),
1998		.eppData0	= r_base(4),
1999		.eppData1	= r_base(5),
2000		.eppData2	= r_base(6),
2001		.eppData3	= r_base(7),
2002		.ecpAFifo	= r_base(0),
2003		.fifo		= r_base_hi(0),
2004		.cnfgA		= r_base_hi(0),
2005		.cnfgB		= r_base_hi(1),
2006		.ecr		= r_base_hi(2)
2007	};
2008#undef r_base_hi
2009#undef r_base
2010}
2011
2012/**
2013 * parport_ip32_probe_port - probe and register IP32 built-in parallel port
2014 *
2015 * Returns the new allocated &parport structure.  On error, an error code is
2016 * encoded in return value with the ERR_PTR function.
2017 */
2018static __init struct parport *parport_ip32_probe_port(void)
2019{
2020	struct parport_ip32_regs regs;
2021	struct parport_ip32_private *priv = NULL;
2022	struct parport_operations *ops = NULL;
2023	struct parport *p = NULL;
2024	int err;
2025
2026	parport_ip32_make_isa_registers(&regs, &mace->isa.parallel,
2027					&mace->isa.ecp1284, 8 /* regshift */);
2028
2029	ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
2030	priv = kmalloc(sizeof(struct parport_ip32_private), GFP_KERNEL);
2031	p = parport_register_port(0, PARPORT_IRQ_NONE, PARPORT_DMA_NONE, ops);
2032	if (ops == NULL || priv == NULL || p == NULL) {
2033		err = -ENOMEM;
2034		goto fail;
2035	}
2036	p->base = MACE_BASE + offsetof(struct sgi_mace, isa.parallel);
2037	p->base_hi = MACE_BASE + offsetof(struct sgi_mace, isa.ecp1284);
2038	p->private_data = priv;
2039
2040	*ops = parport_ip32_ops;
2041	*priv = (struct parport_ip32_private){
2042		.regs			= regs,
2043		.dcr_writable		= DCR_DIR | DCR_SELECT | DCR_nINIT |
2044					  DCR_AUTOFD | DCR_STROBE,
2045		.irq_mode		= PARPORT_IP32_IRQ_FWD,
2046	};
2047	init_completion(&priv->irq_complete);
2048
2049	/* Probe port. */
2050	if (!parport_ip32_ecp_supported(p)) {
2051		err = -ENODEV;
2052		goto fail;
2053	}
2054	parport_ip32_dump_state(p, "begin init", 0);
2055
2056	/* We found what looks like a working ECR register.  Simply assume
2057	 * that all modes are correctly supported.  Enable basic modes. */
2058	p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2059	p->modes |= PARPORT_MODE_TRISTATE;
2060
2061	if (!parport_ip32_fifo_supported(p)) {
2062		printk(KERN_WARNING PPIP32
2063		       "%s: error: FIFO disabled\n", p->name);
2064		/* Disable hardware modes depending on a working FIFO. */
2065		features &= ~PARPORT_IP32_ENABLE_SPP;
2066		features &= ~PARPORT_IP32_ENABLE_ECP;
2067		/* DMA is not needed if FIFO is not supported.  */
2068		features &= ~PARPORT_IP32_ENABLE_DMA;
2069	}
2070
2071	/* Request IRQ */
2072	if (features & PARPORT_IP32_ENABLE_IRQ) {
2073		int irq = MACEISA_PARALLEL_IRQ;
2074		if (request_irq(irq, parport_ip32_interrupt, 0, p->name, p)) {
2075			printk(KERN_WARNING PPIP32
2076			       "%s: error: IRQ disabled\n", p->name);
2077			/* DMA cannot work without interrupts. */
2078			features &= ~PARPORT_IP32_ENABLE_DMA;
2079		} else {
2080			pr_probe(p, "Interrupt support enabled\n");
2081			p->irq = irq;
2082			priv->dcr_writable |= DCR_IRQ;
2083		}
2084	}
2085
2086	/* Allocate DMA resources */
2087	if (features & PARPORT_IP32_ENABLE_DMA) {
2088		if (parport_ip32_dma_register())
2089			printk(KERN_WARNING PPIP32
2090			       "%s: error: DMA disabled\n", p->name);
2091		else {
2092			pr_probe(p, "DMA support enabled\n");
2093			p->dma = 0; /* arbitrary value != PARPORT_DMA_NONE */
2094			p->modes |= PARPORT_MODE_DMA;
2095		}
2096	}
2097
2098	if (features & PARPORT_IP32_ENABLE_SPP) {
2099		/* Enable compatibility FIFO mode */
2100		p->ops->compat_write_data = parport_ip32_compat_write_data;
2101		p->modes |= PARPORT_MODE_COMPAT;
2102		pr_probe(p, "Hardware support for SPP mode enabled\n");
2103	}
2104	if (features & PARPORT_IP32_ENABLE_EPP) {
2105		/* Set up access functions to use EPP hardware. */
2106		p->ops->epp_read_data = parport_ip32_epp_read_data;
2107		p->ops->epp_write_data = parport_ip32_epp_write_data;
2108		p->ops->epp_read_addr = parport_ip32_epp_read_addr;
2109		p->ops->epp_write_addr = parport_ip32_epp_write_addr;
2110		p->modes |= PARPORT_MODE_EPP;
2111		pr_probe(p, "Hardware support for EPP mode enabled\n");
2112	}
2113	if (features & PARPORT_IP32_ENABLE_ECP) {
2114		/* Enable ECP FIFO mode */
2115		p->ops->ecp_write_data = parport_ip32_ecp_write_data;
2116/*		p->ops->ecp_read_data  = parport_ip32_ecp_read_data; */
2117/*		p->ops->ecp_write_addr = parport_ip32_ecp_write_addr; */
2118		p->modes |= PARPORT_MODE_ECP;
2119		pr_probe(p, "Hardware support for ECP mode enabled\n");
2120	}
2121
2122	/* Initialize the port with sensible values */
2123	parport_ip32_set_mode(p, ECR_MODE_PS2);
2124	parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT);
2125	parport_ip32_data_forward(p);
2126	parport_ip32_disable_irq(p);
2127	parport_ip32_write_data(p, 0x00);
2128	parport_ip32_dump_state(p, "end init", 0);
2129
2130	/* Print out what we found */
2131	printk(KERN_INFO "%s: SGI IP32 at 0x%lx (0x%lx)",
2132	       p->name, p->base, p->base_hi);
2133	if (p->irq != PARPORT_IRQ_NONE)
2134		printk(", irq %d", p->irq);
2135	printk(" [");
2136#define printmode(x)	if (p->modes & PARPORT_MODE_##x)		\
2137				printk("%s%s", f++ ? "," : "", #x)
2138	{
2139		unsigned int f = 0;
2140		printmode(PCSPP);
2141		printmode(TRISTATE);
2142		printmode(COMPAT);
2143		printmode(EPP);
2144		printmode(ECP);
2145		printmode(DMA);
2146	}
2147#undef printmode
2148	printk("]\n");
2149
2150	parport_announce_port(p);
2151	return p;
2152
2153fail:
2154	if (p)
2155		parport_put_port(p);
2156	kfree(priv);
2157	kfree(ops);
2158	return ERR_PTR(err);
2159}
2160
2161/**
2162 * parport_ip32_unregister_port - unregister a parallel port
2163 * @p:		pointer to the &struct parport
2164 *
2165 * Unregisters a parallel port and free previously allocated resources
2166 * (memory, IRQ, ...).
2167 */
2168static __exit void parport_ip32_unregister_port(struct parport *p)
2169{
2170	struct parport_ip32_private * const priv = p->physport->private_data;
2171	struct parport_operations *ops = p->ops;
2172
2173	parport_remove_port(p);
2174	if (p->modes & PARPORT_MODE_DMA)
2175		parport_ip32_dma_unregister();
2176	if (p->irq != PARPORT_IRQ_NONE)
2177		free_irq(p->irq, p);
2178	parport_put_port(p);
2179	kfree(priv);
2180	kfree(ops);
2181}
2182
2183/**
2184 * parport_ip32_init - module initialization function
2185 */
2186static int __init parport_ip32_init(void)
2187{
2188	pr_info(PPIP32 "SGI IP32 built-in parallel port driver v0.6\n");
2189	pr_debug1(PPIP32 "Compiled on %s, %s\n", __DATE__, __TIME__);
2190	this_port = parport_ip32_probe_port();
2191	return IS_ERR(this_port) ? PTR_ERR(this_port) : 0;
2192}
2193
2194/**
2195 * parport_ip32_exit - module termination function
2196 */
2197static void __exit parport_ip32_exit(void)
2198{
2199	parport_ip32_unregister_port(this_port);
2200}
2201
2202/*--- Module stuff -----------------------------------------------------*/
2203
2204MODULE_AUTHOR("Arnaud Giersch <arnaud.giersch@free.fr>");
2205MODULE_DESCRIPTION("SGI IP32 built-in parallel port driver");
2206MODULE_LICENSE("GPL");
2207MODULE_VERSION("0.6");		/* update in parport_ip32_init() too */
2208
2209module_init(parport_ip32_init);
2210module_exit(parport_ip32_exit);
2211
2212module_param(verbose_probing, bool, S_IRUGO);
2213MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialization");
2214
2215module_param(features, uint, S_IRUGO);
2216MODULE_PARM_DESC(features,
2217		 "Bit mask of features to enable"
2218		 ", bit 0: IRQ support"
2219		 ", bit 1: DMA support"
2220		 ", bit 2: hardware SPP mode"
2221		 ", bit 3: hardware EPP mode"
2222		 ", bit 4: hardware ECP mode");
2223
2224/*--- Inform (X)Emacs about preferred coding style ---------------------*/
2225/*
2226 * Local Variables:
2227 * mode: c
2228 * c-file-style: "linux"
2229 * indent-tabs-mode: t
2230 * tab-width: 8
2231 * fill-column: 78
2232 * ispell-local-dictionary: "american"
2233 * End:
2234 */
2235