1/* 2 * SuperH IrDA Driver 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 6 * 7 * Based on bfin_sir.c 8 * Copyright 2006-2009 Analog Devices Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15#include <linux/module.h> 16#include <linux/platform_device.h> 17#include <linux/slab.h> 18#include <net/irda/wrapper.h> 19#include <net/irda/irda_device.h> 20#include <asm/clock.h> 21 22#define DRIVER_NAME "sh_sir" 23 24#define RX_PHASE (1 << 0) 25#define TX_PHASE (1 << 1) 26#define TX_COMP_PHASE (1 << 2) /* tx complete */ 27#define NONE_PHASE (1 << 31) 28 29#define IRIF_RINTCLR 0x0016 /* DMA rx interrupt source clear */ 30#define IRIF_TINTCLR 0x0018 /* DMA tx interrupt source clear */ 31#define IRIF_SIR0 0x0020 /* IrDA-SIR10 control */ 32#define IRIF_SIR1 0x0022 /* IrDA-SIR10 baudrate error correction */ 33#define IRIF_SIR2 0x0024 /* IrDA-SIR10 baudrate count */ 34#define IRIF_SIR3 0x0026 /* IrDA-SIR10 status */ 35#define IRIF_SIR_FRM 0x0028 /* Hardware frame processing set */ 36#define IRIF_SIR_EOF 0x002A /* EOF value */ 37#define IRIF_SIR_FLG 0x002C /* Flag clear */ 38#define IRIF_UART_STS2 0x002E /* UART status 2 */ 39#define IRIF_UART0 0x0030 /* UART control */ 40#define IRIF_UART1 0x0032 /* UART status */ 41#define IRIF_UART2 0x0034 /* UART mode */ 42#define IRIF_UART3 0x0036 /* UART transmit data */ 43#define IRIF_UART4 0x0038 /* UART receive data */ 44#define IRIF_UART5 0x003A /* UART interrupt mask */ 45#define IRIF_UART6 0x003C /* UART baud rate error correction */ 46#define IRIF_UART7 0x003E /* UART baud rate count set */ 47#define IRIF_CRC0 0x0040 /* CRC engine control */ 48#define IRIF_CRC1 0x0042 /* CRC engine input data */ 49#define IRIF_CRC2 0x0044 /* CRC engine calculation */ 50#define IRIF_CRC3 0x0046 /* CRC engine output data 1 */ 51#define IRIF_CRC4 0x0048 /* CRC engine output data 2 */ 52 53/* IRIF_SIR0 */ 54#define IRTPW (1 << 1) /* transmit pulse width select */ 55#define IRERRC (1 << 0) /* Clear receive pulse width error */ 56 57/* IRIF_SIR3 */ 58#define IRERR (1 << 0) /* received pulse width Error */ 59 60/* IRIF_SIR_FRM */ 61#define EOFD (1 << 9) /* EOF detection flag */ 62#define FRER (1 << 8) /* Frame Error bit */ 63#define FRP (1 << 0) /* Frame processing set */ 64 65/* IRIF_UART_STS2 */ 66#define IRSME (1 << 6) /* Receive Sum Error flag */ 67#define IROVE (1 << 5) /* Receive Overrun Error flag */ 68#define IRFRE (1 << 4) /* Receive Framing Error flag */ 69#define IRPRE (1 << 3) /* Receive Parity Error flag */ 70 71/* IRIF_UART0_*/ 72#define TBEC (1 << 2) /* Transmit Data Clear */ 73#define RIE (1 << 1) /* Receive Enable */ 74#define TIE (1 << 0) /* Transmit Enable */ 75 76/* IRIF_UART1 */ 77#define URSME (1 << 6) /* Receive Sum Error Flag */ 78#define UROVE (1 << 5) /* Receive Overrun Error Flag */ 79#define URFRE (1 << 4) /* Receive Framing Error Flag */ 80#define URPRE (1 << 3) /* Receive Parity Error Flag */ 81#define RBF (1 << 2) /* Receive Buffer Full Flag */ 82#define TSBE (1 << 1) /* Transmit Shift Buffer Empty Flag */ 83#define TBE (1 << 0) /* Transmit Buffer Empty flag */ 84#define TBCOMP (TSBE | TBE) 85 86/* IRIF_UART5 */ 87#define RSEIM (1 << 6) /* Receive Sum Error Flag IRQ Mask */ 88#define RBFIM (1 << 2) /* Receive Buffer Full Flag IRQ Mask */ 89#define TSBEIM (1 << 1) /* Transmit Shift Buffer Empty Flag IRQ Mask */ 90#define TBEIM (1 << 0) /* Transmit Buffer Empty Flag IRQ Mask */ 91#define RX_MASK (RSEIM | RBFIM) 92 93/* IRIF_CRC0 */ 94#define CRC_RST (1 << 15) /* CRC Engine Reset */ 95#define CRC_CT_MASK 0x0FFF 96 97/************************************************************************ 98 99 100 structure 101 102 103************************************************************************/ 104struct sh_sir_self { 105 void __iomem *membase; 106 unsigned int irq; 107 struct clk *clk; 108 109 struct net_device *ndev; 110 111 struct irlap_cb *irlap; 112 struct qos_info qos; 113 114 iobuff_t tx_buff; 115 iobuff_t rx_buff; 116}; 117 118/************************************************************************ 119 120 121 common function 122 123 124************************************************************************/ 125static void sh_sir_write(struct sh_sir_self *self, u32 offset, u16 data) 126{ 127 iowrite16(data, self->membase + offset); 128} 129 130static u16 sh_sir_read(struct sh_sir_self *self, u32 offset) 131{ 132 return ioread16(self->membase + offset); 133} 134 135static void sh_sir_update_bits(struct sh_sir_self *self, u32 offset, 136 u16 mask, u16 data) 137{ 138 u16 old, new; 139 140 old = sh_sir_read(self, offset); 141 new = (old & ~mask) | data; 142 if (old != new) 143 sh_sir_write(self, offset, new); 144} 145 146/************************************************************************ 147 148 149 CRC function 150 151 152************************************************************************/ 153static void sh_sir_crc_reset(struct sh_sir_self *self) 154{ 155 sh_sir_write(self, IRIF_CRC0, CRC_RST); 156} 157 158static void sh_sir_crc_add(struct sh_sir_self *self, u8 data) 159{ 160 sh_sir_write(self, IRIF_CRC1, (u16)data); 161} 162 163static u16 sh_sir_crc_cnt(struct sh_sir_self *self) 164{ 165 return CRC_CT_MASK & sh_sir_read(self, IRIF_CRC0); 166} 167 168static u16 sh_sir_crc_out(struct sh_sir_self *self) 169{ 170 return sh_sir_read(self, IRIF_CRC4); 171} 172 173static int sh_sir_crc_init(struct sh_sir_self *self) 174{ 175 struct device *dev = &self->ndev->dev; 176 int ret = -EIO; 177 u16 val; 178 179 sh_sir_crc_reset(self); 180 181 sh_sir_crc_add(self, 0xCC); 182 sh_sir_crc_add(self, 0xF5); 183 sh_sir_crc_add(self, 0xF1); 184 sh_sir_crc_add(self, 0xA7); 185 186 val = sh_sir_crc_cnt(self); 187 if (4 != val) { 188 dev_err(dev, "CRC count error %x\n", val); 189 goto crc_init_out; 190 } 191 192 val = sh_sir_crc_out(self); 193 if (0x51DF != val) { 194 dev_err(dev, "CRC result error%x\n", val); 195 goto crc_init_out; 196 } 197 198 ret = 0; 199 200crc_init_out: 201 202 sh_sir_crc_reset(self); 203 return ret; 204} 205 206/************************************************************************ 207 208 209 baud rate functions 210 211 212************************************************************************/ 213#define SCLK_BASE 1843200 /* 1.8432MHz */ 214 215static u32 sh_sir_find_sclk(struct clk *irda_clk) 216{ 217 struct cpufreq_frequency_table *freq_table = irda_clk->freq_table; 218 struct clk *pclk = clk_get(NULL, "peripheral_clk"); 219 u32 limit, min = 0xffffffff, tmp; 220 int i, index = 0; 221 222 limit = clk_get_rate(pclk); 223 clk_put(pclk); 224 225 /* IrDA can not set over peripheral_clk */ 226 for (i = 0; 227 freq_table[i].frequency != CPUFREQ_TABLE_END; 228 i++) { 229 u32 freq = freq_table[i].frequency; 230 231 if (freq == CPUFREQ_ENTRY_INVALID) 232 continue; 233 234 /* IrDA should not over peripheral_clk */ 235 if (freq > limit) 236 continue; 237 238 tmp = freq % SCLK_BASE; 239 if (tmp < min) { 240 min = tmp; 241 index = i; 242 } 243 } 244 245 return freq_table[index].frequency; 246} 247 248#define ERR_ROUNDING(a) ((a + 5000) / 10000) 249static int sh_sir_set_baudrate(struct sh_sir_self *self, u32 baudrate) 250{ 251 struct clk *clk; 252 struct device *dev = &self->ndev->dev; 253 u32 rate; 254 u16 uabca, uabc; 255 u16 irbca, irbc; 256 u32 min, rerr, tmp; 257 int i; 258 259 /* Baud Rate Error Correction x 10000 */ 260 u32 rate_err_array[] = { 261 0000, 0625, 1250, 1875, 262 2500, 3125, 3750, 4375, 263 5000, 5625, 6250, 6875, 264 7500, 8125, 8750, 9375, 265 }; 266 267 switch (baudrate) { 268 case 9600: 269 break; 270 default: 271 dev_err(dev, "un-supported baudrate %d\n", baudrate); 272 return -EIO; 273 } 274 275 clk = clk_get(NULL, "irda_clk"); 276 if (!clk) { 277 dev_err(dev, "can not get irda_clk\n"); 278 return -EIO; 279 } 280 281 clk_set_rate(clk, sh_sir_find_sclk(clk)); 282 rate = clk_get_rate(clk); 283 clk_put(clk); 284 285 dev_dbg(dev, "selected sclk = %d\n", rate); 286 287 /* 288 * CALCULATION 289 * 290 * 1843200 = system rate / (irbca + (irbc + 1)) 291 */ 292 293 irbc = rate / SCLK_BASE; 294 295 tmp = rate - (SCLK_BASE * irbc); 296 tmp *= 10000; 297 298 rerr = tmp / SCLK_BASE; 299 300 min = 0xffffffff; 301 irbca = 0; 302 for (i = 0; i < ARRAY_SIZE(rate_err_array); i++) { 303 tmp = abs(rate_err_array[i] - rerr); 304 if (min > tmp) { 305 min = tmp; 306 irbca = i; 307 } 308 } 309 310 tmp = rate / (irbc + ERR_ROUNDING(rate_err_array[irbca])); 311 if ((SCLK_BASE / 100) < abs(tmp - SCLK_BASE)) 312 dev_warn(dev, "IrDA freq error margin over %d\n", tmp); 313 314 dev_dbg(dev, "target = %d, result = %d, infrared = %d.%d\n", 315 SCLK_BASE, tmp, irbc, rate_err_array[irbca]); 316 317 irbca = (irbca & 0xF) << 4; 318 irbc = (irbc - 1) & 0xF; 319 320 if (!irbc) { 321 dev_err(dev, "sh_sir can not set 0 in IRIF_SIR2\n"); 322 return -EIO; 323 } 324 325 sh_sir_write(self, IRIF_SIR0, IRTPW | IRERRC); 326 sh_sir_write(self, IRIF_SIR1, irbca); 327 sh_sir_write(self, IRIF_SIR2, irbc); 328 329 /* 330 * CALCULATION 331 * 332 * BaudRate[bps] = system rate / (uabca + (uabc + 1) x 16) 333 */ 334 335 uabc = rate / baudrate; 336 uabc = (uabc / 16) - 1; 337 uabc = (uabc + 1) * 16; 338 339 tmp = rate - (uabc * baudrate); 340 tmp *= 10000; 341 342 rerr = tmp / baudrate; 343 344 min = 0xffffffff; 345 uabca = 0; 346 for (i = 0; i < ARRAY_SIZE(rate_err_array); i++) { 347 tmp = abs(rate_err_array[i] - rerr); 348 if (min > tmp) { 349 min = tmp; 350 uabca = i; 351 } 352 } 353 354 tmp = rate / (uabc + ERR_ROUNDING(rate_err_array[uabca])); 355 if ((baudrate / 100) < abs(tmp - baudrate)) 356 dev_warn(dev, "UART freq error margin over %d\n", tmp); 357 358 dev_dbg(dev, "target = %d, result = %d, uart = %d.%d\n", 359 baudrate, tmp, 360 uabc, rate_err_array[uabca]); 361 362 uabca = (uabca & 0xF) << 4; 363 uabc = (uabc / 16) - 1; 364 365 sh_sir_write(self, IRIF_UART6, uabca); 366 sh_sir_write(self, IRIF_UART7, uabc); 367 368 return 0; 369} 370 371/************************************************************************ 372 373 374 iobuf function 375 376 377************************************************************************/ 378static int __sh_sir_init_iobuf(iobuff_t *io, int size) 379{ 380 io->head = kmalloc(size, GFP_KERNEL); 381 if (!io->head) 382 return -ENOMEM; 383 384 io->truesize = size; 385 io->in_frame = FALSE; 386 io->state = OUTSIDE_FRAME; 387 io->data = io->head; 388 389 return 0; 390} 391 392static void sh_sir_remove_iobuf(struct sh_sir_self *self) 393{ 394 kfree(self->rx_buff.head); 395 kfree(self->tx_buff.head); 396 397 self->rx_buff.head = NULL; 398 self->tx_buff.head = NULL; 399} 400 401static int sh_sir_init_iobuf(struct sh_sir_self *self, int rxsize, int txsize) 402{ 403 int err = -ENOMEM; 404 405 if (self->rx_buff.head || 406 self->tx_buff.head) { 407 dev_err(&self->ndev->dev, "iobuff has already existed."); 408 return err; 409 } 410 411 err = __sh_sir_init_iobuf(&self->rx_buff, rxsize); 412 if (err) 413 goto iobuf_err; 414 415 err = __sh_sir_init_iobuf(&self->tx_buff, txsize); 416 417iobuf_err: 418 if (err) 419 sh_sir_remove_iobuf(self); 420 421 return err; 422} 423 424/************************************************************************ 425 426 427 status function 428 429 430************************************************************************/ 431static void sh_sir_clear_all_err(struct sh_sir_self *self) 432{ 433 /* Clear error flag for receive pulse width */ 434 sh_sir_update_bits(self, IRIF_SIR0, IRERRC, IRERRC); 435 436 /* Clear frame / EOF error flag */ 437 sh_sir_write(self, IRIF_SIR_FLG, 0xffff); 438 439 /* Clear all status error */ 440 sh_sir_write(self, IRIF_UART_STS2, 0); 441} 442 443static void sh_sir_set_phase(struct sh_sir_self *self, int phase) 444{ 445 u16 uart5 = 0; 446 u16 uart0 = 0; 447 448 switch (phase) { 449 case TX_PHASE: 450 uart5 = TBEIM; 451 uart0 = TBEC | TIE; 452 break; 453 case TX_COMP_PHASE: 454 uart5 = TSBEIM; 455 uart0 = TIE; 456 break; 457 case RX_PHASE: 458 uart5 = RX_MASK; 459 uart0 = RIE; 460 break; 461 default: 462 break; 463 } 464 465 sh_sir_write(self, IRIF_UART5, uart5); 466 sh_sir_write(self, IRIF_UART0, uart0); 467} 468 469static int sh_sir_is_which_phase(struct sh_sir_self *self) 470{ 471 u16 val = sh_sir_read(self, IRIF_UART5); 472 473 if (val & TBEIM) 474 return TX_PHASE; 475 476 if (val & TSBEIM) 477 return TX_COMP_PHASE; 478 479 if (val & RX_MASK) 480 return RX_PHASE; 481 482 return NONE_PHASE; 483} 484 485static void sh_sir_tx(struct sh_sir_self *self, int phase) 486{ 487 switch (phase) { 488 case TX_PHASE: 489 if (0 >= self->tx_buff.len) { 490 sh_sir_set_phase(self, TX_COMP_PHASE); 491 } else { 492 sh_sir_write(self, IRIF_UART3, self->tx_buff.data[0]); 493 self->tx_buff.len--; 494 self->tx_buff.data++; 495 } 496 break; 497 case TX_COMP_PHASE: 498 sh_sir_set_phase(self, RX_PHASE); 499 netif_wake_queue(self->ndev); 500 break; 501 default: 502 dev_err(&self->ndev->dev, "should not happen\n"); 503 break; 504 } 505} 506 507static int sh_sir_read_data(struct sh_sir_self *self) 508{ 509 u16 val; 510 int timeout = 1024; 511 512 while (timeout--) { 513 val = sh_sir_read(self, IRIF_UART1); 514 515 /* data get */ 516 if (val & RBF) { 517 if (val & (URSME | UROVE | URFRE | URPRE)) 518 break; 519 520 return (int)sh_sir_read(self, IRIF_UART4); 521 } 522 523 udelay(1); 524 } 525 526 dev_err(&self->ndev->dev, "UART1 %04x : STATUS %04x\n", 527 val, sh_sir_read(self, IRIF_UART_STS2)); 528 529 /* read data register for clear error */ 530 sh_sir_read(self, IRIF_UART4); 531 532 return -1; 533} 534 535static void sh_sir_rx(struct sh_sir_self *self) 536{ 537 int timeout = 1024; 538 int data; 539 540 while (timeout--) { 541 data = sh_sir_read_data(self); 542 if (data < 0) 543 break; 544 545 async_unwrap_char(self->ndev, &self->ndev->stats, 546 &self->rx_buff, (u8)data); 547 self->ndev->last_rx = jiffies; 548 549 if (EOFD & sh_sir_read(self, IRIF_SIR_FRM)) 550 continue; 551 552 break; 553 } 554} 555 556static irqreturn_t sh_sir_irq(int irq, void *dev_id) 557{ 558 struct sh_sir_self *self = dev_id; 559 struct device *dev = &self->ndev->dev; 560 int phase = sh_sir_is_which_phase(self); 561 562 switch (phase) { 563 case TX_COMP_PHASE: 564 case TX_PHASE: 565 sh_sir_tx(self, phase); 566 break; 567 case RX_PHASE: 568 if (sh_sir_read(self, IRIF_SIR3)) 569 dev_err(dev, "rcv pulse width error occurred\n"); 570 571 sh_sir_rx(self); 572 sh_sir_clear_all_err(self); 573 break; 574 default: 575 dev_err(dev, "unknown interrupt\n"); 576 } 577 578 return IRQ_HANDLED; 579} 580 581/************************************************************************ 582 583 584 net_device_ops function 585 586 587************************************************************************/ 588static int sh_sir_hard_xmit(struct sk_buff *skb, struct net_device *ndev) 589{ 590 struct sh_sir_self *self = netdev_priv(ndev); 591 int speed = irda_get_next_speed(skb); 592 593 if ((0 < speed) && 594 (9600 != speed)) { 595 dev_err(&ndev->dev, "support 9600 only (%d)\n", speed); 596 return -EIO; 597 } 598 599 netif_stop_queue(ndev); 600 601 self->tx_buff.data = self->tx_buff.head; 602 self->tx_buff.len = 0; 603 if (skb->len) 604 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data, 605 self->tx_buff.truesize); 606 607 sh_sir_set_phase(self, TX_PHASE); 608 dev_kfree_skb(skb); 609 610 return 0; 611} 612 613static int sh_sir_ioctl(struct net_device *ndev, struct ifreq *ifreq, int cmd) 614{ 615 return 0; 616} 617 618static struct net_device_stats *sh_sir_stats(struct net_device *ndev) 619{ 620 struct sh_sir_self *self = netdev_priv(ndev); 621 622 return &self->ndev->stats; 623} 624 625static int sh_sir_open(struct net_device *ndev) 626{ 627 struct sh_sir_self *self = netdev_priv(ndev); 628 int err; 629 630 clk_enable(self->clk); 631 err = sh_sir_crc_init(self); 632 if (err) 633 goto open_err; 634 635 sh_sir_set_baudrate(self, 9600); 636 637 self->irlap = irlap_open(ndev, &self->qos, DRIVER_NAME); 638 if (!self->irlap) { 639 err = -ENODEV; 640 goto open_err; 641 } 642 643 /* 644 * Now enable the interrupt then start the queue 645 */ 646 sh_sir_update_bits(self, IRIF_SIR_FRM, FRP, FRP); 647 sh_sir_read(self, IRIF_UART1); /* flag clear */ 648 sh_sir_read(self, IRIF_UART4); /* flag clear */ 649 sh_sir_set_phase(self, RX_PHASE); 650 651 netif_start_queue(ndev); 652 653 dev_info(&self->ndev->dev, "opened\n"); 654 655 return 0; 656 657open_err: 658 clk_disable(self->clk); 659 660 return err; 661} 662 663static int sh_sir_stop(struct net_device *ndev) 664{ 665 struct sh_sir_self *self = netdev_priv(ndev); 666 667 /* Stop IrLAP */ 668 if (self->irlap) { 669 irlap_close(self->irlap); 670 self->irlap = NULL; 671 } 672 673 netif_stop_queue(ndev); 674 675 dev_info(&ndev->dev, "stoped\n"); 676 677 return 0; 678} 679 680static const struct net_device_ops sh_sir_ndo = { 681 .ndo_open = sh_sir_open, 682 .ndo_stop = sh_sir_stop, 683 .ndo_start_xmit = sh_sir_hard_xmit, 684 .ndo_do_ioctl = sh_sir_ioctl, 685 .ndo_get_stats = sh_sir_stats, 686}; 687 688/************************************************************************ 689 690 691 platform_driver function 692 693 694************************************************************************/ 695static int __devinit sh_sir_probe(struct platform_device *pdev) 696{ 697 struct net_device *ndev; 698 struct sh_sir_self *self; 699 struct resource *res; 700 char clk_name[8]; 701 int irq; 702 int err = -ENOMEM; 703 704 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 705 irq = platform_get_irq(pdev, 0); 706 if (!res || irq < 0) { 707 dev_err(&pdev->dev, "Not enough platform resources.\n"); 708 goto exit; 709 } 710 711 ndev = alloc_irdadev(sizeof(*self)); 712 if (!ndev) 713 goto exit; 714 715 self = netdev_priv(ndev); 716 self->membase = ioremap_nocache(res->start, resource_size(res)); 717 if (!self->membase) { 718 err = -ENXIO; 719 dev_err(&pdev->dev, "Unable to ioremap.\n"); 720 goto err_mem_1; 721 } 722 723 err = sh_sir_init_iobuf(self, IRDA_SKB_MAX_MTU, IRDA_SIR_MAX_FRAME); 724 if (err) 725 goto err_mem_2; 726 727 snprintf(clk_name, sizeof(clk_name), "irda%d", pdev->id); 728 self->clk = clk_get(&pdev->dev, clk_name); 729 if (IS_ERR(self->clk)) { 730 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name); 731 goto err_mem_3; 732 } 733 734 irda_init_max_qos_capabilies(&self->qos); 735 736 ndev->netdev_ops = &sh_sir_ndo; 737 ndev->irq = irq; 738 739 self->ndev = ndev; 740 self->qos.baud_rate.bits &= IR_9600; 741 self->qos.min_turn_time.bits = 1; /* 10 ms or more */ 742 743 irda_qos_bits_to_value(&self->qos); 744 745 err = register_netdev(ndev); 746 if (err) 747 goto err_mem_4; 748 749 platform_set_drvdata(pdev, ndev); 750 751 if (request_irq(irq, sh_sir_irq, IRQF_DISABLED, "sh_sir", self)) { 752 dev_warn(&pdev->dev, "Unable to attach sh_sir interrupt\n"); 753 goto err_mem_4; 754 } 755 756 dev_info(&pdev->dev, "SuperH IrDA probed\n"); 757 758 goto exit; 759 760err_mem_4: 761 clk_put(self->clk); 762err_mem_3: 763 sh_sir_remove_iobuf(self); 764err_mem_2: 765 iounmap(self->membase); 766err_mem_1: 767 free_netdev(ndev); 768exit: 769 return err; 770} 771 772static int __devexit sh_sir_remove(struct platform_device *pdev) 773{ 774 struct net_device *ndev = platform_get_drvdata(pdev); 775 struct sh_sir_self *self = netdev_priv(ndev); 776 777 if (!self) 778 return 0; 779 780 unregister_netdev(ndev); 781 clk_put(self->clk); 782 sh_sir_remove_iobuf(self); 783 iounmap(self->membase); 784 free_netdev(ndev); 785 platform_set_drvdata(pdev, NULL); 786 787 return 0; 788} 789 790static struct platform_driver sh_sir_driver = { 791 .probe = sh_sir_probe, 792 .remove = __devexit_p(sh_sir_remove), 793 .driver = { 794 .name = DRIVER_NAME, 795 }, 796}; 797 798static int __init sh_sir_init(void) 799{ 800 return platform_driver_register(&sh_sir_driver); 801} 802 803static void __exit sh_sir_exit(void) 804{ 805 platform_driver_unregister(&sh_sir_driver); 806} 807 808module_init(sh_sir_init); 809module_exit(sh_sir_exit); 810 811MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); 812MODULE_DESCRIPTION("SuperH IrDA driver"); 813MODULE_LICENSE("GPL"); 814