1/* 2 * drivers/net/ibm_newemac/debug.c 3 * 4 * Driver for PowerPC 4xx on-chip ethernet controller, debug print routines. 5 * 6 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp. 7 * <benh@kernel.crashing.org> 8 * 9 * Based on the arch/ppc version of the driver: 10 * 11 * Copyright (c) 2004, 2005 Zultys Technologies 12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 13 * 14 * This program is free software; you can redistribute it and/or modify it 15 * under the terms of the GNU General Public License as published by the 16 * Free Software Foundation; either version 2 of the License, or (at your 17 * option) any later version. 18 * 19 */ 20#include <linux/init.h> 21#include <linux/module.h> 22#include <linux/kernel.h> 23#include <linux/netdevice.h> 24#include <linux/sysrq.h> 25#include <asm/io.h> 26 27#include "core.h" 28 29static DEFINE_SPINLOCK(emac_dbg_lock); 30 31static void emac_desc_dump(struct emac_instance *p) 32{ 33 int i; 34 printk("** EMAC %s TX BDs **\n" 35 " tx_cnt = %d tx_slot = %d ack_slot = %d\n", 36 p->ofdev->dev.of_node->full_name, 37 p->tx_cnt, p->tx_slot, p->ack_slot); 38 for (i = 0; i < NUM_TX_BUFF / 2; ++i) 39 printk 40 ("bd[%2d] 0x%08x %c 0x%04x %4u - bd[%2d] 0x%08x %c 0x%04x %4u\n", 41 i, p->tx_desc[i].data_ptr, p->tx_skb[i] ? 'V' : ' ', 42 p->tx_desc[i].ctrl, p->tx_desc[i].data_len, 43 NUM_TX_BUFF / 2 + i, 44 p->tx_desc[NUM_TX_BUFF / 2 + i].data_ptr, 45 p->tx_skb[NUM_TX_BUFF / 2 + i] ? 'V' : ' ', 46 p->tx_desc[NUM_TX_BUFF / 2 + i].ctrl, 47 p->tx_desc[NUM_TX_BUFF / 2 + i].data_len); 48 49 printk("** EMAC %s RX BDs **\n" 50 " rx_slot = %d flags = 0x%lx rx_skb_size = %d rx_sync_size = %d\n" 51 " rx_sg_skb = 0x%p\n", 52 p->ofdev->dev.of_node->full_name, 53 p->rx_slot, p->commac.flags, p->rx_skb_size, 54 p->rx_sync_size, p->rx_sg_skb); 55 for (i = 0; i < NUM_RX_BUFF / 2; ++i) 56 printk 57 ("bd[%2d] 0x%08x %c 0x%04x %4u - bd[%2d] 0x%08x %c 0x%04x %4u\n", 58 i, p->rx_desc[i].data_ptr, p->rx_skb[i] ? 'V' : ' ', 59 p->rx_desc[i].ctrl, p->rx_desc[i].data_len, 60 NUM_RX_BUFF / 2 + i, 61 p->rx_desc[NUM_RX_BUFF / 2 + i].data_ptr, 62 p->rx_skb[NUM_RX_BUFF / 2 + i] ? 'V' : ' ', 63 p->rx_desc[NUM_RX_BUFF / 2 + i].ctrl, 64 p->rx_desc[NUM_RX_BUFF / 2 + i].data_len); 65} 66 67static void emac_mac_dump(struct emac_instance *dev) 68{ 69 struct emac_regs __iomem *p = dev->emacp; 70 const int xaht_regs = EMAC_XAHT_REGS(dev); 71 u32 *gaht_base = emac_gaht_base(dev); 72 u32 *iaht_base = emac_iaht_base(dev); 73 int emac4sync = emac_has_feature(dev, EMAC_FTR_EMAC4SYNC); 74 int n; 75 76 printk("** EMAC %s registers **\n" 77 "MR0 = 0x%08x MR1 = 0x%08x TMR0 = 0x%08x TMR1 = 0x%08x\n" 78 "RMR = 0x%08x ISR = 0x%08x ISER = 0x%08x\n" 79 "IAR = %04x%08x VTPID = 0x%04x VTCI = 0x%04x\n", 80 dev->ofdev->dev.of_node->full_name, 81 in_be32(&p->mr0), in_be32(&p->mr1), 82 in_be32(&p->tmr0), in_be32(&p->tmr1), 83 in_be32(&p->rmr), in_be32(&p->isr), in_be32(&p->iser), 84 in_be32(&p->iahr), in_be32(&p->ialr), in_be32(&p->vtpid), 85 in_be32(&p->vtci) 86 ); 87 88 if (emac4sync) 89 printk("MAR = %04x%08x MMAR = %04x%08x\n", 90 in_be32(&p->u0.emac4sync.mahr), 91 in_be32(&p->u0.emac4sync.malr), 92 in_be32(&p->u0.emac4sync.mmahr), 93 in_be32(&p->u0.emac4sync.mmalr) 94 ); 95 96 for (n = 0; n < xaht_regs; n++) 97 printk("IAHT%02d = 0x%08x\n", n + 1, in_be32(iaht_base + n)); 98 99 for (n = 0; n < xaht_regs; n++) 100 printk("GAHT%02d = 0x%08x\n", n + 1, in_be32(gaht_base + n)); 101 102 printk("LSA = %04x%08x IPGVR = 0x%04x\n" 103 "STACR = 0x%08x TRTR = 0x%08x RWMR = 0x%08x\n" 104 "OCTX = 0x%08x OCRX = 0x%08x\n", 105 in_be32(&p->lsah), in_be32(&p->lsal), in_be32(&p->ipgvr), 106 in_be32(&p->stacr), in_be32(&p->trtr), in_be32(&p->rwmr), 107 in_be32(&p->octx), in_be32(&p->ocrx) 108 ); 109 110 if (!emac4sync) { 111 printk("IPCR = 0x%08x\n", 112 in_be32(&p->u1.emac4.ipcr) 113 ); 114 } else { 115 printk("REVID = 0x%08x TPC = 0x%08x\n", 116 in_be32(&p->u1.emac4sync.revid), 117 in_be32(&p->u1.emac4sync.tpc) 118 ); 119 } 120 121 emac_desc_dump(dev); 122} 123 124static void emac_mal_dump(struct mal_instance *mal) 125{ 126 int i; 127 128 printk("** MAL %s Registers **\n" 129 "CFG = 0x%08x ESR = 0x%08x IER = 0x%08x\n" 130 "TX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x\n" 131 "RX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x\n", 132 mal->ofdev->dev.of_node->full_name, 133 get_mal_dcrn(mal, MAL_CFG), get_mal_dcrn(mal, MAL_ESR), 134 get_mal_dcrn(mal, MAL_IER), 135 get_mal_dcrn(mal, MAL_TXCASR), get_mal_dcrn(mal, MAL_TXCARR), 136 get_mal_dcrn(mal, MAL_TXEOBISR), get_mal_dcrn(mal, MAL_TXDEIR), 137 get_mal_dcrn(mal, MAL_RXCASR), get_mal_dcrn(mal, MAL_RXCARR), 138 get_mal_dcrn(mal, MAL_RXEOBISR), get_mal_dcrn(mal, MAL_RXDEIR) 139 ); 140 141 printk("TX|"); 142 for (i = 0; i < mal->num_tx_chans; ++i) { 143 if (i && !(i % 4)) 144 printk("\n "); 145 printk("CTP%d = 0x%08x ", i, get_mal_dcrn(mal, MAL_TXCTPR(i))); 146 } 147 printk("\nRX|"); 148 for (i = 0; i < mal->num_rx_chans; ++i) { 149 if (i && !(i % 4)) 150 printk("\n "); 151 printk("CTP%d = 0x%08x ", i, get_mal_dcrn(mal, MAL_RXCTPR(i))); 152 } 153 printk("\n "); 154 for (i = 0; i < mal->num_rx_chans; ++i) { 155 u32 r = get_mal_dcrn(mal, MAL_RCBS(i)); 156 if (i && !(i % 3)) 157 printk("\n "); 158 printk("RCBS%d = 0x%08x (%d) ", i, r, r * 16); 159 } 160 printk("\n"); 161} 162 163static struct emac_instance *__emacs[4]; 164static struct mal_instance *__mals[1]; 165 166void emac_dbg_register(struct emac_instance *dev) 167{ 168 unsigned long flags; 169 int i; 170 171 spin_lock_irqsave(&emac_dbg_lock, flags); 172 for (i = 0; i < ARRAY_SIZE(__emacs); i++) 173 if (__emacs[i] == NULL) { 174 __emacs[i] = dev; 175 break; 176 } 177 spin_unlock_irqrestore(&emac_dbg_lock, flags); 178} 179 180void emac_dbg_unregister(struct emac_instance *dev) 181{ 182 unsigned long flags; 183 int i; 184 185 spin_lock_irqsave(&emac_dbg_lock, flags); 186 for (i = 0; i < ARRAY_SIZE(__emacs); i++) 187 if (__emacs[i] == dev) { 188 __emacs[i] = NULL; 189 break; 190 } 191 spin_unlock_irqrestore(&emac_dbg_lock, flags); 192} 193 194void mal_dbg_register(struct mal_instance *mal) 195{ 196 unsigned long flags; 197 int i; 198 199 spin_lock_irqsave(&emac_dbg_lock, flags); 200 for (i = 0; i < ARRAY_SIZE(__mals); i++) 201 if (__mals[i] == NULL) { 202 __mals[i] = mal; 203 break; 204 } 205 spin_unlock_irqrestore(&emac_dbg_lock, flags); 206} 207 208void mal_dbg_unregister(struct mal_instance *mal) 209{ 210 unsigned long flags; 211 int i; 212 213 spin_lock_irqsave(&emac_dbg_lock, flags); 214 for (i = 0; i < ARRAY_SIZE(__mals); i++) 215 if (__mals[i] == mal) { 216 __mals[i] = NULL; 217 break; 218 } 219 spin_unlock_irqrestore(&emac_dbg_lock, flags); 220} 221 222void emac_dbg_dump_all(void) 223{ 224 unsigned int i; 225 unsigned long flags; 226 227 spin_lock_irqsave(&emac_dbg_lock, flags); 228 229 for (i = 0; i < ARRAY_SIZE(__mals); ++i) 230 if (__mals[i]) 231 emac_mal_dump(__mals[i]); 232 233 for (i = 0; i < ARRAY_SIZE(__emacs); ++i) 234 if (__emacs[i]) 235 emac_mac_dump(__emacs[i]); 236 237 spin_unlock_irqrestore(&emac_dbg_lock, flags); 238} 239 240#if defined(CONFIG_MAGIC_SYSRQ) 241static void emac_sysrq_handler(int key) 242{ 243 emac_dbg_dump_all(); 244} 245 246static struct sysrq_key_op emac_sysrq_op = { 247 .handler = emac_sysrq_handler, 248 .help_msg = "emaC", 249 .action_msg = "Show EMAC(s) status", 250}; 251 252int __init emac_init_debug(void) 253{ 254 return register_sysrq_key('c', &emac_sysrq_op); 255} 256 257void __exit emac_fini_debug(void) 258{ 259 unregister_sysrq_key('c', &emac_sysrq_op); 260} 261 262#else 263int __init emac_init_debug(void) 264{ 265 return 0; 266} 267void __exit emac_fini_debug(void) 268{ 269} 270#endif /* CONFIG_MAGIC_SYSRQ */ 271