1/* 2 * drivers/net/ibm_newemac/core.h 3 * 4 * Driver for PowerPC 4xx on-chip ethernet controller. 5 * 6 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp. 7 * <benh@kernel.crashing.org> 8 * 9 * Based on the arch/ppc version of the driver: 10 * 11 * Copyright (c) 2004, 2005 Zultys Technologies. 12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 13 * 14 * Based on original work by 15 * Armin Kuster <akuster@mvista.com> 16 * Johnnie Peters <jpeters@mvista.com> 17 * Copyright 2000, 2001 MontaVista Softare Inc. 18 * 19 * This program is free software; you can redistribute it and/or modify it 20 * under the terms of the GNU General Public License as published by the 21 * Free Software Foundation; either version 2 of the License, or (at your 22 * option) any later version. 23 * 24 */ 25#ifndef __IBM_NEWEMAC_CORE_H 26#define __IBM_NEWEMAC_CORE_H 27 28#include <linux/module.h> 29#include <linux/init.h> 30#include <linux/list.h> 31#include <linux/kernel.h> 32#include <linux/interrupt.h> 33#include <linux/netdevice.h> 34#include <linux/dma-mapping.h> 35#include <linux/spinlock.h> 36#include <linux/of_platform.h> 37#include <linux/slab.h> 38 39#include <asm/io.h> 40#include <asm/dcr.h> 41 42#include "emac.h" 43#include "phy.h" 44#include "zmii.h" 45#include "rgmii.h" 46#include "mal.h" 47#include "tah.h" 48#include "debug.h" 49 50#define NUM_TX_BUFF CONFIG_IBM_NEW_EMAC_TXB 51#define NUM_RX_BUFF CONFIG_IBM_NEW_EMAC_RXB 52 53/* Simple sanity check */ 54#if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256 55#error Invalid number of buffer descriptors (greater than 256) 56#endif 57 58#define EMAC_MIN_MTU 46 59 60/* Maximum L2 header length (VLAN tagged, no FCS) */ 61#define EMAC_MTU_OVERHEAD (6 * 2 + 2 + 4) 62 63/* RX BD size for the given MTU */ 64static inline int emac_rx_size(int mtu) 65{ 66 if (mtu > ETH_DATA_LEN) 67 return MAL_MAX_RX_SIZE; 68 else 69 return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD); 70} 71 72#define EMAC_DMA_ALIGN(x) ALIGN((x), dma_get_cache_alignment()) 73 74#define EMAC_RX_SKB_HEADROOM \ 75 EMAC_DMA_ALIGN(CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM) 76 77/* Size of RX skb for the given MTU */ 78static inline int emac_rx_skb_size(int mtu) 79{ 80 int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu)); 81 return EMAC_DMA_ALIGN(size + 2) + EMAC_RX_SKB_HEADROOM; 82} 83 84/* RX DMA sync size */ 85static inline int emac_rx_sync_size(int mtu) 86{ 87 return EMAC_DMA_ALIGN(emac_rx_size(mtu) + 2); 88} 89 90/* Driver statistcs is split into two parts to make it more cache friendly: 91 * - normal statistics (packet count, etc) 92 * - error statistics 93 * 94 * When statistics is requested by ethtool, these parts are concatenated, 95 * normal one goes first. 96 * 97 * Please, keep these structures in sync with emac_stats_keys. 98 */ 99 100/* Normal TX/RX Statistics */ 101struct emac_stats { 102 u64 rx_packets; 103 u64 rx_bytes; 104 u64 tx_packets; 105 u64 tx_bytes; 106 u64 rx_packets_csum; 107 u64 tx_packets_csum; 108}; 109 110/* Error statistics */ 111struct emac_error_stats { 112 u64 tx_undo; 113 114 /* Software RX Errors */ 115 u64 rx_dropped_stack; 116 u64 rx_dropped_oom; 117 u64 rx_dropped_error; 118 u64 rx_dropped_resize; 119 u64 rx_dropped_mtu; 120 u64 rx_stopped; 121 /* BD reported RX errors */ 122 u64 rx_bd_errors; 123 u64 rx_bd_overrun; 124 u64 rx_bd_bad_packet; 125 u64 rx_bd_runt_packet; 126 u64 rx_bd_short_event; 127 u64 rx_bd_alignment_error; 128 u64 rx_bd_bad_fcs; 129 u64 rx_bd_packet_too_long; 130 u64 rx_bd_out_of_range; 131 u64 rx_bd_in_range; 132 /* EMAC IRQ reported RX errors */ 133 u64 rx_parity; 134 u64 rx_fifo_overrun; 135 u64 rx_overrun; 136 u64 rx_bad_packet; 137 u64 rx_runt_packet; 138 u64 rx_short_event; 139 u64 rx_alignment_error; 140 u64 rx_bad_fcs; 141 u64 rx_packet_too_long; 142 u64 rx_out_of_range; 143 u64 rx_in_range; 144 145 /* Software TX Errors */ 146 u64 tx_dropped; 147 /* BD reported TX errors */ 148 u64 tx_bd_errors; 149 u64 tx_bd_bad_fcs; 150 u64 tx_bd_carrier_loss; 151 u64 tx_bd_excessive_deferral; 152 u64 tx_bd_excessive_collisions; 153 u64 tx_bd_late_collision; 154 u64 tx_bd_multple_collisions; 155 u64 tx_bd_single_collision; 156 u64 tx_bd_underrun; 157 u64 tx_bd_sqe; 158 /* EMAC IRQ reported TX errors */ 159 u64 tx_parity; 160 u64 tx_underrun; 161 u64 tx_sqe; 162 u64 tx_errors; 163}; 164 165#define EMAC_ETHTOOL_STATS_COUNT ((sizeof(struct emac_stats) + \ 166 sizeof(struct emac_error_stats)) \ 167 / sizeof(u64)) 168 169struct emac_instance { 170 struct net_device *ndev; 171 struct resource rsrc_regs; 172 struct emac_regs __iomem *emacp; 173 struct platform_device *ofdev; 174 struct device_node **blist; /* bootlist entry */ 175 176 /* MAL linkage */ 177 u32 mal_ph; 178 struct platform_device *mal_dev; 179 u32 mal_rx_chan; 180 u32 mal_tx_chan; 181 struct mal_instance *mal; 182 struct mal_commac commac; 183 184 /* PHY infos */ 185 u32 phy_mode; 186 u32 phy_map; 187 u32 phy_address; 188 u32 phy_feat_exc; 189 struct mii_phy phy; 190 struct mutex link_lock; 191 struct delayed_work link_work; 192 int link_polling; 193 194 /* GPCS PHY infos */ 195 u32 gpcs_address; 196 197 /* Shared MDIO if any */ 198 u32 mdio_ph; 199 struct platform_device *mdio_dev; 200 struct emac_instance *mdio_instance; 201 struct mutex mdio_lock; 202 203 /* ZMII infos if any */ 204 u32 zmii_ph; 205 u32 zmii_port; 206 struct platform_device *zmii_dev; 207 208 /* RGMII infos if any */ 209 u32 rgmii_ph; 210 u32 rgmii_port; 211 struct platform_device *rgmii_dev; 212 213 /* TAH infos if any */ 214 u32 tah_ph; 215 u32 tah_port; 216 struct platform_device *tah_dev; 217 218 /* IRQs */ 219 int wol_irq; 220 int emac_irq; 221 222 /* OPB bus frequency in Mhz */ 223 u32 opb_bus_freq; 224 225 /* Cell index within an ASIC (for clk mgmnt) */ 226 u32 cell_index; 227 228 /* Max supported MTU */ 229 u32 max_mtu; 230 231 /* Feature bits (from probe table) */ 232 unsigned int features; 233 234 /* Tx and Rx fifo sizes & other infos in bytes */ 235 u32 tx_fifo_size; 236 u32 tx_fifo_size_gige; 237 u32 rx_fifo_size; 238 u32 rx_fifo_size_gige; 239 u32 fifo_entry_size; 240 u32 mal_burst_size; /* move to MAL ? */ 241 242 /* IAHT and GAHT filter parameterization */ 243 u32 xaht_slots_shift; 244 u32 xaht_width_shift; 245 246 /* Descriptor management 247 */ 248 struct mal_descriptor *tx_desc; 249 int tx_cnt; 250 int tx_slot; 251 int ack_slot; 252 253 struct mal_descriptor *rx_desc; 254 int rx_slot; 255 struct sk_buff *rx_sg_skb; /* 1 */ 256 int rx_skb_size; 257 int rx_sync_size; 258 259 struct sk_buff *tx_skb[NUM_TX_BUFF]; 260 struct sk_buff *rx_skb[NUM_RX_BUFF]; 261 262 /* Stats 263 */ 264 struct emac_error_stats estats; 265 struct net_device_stats nstats; 266 struct emac_stats stats; 267 268 /* Misc 269 */ 270 int reset_failed; 271 int stop_timeout; /* in us */ 272 int no_mcast; 273 int mcast_pending; 274 int opened; 275 struct work_struct reset_work; 276 spinlock_t lock; 277}; 278 279/* 280 * Features of various EMAC implementations 281 */ 282 283/* 284 * No flow control on 40x according to the original driver 285 */ 286#define EMAC_FTR_NO_FLOW_CONTROL_40x 0x00000001 287/* 288 * Cell is an EMAC4 289 */ 290#define EMAC_FTR_EMAC4 0x00000002 291/* 292 * For the 440SPe, AMCC inexplicably changed the polarity of 293 * the "operation complete" bit in the MII control register. 294 */ 295#define EMAC_FTR_STACR_OC_INVERT 0x00000004 296/* 297 * Set if we have a TAH. 298 */ 299#define EMAC_FTR_HAS_TAH 0x00000008 300/* 301 * Set if we have a ZMII. 302 */ 303#define EMAC_FTR_HAS_ZMII 0x00000010 304/* 305 * Set if we have a RGMII. 306 */ 307#define EMAC_FTR_HAS_RGMII 0x00000020 308/* 309 * Set if we have new type STACR with STAOPC 310 */ 311#define EMAC_FTR_HAS_NEW_STACR 0x00000040 312#define EMAC_FTR_440GX_PHY_CLK_FIX 0x00000080 313#define EMAC_FTR_440EP_PHY_CLK_FIX 0x00000100 314/* 315 * The 405EX and 460EX contain the EMAC4SYNC core 316 */ 317#define EMAC_FTR_EMAC4SYNC 0x00000200 318#define EMAC_FTR_460EX_PHY_CLK_FIX 0x00000400 319 320 321/* Right now, we don't quite handle the always/possible masks on the 322 * most optimal way as we don't have a way to say something like 323 * always EMAC4. Patches welcome. 324 */ 325enum { 326 EMAC_FTRS_ALWAYS = 0, 327 328 EMAC_FTRS_POSSIBLE = 329#ifdef CONFIG_IBM_NEW_EMAC_EMAC4 330 EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC | 331 EMAC_FTR_HAS_NEW_STACR | 332 EMAC_FTR_STACR_OC_INVERT | EMAC_FTR_440GX_PHY_CLK_FIX | 333#endif 334#ifdef CONFIG_IBM_NEW_EMAC_TAH 335 EMAC_FTR_HAS_TAH | 336#endif 337#ifdef CONFIG_IBM_NEW_EMAC_ZMII 338 EMAC_FTR_HAS_ZMII | 339#endif 340#ifdef CONFIG_IBM_NEW_EMAC_RGMII 341 EMAC_FTR_HAS_RGMII | 342#endif 343#ifdef CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL 344 EMAC_FTR_NO_FLOW_CONTROL_40x | 345#endif 346 EMAC_FTR_460EX_PHY_CLK_FIX | 347 EMAC_FTR_440EP_PHY_CLK_FIX, 348}; 349 350static inline int emac_has_feature(struct emac_instance *dev, 351 unsigned long feature) 352{ 353 return (EMAC_FTRS_ALWAYS & feature) || 354 (EMAC_FTRS_POSSIBLE & dev->features & feature); 355} 356 357/* 358 * Various instances of the EMAC core have varying 1) number of 359 * address match slots, 2) width of the registers for handling address 360 * match slots, 3) number of registers for handling address match 361 * slots and 4) base offset for those registers. 362 * 363 * These macros and inlines handle these differences based on 364 * parameters supplied by the device structure which are, in turn, 365 * initialized based on the "compatible" entry in the device tree. 366 */ 367 368#define EMAC4_XAHT_SLOTS_SHIFT 6 369#define EMAC4_XAHT_WIDTH_SHIFT 4 370 371#define EMAC4SYNC_XAHT_SLOTS_SHIFT 8 372#define EMAC4SYNC_XAHT_WIDTH_SHIFT 5 373 374#define EMAC_XAHT_SLOTS(dev) (1 << (dev)->xaht_slots_shift) 375#define EMAC_XAHT_WIDTH(dev) (1 << (dev)->xaht_width_shift) 376#define EMAC_XAHT_REGS(dev) (1 << ((dev)->xaht_slots_shift - \ 377 (dev)->xaht_width_shift)) 378 379#define EMAC_XAHT_CRC_TO_SLOT(dev, crc) \ 380 ((EMAC_XAHT_SLOTS(dev) - 1) - \ 381 ((crc) >> ((sizeof (u32) * BITS_PER_BYTE) - \ 382 (dev)->xaht_slots_shift))) 383 384#define EMAC_XAHT_SLOT_TO_REG(dev, slot) \ 385 ((slot) >> (dev)->xaht_width_shift) 386 387#define EMAC_XAHT_SLOT_TO_MASK(dev, slot) \ 388 ((u32)(1 << (EMAC_XAHT_WIDTH(dev) - 1)) >> \ 389 ((slot) & (u32)(EMAC_XAHT_WIDTH(dev) - 1))) 390 391static inline u32 *emac_xaht_base(struct emac_instance *dev) 392{ 393 struct emac_regs __iomem *p = dev->emacp; 394 int offset; 395 396 /* The first IAHT entry always is the base of the block of 397 * IAHT and GAHT registers. 398 */ 399 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) 400 offset = offsetof(struct emac_regs, u1.emac4sync.iaht1); 401 else 402 offset = offsetof(struct emac_regs, u0.emac4.iaht1); 403 404 return ((u32 *)((ptrdiff_t)p + offset)); 405} 406 407static inline u32 *emac_gaht_base(struct emac_instance *dev) 408{ 409 /* GAHT registers always come after an identical number of 410 * IAHT registers. 411 */ 412 return (emac_xaht_base(dev) + EMAC_XAHT_REGS(dev)); 413} 414 415static inline u32 *emac_iaht_base(struct emac_instance *dev) 416{ 417 /* IAHT registers always come before an identical number of 418 * GAHT registers. 419 */ 420 return (emac_xaht_base(dev)); 421} 422 423/* Ethtool get_regs complex data. 424 * We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH 425 * when available. 426 * 427 * Returned BLOB consists of the ibm_emac_ethtool_regs_hdr, 428 * MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers. 429 * Each register component is preceded with emac_ethtool_regs_subhdr. 430 * Order of the optional headers follows their relative bit posititions 431 * in emac_ethtool_regs_hdr.components 432 */ 433#define EMAC_ETHTOOL_REGS_ZMII 0x00000001 434#define EMAC_ETHTOOL_REGS_RGMII 0x00000002 435#define EMAC_ETHTOOL_REGS_TAH 0x00000004 436 437struct emac_ethtool_regs_hdr { 438 u32 components; 439}; 440 441struct emac_ethtool_regs_subhdr { 442 u32 version; 443 u32 index; 444}; 445 446#define EMAC_ETHTOOL_REGS_VER 0 447#define EMAC_ETHTOOL_REGS_SIZE(dev) ((dev)->rsrc_regs.end - \ 448 (dev)->rsrc_regs.start + 1) 449#define EMAC4_ETHTOOL_REGS_VER 1 450#define EMAC4_ETHTOOL_REGS_SIZE(dev) ((dev)->rsrc_regs.end - \ 451 (dev)->rsrc_regs.start + 1) 452 453#endif /* __IBM_NEWEMAC_CORE_H */ 454