1/* 2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> 3 * JZ4740 SD/MMC controller driver 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * You should have received a copy of the GNU General Public License along 11 * with this program; if not, write to the Free Software Foundation, Inc., 12 * 675 Mass Ave, Cambridge, MA 02139, USA. 13 * 14 */ 15 16#include <linux/mmc/host.h> 17#include <linux/io.h> 18#include <linux/irq.h> 19#include <linux/interrupt.h> 20#include <linux/module.h> 21#include <linux/platform_device.h> 22#include <linux/delay.h> 23#include <linux/scatterlist.h> 24#include <linux/clk.h> 25 26#include <linux/bitops.h> 27#include <linux/gpio.h> 28#include <asm/mach-jz4740/gpio.h> 29#include <asm/cacheflush.h> 30#include <linux/dma-mapping.h> 31 32#include <asm/mach-jz4740/jz4740_mmc.h> 33 34#define JZ_REG_MMC_STRPCL 0x00 35#define JZ_REG_MMC_STATUS 0x04 36#define JZ_REG_MMC_CLKRT 0x08 37#define JZ_REG_MMC_CMDAT 0x0C 38#define JZ_REG_MMC_RESTO 0x10 39#define JZ_REG_MMC_RDTO 0x14 40#define JZ_REG_MMC_BLKLEN 0x18 41#define JZ_REG_MMC_NOB 0x1C 42#define JZ_REG_MMC_SNOB 0x20 43#define JZ_REG_MMC_IMASK 0x24 44#define JZ_REG_MMC_IREG 0x28 45#define JZ_REG_MMC_CMD 0x2C 46#define JZ_REG_MMC_ARG 0x30 47#define JZ_REG_MMC_RESP_FIFO 0x34 48#define JZ_REG_MMC_RXFIFO 0x38 49#define JZ_REG_MMC_TXFIFO 0x3C 50 51#define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7) 52#define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6) 53#define JZ_MMC_STRPCL_START_READWAIT BIT(5) 54#define JZ_MMC_STRPCL_STOP_READWAIT BIT(4) 55#define JZ_MMC_STRPCL_RESET BIT(3) 56#define JZ_MMC_STRPCL_START_OP BIT(2) 57#define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0)) 58#define JZ_MMC_STRPCL_CLOCK_STOP BIT(0) 59#define JZ_MMC_STRPCL_CLOCK_START BIT(1) 60 61 62#define JZ_MMC_STATUS_IS_RESETTING BIT(15) 63#define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14) 64#define JZ_MMC_STATUS_PRG_DONE BIT(13) 65#define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12) 66#define JZ_MMC_STATUS_END_CMD_RES BIT(11) 67#define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10) 68#define JZ_MMC_STATUS_IS_READWAIT BIT(9) 69#define JZ_MMC_STATUS_CLK_EN BIT(8) 70#define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7) 71#define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6) 72#define JZ_MMC_STATUS_CRC_RES_ERR BIT(5) 73#define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4) 74#define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3) 75#define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2) 76#define JZ_MMC_STATUS_TIMEOUT_RES BIT(1) 77#define JZ_MMC_STATUS_TIMEOUT_READ BIT(0) 78 79#define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0)) 80#define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2)) 81 82 83#define JZ_MMC_CMDAT_IO_ABORT BIT(11) 84#define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10) 85#define JZ_MMC_CMDAT_DMA_EN BIT(8) 86#define JZ_MMC_CMDAT_INIT BIT(7) 87#define JZ_MMC_CMDAT_BUSY BIT(6) 88#define JZ_MMC_CMDAT_STREAM BIT(5) 89#define JZ_MMC_CMDAT_WRITE BIT(4) 90#define JZ_MMC_CMDAT_DATA_EN BIT(3) 91#define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0)) 92#define JZ_MMC_CMDAT_RSP_R1 1 93#define JZ_MMC_CMDAT_RSP_R2 2 94#define JZ_MMC_CMDAT_RSP_R3 3 95 96#define JZ_MMC_IRQ_SDIO BIT(7) 97#define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6) 98#define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5) 99#define JZ_MMC_IRQ_END_CMD_RES BIT(2) 100#define JZ_MMC_IRQ_PRG_DONE BIT(1) 101#define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0) 102 103 104#define JZ_MMC_CLK_RATE 24000000 105 106enum jz4740_mmc_state { 107 JZ4740_MMC_STATE_READ_RESPONSE, 108 JZ4740_MMC_STATE_TRANSFER_DATA, 109 JZ4740_MMC_STATE_SEND_STOP, 110 JZ4740_MMC_STATE_DONE, 111}; 112 113struct jz4740_mmc_host { 114 struct mmc_host *mmc; 115 struct platform_device *pdev; 116 struct jz4740_mmc_platform_data *pdata; 117 struct clk *clk; 118 119 int irq; 120 int card_detect_irq; 121 122 struct resource *mem; 123 void __iomem *base; 124 struct mmc_request *req; 125 struct mmc_command *cmd; 126 127 unsigned long waiting; 128 129 uint32_t cmdat; 130 131 uint16_t irq_mask; 132 133 spinlock_t lock; 134 135 struct timer_list timeout_timer; 136 struct sg_mapping_iter miter; 137 enum jz4740_mmc_state state; 138}; 139 140static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host, 141 unsigned int irq, bool enabled) 142{ 143 unsigned long flags; 144 145 spin_lock_irqsave(&host->lock, flags); 146 if (enabled) 147 host->irq_mask &= ~irq; 148 else 149 host->irq_mask |= irq; 150 spin_unlock_irqrestore(&host->lock, flags); 151 152 writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK); 153} 154 155static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, 156 bool start_transfer) 157{ 158 uint16_t val = JZ_MMC_STRPCL_CLOCK_START; 159 160 if (start_transfer) 161 val |= JZ_MMC_STRPCL_START_OP; 162 163 writew(val, host->base + JZ_REG_MMC_STRPCL); 164} 165 166static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host) 167{ 168 uint32_t status; 169 unsigned int timeout = 1000; 170 171 writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL); 172 do { 173 status = readl(host->base + JZ_REG_MMC_STATUS); 174 } while (status & JZ_MMC_STATUS_CLK_EN && --timeout); 175} 176 177static void jz4740_mmc_reset(struct jz4740_mmc_host *host) 178{ 179 uint32_t status; 180 unsigned int timeout = 1000; 181 182 writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL); 183 udelay(10); 184 do { 185 status = readl(host->base + JZ_REG_MMC_STATUS); 186 } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout); 187} 188 189static void jz4740_mmc_request_done(struct jz4740_mmc_host *host) 190{ 191 struct mmc_request *req; 192 193 req = host->req; 194 host->req = NULL; 195 196 mmc_request_done(host->mmc, req); 197} 198 199static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host, 200 unsigned int irq) 201{ 202 unsigned int timeout = 0x800; 203 uint16_t status; 204 205 do { 206 status = readw(host->base + JZ_REG_MMC_IREG); 207 } while (!(status & irq) && --timeout); 208 209 if (timeout == 0) { 210 set_bit(0, &host->waiting); 211 mod_timer(&host->timeout_timer, jiffies + 5*HZ); 212 jz4740_mmc_set_irq_enabled(host, irq, true); 213 return true; 214 } 215 216 return false; 217} 218 219static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host, 220 struct mmc_data *data) 221{ 222 int status; 223 224 status = readl(host->base + JZ_REG_MMC_STATUS); 225 if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) { 226 if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) { 227 host->req->cmd->error = -ETIMEDOUT; 228 data->error = -ETIMEDOUT; 229 } else { 230 host->req->cmd->error = -EIO; 231 data->error = -EIO; 232 } 233 } 234} 235 236static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host, 237 struct mmc_data *data) 238{ 239 struct sg_mapping_iter *miter = &host->miter; 240 void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO; 241 uint32_t *buf; 242 bool timeout; 243 size_t i, j; 244 245 while (sg_miter_next(miter)) { 246 buf = miter->addr; 247 i = miter->length / 4; 248 j = i / 8; 249 i = i & 0x7; 250 while (j) { 251 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); 252 if (unlikely(timeout)) 253 goto poll_timeout; 254 255 writel(buf[0], fifo_addr); 256 writel(buf[1], fifo_addr); 257 writel(buf[2], fifo_addr); 258 writel(buf[3], fifo_addr); 259 writel(buf[4], fifo_addr); 260 writel(buf[5], fifo_addr); 261 writel(buf[6], fifo_addr); 262 writel(buf[7], fifo_addr); 263 buf += 8; 264 --j; 265 } 266 if (unlikely(i)) { 267 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); 268 if (unlikely(timeout)) 269 goto poll_timeout; 270 271 while (i) { 272 writel(*buf, fifo_addr); 273 ++buf; 274 --i; 275 } 276 } 277 data->bytes_xfered += miter->length; 278 } 279 sg_miter_stop(miter); 280 281 return false; 282 283poll_timeout: 284 miter->consumed = (void *)buf - miter->addr; 285 data->bytes_xfered += miter->consumed; 286 sg_miter_stop(miter); 287 288 return true; 289} 290 291static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host, 292 struct mmc_data *data) 293{ 294 struct sg_mapping_iter *miter = &host->miter; 295 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO; 296 uint32_t *buf; 297 uint32_t d; 298 uint16_t status; 299 size_t i, j; 300 unsigned int timeout; 301 302 while (sg_miter_next(miter)) { 303 buf = miter->addr; 304 i = miter->length; 305 j = i / 32; 306 i = i & 0x1f; 307 while (j) { 308 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); 309 if (unlikely(timeout)) 310 goto poll_timeout; 311 312 buf[0] = readl(fifo_addr); 313 buf[1] = readl(fifo_addr); 314 buf[2] = readl(fifo_addr); 315 buf[3] = readl(fifo_addr); 316 buf[4] = readl(fifo_addr); 317 buf[5] = readl(fifo_addr); 318 buf[6] = readl(fifo_addr); 319 buf[7] = readl(fifo_addr); 320 321 buf += 8; 322 --j; 323 } 324 325 if (unlikely(i)) { 326 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); 327 if (unlikely(timeout)) 328 goto poll_timeout; 329 330 while (i >= 4) { 331 *buf++ = readl(fifo_addr); 332 i -= 4; 333 } 334 if (unlikely(i > 0)) { 335 d = readl(fifo_addr); 336 memcpy(buf, &d, i); 337 } 338 } 339 data->bytes_xfered += miter->length; 340 341 /* This can go away once MIPS implements 342 * flush_kernel_dcache_page */ 343 flush_dcache_page(miter->page); 344 } 345 sg_miter_stop(miter); 346 347 /* For whatever reason there is sometime one word more in the fifo then 348 * requested */ 349 timeout = 1000; 350 status = readl(host->base + JZ_REG_MMC_STATUS); 351 while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) { 352 d = readl(fifo_addr); 353 status = readl(host->base + JZ_REG_MMC_STATUS); 354 } 355 356 return false; 357 358poll_timeout: 359 miter->consumed = (void *)buf - miter->addr; 360 data->bytes_xfered += miter->consumed; 361 sg_miter_stop(miter); 362 363 return true; 364} 365 366static void jz4740_mmc_timeout(unsigned long data) 367{ 368 struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)data; 369 370 if (!test_and_clear_bit(0, &host->waiting)) 371 return; 372 373 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false); 374 375 host->req->cmd->error = -ETIMEDOUT; 376 jz4740_mmc_request_done(host); 377} 378 379static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, 380 struct mmc_command *cmd) 381{ 382 int i; 383 uint16_t tmp; 384 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO; 385 386 if (cmd->flags & MMC_RSP_136) { 387 tmp = readw(fifo_addr); 388 for (i = 0; i < 4; ++i) { 389 cmd->resp[i] = tmp << 24; 390 tmp = readw(fifo_addr); 391 cmd->resp[i] |= tmp << 8; 392 tmp = readw(fifo_addr); 393 cmd->resp[i] |= tmp >> 8; 394 } 395 } else { 396 cmd->resp[0] = readw(fifo_addr) << 24; 397 cmd->resp[0] |= readw(fifo_addr) << 8; 398 cmd->resp[0] |= readw(fifo_addr) & 0xff; 399 } 400} 401 402static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, 403 struct mmc_command *cmd) 404{ 405 uint32_t cmdat = host->cmdat; 406 407 host->cmdat &= ~JZ_MMC_CMDAT_INIT; 408 jz4740_mmc_clock_disable(host); 409 410 host->cmd = cmd; 411 412 if (cmd->flags & MMC_RSP_BUSY) 413 cmdat |= JZ_MMC_CMDAT_BUSY; 414 415 switch (mmc_resp_type(cmd)) { 416 case MMC_RSP_R1B: 417 case MMC_RSP_R1: 418 cmdat |= JZ_MMC_CMDAT_RSP_R1; 419 break; 420 case MMC_RSP_R2: 421 cmdat |= JZ_MMC_CMDAT_RSP_R2; 422 break; 423 case MMC_RSP_R3: 424 cmdat |= JZ_MMC_CMDAT_RSP_R3; 425 break; 426 default: 427 break; 428 } 429 430 if (cmd->data) { 431 cmdat |= JZ_MMC_CMDAT_DATA_EN; 432 if (cmd->data->flags & MMC_DATA_WRITE) 433 cmdat |= JZ_MMC_CMDAT_WRITE; 434 if (cmd->data->flags & MMC_DATA_STREAM) 435 cmdat |= JZ_MMC_CMDAT_STREAM; 436 437 writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN); 438 writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB); 439 } 440 441 writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD); 442 writel(cmd->arg, host->base + JZ_REG_MMC_ARG); 443 writel(cmdat, host->base + JZ_REG_MMC_CMDAT); 444 445 jz4740_mmc_clock_enable(host, 1); 446} 447 448static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host) 449{ 450 struct mmc_command *cmd = host->req->cmd; 451 struct mmc_data *data = cmd->data; 452 int direction; 453 454 if (data->flags & MMC_DATA_READ) 455 direction = SG_MITER_TO_SG; 456 else 457 direction = SG_MITER_FROM_SG; 458 459 sg_miter_start(&host->miter, data->sg, data->sg_len, direction); 460} 461 462 463static irqreturn_t jz_mmc_irq_worker(int irq, void *devid) 464{ 465 struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid; 466 struct mmc_command *cmd = host->req->cmd; 467 struct mmc_request *req = host->req; 468 bool timeout = false; 469 470 if (cmd->error) 471 host->state = JZ4740_MMC_STATE_DONE; 472 473 switch (host->state) { 474 case JZ4740_MMC_STATE_READ_RESPONSE: 475 if (cmd->flags & MMC_RSP_PRESENT) 476 jz4740_mmc_read_response(host, cmd); 477 478 if (!cmd->data) 479 break; 480 481 jz_mmc_prepare_data_transfer(host); 482 483 case JZ4740_MMC_STATE_TRANSFER_DATA: 484 if (cmd->data->flags & MMC_DATA_READ) 485 timeout = jz4740_mmc_read_data(host, cmd->data); 486 else 487 timeout = jz4740_mmc_write_data(host, cmd->data); 488 489 if (unlikely(timeout)) { 490 host->state = JZ4740_MMC_STATE_TRANSFER_DATA; 491 break; 492 } 493 494 jz4740_mmc_transfer_check_state(host, cmd->data); 495 496 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE); 497 if (unlikely(timeout)) { 498 host->state = JZ4740_MMC_STATE_SEND_STOP; 499 break; 500 } 501 writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG); 502 503 case JZ4740_MMC_STATE_SEND_STOP: 504 if (!req->stop) 505 break; 506 507 jz4740_mmc_send_command(host, req->stop); 508 509 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_PRG_DONE); 510 if (timeout) { 511 host->state = JZ4740_MMC_STATE_DONE; 512 break; 513 } 514 case JZ4740_MMC_STATE_DONE: 515 break; 516 } 517 518 if (!timeout) 519 jz4740_mmc_request_done(host); 520 521 return IRQ_HANDLED; 522} 523 524static irqreturn_t jz_mmc_irq(int irq, void *devid) 525{ 526 struct jz4740_mmc_host *host = devid; 527 struct mmc_command *cmd = host->cmd; 528 uint16_t irq_reg, status, tmp; 529 530 irq_reg = readw(host->base + JZ_REG_MMC_IREG); 531 532 tmp = irq_reg; 533 irq_reg &= ~host->irq_mask; 534 535 tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ | 536 JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE); 537 538 if (tmp != irq_reg) 539 writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG); 540 541 if (irq_reg & JZ_MMC_IRQ_SDIO) { 542 writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG); 543 mmc_signal_sdio_irq(host->mmc); 544 irq_reg &= ~JZ_MMC_IRQ_SDIO; 545 } 546 547 if (host->req && cmd && irq_reg) { 548 if (test_and_clear_bit(0, &host->waiting)) { 549 del_timer(&host->timeout_timer); 550 551 status = readl(host->base + JZ_REG_MMC_STATUS); 552 553 if (status & JZ_MMC_STATUS_TIMEOUT_RES) { 554 cmd->error = -ETIMEDOUT; 555 } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) { 556 cmd->error = -EIO; 557 } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR | 558 JZ_MMC_STATUS_CRC_WRITE_ERROR)) { 559 if (cmd->data) 560 cmd->data->error = -EIO; 561 cmd->error = -EIO; 562 } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR | 563 JZ_MMC_STATUS_CRC_WRITE_ERROR)) { 564 if (cmd->data) 565 cmd->data->error = -EIO; 566 cmd->error = -EIO; 567 } 568 569 jz4740_mmc_set_irq_enabled(host, irq_reg, false); 570 writew(irq_reg, host->base + JZ_REG_MMC_IREG); 571 572 return IRQ_WAKE_THREAD; 573 } 574 } 575 576 return IRQ_HANDLED; 577} 578 579static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) 580{ 581 int div = 0; 582 int real_rate; 583 584 jz4740_mmc_clock_disable(host); 585 clk_set_rate(host->clk, JZ_MMC_CLK_RATE); 586 587 real_rate = clk_get_rate(host->clk); 588 589 while (real_rate > rate && div < 7) { 590 ++div; 591 real_rate >>= 1; 592 } 593 594 writew(div, host->base + JZ_REG_MMC_CLKRT); 595 return real_rate; 596} 597 598static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req) 599{ 600 struct jz4740_mmc_host *host = mmc_priv(mmc); 601 602 host->req = req; 603 604 writew(0xffff, host->base + JZ_REG_MMC_IREG); 605 606 writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG); 607 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true); 608 609 host->state = JZ4740_MMC_STATE_READ_RESPONSE; 610 set_bit(0, &host->waiting); 611 mod_timer(&host->timeout_timer, jiffies + 5*HZ); 612 jz4740_mmc_send_command(host, req->cmd); 613} 614 615static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 616{ 617 struct jz4740_mmc_host *host = mmc_priv(mmc); 618 if (ios->clock) 619 jz4740_mmc_set_clock_rate(host, ios->clock); 620 621 switch (ios->power_mode) { 622 case MMC_POWER_UP: 623 jz4740_mmc_reset(host); 624 if (gpio_is_valid(host->pdata->gpio_power)) 625 gpio_set_value(host->pdata->gpio_power, 626 !host->pdata->power_active_low); 627 host->cmdat |= JZ_MMC_CMDAT_INIT; 628 clk_enable(host->clk); 629 break; 630 case MMC_POWER_ON: 631 break; 632 default: 633 if (gpio_is_valid(host->pdata->gpio_power)) 634 gpio_set_value(host->pdata->gpio_power, 635 host->pdata->power_active_low); 636 clk_disable(host->clk); 637 break; 638 } 639 640 switch (ios->bus_width) { 641 case MMC_BUS_WIDTH_1: 642 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT; 643 break; 644 case MMC_BUS_WIDTH_4: 645 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT; 646 break; 647 default: 648 break; 649 } 650} 651 652static int jz4740_mmc_get_ro(struct mmc_host *mmc) 653{ 654 struct jz4740_mmc_host *host = mmc_priv(mmc); 655 if (!gpio_is_valid(host->pdata->gpio_read_only)) 656 return -ENOSYS; 657 658 return gpio_get_value(host->pdata->gpio_read_only) ^ 659 host->pdata->read_only_active_low; 660} 661 662static int jz4740_mmc_get_cd(struct mmc_host *mmc) 663{ 664 struct jz4740_mmc_host *host = mmc_priv(mmc); 665 if (!gpio_is_valid(host->pdata->gpio_card_detect)) 666 return -ENOSYS; 667 668 return gpio_get_value(host->pdata->gpio_card_detect) ^ 669 host->pdata->card_detect_active_low; 670} 671 672static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid) 673{ 674 struct jz4740_mmc_host *host = devid; 675 676 mmc_detect_change(host->mmc, HZ / 2); 677 678 return IRQ_HANDLED; 679} 680 681static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 682{ 683 struct jz4740_mmc_host *host = mmc_priv(mmc); 684 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable); 685} 686 687static const struct mmc_host_ops jz4740_mmc_ops = { 688 .request = jz4740_mmc_request, 689 .set_ios = jz4740_mmc_set_ios, 690 .get_ro = jz4740_mmc_get_ro, 691 .get_cd = jz4740_mmc_get_cd, 692 .enable_sdio_irq = jz4740_mmc_enable_sdio_irq, 693}; 694 695static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = { 696 JZ_GPIO_BULK_PIN(MSC_CMD), 697 JZ_GPIO_BULK_PIN(MSC_CLK), 698 JZ_GPIO_BULK_PIN(MSC_DATA0), 699 JZ_GPIO_BULK_PIN(MSC_DATA1), 700 JZ_GPIO_BULK_PIN(MSC_DATA2), 701 JZ_GPIO_BULK_PIN(MSC_DATA3), 702}; 703 704static int __devinit jz4740_mmc_request_gpio(struct device *dev, int gpio, 705 const char *name, bool output, int value) 706{ 707 int ret; 708 709 if (!gpio_is_valid(gpio)) 710 return 0; 711 712 ret = gpio_request(gpio, name); 713 if (ret) { 714 dev_err(dev, "Failed to request %s gpio: %d\n", name, ret); 715 return ret; 716 } 717 718 if (output) 719 gpio_direction_output(gpio, value); 720 else 721 gpio_direction_input(gpio); 722 723 return 0; 724} 725 726static int __devinit jz4740_mmc_request_gpios(struct platform_device *pdev) 727{ 728 int ret; 729 struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; 730 731 if (!pdata) 732 return 0; 733 734 ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_card_detect, 735 "MMC detect change", false, 0); 736 if (ret) 737 goto err; 738 739 ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_read_only, 740 "MMC read only", false, 0); 741 if (ret) 742 goto err_free_gpio_card_detect; 743 744 ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power, 745 "MMC read only", true, pdata->power_active_low); 746 if (ret) 747 goto err_free_gpio_read_only; 748 749 return 0; 750 751err_free_gpio_read_only: 752 if (gpio_is_valid(pdata->gpio_read_only)) 753 gpio_free(pdata->gpio_read_only); 754err_free_gpio_card_detect: 755 if (gpio_is_valid(pdata->gpio_card_detect)) 756 gpio_free(pdata->gpio_card_detect); 757err: 758 return ret; 759} 760 761static int __devinit jz4740_mmc_request_cd_irq(struct platform_device *pdev, 762 struct jz4740_mmc_host *host) 763{ 764 struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; 765 766 if (!gpio_is_valid(pdata->gpio_card_detect)) 767 return 0; 768 769 host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect); 770 if (host->card_detect_irq < 0) { 771 dev_warn(&pdev->dev, "Failed to get card detect irq\n"); 772 return 0; 773 } 774 775 return request_irq(host->card_detect_irq, jz4740_mmc_card_detect_irq, 776 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 777 "MMC card detect", host); 778} 779 780static void jz4740_mmc_free_gpios(struct platform_device *pdev) 781{ 782 struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; 783 784 if (!pdata) 785 return; 786 787 if (gpio_is_valid(pdata->gpio_power)) 788 gpio_free(pdata->gpio_power); 789 if (gpio_is_valid(pdata->gpio_read_only)) 790 gpio_free(pdata->gpio_read_only); 791 if (gpio_is_valid(pdata->gpio_card_detect)) 792 gpio_free(pdata->gpio_card_detect); 793} 794 795static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host) 796{ 797 size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins); 798 if (host->pdata && host->pdata->data_1bit) 799 num_pins -= 3; 800 801 return num_pins; 802} 803 804static int __devinit jz4740_mmc_probe(struct platform_device* pdev) 805{ 806 int ret; 807 struct mmc_host *mmc; 808 struct jz4740_mmc_host *host; 809 struct jz4740_mmc_platform_data *pdata; 810 811 pdata = pdev->dev.platform_data; 812 813 mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev); 814 if (!mmc) { 815 dev_err(&pdev->dev, "Failed to alloc mmc host structure\n"); 816 return -ENOMEM; 817 } 818 819 host = mmc_priv(mmc); 820 host->pdata = pdata; 821 822 host->irq = platform_get_irq(pdev, 0); 823 if (host->irq < 0) { 824 ret = host->irq; 825 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); 826 goto err_free_host; 827 } 828 829 host->clk = clk_get(&pdev->dev, "mmc"); 830 if (!host->clk) { 831 ret = -ENOENT; 832 dev_err(&pdev->dev, "Failed to get mmc clock\n"); 833 goto err_free_host; 834 } 835 836 host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 837 if (!host->mem) { 838 ret = -ENOENT; 839 dev_err(&pdev->dev, "Failed to get base platform memory\n"); 840 goto err_clk_put; 841 } 842 843 host->mem = request_mem_region(host->mem->start, 844 resource_size(host->mem), pdev->name); 845 if (!host->mem) { 846 ret = -EBUSY; 847 dev_err(&pdev->dev, "Failed to request base memory region\n"); 848 goto err_clk_put; 849 } 850 851 host->base = ioremap_nocache(host->mem->start, resource_size(host->mem)); 852 if (!host->base) { 853 ret = -EBUSY; 854 dev_err(&pdev->dev, "Failed to ioremap base memory\n"); 855 goto err_release_mem_region; 856 } 857 858 ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); 859 if (ret) { 860 dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret); 861 goto err_iounmap; 862 } 863 864 ret = jz4740_mmc_request_gpios(pdev); 865 if (ret) 866 goto err_gpio_bulk_free; 867 868 mmc->ops = &jz4740_mmc_ops; 869 mmc->f_min = JZ_MMC_CLK_RATE / 128; 870 mmc->f_max = JZ_MMC_CLK_RATE; 871 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 872 mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA; 873 mmc->caps |= MMC_CAP_SDIO_IRQ; 874 875 mmc->max_blk_size = (1 << 10) - 1; 876 mmc->max_blk_count = (1 << 15) - 1; 877 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 878 879 mmc->max_phys_segs = 128; 880 mmc->max_hw_segs = 128; 881 mmc->max_seg_size = mmc->max_req_size; 882 883 host->mmc = mmc; 884 host->pdev = pdev; 885 spin_lock_init(&host->lock); 886 host->irq_mask = 0xffff; 887 888 ret = jz4740_mmc_request_cd_irq(pdev, host); 889 if (ret) { 890 dev_err(&pdev->dev, "Failed to request card detect irq\n"); 891 goto err_free_gpios; 892 } 893 894 ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0, 895 dev_name(&pdev->dev), host); 896 if (ret) { 897 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); 898 goto err_free_card_detect_irq; 899 } 900 901 jz4740_mmc_reset(host); 902 jz4740_mmc_clock_disable(host); 903 setup_timer(&host->timeout_timer, jz4740_mmc_timeout, 904 (unsigned long)host); 905 /* It is not important when it times out, it just needs to timeout. */ 906 set_timer_slack(&host->timeout_timer, HZ); 907 908 platform_set_drvdata(pdev, host); 909 ret = mmc_add_host(mmc); 910 911 if (ret) { 912 dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret); 913 goto err_free_irq; 914 } 915 dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n"); 916 917 return 0; 918 919err_free_irq: 920 free_irq(host->irq, host); 921err_free_card_detect_irq: 922 if (host->card_detect_irq >= 0) 923 free_irq(host->card_detect_irq, host); 924err_free_gpios: 925 jz4740_mmc_free_gpios(pdev); 926err_gpio_bulk_free: 927 jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); 928err_iounmap: 929 iounmap(host->base); 930err_release_mem_region: 931 release_mem_region(host->mem->start, resource_size(host->mem)); 932err_clk_put: 933 clk_put(host->clk); 934err_free_host: 935 platform_set_drvdata(pdev, NULL); 936 mmc_free_host(mmc); 937 938 return ret; 939} 940 941static int __devexit jz4740_mmc_remove(struct platform_device *pdev) 942{ 943 struct jz4740_mmc_host *host = platform_get_drvdata(pdev); 944 945 del_timer_sync(&host->timeout_timer); 946 jz4740_mmc_set_irq_enabled(host, 0xff, false); 947 jz4740_mmc_reset(host); 948 949 mmc_remove_host(host->mmc); 950 951 free_irq(host->irq, host); 952 if (host->card_detect_irq >= 0) 953 free_irq(host->card_detect_irq, host); 954 955 jz4740_mmc_free_gpios(pdev); 956 jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); 957 958 iounmap(host->base); 959 release_mem_region(host->mem->start, resource_size(host->mem)); 960 961 clk_put(host->clk); 962 963 platform_set_drvdata(pdev, NULL); 964 mmc_free_host(host->mmc); 965 966 return 0; 967} 968 969#ifdef CONFIG_PM 970 971static int jz4740_mmc_suspend(struct device *dev) 972{ 973 struct jz4740_mmc_host *host = dev_get_drvdata(dev); 974 975 mmc_suspend_host(host->mmc); 976 977 jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); 978 979 return 0; 980} 981 982static int jz4740_mmc_resume(struct device *dev) 983{ 984 struct jz4740_mmc_host *host = dev_get_drvdata(dev); 985 986 jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); 987 988 mmc_resume_host(host->mmc); 989 990 return 0; 991} 992 993const struct dev_pm_ops jz4740_mmc_pm_ops = { 994 .suspend = jz4740_mmc_suspend, 995 .resume = jz4740_mmc_resume, 996 .poweroff = jz4740_mmc_suspend, 997 .restore = jz4740_mmc_resume, 998}; 999 1000#define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops) 1001#else 1002#define JZ4740_MMC_PM_OPS NULL 1003#endif 1004 1005static struct platform_driver jz4740_mmc_driver = { 1006 .probe = jz4740_mmc_probe, 1007 .remove = __devexit_p(jz4740_mmc_remove), 1008 .driver = { 1009 .name = "jz4740-mmc", 1010 .owner = THIS_MODULE, 1011 .pm = JZ4740_MMC_PM_OPS, 1012 }, 1013}; 1014 1015static int __init jz4740_mmc_init(void) 1016{ 1017 return platform_driver_register(&jz4740_mmc_driver); 1018} 1019module_init(jz4740_mmc_init); 1020 1021static void __exit jz4740_mmc_exit(void) 1022{ 1023 platform_driver_unregister(&jz4740_mmc_driver); 1024} 1025module_exit(jz4740_mmc_exit); 1026 1027MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver"); 1028MODULE_LICENSE("GPL"); 1029MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1030