1/* 2 * A V4L2 driver for OmniVision OV7670 cameras. 3 * 4 * Copyright 2006 One Laptop Per Child Association, Inc. Written 5 * by Jonathan Corbet with substantial inspiration from Mark 6 * McClelland's ovcamchip code. 7 * 8 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> 9 * 10 * This file may be distributed under the terms of the GNU General 11 * Public License, version 2. 12 */ 13#include <linux/init.h> 14#include <linux/module.h> 15#include <linux/slab.h> 16#include <linux/i2c.h> 17#include <linux/delay.h> 18#include <linux/videodev2.h> 19#include <media/v4l2-device.h> 20#include <media/v4l2-chip-ident.h> 21#include <media/v4l2-i2c-drv.h> 22 23 24MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>"); 25MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors"); 26MODULE_LICENSE("GPL"); 27 28static int debug; 29module_param(debug, bool, 0644); 30MODULE_PARM_DESC(debug, "Debug level (0-1)"); 31 32/* 33 * Basic window sizes. These probably belong somewhere more globally 34 * useful. 35 */ 36#define VGA_WIDTH 640 37#define VGA_HEIGHT 480 38#define QVGA_WIDTH 320 39#define QVGA_HEIGHT 240 40#define CIF_WIDTH 352 41#define CIF_HEIGHT 288 42#define QCIF_WIDTH 176 43#define QCIF_HEIGHT 144 44 45/* 46 * Our nominal (default) frame rate. 47 */ 48#define OV7670_FRAME_RATE 30 49 50/* 51 * The 7670 sits on i2c with ID 0x42 52 */ 53#define OV7670_I2C_ADDR 0x42 54 55/* Registers */ 56#define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ 57#define REG_BLUE 0x01 /* blue gain */ 58#define REG_RED 0x02 /* red gain */ 59#define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ 60#define REG_COM1 0x04 /* Control 1 */ 61#define COM1_CCIR656 0x40 /* CCIR656 enable */ 62#define REG_BAVE 0x05 /* U/B Average level */ 63#define REG_GbAVE 0x06 /* Y/Gb Average level */ 64#define REG_AECHH 0x07 /* AEC MS 5 bits */ 65#define REG_RAVE 0x08 /* V/R Average level */ 66#define REG_COM2 0x09 /* Control 2 */ 67#define COM2_SSLEEP 0x10 /* Soft sleep mode */ 68#define REG_PID 0x0a /* Product ID MSB */ 69#define REG_VER 0x0b /* Product ID LSB */ 70#define REG_COM3 0x0c /* Control 3 */ 71#define COM3_SWAP 0x40 /* Byte swap */ 72#define COM3_SCALEEN 0x08 /* Enable scaling */ 73#define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ 74#define REG_COM4 0x0d /* Control 4 */ 75#define REG_COM5 0x0e /* All "reserved" */ 76#define REG_COM6 0x0f /* Control 6 */ 77#define REG_AECH 0x10 /* More bits of AEC value */ 78#define REG_CLKRC 0x11 /* Clocl control */ 79#define CLK_EXT 0x40 /* Use external clock directly */ 80#define CLK_SCALE 0x3f /* Mask for internal clock scale */ 81#define REG_COM7 0x12 /* Control 7 */ 82#define COM7_RESET 0x80 /* Register reset */ 83#define COM7_FMT_MASK 0x38 84#define COM7_FMT_VGA 0x00 85#define COM7_FMT_CIF 0x20 /* CIF format */ 86#define COM7_FMT_QVGA 0x10 /* QVGA format */ 87#define COM7_FMT_QCIF 0x08 /* QCIF format */ 88#define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ 89#define COM7_YUV 0x00 /* YUV */ 90#define COM7_BAYER 0x01 /* Bayer format */ 91#define COM7_PBAYER 0x05 /* "Processed bayer" */ 92#define REG_COM8 0x13 /* Control 8 */ 93#define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ 94#define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ 95#define COM8_BFILT 0x20 /* Band filter enable */ 96#define COM8_AGC 0x04 /* Auto gain enable */ 97#define COM8_AWB 0x02 /* White balance enable */ 98#define COM8_AEC 0x01 /* Auto exposure enable */ 99#define REG_COM9 0x14 /* Control 9 - gain ceiling */ 100#define REG_COM10 0x15 /* Control 10 */ 101#define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ 102#define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ 103#define COM10_HREF_REV 0x08 /* Reverse HREF */ 104#define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ 105#define COM10_VS_NEG 0x02 /* VSYNC negative */ 106#define COM10_HS_NEG 0x01 /* HSYNC negative */ 107#define REG_HSTART 0x17 /* Horiz start high bits */ 108#define REG_HSTOP 0x18 /* Horiz stop high bits */ 109#define REG_VSTART 0x19 /* Vert start high bits */ 110#define REG_VSTOP 0x1a /* Vert stop high bits */ 111#define REG_PSHFT 0x1b /* Pixel delay after HREF */ 112#define REG_MIDH 0x1c /* Manuf. ID high */ 113#define REG_MIDL 0x1d /* Manuf. ID low */ 114#define REG_MVFP 0x1e /* Mirror / vflip */ 115#define MVFP_MIRROR 0x20 /* Mirror image */ 116#define MVFP_FLIP 0x10 /* Vertical flip */ 117 118#define REG_AEW 0x24 /* AGC upper limit */ 119#define REG_AEB 0x25 /* AGC lower limit */ 120#define REG_VPT 0x26 /* AGC/AEC fast mode op region */ 121#define REG_HSYST 0x30 /* HSYNC rising edge delay */ 122#define REG_HSYEN 0x31 /* HSYNC falling edge delay */ 123#define REG_HREF 0x32 /* HREF pieces */ 124#define REG_TSLB 0x3a /* lots of stuff */ 125#define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ 126#define REG_COM11 0x3b /* Control 11 */ 127#define COM11_NIGHT 0x80 /* NIght mode enable */ 128#define COM11_NMFR 0x60 /* Two bit NM frame rate */ 129#define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ 130#define COM11_50HZ 0x08 /* Manual 50Hz select */ 131#define COM11_EXP 0x02 132#define REG_COM12 0x3c /* Control 12 */ 133#define COM12_HREF 0x80 /* HREF always */ 134#define REG_COM13 0x3d /* Control 13 */ 135#define COM13_GAMMA 0x80 /* Gamma enable */ 136#define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ 137#define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ 138#define REG_COM14 0x3e /* Control 14 */ 139#define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ 140#define REG_EDGE 0x3f /* Edge enhancement factor */ 141#define REG_COM15 0x40 /* Control 15 */ 142#define COM15_R10F0 0x00 /* Data range 10 to F0 */ 143#define COM15_R01FE 0x80 /* 01 to FE */ 144#define COM15_R00FF 0xc0 /* 00 to FF */ 145#define COM15_RGB565 0x10 /* RGB565 output */ 146#define COM15_RGB555 0x30 /* RGB555 output */ 147#define REG_COM16 0x41 /* Control 16 */ 148#define COM16_AWBGAIN 0x08 /* AWB gain enable */ 149#define REG_COM17 0x42 /* Control 17 */ 150#define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ 151#define COM17_CBAR 0x08 /* DSP Color bar */ 152 153/* 154 * This matrix defines how the colors are generated, must be 155 * tweaked to adjust hue and saturation. 156 * 157 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue 158 * 159 * They are nine-bit signed quantities, with the sign bit 160 * stored in 0x58. Sign for v-red is bit 0, and up from there. 161 */ 162#define REG_CMATRIX_BASE 0x4f 163#define CMATRIX_LEN 6 164#define REG_CMATRIX_SIGN 0x58 165 166 167#define REG_BRIGHT 0x55 /* Brightness */ 168#define REG_CONTRAS 0x56 /* Contrast control */ 169 170#define REG_GFIX 0x69 /* Fix gain control */ 171 172#define REG_REG76 0x76 /* OV's name */ 173#define R76_BLKPCOR 0x80 /* Black pixel correction enable */ 174#define R76_WHTPCOR 0x40 /* White pixel correction enable */ 175 176#define REG_RGB444 0x8c /* RGB 444 control */ 177#define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ 178#define R444_RGBX 0x01 /* Empty nibble at end */ 179 180#define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ 181#define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ 182 183#define REG_BD50MAX 0xa5 /* 50hz banding step limit */ 184#define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ 185#define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ 186#define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ 187#define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ 188#define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ 189#define REG_BD60MAX 0xab /* 60hz banding step limit */ 190 191 192/* 193 * Information we maintain about a known sensor. 194 */ 195struct ov7670_format_struct; /* coming later */ 196struct ov7670_info { 197 struct v4l2_subdev sd; 198 struct ov7670_format_struct *fmt; /* Current format */ 199 unsigned char sat; /* Saturation value */ 200 int hue; /* Hue value */ 201 u8 clkrc; /* Clock divider value */ 202}; 203 204static inline struct ov7670_info *to_state(struct v4l2_subdev *sd) 205{ 206 return container_of(sd, struct ov7670_info, sd); 207} 208 209 210 211/* 212 * The default register settings, as obtained from OmniVision. There 213 * is really no making sense of most of these - lots of "reserved" values 214 * and such. 215 * 216 * These settings give VGA YUYV. 217 */ 218 219struct regval_list { 220 unsigned char reg_num; 221 unsigned char value; 222}; 223 224static struct regval_list ov7670_default_regs[] = { 225 { REG_COM7, COM7_RESET }, 226/* 227 * Clock scale: 3 = 15fps 228 * 2 = 20fps 229 * 1 = 30fps 230 */ 231 { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */ 232 { REG_TSLB, 0x04 }, /* OV */ 233 { REG_COM7, 0 }, /* VGA */ 234 /* 235 * Set the hardware window. These values from OV don't entirely 236 * make sense - hstop is less than hstart. But they work... 237 */ 238 { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 }, 239 { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 }, 240 { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a }, 241 242 { REG_COM3, 0 }, { REG_COM14, 0 }, 243 /* Mystery scaling numbers */ 244 { 0x70, 0x3a }, { 0x71, 0x35 }, 245 { 0x72, 0x11 }, { 0x73, 0xf0 }, 246 { 0xa2, 0x02 }, { REG_COM10, 0x0 }, 247 248 /* Gamma curve values */ 249 { 0x7a, 0x20 }, { 0x7b, 0x10 }, 250 { 0x7c, 0x1e }, { 0x7d, 0x35 }, 251 { 0x7e, 0x5a }, { 0x7f, 0x69 }, 252 { 0x80, 0x76 }, { 0x81, 0x80 }, 253 { 0x82, 0x88 }, { 0x83, 0x8f }, 254 { 0x84, 0x96 }, { 0x85, 0xa3 }, 255 { 0x86, 0xaf }, { 0x87, 0xc4 }, 256 { 0x88, 0xd7 }, { 0x89, 0xe8 }, 257 258 /* AGC and AEC parameters. Note we start by disabling those features, 259 then turn them only after tweaking the values. */ 260 { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT }, 261 { REG_GAIN, 0 }, { REG_AECH, 0 }, 262 { REG_COM4, 0x40 }, /* magic reserved bit */ 263 { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */ 264 { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 }, 265 { REG_AEW, 0x95 }, { REG_AEB, 0x33 }, 266 { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 }, 267 { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */ 268 { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 }, 269 { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 }, 270 { REG_HAECC7, 0x94 }, 271 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC }, 272 273 /* Almost all of these are magic "reserved" values. */ 274 { REG_COM5, 0x61 }, { REG_COM6, 0x4b }, 275 { 0x16, 0x02 }, { REG_MVFP, 0x07 }, 276 { 0x21, 0x02 }, { 0x22, 0x91 }, 277 { 0x29, 0x07 }, { 0x33, 0x0b }, 278 { 0x35, 0x0b }, { 0x37, 0x1d }, 279 { 0x38, 0x71 }, { 0x39, 0x2a }, 280 { REG_COM12, 0x78 }, { 0x4d, 0x40 }, 281 { 0x4e, 0x20 }, { REG_GFIX, 0 }, 282 { 0x6b, 0x4a }, { 0x74, 0x10 }, 283 { 0x8d, 0x4f }, { 0x8e, 0 }, 284 { 0x8f, 0 }, { 0x90, 0 }, 285 { 0x91, 0 }, { 0x96, 0 }, 286 { 0x9a, 0 }, { 0xb0, 0x84 }, 287 { 0xb1, 0x0c }, { 0xb2, 0x0e }, 288 { 0xb3, 0x82 }, { 0xb8, 0x0a }, 289 290 /* More reserved magic, some of which tweaks white balance */ 291 { 0x43, 0x0a }, { 0x44, 0xf0 }, 292 { 0x45, 0x34 }, { 0x46, 0x58 }, 293 { 0x47, 0x28 }, { 0x48, 0x3a }, 294 { 0x59, 0x88 }, { 0x5a, 0x88 }, 295 { 0x5b, 0x44 }, { 0x5c, 0x67 }, 296 { 0x5d, 0x49 }, { 0x5e, 0x0e }, 297 { 0x6c, 0x0a }, { 0x6d, 0x55 }, 298 { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */ 299 { 0x6a, 0x40 }, { REG_BLUE, 0x40 }, 300 { REG_RED, 0x60 }, 301 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB }, 302 303 /* Matrix coefficients */ 304 { 0x4f, 0x80 }, { 0x50, 0x80 }, 305 { 0x51, 0 }, { 0x52, 0x22 }, 306 { 0x53, 0x5e }, { 0x54, 0x80 }, 307 { 0x58, 0x9e }, 308 309 { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 }, 310 { 0x75, 0x05 }, { 0x76, 0xe1 }, 311 { 0x4c, 0 }, { 0x77, 0x01 }, 312 { REG_COM13, 0xc3 }, { 0x4b, 0x09 }, 313 { 0xc9, 0x60 }, { REG_COM16, 0x38 }, 314 { 0x56, 0x40 }, 315 316 { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO }, 317 { 0xa4, 0x88 }, { 0x96, 0 }, 318 { 0x97, 0x30 }, { 0x98, 0x20 }, 319 { 0x99, 0x30 }, { 0x9a, 0x84 }, 320 { 0x9b, 0x29 }, { 0x9c, 0x03 }, 321 { 0x9d, 0x4c }, { 0x9e, 0x3f }, 322 { 0x78, 0x04 }, 323 324 /* Extra-weird stuff. Some sort of multiplexor register */ 325 { 0x79, 0x01 }, { 0xc8, 0xf0 }, 326 { 0x79, 0x0f }, { 0xc8, 0x00 }, 327 { 0x79, 0x10 }, { 0xc8, 0x7e }, 328 { 0x79, 0x0a }, { 0xc8, 0x80 }, 329 { 0x79, 0x0b }, { 0xc8, 0x01 }, 330 { 0x79, 0x0c }, { 0xc8, 0x0f }, 331 { 0x79, 0x0d }, { 0xc8, 0x20 }, 332 { 0x79, 0x09 }, { 0xc8, 0x80 }, 333 { 0x79, 0x02 }, { 0xc8, 0xc0 }, 334 { 0x79, 0x03 }, { 0xc8, 0x40 }, 335 { 0x79, 0x05 }, { 0xc8, 0x30 }, 336 { 0x79, 0x26 }, 337 338 { 0xff, 0xff }, /* END MARKER */ 339}; 340 341 342/* 343 * Here we'll try to encapsulate the changes for just the output 344 * video format. 345 * 346 * RGB656 and YUV422 come from OV; RGB444 is homebrewed. 347 * 348 * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why. 349 */ 350 351 352static struct regval_list ov7670_fmt_yuv422[] = { 353 { REG_COM7, 0x0 }, /* Selects YUV mode */ 354 { REG_RGB444, 0 }, /* No RGB444 please */ 355 { REG_COM1, 0 }, /* CCIR601 */ 356 { REG_COM15, COM15_R00FF }, 357 { REG_COM9, 0x18 }, /* 4x gain ceiling; 0x8 is reserved bit */ 358 { 0x4f, 0x80 }, /* "matrix coefficient 1" */ 359 { 0x50, 0x80 }, /* "matrix coefficient 2" */ 360 { 0x51, 0 }, /* vb */ 361 { 0x52, 0x22 }, /* "matrix coefficient 4" */ 362 { 0x53, 0x5e }, /* "matrix coefficient 5" */ 363 { 0x54, 0x80 }, /* "matrix coefficient 6" */ 364 { REG_COM13, COM13_GAMMA|COM13_UVSAT }, 365 { 0xff, 0xff }, 366}; 367 368static struct regval_list ov7670_fmt_rgb565[] = { 369 { REG_COM7, COM7_RGB }, /* Selects RGB mode */ 370 { REG_RGB444, 0 }, /* No RGB444 please */ 371 { REG_COM1, 0x0 }, /* CCIR601 */ 372 { REG_COM15, COM15_RGB565 }, 373 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ 374 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 375 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 376 { 0x51, 0 }, /* vb */ 377 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 378 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 379 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 380 { REG_COM13, COM13_GAMMA|COM13_UVSAT }, 381 { 0xff, 0xff }, 382}; 383 384static struct regval_list ov7670_fmt_rgb444[] = { 385 { REG_COM7, COM7_RGB }, /* Selects RGB mode */ 386 { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */ 387 { REG_COM1, 0x0 }, /* CCIR601 */ 388 { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */ 389 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ 390 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 391 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 392 { 0x51, 0 }, /* vb */ 393 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 394 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 395 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 396 { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */ 397 { 0xff, 0xff }, 398}; 399 400static struct regval_list ov7670_fmt_raw[] = { 401 { REG_COM7, COM7_BAYER }, 402 { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */ 403 { REG_COM16, 0x3d }, /* Edge enhancement, denoise */ 404 { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */ 405 { 0xff, 0xff }, 406}; 407 408 409 410/* 411 * Low-level register I/O. 412 * 413 * Note that there are two versions of these. On the XO 1, the 414 * i2c controller only does SMBUS, so that's what we use. The 415 * ov7670 is not really an SMBUS device, though, so the communication 416 * is not always entirely reliable. 417 */ 418#ifdef CONFIG_OLPC_XO_1 419static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg, 420 unsigned char *value) 421{ 422 struct i2c_client *client = v4l2_get_subdevdata(sd); 423 int ret; 424 425 ret = i2c_smbus_read_byte_data(client, reg); 426 if (ret >= 0) { 427 *value = (unsigned char)ret; 428 ret = 0; 429 } 430 return ret; 431} 432 433 434static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg, 435 unsigned char value) 436{ 437 struct i2c_client *client = v4l2_get_subdevdata(sd); 438 int ret = i2c_smbus_write_byte_data(client, reg, value); 439 440 if (reg == REG_COM7 && (value & COM7_RESET)) 441 msleep(5); /* Wait for reset to run */ 442 return ret; 443} 444 445#else /* ! CONFIG_OLPC_XO_1 */ 446/* 447 * On most platforms, we'd rather do straight i2c I/O. 448 */ 449static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg, 450 unsigned char *value) 451{ 452 struct i2c_client *client = v4l2_get_subdevdata(sd); 453 u8 data = reg; 454 struct i2c_msg msg; 455 int ret; 456 457 /* 458 * Send out the register address... 459 */ 460 msg.addr = client->addr; 461 msg.flags = 0; 462 msg.len = 1; 463 msg.buf = &data; 464 ret = i2c_transfer(client->adapter, &msg, 1); 465 if (ret < 0) { 466 printk(KERN_ERR "Error %d on register write\n", ret); 467 return ret; 468 } 469 /* 470 * ...then read back the result. 471 */ 472 msg.flags = I2C_M_RD; 473 ret = i2c_transfer(client->adapter, &msg, 1); 474 if (ret >= 0) { 475 *value = data; 476 ret = 0; 477 } 478 return ret; 479} 480 481 482static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg, 483 unsigned char value) 484{ 485 struct i2c_client *client = v4l2_get_subdevdata(sd); 486 struct i2c_msg msg; 487 unsigned char data[2] = { reg, value }; 488 int ret; 489 490 msg.addr = client->addr; 491 msg.flags = 0; 492 msg.len = 2; 493 msg.buf = data; 494 ret = i2c_transfer(client->adapter, &msg, 1); 495 if (ret > 0) 496 ret = 0; 497 if (reg == REG_COM7 && (value & COM7_RESET)) 498 msleep(5); /* Wait for reset to run */ 499 return ret; 500} 501#endif /* CONFIG_OLPC_XO_1 */ 502 503 504/* 505 * Write a list of register settings; ff/ff stops the process. 506 */ 507static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals) 508{ 509 while (vals->reg_num != 0xff || vals->value != 0xff) { 510 int ret = ov7670_write(sd, vals->reg_num, vals->value); 511 if (ret < 0) 512 return ret; 513 vals++; 514 } 515 return 0; 516} 517 518 519/* 520 * Stuff that knows about the sensor. 521 */ 522static int ov7670_reset(struct v4l2_subdev *sd, u32 val) 523{ 524 ov7670_write(sd, REG_COM7, COM7_RESET); 525 msleep(1); 526 return 0; 527} 528 529 530static int ov7670_init(struct v4l2_subdev *sd, u32 val) 531{ 532 return ov7670_write_array(sd, ov7670_default_regs); 533} 534 535 536 537static int ov7670_detect(struct v4l2_subdev *sd) 538{ 539 unsigned char v; 540 int ret; 541 542 ret = ov7670_init(sd, 0); 543 if (ret < 0) 544 return ret; 545 ret = ov7670_read(sd, REG_MIDH, &v); 546 if (ret < 0) 547 return ret; 548 if (v != 0x7f) /* OV manuf. id. */ 549 return -ENODEV; 550 ret = ov7670_read(sd, REG_MIDL, &v); 551 if (ret < 0) 552 return ret; 553 if (v != 0xa2) 554 return -ENODEV; 555 /* 556 * OK, we know we have an OmniVision chip...but which one? 557 */ 558 ret = ov7670_read(sd, REG_PID, &v); 559 if (ret < 0) 560 return ret; 561 if (v != 0x76) /* PID + VER = 0x76 / 0x73 */ 562 return -ENODEV; 563 ret = ov7670_read(sd, REG_VER, &v); 564 if (ret < 0) 565 return ret; 566 if (v != 0x73) /* PID + VER = 0x76 / 0x73 */ 567 return -ENODEV; 568 return 0; 569} 570 571 572/* 573 * Store information about the video data format. The color matrix 574 * is deeply tied into the format, so keep the relevant values here. 575 * The magic matrix nubmers come from OmniVision. 576 */ 577static struct ov7670_format_struct { 578 __u8 *desc; 579 __u32 pixelformat; 580 struct regval_list *regs; 581 int cmatrix[CMATRIX_LEN]; 582 int bpp; /* Bytes per pixel */ 583} ov7670_formats[] = { 584 { 585 .desc = "YUYV 4:2:2", 586 .pixelformat = V4L2_PIX_FMT_YUYV, 587 .regs = ov7670_fmt_yuv422, 588 .cmatrix = { 128, -128, 0, -34, -94, 128 }, 589 .bpp = 2, 590 }, 591 { 592 .desc = "RGB 444", 593 .pixelformat = V4L2_PIX_FMT_RGB444, 594 .regs = ov7670_fmt_rgb444, 595 .cmatrix = { 179, -179, 0, -61, -176, 228 }, 596 .bpp = 2, 597 }, 598 { 599 .desc = "RGB 565", 600 .pixelformat = V4L2_PIX_FMT_RGB565, 601 .regs = ov7670_fmt_rgb565, 602 .cmatrix = { 179, -179, 0, -61, -176, 228 }, 603 .bpp = 2, 604 }, 605 { 606 .desc = "Raw RGB Bayer", 607 .pixelformat = V4L2_PIX_FMT_SBGGR8, 608 .regs = ov7670_fmt_raw, 609 .cmatrix = { 0, 0, 0, 0, 0, 0 }, 610 .bpp = 1 611 }, 612}; 613#define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats) 614 615 616/* 617 * Then there is the issue of window sizes. Try to capture the info here. 618 */ 619 620/* 621 * QCIF mode is done (by OV) in a very strange way - it actually looks like 622 * VGA with weird scaling options - they do *not* use the canned QCIF mode 623 * which is allegedly provided by the sensor. So here's the weird register 624 * settings. 625 */ 626static struct regval_list ov7670_qcif_regs[] = { 627 { REG_COM3, COM3_SCALEEN|COM3_DCWEN }, 628 { REG_COM3, COM3_DCWEN }, 629 { REG_COM14, COM14_DCWEN | 0x01}, 630 { 0x73, 0xf1 }, 631 { 0xa2, 0x52 }, 632 { 0x7b, 0x1c }, 633 { 0x7c, 0x28 }, 634 { 0x7d, 0x3c }, 635 { 0x7f, 0x69 }, 636 { REG_COM9, 0x38 }, 637 { 0xa1, 0x0b }, 638 { 0x74, 0x19 }, 639 { 0x9a, 0x80 }, 640 { 0x43, 0x14 }, 641 { REG_COM13, 0xc0 }, 642 { 0xff, 0xff }, 643}; 644 645static struct ov7670_win_size { 646 int width; 647 int height; 648 unsigned char com7_bit; 649 int hstart; /* Start/stop values for the camera. Note */ 650 int hstop; /* that they do not always make complete */ 651 int vstart; /* sense to humans, but evidently the sensor */ 652 int vstop; /* will do the right thing... */ 653 struct regval_list *regs; /* Regs to tweak */ 654/* h/vref stuff */ 655} ov7670_win_sizes[] = { 656 /* VGA */ 657 { 658 .width = VGA_WIDTH, 659 .height = VGA_HEIGHT, 660 .com7_bit = COM7_FMT_VGA, 661 .hstart = 158, /* These values from */ 662 .hstop = 14, /* Omnivision */ 663 .vstart = 10, 664 .vstop = 490, 665 .regs = NULL, 666 }, 667 /* CIF */ 668 { 669 .width = CIF_WIDTH, 670 .height = CIF_HEIGHT, 671 .com7_bit = COM7_FMT_CIF, 672 .hstart = 170, /* Empirically determined */ 673 .hstop = 90, 674 .vstart = 14, 675 .vstop = 494, 676 .regs = NULL, 677 }, 678 /* QVGA */ 679 { 680 .width = QVGA_WIDTH, 681 .height = QVGA_HEIGHT, 682 .com7_bit = COM7_FMT_QVGA, 683 .hstart = 164, /* Empirically determined */ 684 .hstop = 20, 685 .vstart = 14, 686 .vstop = 494, 687 .regs = NULL, 688 }, 689 /* QCIF */ 690 { 691 .width = QCIF_WIDTH, 692 .height = QCIF_HEIGHT, 693 .com7_bit = COM7_FMT_VGA, /* see comment above */ 694 .hstart = 456, /* Empirically determined */ 695 .hstop = 24, 696 .vstart = 14, 697 .vstop = 494, 698 .regs = ov7670_qcif_regs, 699 }, 700}; 701 702#define N_WIN_SIZES (ARRAY_SIZE(ov7670_win_sizes)) 703 704 705/* 706 * Store a set of start/stop values into the camera. 707 */ 708static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop, 709 int vstart, int vstop) 710{ 711 int ret; 712 unsigned char v; 713/* 714 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of 715 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is 716 * a mystery "edge offset" value in the top two bits of href. 717 */ 718 ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff); 719 ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff); 720 ret += ov7670_read(sd, REG_HREF, &v); 721 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7); 722 msleep(10); 723 ret += ov7670_write(sd, REG_HREF, v); 724/* 725 * Vertical: similar arrangement, but only 10 bits. 726 */ 727 ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff); 728 ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff); 729 ret += ov7670_read(sd, REG_VREF, &v); 730 v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3); 731 msleep(10); 732 ret += ov7670_write(sd, REG_VREF, v); 733 return ret; 734} 735 736 737static int ov7670_enum_fmt(struct v4l2_subdev *sd, struct v4l2_fmtdesc *fmt) 738{ 739 struct ov7670_format_struct *ofmt; 740 741 if (fmt->index >= N_OV7670_FMTS) 742 return -EINVAL; 743 744 ofmt = ov7670_formats + fmt->index; 745 fmt->flags = 0; 746 strcpy(fmt->description, ofmt->desc); 747 fmt->pixelformat = ofmt->pixelformat; 748 return 0; 749} 750 751 752static int ov7670_try_fmt_internal(struct v4l2_subdev *sd, 753 struct v4l2_format *fmt, 754 struct ov7670_format_struct **ret_fmt, 755 struct ov7670_win_size **ret_wsize) 756{ 757 int index; 758 struct ov7670_win_size *wsize; 759 struct v4l2_pix_format *pix = &fmt->fmt.pix; 760 761 for (index = 0; index < N_OV7670_FMTS; index++) 762 if (ov7670_formats[index].pixelformat == pix->pixelformat) 763 break; 764 if (index >= N_OV7670_FMTS) { 765 /* default to first format */ 766 index = 0; 767 pix->pixelformat = ov7670_formats[0].pixelformat; 768 } 769 if (ret_fmt != NULL) 770 *ret_fmt = ov7670_formats + index; 771 /* 772 * Fields: the OV devices claim to be progressive. 773 */ 774 pix->field = V4L2_FIELD_NONE; 775 /* 776 * Round requested image size down to the nearest 777 * we support, but not below the smallest. 778 */ 779 for (wsize = ov7670_win_sizes; wsize < ov7670_win_sizes + N_WIN_SIZES; 780 wsize++) 781 if (pix->width >= wsize->width && pix->height >= wsize->height) 782 break; 783 if (wsize >= ov7670_win_sizes + N_WIN_SIZES) 784 wsize--; /* Take the smallest one */ 785 if (ret_wsize != NULL) 786 *ret_wsize = wsize; 787 /* 788 * Note the size we'll actually handle. 789 */ 790 pix->width = wsize->width; 791 pix->height = wsize->height; 792 pix->bytesperline = pix->width*ov7670_formats[index].bpp; 793 pix->sizeimage = pix->height*pix->bytesperline; 794 return 0; 795} 796 797static int ov7670_try_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt) 798{ 799 return ov7670_try_fmt_internal(sd, fmt, NULL, NULL); 800} 801 802/* 803 * Set a format. 804 */ 805static int ov7670_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt) 806{ 807 int ret; 808 struct ov7670_format_struct *ovfmt; 809 struct ov7670_win_size *wsize; 810 struct ov7670_info *info = to_state(sd); 811 unsigned char com7; 812 813 ret = ov7670_try_fmt_internal(sd, fmt, &ovfmt, &wsize); 814 if (ret) 815 return ret; 816 /* 817 * COM7 is a pain in the ass, it doesn't like to be read then 818 * quickly written afterward. But we have everything we need 819 * to set it absolutely here, as long as the format-specific 820 * register sets list it first. 821 */ 822 com7 = ovfmt->regs[0].value; 823 com7 |= wsize->com7_bit; 824 ov7670_write(sd, REG_COM7, com7); 825 /* 826 * Now write the rest of the array. Also store start/stops 827 */ 828 ov7670_write_array(sd, ovfmt->regs + 1); 829 ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart, 830 wsize->vstop); 831 ret = 0; 832 if (wsize->regs) 833 ret = ov7670_write_array(sd, wsize->regs); 834 info->fmt = ovfmt; 835 836 /* 837 * If we're running RGB565, we must rewrite clkrc after setting 838 * the other parameters or the image looks poor. If we're *not* 839 * doing RGB565, we must not rewrite clkrc or the image looks 840 * *really* poor. 841 * 842 * (Update) Now that we retain clkrc state, we should be able 843 * to write it unconditionally, and that will make the frame 844 * rate persistent too. 845 */ 846 if (ret == 0) 847 ret = ov7670_write(sd, REG_CLKRC, info->clkrc); 848 return ret; 849} 850 851/* 852 * Implement G/S_PARM. There is a "high quality" mode we could try 853 * to do someday; for now, we just do the frame rate tweak. 854 */ 855static int ov7670_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) 856{ 857 struct v4l2_captureparm *cp = &parms->parm.capture; 858 struct ov7670_info *info = to_state(sd); 859 860 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 861 return -EINVAL; 862 863 memset(cp, 0, sizeof(struct v4l2_captureparm)); 864 cp->capability = V4L2_CAP_TIMEPERFRAME; 865 cp->timeperframe.numerator = 1; 866 cp->timeperframe.denominator = OV7670_FRAME_RATE; 867 if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1) 868 cp->timeperframe.denominator /= (info->clkrc & CLK_SCALE); 869 return 0; 870} 871 872static int ov7670_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) 873{ 874 struct v4l2_captureparm *cp = &parms->parm.capture; 875 struct v4l2_fract *tpf = &cp->timeperframe; 876 struct ov7670_info *info = to_state(sd); 877 int div; 878 879 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 880 return -EINVAL; 881 if (cp->extendedmode != 0) 882 return -EINVAL; 883 884 if (tpf->numerator == 0 || tpf->denominator == 0) 885 div = 1; /* Reset to full rate */ 886 else 887 div = (tpf->numerator*OV7670_FRAME_RATE)/tpf->denominator; 888 if (div == 0) 889 div = 1; 890 else if (div > CLK_SCALE) 891 div = CLK_SCALE; 892 info->clkrc = (info->clkrc & 0x80) | div; 893 tpf->numerator = 1; 894 tpf->denominator = OV7670_FRAME_RATE/div; 895 return ov7670_write(sd, REG_CLKRC, info->clkrc); 896} 897 898 899 900/* 901 * Code for dealing with controls. 902 */ 903 904 905 906 907 908static int ov7670_store_cmatrix(struct v4l2_subdev *sd, 909 int matrix[CMATRIX_LEN]) 910{ 911 int i, ret; 912 unsigned char signbits = 0; 913 914 /* 915 * Weird crap seems to exist in the upper part of 916 * the sign bits register, so let's preserve it. 917 */ 918 ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits); 919 signbits &= 0xc0; 920 921 for (i = 0; i < CMATRIX_LEN; i++) { 922 unsigned char raw; 923 924 if (matrix[i] < 0) { 925 signbits |= (1 << i); 926 if (matrix[i] < -255) 927 raw = 0xff; 928 else 929 raw = (-1 * matrix[i]) & 0xff; 930 } 931 else { 932 if (matrix[i] > 255) 933 raw = 0xff; 934 else 935 raw = matrix[i] & 0xff; 936 } 937 ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw); 938 } 939 ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits); 940 return ret; 941} 942 943 944/* 945 * Hue also requires messing with the color matrix. It also requires 946 * trig functions, which tend not to be well supported in the kernel. 947 * So here is a simple table of sine values, 0-90 degrees, in steps 948 * of five degrees. Values are multiplied by 1000. 949 * 950 * The following naive approximate trig functions require an argument 951 * carefully limited to -180 <= theta <= 180. 952 */ 953#define SIN_STEP 5 954static const int ov7670_sin_table[] = { 955 0, 87, 173, 258, 342, 422, 956 499, 573, 642, 707, 766, 819, 957 866, 906, 939, 965, 984, 996, 958 1000 959}; 960 961static int ov7670_sine(int theta) 962{ 963 int chs = 1; 964 int sine; 965 966 if (theta < 0) { 967 theta = -theta; 968 chs = -1; 969 } 970 if (theta <= 90) 971 sine = ov7670_sin_table[theta/SIN_STEP]; 972 else { 973 theta -= 90; 974 sine = 1000 - ov7670_sin_table[theta/SIN_STEP]; 975 } 976 return sine*chs; 977} 978 979static int ov7670_cosine(int theta) 980{ 981 theta = 90 - theta; 982 if (theta > 180) 983 theta -= 360; 984 else if (theta < -180) 985 theta += 360; 986 return ov7670_sine(theta); 987} 988 989 990 991 992static void ov7670_calc_cmatrix(struct ov7670_info *info, 993 int matrix[CMATRIX_LEN]) 994{ 995 int i; 996 /* 997 * Apply the current saturation setting first. 998 */ 999 for (i = 0; i < CMATRIX_LEN; i++) 1000 matrix[i] = (info->fmt->cmatrix[i]*info->sat) >> 7; 1001 /* 1002 * Then, if need be, rotate the hue value. 1003 */ 1004 if (info->hue != 0) { 1005 int sinth, costh, tmpmatrix[CMATRIX_LEN]; 1006 1007 memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int)); 1008 sinth = ov7670_sine(info->hue); 1009 costh = ov7670_cosine(info->hue); 1010 1011 matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000; 1012 matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000; 1013 matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000; 1014 matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000; 1015 matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000; 1016 matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000; 1017 } 1018} 1019 1020 1021 1022static int ov7670_s_sat(struct v4l2_subdev *sd, int value) 1023{ 1024 struct ov7670_info *info = to_state(sd); 1025 int matrix[CMATRIX_LEN]; 1026 int ret; 1027 1028 info->sat = value; 1029 ov7670_calc_cmatrix(info, matrix); 1030 ret = ov7670_store_cmatrix(sd, matrix); 1031 return ret; 1032} 1033 1034static int ov7670_g_sat(struct v4l2_subdev *sd, __s32 *value) 1035{ 1036 struct ov7670_info *info = to_state(sd); 1037 1038 *value = info->sat; 1039 return 0; 1040} 1041 1042static int ov7670_s_hue(struct v4l2_subdev *sd, int value) 1043{ 1044 struct ov7670_info *info = to_state(sd); 1045 int matrix[CMATRIX_LEN]; 1046 int ret; 1047 1048 if (value < -180 || value > 180) 1049 return -EINVAL; 1050 info->hue = value; 1051 ov7670_calc_cmatrix(info, matrix); 1052 ret = ov7670_store_cmatrix(sd, matrix); 1053 return ret; 1054} 1055 1056 1057static int ov7670_g_hue(struct v4l2_subdev *sd, __s32 *value) 1058{ 1059 struct ov7670_info *info = to_state(sd); 1060 1061 *value = info->hue; 1062 return 0; 1063} 1064 1065 1066/* 1067 * Some weird registers seem to store values in a sign/magnitude format! 1068 */ 1069static unsigned char ov7670_sm_to_abs(unsigned char v) 1070{ 1071 if ((v & 0x80) == 0) 1072 return v + 128; 1073 return 128 - (v & 0x7f); 1074} 1075 1076 1077static unsigned char ov7670_abs_to_sm(unsigned char v) 1078{ 1079 if (v > 127) 1080 return v & 0x7f; 1081 return (128 - v) | 0x80; 1082} 1083 1084static int ov7670_s_brightness(struct v4l2_subdev *sd, int value) 1085{ 1086 unsigned char com8 = 0, v; 1087 int ret; 1088 1089 ov7670_read(sd, REG_COM8, &com8); 1090 com8 &= ~COM8_AEC; 1091 ov7670_write(sd, REG_COM8, com8); 1092 v = ov7670_abs_to_sm(value); 1093 ret = ov7670_write(sd, REG_BRIGHT, v); 1094 return ret; 1095} 1096 1097static int ov7670_g_brightness(struct v4l2_subdev *sd, __s32 *value) 1098{ 1099 unsigned char v = 0; 1100 int ret = ov7670_read(sd, REG_BRIGHT, &v); 1101 1102 *value = ov7670_sm_to_abs(v); 1103 return ret; 1104} 1105 1106static int ov7670_s_contrast(struct v4l2_subdev *sd, int value) 1107{ 1108 return ov7670_write(sd, REG_CONTRAS, (unsigned char) value); 1109} 1110 1111static int ov7670_g_contrast(struct v4l2_subdev *sd, __s32 *value) 1112{ 1113 unsigned char v = 0; 1114 int ret = ov7670_read(sd, REG_CONTRAS, &v); 1115 1116 *value = v; 1117 return ret; 1118} 1119 1120static int ov7670_g_hflip(struct v4l2_subdev *sd, __s32 *value) 1121{ 1122 int ret; 1123 unsigned char v = 0; 1124 1125 ret = ov7670_read(sd, REG_MVFP, &v); 1126 *value = (v & MVFP_MIRROR) == MVFP_MIRROR; 1127 return ret; 1128} 1129 1130 1131static int ov7670_s_hflip(struct v4l2_subdev *sd, int value) 1132{ 1133 unsigned char v = 0; 1134 int ret; 1135 1136 ret = ov7670_read(sd, REG_MVFP, &v); 1137 if (value) 1138 v |= MVFP_MIRROR; 1139 else 1140 v &= ~MVFP_MIRROR; 1141 msleep(10); 1142 ret += ov7670_write(sd, REG_MVFP, v); 1143 return ret; 1144} 1145 1146 1147 1148static int ov7670_g_vflip(struct v4l2_subdev *sd, __s32 *value) 1149{ 1150 int ret; 1151 unsigned char v = 0; 1152 1153 ret = ov7670_read(sd, REG_MVFP, &v); 1154 *value = (v & MVFP_FLIP) == MVFP_FLIP; 1155 return ret; 1156} 1157 1158 1159static int ov7670_s_vflip(struct v4l2_subdev *sd, int value) 1160{ 1161 unsigned char v = 0; 1162 int ret; 1163 1164 ret = ov7670_read(sd, REG_MVFP, &v); 1165 if (value) 1166 v |= MVFP_FLIP; 1167 else 1168 v &= ~MVFP_FLIP; 1169 msleep(10); 1170 ret += ov7670_write(sd, REG_MVFP, v); 1171 return ret; 1172} 1173 1174/* 1175 * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes 1176 * the data sheet, the VREF parts should be the most significant, but 1177 * experience shows otherwise. There seems to be little value in 1178 * messing with the VREF bits, so we leave them alone. 1179 */ 1180static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value) 1181{ 1182 int ret; 1183 unsigned char gain; 1184 1185 ret = ov7670_read(sd, REG_GAIN, &gain); 1186 *value = gain; 1187 return ret; 1188} 1189 1190static int ov7670_s_gain(struct v4l2_subdev *sd, int value) 1191{ 1192 int ret; 1193 unsigned char com8; 1194 1195 ret = ov7670_write(sd, REG_GAIN, value & 0xff); 1196 /* Have to turn off AGC as well */ 1197 if (ret == 0) { 1198 ret = ov7670_read(sd, REG_COM8, &com8); 1199 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC); 1200 } 1201 return ret; 1202} 1203 1204/* 1205 * Tweak autogain. 1206 */ 1207static int ov7670_g_autogain(struct v4l2_subdev *sd, __s32 *value) 1208{ 1209 int ret; 1210 unsigned char com8; 1211 1212 ret = ov7670_read(sd, REG_COM8, &com8); 1213 *value = (com8 & COM8_AGC) != 0; 1214 return ret; 1215} 1216 1217static int ov7670_s_autogain(struct v4l2_subdev *sd, int value) 1218{ 1219 int ret; 1220 unsigned char com8; 1221 1222 ret = ov7670_read(sd, REG_COM8, &com8); 1223 if (ret == 0) { 1224 if (value) 1225 com8 |= COM8_AGC; 1226 else 1227 com8 &= ~COM8_AGC; 1228 ret = ov7670_write(sd, REG_COM8, com8); 1229 } 1230 return ret; 1231} 1232 1233/* 1234 * Exposure is spread all over the place: top 6 bits in AECHH, middle 1235 * 8 in AECH, and two stashed in COM1 just for the hell of it. 1236 */ 1237static int ov7670_g_exp(struct v4l2_subdev *sd, __s32 *value) 1238{ 1239 int ret; 1240 unsigned char com1, aech, aechh; 1241 1242 ret = ov7670_read(sd, REG_COM1, &com1) + 1243 ov7670_read(sd, REG_AECH, &aech) + 1244 ov7670_read(sd, REG_AECHH, &aechh); 1245 *value = ((aechh & 0x3f) << 10) | (aech << 2) | (com1 & 0x03); 1246 return ret; 1247} 1248 1249static int ov7670_s_exp(struct v4l2_subdev *sd, int value) 1250{ 1251 int ret; 1252 unsigned char com1, com8, aech, aechh; 1253 1254 ret = ov7670_read(sd, REG_COM1, &com1) + 1255 ov7670_read(sd, REG_COM8, &com8); 1256 ov7670_read(sd, REG_AECHH, &aechh); 1257 if (ret) 1258 return ret; 1259 1260 com1 = (com1 & 0xfc) | (value & 0x03); 1261 aech = (value >> 2) & 0xff; 1262 aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f); 1263 ret = ov7670_write(sd, REG_COM1, com1) + 1264 ov7670_write(sd, REG_AECH, aech) + 1265 ov7670_write(sd, REG_AECHH, aechh); 1266 /* Have to turn off AEC as well */ 1267 if (ret == 0) 1268 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC); 1269 return ret; 1270} 1271 1272/* 1273 * Tweak autoexposure. 1274 */ 1275static int ov7670_g_autoexp(struct v4l2_subdev *sd, __s32 *value) 1276{ 1277 int ret; 1278 unsigned char com8; 1279 enum v4l2_exposure_auto_type *atype = (enum v4l2_exposure_auto_type *) value; 1280 1281 ret = ov7670_read(sd, REG_COM8, &com8); 1282 if (com8 & COM8_AEC) 1283 *atype = V4L2_EXPOSURE_AUTO; 1284 else 1285 *atype = V4L2_EXPOSURE_MANUAL; 1286 return ret; 1287} 1288 1289static int ov7670_s_autoexp(struct v4l2_subdev *sd, 1290 enum v4l2_exposure_auto_type value) 1291{ 1292 int ret; 1293 unsigned char com8; 1294 1295 ret = ov7670_read(sd, REG_COM8, &com8); 1296 if (ret == 0) { 1297 if (value == V4L2_EXPOSURE_AUTO) 1298 com8 |= COM8_AEC; 1299 else 1300 com8 &= ~COM8_AEC; 1301 ret = ov7670_write(sd, REG_COM8, com8); 1302 } 1303 return ret; 1304} 1305 1306 1307 1308static int ov7670_queryctrl(struct v4l2_subdev *sd, 1309 struct v4l2_queryctrl *qc) 1310{ 1311 /* Fill in min, max, step and default value for these controls. */ 1312 switch (qc->id) { 1313 case V4L2_CID_BRIGHTNESS: 1314 return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128); 1315 case V4L2_CID_CONTRAST: 1316 return v4l2_ctrl_query_fill(qc, 0, 127, 1, 64); 1317 case V4L2_CID_VFLIP: 1318 case V4L2_CID_HFLIP: 1319 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0); 1320 case V4L2_CID_SATURATION: 1321 return v4l2_ctrl_query_fill(qc, 0, 256, 1, 128); 1322 case V4L2_CID_HUE: 1323 return v4l2_ctrl_query_fill(qc, -180, 180, 5, 0); 1324 case V4L2_CID_GAIN: 1325 return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128); 1326 case V4L2_CID_AUTOGAIN: 1327 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 1); 1328 case V4L2_CID_EXPOSURE: 1329 return v4l2_ctrl_query_fill(qc, 0, 65535, 1, 500); 1330 case V4L2_CID_EXPOSURE_AUTO: 1331 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0); 1332 } 1333 return -EINVAL; 1334} 1335 1336static int ov7670_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) 1337{ 1338 switch (ctrl->id) { 1339 case V4L2_CID_BRIGHTNESS: 1340 return ov7670_g_brightness(sd, &ctrl->value); 1341 case V4L2_CID_CONTRAST: 1342 return ov7670_g_contrast(sd, &ctrl->value); 1343 case V4L2_CID_SATURATION: 1344 return ov7670_g_sat(sd, &ctrl->value); 1345 case V4L2_CID_HUE: 1346 return ov7670_g_hue(sd, &ctrl->value); 1347 case V4L2_CID_VFLIP: 1348 return ov7670_g_vflip(sd, &ctrl->value); 1349 case V4L2_CID_HFLIP: 1350 return ov7670_g_hflip(sd, &ctrl->value); 1351 case V4L2_CID_GAIN: 1352 return ov7670_g_gain(sd, &ctrl->value); 1353 case V4L2_CID_AUTOGAIN: 1354 return ov7670_g_autogain(sd, &ctrl->value); 1355 case V4L2_CID_EXPOSURE: 1356 return ov7670_g_exp(sd, &ctrl->value); 1357 case V4L2_CID_EXPOSURE_AUTO: 1358 return ov7670_g_autoexp(sd, &ctrl->value); 1359 } 1360 return -EINVAL; 1361} 1362 1363static int ov7670_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) 1364{ 1365 switch (ctrl->id) { 1366 case V4L2_CID_BRIGHTNESS: 1367 return ov7670_s_brightness(sd, ctrl->value); 1368 case V4L2_CID_CONTRAST: 1369 return ov7670_s_contrast(sd, ctrl->value); 1370 case V4L2_CID_SATURATION: 1371 return ov7670_s_sat(sd, ctrl->value); 1372 case V4L2_CID_HUE: 1373 return ov7670_s_hue(sd, ctrl->value); 1374 case V4L2_CID_VFLIP: 1375 return ov7670_s_vflip(sd, ctrl->value); 1376 case V4L2_CID_HFLIP: 1377 return ov7670_s_hflip(sd, ctrl->value); 1378 case V4L2_CID_GAIN: 1379 return ov7670_s_gain(sd, ctrl->value); 1380 case V4L2_CID_AUTOGAIN: 1381 return ov7670_s_autogain(sd, ctrl->value); 1382 case V4L2_CID_EXPOSURE: 1383 return ov7670_s_exp(sd, ctrl->value); 1384 case V4L2_CID_EXPOSURE_AUTO: 1385 return ov7670_s_autoexp(sd, 1386 (enum v4l2_exposure_auto_type) ctrl->value); 1387 } 1388 return -EINVAL; 1389} 1390 1391static int ov7670_g_chip_ident(struct v4l2_subdev *sd, 1392 struct v4l2_dbg_chip_ident *chip) 1393{ 1394 struct i2c_client *client = v4l2_get_subdevdata(sd); 1395 1396 return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_OV7670, 0); 1397} 1398 1399#ifdef CONFIG_VIDEO_ADV_DEBUG 1400static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) 1401{ 1402 struct i2c_client *client = v4l2_get_subdevdata(sd); 1403 unsigned char val = 0; 1404 int ret; 1405 1406 if (!v4l2_chip_match_i2c_client(client, ®->match)) 1407 return -EINVAL; 1408 if (!capable(CAP_SYS_ADMIN)) 1409 return -EPERM; 1410 ret = ov7670_read(sd, reg->reg & 0xff, &val); 1411 reg->val = val; 1412 reg->size = 1; 1413 return ret; 1414} 1415 1416static int ov7670_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) 1417{ 1418 struct i2c_client *client = v4l2_get_subdevdata(sd); 1419 1420 if (!v4l2_chip_match_i2c_client(client, ®->match)) 1421 return -EINVAL; 1422 if (!capable(CAP_SYS_ADMIN)) 1423 return -EPERM; 1424 ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff); 1425 return 0; 1426} 1427#endif 1428 1429/* ----------------------------------------------------------------------- */ 1430 1431static const struct v4l2_subdev_core_ops ov7670_core_ops = { 1432 .g_chip_ident = ov7670_g_chip_ident, 1433 .g_ctrl = ov7670_g_ctrl, 1434 .s_ctrl = ov7670_s_ctrl, 1435 .queryctrl = ov7670_queryctrl, 1436 .reset = ov7670_reset, 1437 .init = ov7670_init, 1438#ifdef CONFIG_VIDEO_ADV_DEBUG 1439 .g_register = ov7670_g_register, 1440 .s_register = ov7670_s_register, 1441#endif 1442}; 1443 1444static const struct v4l2_subdev_video_ops ov7670_video_ops = { 1445 .enum_fmt = ov7670_enum_fmt, 1446 .try_fmt = ov7670_try_fmt, 1447 .s_fmt = ov7670_s_fmt, 1448 .s_parm = ov7670_s_parm, 1449 .g_parm = ov7670_g_parm, 1450}; 1451 1452static const struct v4l2_subdev_ops ov7670_ops = { 1453 .core = &ov7670_core_ops, 1454 .video = &ov7670_video_ops, 1455}; 1456 1457/* ----------------------------------------------------------------------- */ 1458 1459static int ov7670_probe(struct i2c_client *client, 1460 const struct i2c_device_id *id) 1461{ 1462 struct v4l2_subdev *sd; 1463 struct ov7670_info *info; 1464 int ret; 1465 1466 info = kzalloc(sizeof(struct ov7670_info), GFP_KERNEL); 1467 if (info == NULL) 1468 return -ENOMEM; 1469 sd = &info->sd; 1470 v4l2_i2c_subdev_init(sd, client, &ov7670_ops); 1471 1472 /* Make sure it's an ov7670 */ 1473 ret = ov7670_detect(sd); 1474 if (ret) { 1475 v4l_dbg(1, debug, client, 1476 "chip found @ 0x%x (%s) is not an ov7670 chip.\n", 1477 client->addr << 1, client->adapter->name); 1478 kfree(info); 1479 return ret; 1480 } 1481 v4l_info(client, "chip found @ 0x%02x (%s)\n", 1482 client->addr << 1, client->adapter->name); 1483 1484 info->fmt = &ov7670_formats[0]; 1485 info->sat = 128; /* Review this */ 1486 info->clkrc = 1; /* 30fps */ 1487 1488 return 0; 1489} 1490 1491 1492static int ov7670_remove(struct i2c_client *client) 1493{ 1494 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1495 1496 v4l2_device_unregister_subdev(sd); 1497 kfree(to_state(sd)); 1498 return 0; 1499} 1500 1501static const struct i2c_device_id ov7670_id[] = { 1502 { "ov7670", 0 }, 1503 { } 1504}; 1505MODULE_DEVICE_TABLE(i2c, ov7670_id); 1506 1507static struct v4l2_i2c_driver_data v4l2_i2c_data = { 1508 .name = "ov7670", 1509 .probe = ov7670_probe, 1510 .remove = ov7670_remove, 1511 .id_table = ov7670_id, 1512}; 1513