1/* 2 STV0900/0903 Multistandard Broadcast Frontend driver 3 Copyright (C) Manu Abraham <abraham.manu@gmail.com> 4 5 Copyright (C) ST Microelectronics 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20*/ 21 22#include <linux/init.h> 23#include <linux/kernel.h> 24#include <linux/module.h> 25#include <linux/string.h> 26#include <linux/slab.h> 27#include <linux/mutex.h> 28 29#include <linux/dvb/frontend.h> 30#include "dvb_frontend.h" 31 32#include "stv6110x.h" /* for demodulator internal modes */ 33 34#include "stv090x_reg.h" 35#include "stv090x.h" 36#include "stv090x_priv.h" 37 38static unsigned int verbose; 39module_param(verbose, int, 0644); 40 41/* internal params node */ 42struct stv090x_dev { 43 /* pointer for internal params, one for each pair of demods */ 44 struct stv090x_internal *internal; 45 struct stv090x_dev *next_dev; 46}; 47 48/* first internal params */ 49static struct stv090x_dev *stv090x_first_dev; 50 51/* find chip by i2c adapter and i2c address */ 52static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap, 53 u8 i2c_addr) 54{ 55 struct stv090x_dev *temp_dev = stv090x_first_dev; 56 57 /* 58 Search of the last stv0900 chip or 59 find it by i2c adapter and i2c address */ 60 while ((temp_dev != NULL) && 61 ((temp_dev->internal->i2c_adap != i2c_adap) || 62 (temp_dev->internal->i2c_addr != i2c_addr))) { 63 64 temp_dev = temp_dev->next_dev; 65 } 66 67 return temp_dev; 68} 69 70/* deallocating chip */ 71static void remove_dev(struct stv090x_internal *internal) 72{ 73 struct stv090x_dev *prev_dev = stv090x_first_dev; 74 struct stv090x_dev *del_dev = find_dev(internal->i2c_adap, 75 internal->i2c_addr); 76 77 if (del_dev != NULL) { 78 if (del_dev == stv090x_first_dev) { 79 stv090x_first_dev = del_dev->next_dev; 80 } else { 81 while (prev_dev->next_dev != del_dev) 82 prev_dev = prev_dev->next_dev; 83 84 prev_dev->next_dev = del_dev->next_dev; 85 } 86 87 kfree(del_dev); 88 } 89} 90 91/* allocating new chip */ 92static struct stv090x_dev *append_internal(struct stv090x_internal *internal) 93{ 94 struct stv090x_dev *new_dev; 95 struct stv090x_dev *temp_dev; 96 97 new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL); 98 if (new_dev != NULL) { 99 new_dev->internal = internal; 100 new_dev->next_dev = NULL; 101 102 /* append to list */ 103 if (stv090x_first_dev == NULL) { 104 stv090x_first_dev = new_dev; 105 } else { 106 temp_dev = stv090x_first_dev; 107 while (temp_dev->next_dev != NULL) 108 temp_dev = temp_dev->next_dev; 109 110 temp_dev->next_dev = new_dev; 111 } 112 } 113 114 return new_dev; 115} 116 117 118/* DVBS1 and DSS C/N Lookup table */ 119static const struct stv090x_tab stv090x_s1cn_tab[] = { 120 { 0, 8917 }, /* 0.0dB */ 121 { 5, 8801 }, /* 0.5dB */ 122 { 10, 8667 }, /* 1.0dB */ 123 { 15, 8522 }, /* 1.5dB */ 124 { 20, 8355 }, /* 2.0dB */ 125 { 25, 8175 }, /* 2.5dB */ 126 { 30, 7979 }, /* 3.0dB */ 127 { 35, 7763 }, /* 3.5dB */ 128 { 40, 7530 }, /* 4.0dB */ 129 { 45, 7282 }, /* 4.5dB */ 130 { 50, 7026 }, /* 5.0dB */ 131 { 55, 6781 }, /* 5.5dB */ 132 { 60, 6514 }, /* 6.0dB */ 133 { 65, 6241 }, /* 6.5dB */ 134 { 70, 5965 }, /* 7.0dB */ 135 { 75, 5690 }, /* 7.5dB */ 136 { 80, 5424 }, /* 8.0dB */ 137 { 85, 5161 }, /* 8.5dB */ 138 { 90, 4902 }, /* 9.0dB */ 139 { 95, 4654 }, /* 9.5dB */ 140 { 100, 4417 }, /* 10.0dB */ 141 { 105, 4186 }, /* 10.5dB */ 142 { 110, 3968 }, /* 11.0dB */ 143 { 115, 3757 }, /* 11.5dB */ 144 { 120, 3558 }, /* 12.0dB */ 145 { 125, 3366 }, /* 12.5dB */ 146 { 130, 3185 }, /* 13.0dB */ 147 { 135, 3012 }, /* 13.5dB */ 148 { 140, 2850 }, /* 14.0dB */ 149 { 145, 2698 }, /* 14.5dB */ 150 { 150, 2550 }, /* 15.0dB */ 151 { 160, 2283 }, /* 16.0dB */ 152 { 170, 2042 }, /* 17.0dB */ 153 { 180, 1827 }, /* 18.0dB */ 154 { 190, 1636 }, /* 19.0dB */ 155 { 200, 1466 }, /* 20.0dB */ 156 { 210, 1315 }, /* 21.0dB */ 157 { 220, 1181 }, /* 22.0dB */ 158 { 230, 1064 }, /* 23.0dB */ 159 { 240, 960 }, /* 24.0dB */ 160 { 250, 869 }, /* 25.0dB */ 161 { 260, 792 }, /* 26.0dB */ 162 { 270, 724 }, /* 27.0dB */ 163 { 280, 665 }, /* 28.0dB */ 164 { 290, 616 }, /* 29.0dB */ 165 { 300, 573 }, /* 30.0dB */ 166 { 310, 537 }, /* 31.0dB */ 167 { 320, 507 }, /* 32.0dB */ 168 { 330, 483 }, /* 33.0dB */ 169 { 400, 398 }, /* 40.0dB */ 170 { 450, 381 }, /* 45.0dB */ 171 { 500, 377 } /* 50.0dB */ 172}; 173 174/* DVBS2 C/N Lookup table */ 175static const struct stv090x_tab stv090x_s2cn_tab[] = { 176 { -30, 13348 }, /* -3.0dB */ 177 { -20, 12640 }, /* -2d.0B */ 178 { -10, 11883 }, /* -1.0dB */ 179 { 0, 11101 }, /* -0.0dB */ 180 { 5, 10718 }, /* 0.5dB */ 181 { 10, 10339 }, /* 1.0dB */ 182 { 15, 9947 }, /* 1.5dB */ 183 { 20, 9552 }, /* 2.0dB */ 184 { 25, 9183 }, /* 2.5dB */ 185 { 30, 8799 }, /* 3.0dB */ 186 { 35, 8422 }, /* 3.5dB */ 187 { 40, 8062 }, /* 4.0dB */ 188 { 45, 7707 }, /* 4.5dB */ 189 { 50, 7353 }, /* 5.0dB */ 190 { 55, 7025 }, /* 5.5dB */ 191 { 60, 6684 }, /* 6.0dB */ 192 { 65, 6331 }, /* 6.5dB */ 193 { 70, 6036 }, /* 7.0dB */ 194 { 75, 5727 }, /* 7.5dB */ 195 { 80, 5437 }, /* 8.0dB */ 196 { 85, 5164 }, /* 8.5dB */ 197 { 90, 4902 }, /* 9.0dB */ 198 { 95, 4653 }, /* 9.5dB */ 199 { 100, 4408 }, /* 10.0dB */ 200 { 105, 4187 }, /* 10.5dB */ 201 { 110, 3961 }, /* 11.0dB */ 202 { 115, 3751 }, /* 11.5dB */ 203 { 120, 3558 }, /* 12.0dB */ 204 { 125, 3368 }, /* 12.5dB */ 205 { 130, 3191 }, /* 13.0dB */ 206 { 135, 3017 }, /* 13.5dB */ 207 { 140, 2862 }, /* 14.0dB */ 208 { 145, 2710 }, /* 14.5dB */ 209 { 150, 2565 }, /* 15.0dB */ 210 { 160, 2300 }, /* 16.0dB */ 211 { 170, 2058 }, /* 17.0dB */ 212 { 180, 1849 }, /* 18.0dB */ 213 { 190, 1663 }, /* 19.0dB */ 214 { 200, 1495 }, /* 20.0dB */ 215 { 210, 1349 }, /* 21.0dB */ 216 { 220, 1222 }, /* 22.0dB */ 217 { 230, 1110 }, /* 23.0dB */ 218 { 240, 1011 }, /* 24.0dB */ 219 { 250, 925 }, /* 25.0dB */ 220 { 260, 853 }, /* 26.0dB */ 221 { 270, 789 }, /* 27.0dB */ 222 { 280, 734 }, /* 28.0dB */ 223 { 290, 690 }, /* 29.0dB */ 224 { 300, 650 }, /* 30.0dB */ 225 { 310, 619 }, /* 31.0dB */ 226 { 320, 593 }, /* 32.0dB */ 227 { 330, 571 }, /* 33.0dB */ 228 { 400, 498 }, /* 40.0dB */ 229 { 450, 484 }, /* 45.0dB */ 230 { 500, 481 } /* 50.0dB */ 231}; 232 233/* RF level C/N lookup table */ 234static const struct stv090x_tab stv090x_rf_tab[] = { 235 { -5, 0xcaa1 }, /* -5dBm */ 236 { -10, 0xc229 }, /* -10dBm */ 237 { -15, 0xbb08 }, /* -15dBm */ 238 { -20, 0xb4bc }, /* -20dBm */ 239 { -25, 0xad5a }, /* -25dBm */ 240 { -30, 0xa298 }, /* -30dBm */ 241 { -35, 0x98a8 }, /* -35dBm */ 242 { -40, 0x8389 }, /* -40dBm */ 243 { -45, 0x59be }, /* -45dBm */ 244 { -50, 0x3a14 }, /* -50dBm */ 245 { -55, 0x2d11 }, /* -55dBm */ 246 { -60, 0x210d }, /* -60dBm */ 247 { -65, 0xa14f }, /* -65dBm */ 248 { -70, 0x07aa } /* -70dBm */ 249}; 250 251 252static struct stv090x_reg stv0900_initval[] = { 253 254 { STV090x_OUTCFG, 0x00 }, 255 { STV090x_MODECFG, 0xff }, 256 { STV090x_AGCRF1CFG, 0x11 }, 257 { STV090x_AGCRF2CFG, 0x13 }, 258 { STV090x_TSGENERAL1X, 0x14 }, 259 { STV090x_TSTTNR2, 0x21 }, 260 { STV090x_TSTTNR4, 0x21 }, 261 { STV090x_P2_DISTXCTL, 0x22 }, 262 { STV090x_P2_F22TX, 0xc0 }, 263 { STV090x_P2_F22RX, 0xc0 }, 264 { STV090x_P2_DISRXCTL, 0x00 }, 265 { STV090x_P2_DMDCFGMD, 0xF9 }, 266 { STV090x_P2_DEMOD, 0x08 }, 267 { STV090x_P2_DMDCFG3, 0xc4 }, 268 { STV090x_P2_CARFREQ, 0xed }, 269 { STV090x_P2_LDT, 0xd0 }, 270 { STV090x_P2_LDT2, 0xb8 }, 271 { STV090x_P2_TMGCFG, 0xd2 }, 272 { STV090x_P2_TMGTHRISE, 0x20 }, 273 { STV090x_P1_TMGCFG, 0xd2 }, 274 275 { STV090x_P2_TMGTHFALL, 0x00 }, 276 { STV090x_P2_FECSPY, 0x88 }, 277 { STV090x_P2_FSPYDATA, 0x3a }, 278 { STV090x_P2_FBERCPT4, 0x00 }, 279 { STV090x_P2_FSPYBER, 0x10 }, 280 { STV090x_P2_ERRCTRL1, 0x35 }, 281 { STV090x_P2_ERRCTRL2, 0xc1 }, 282 { STV090x_P2_CFRICFG, 0xf8 }, 283 { STV090x_P2_NOSCFG, 0x1c }, 284 { STV090x_P2_DMDTOM, 0x20 }, 285 { STV090x_P2_CORRELMANT, 0x70 }, 286 { STV090x_P2_CORRELABS, 0x88 }, 287 { STV090x_P2_AGC2O, 0x5b }, 288 { STV090x_P2_AGC2REF, 0x38 }, 289 { STV090x_P2_CARCFG, 0xe4 }, 290 { STV090x_P2_ACLC, 0x1A }, 291 { STV090x_P2_BCLC, 0x09 }, 292 { STV090x_P2_CARHDR, 0x08 }, 293 { STV090x_P2_KREFTMG, 0xc1 }, 294 { STV090x_P2_SFRUPRATIO, 0xf0 }, 295 { STV090x_P2_SFRLOWRATIO, 0x70 }, 296 { STV090x_P2_SFRSTEP, 0x58 }, 297 { STV090x_P2_TMGCFG2, 0x01 }, 298 { STV090x_P2_CAR2CFG, 0x26 }, 299 { STV090x_P2_BCLC2S2Q, 0x86 }, 300 { STV090x_P2_BCLC2S28, 0x86 }, 301 { STV090x_P2_SMAPCOEF7, 0x77 }, 302 { STV090x_P2_SMAPCOEF6, 0x85 }, 303 { STV090x_P2_SMAPCOEF5, 0x77 }, 304 { STV090x_P2_TSCFGL, 0x20 }, 305 { STV090x_P2_DMDCFG2, 0x3b }, 306 { STV090x_P2_MODCODLST0, 0xff }, 307 { STV090x_P2_MODCODLST1, 0xff }, 308 { STV090x_P2_MODCODLST2, 0xff }, 309 { STV090x_P2_MODCODLST3, 0xff }, 310 { STV090x_P2_MODCODLST4, 0xff }, 311 { STV090x_P2_MODCODLST5, 0xff }, 312 { STV090x_P2_MODCODLST6, 0xff }, 313 { STV090x_P2_MODCODLST7, 0xcc }, 314 { STV090x_P2_MODCODLST8, 0xcc }, 315 { STV090x_P2_MODCODLST9, 0xcc }, 316 { STV090x_P2_MODCODLSTA, 0xcc }, 317 { STV090x_P2_MODCODLSTB, 0xcc }, 318 { STV090x_P2_MODCODLSTC, 0xcc }, 319 { STV090x_P2_MODCODLSTD, 0xcc }, 320 { STV090x_P2_MODCODLSTE, 0xcc }, 321 { STV090x_P2_MODCODLSTF, 0xcf }, 322 { STV090x_P1_DISTXCTL, 0x22 }, 323 { STV090x_P1_F22TX, 0xc0 }, 324 { STV090x_P1_F22RX, 0xc0 }, 325 { STV090x_P1_DISRXCTL, 0x00 }, 326 { STV090x_P1_DMDCFGMD, 0xf9 }, 327 { STV090x_P1_DEMOD, 0x08 }, 328 { STV090x_P1_DMDCFG3, 0xc4 }, 329 { STV090x_P1_DMDTOM, 0x20 }, 330 { STV090x_P1_CARFREQ, 0xed }, 331 { STV090x_P1_LDT, 0xd0 }, 332 { STV090x_P1_LDT2, 0xb8 }, 333 { STV090x_P1_TMGCFG, 0xd2 }, 334 { STV090x_P1_TMGTHRISE, 0x20 }, 335 { STV090x_P1_TMGTHFALL, 0x00 }, 336 { STV090x_P1_SFRUPRATIO, 0xf0 }, 337 { STV090x_P1_SFRLOWRATIO, 0x70 }, 338 { STV090x_P1_TSCFGL, 0x20 }, 339 { STV090x_P1_FECSPY, 0x88 }, 340 { STV090x_P1_FSPYDATA, 0x3a }, 341 { STV090x_P1_FBERCPT4, 0x00 }, 342 { STV090x_P1_FSPYBER, 0x10 }, 343 { STV090x_P1_ERRCTRL1, 0x35 }, 344 { STV090x_P1_ERRCTRL2, 0xc1 }, 345 { STV090x_P1_CFRICFG, 0xf8 }, 346 { STV090x_P1_NOSCFG, 0x1c }, 347 { STV090x_P1_CORRELMANT, 0x70 }, 348 { STV090x_P1_CORRELABS, 0x88 }, 349 { STV090x_P1_AGC2O, 0x5b }, 350 { STV090x_P1_AGC2REF, 0x38 }, 351 { STV090x_P1_CARCFG, 0xe4 }, 352 { STV090x_P1_ACLC, 0x1A }, 353 { STV090x_P1_BCLC, 0x09 }, 354 { STV090x_P1_CARHDR, 0x08 }, 355 { STV090x_P1_KREFTMG, 0xc1 }, 356 { STV090x_P1_SFRSTEP, 0x58 }, 357 { STV090x_P1_TMGCFG2, 0x01 }, 358 { STV090x_P1_CAR2CFG, 0x26 }, 359 { STV090x_P1_BCLC2S2Q, 0x86 }, 360 { STV090x_P1_BCLC2S28, 0x86 }, 361 { STV090x_P1_SMAPCOEF7, 0x77 }, 362 { STV090x_P1_SMAPCOEF6, 0x85 }, 363 { STV090x_P1_SMAPCOEF5, 0x77 }, 364 { STV090x_P1_DMDCFG2, 0x3b }, 365 { STV090x_P1_MODCODLST0, 0xff }, 366 { STV090x_P1_MODCODLST1, 0xff }, 367 { STV090x_P1_MODCODLST2, 0xff }, 368 { STV090x_P1_MODCODLST3, 0xff }, 369 { STV090x_P1_MODCODLST4, 0xff }, 370 { STV090x_P1_MODCODLST5, 0xff }, 371 { STV090x_P1_MODCODLST6, 0xff }, 372 { STV090x_P1_MODCODLST7, 0xcc }, 373 { STV090x_P1_MODCODLST8, 0xcc }, 374 { STV090x_P1_MODCODLST9, 0xcc }, 375 { STV090x_P1_MODCODLSTA, 0xcc }, 376 { STV090x_P1_MODCODLSTB, 0xcc }, 377 { STV090x_P1_MODCODLSTC, 0xcc }, 378 { STV090x_P1_MODCODLSTD, 0xcc }, 379 { STV090x_P1_MODCODLSTE, 0xcc }, 380 { STV090x_P1_MODCODLSTF, 0xcf }, 381 { STV090x_GENCFG, 0x1d }, 382 { STV090x_NBITER_NF4, 0x37 }, 383 { STV090x_NBITER_NF5, 0x29 }, 384 { STV090x_NBITER_NF6, 0x37 }, 385 { STV090x_NBITER_NF7, 0x33 }, 386 { STV090x_NBITER_NF8, 0x31 }, 387 { STV090x_NBITER_NF9, 0x2f }, 388 { STV090x_NBITER_NF10, 0x39 }, 389 { STV090x_NBITER_NF11, 0x3a }, 390 { STV090x_NBITER_NF12, 0x29 }, 391 { STV090x_NBITER_NF13, 0x37 }, 392 { STV090x_NBITER_NF14, 0x33 }, 393 { STV090x_NBITER_NF15, 0x2f }, 394 { STV090x_NBITER_NF16, 0x39 }, 395 { STV090x_NBITER_NF17, 0x3a }, 396 { STV090x_NBITERNOERR, 0x04 }, 397 { STV090x_GAINLLR_NF4, 0x0C }, 398 { STV090x_GAINLLR_NF5, 0x0F }, 399 { STV090x_GAINLLR_NF6, 0x11 }, 400 { STV090x_GAINLLR_NF7, 0x14 }, 401 { STV090x_GAINLLR_NF8, 0x17 }, 402 { STV090x_GAINLLR_NF9, 0x19 }, 403 { STV090x_GAINLLR_NF10, 0x20 }, 404 { STV090x_GAINLLR_NF11, 0x21 }, 405 { STV090x_GAINLLR_NF12, 0x0D }, 406 { STV090x_GAINLLR_NF13, 0x0F }, 407 { STV090x_GAINLLR_NF14, 0x13 }, 408 { STV090x_GAINLLR_NF15, 0x1A }, 409 { STV090x_GAINLLR_NF16, 0x1F }, 410 { STV090x_GAINLLR_NF17, 0x21 }, 411 { STV090x_RCCFGH, 0x20 }, 412 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */ 413 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */ 414 { STV090x_P1_PRVIT, 0x2F }, 415 { STV090x_P2_PRVIT, 0x2F }, 416}; 417 418static struct stv090x_reg stv0903_initval[] = { 419 { STV090x_OUTCFG, 0x00 }, 420 { STV090x_AGCRF1CFG, 0x11 }, 421 { STV090x_STOPCLK1, 0x48 }, 422 { STV090x_STOPCLK2, 0x14 }, 423 { STV090x_TSTTNR1, 0x27 }, 424 { STV090x_TSTTNR2, 0x21 }, 425 { STV090x_P1_DISTXCTL, 0x22 }, 426 { STV090x_P1_F22TX, 0xc0 }, 427 { STV090x_P1_F22RX, 0xc0 }, 428 { STV090x_P1_DISRXCTL, 0x00 }, 429 { STV090x_P1_DMDCFGMD, 0xF9 }, 430 { STV090x_P1_DEMOD, 0x08 }, 431 { STV090x_P1_DMDCFG3, 0xc4 }, 432 { STV090x_P1_CARFREQ, 0xed }, 433 { STV090x_P1_TNRCFG2, 0x82 }, 434 { STV090x_P1_LDT, 0xd0 }, 435 { STV090x_P1_LDT2, 0xb8 }, 436 { STV090x_P1_TMGCFG, 0xd2 }, 437 { STV090x_P1_TMGTHRISE, 0x20 }, 438 { STV090x_P1_TMGTHFALL, 0x00 }, 439 { STV090x_P1_SFRUPRATIO, 0xf0 }, 440 { STV090x_P1_SFRLOWRATIO, 0x70 }, 441 { STV090x_P1_TSCFGL, 0x20 }, 442 { STV090x_P1_FECSPY, 0x88 }, 443 { STV090x_P1_FSPYDATA, 0x3a }, 444 { STV090x_P1_FBERCPT4, 0x00 }, 445 { STV090x_P1_FSPYBER, 0x10 }, 446 { STV090x_P1_ERRCTRL1, 0x35 }, 447 { STV090x_P1_ERRCTRL2, 0xc1 }, 448 { STV090x_P1_CFRICFG, 0xf8 }, 449 { STV090x_P1_NOSCFG, 0x1c }, 450 { STV090x_P1_DMDTOM, 0x20 }, 451 { STV090x_P1_CORRELMANT, 0x70 }, 452 { STV090x_P1_CORRELABS, 0x88 }, 453 { STV090x_P1_AGC2O, 0x5b }, 454 { STV090x_P1_AGC2REF, 0x38 }, 455 { STV090x_P1_CARCFG, 0xe4 }, 456 { STV090x_P1_ACLC, 0x1A }, 457 { STV090x_P1_BCLC, 0x09 }, 458 { STV090x_P1_CARHDR, 0x08 }, 459 { STV090x_P1_KREFTMG, 0xc1 }, 460 { STV090x_P1_SFRSTEP, 0x58 }, 461 { STV090x_P1_TMGCFG2, 0x01 }, 462 { STV090x_P1_CAR2CFG, 0x26 }, 463 { STV090x_P1_BCLC2S2Q, 0x86 }, 464 { STV090x_P1_BCLC2S28, 0x86 }, 465 { STV090x_P1_SMAPCOEF7, 0x77 }, 466 { STV090x_P1_SMAPCOEF6, 0x85 }, 467 { STV090x_P1_SMAPCOEF5, 0x77 }, 468 { STV090x_P1_DMDCFG2, 0x3b }, 469 { STV090x_P1_MODCODLST0, 0xff }, 470 { STV090x_P1_MODCODLST1, 0xff }, 471 { STV090x_P1_MODCODLST2, 0xff }, 472 { STV090x_P1_MODCODLST3, 0xff }, 473 { STV090x_P1_MODCODLST4, 0xff }, 474 { STV090x_P1_MODCODLST5, 0xff }, 475 { STV090x_P1_MODCODLST6, 0xff }, 476 { STV090x_P1_MODCODLST7, 0xcc }, 477 { STV090x_P1_MODCODLST8, 0xcc }, 478 { STV090x_P1_MODCODLST9, 0xcc }, 479 { STV090x_P1_MODCODLSTA, 0xcc }, 480 { STV090x_P1_MODCODLSTB, 0xcc }, 481 { STV090x_P1_MODCODLSTC, 0xcc }, 482 { STV090x_P1_MODCODLSTD, 0xcc }, 483 { STV090x_P1_MODCODLSTE, 0xcc }, 484 { STV090x_P1_MODCODLSTF, 0xcf }, 485 { STV090x_GENCFG, 0x1c }, 486 { STV090x_NBITER_NF4, 0x37 }, 487 { STV090x_NBITER_NF5, 0x29 }, 488 { STV090x_NBITER_NF6, 0x37 }, 489 { STV090x_NBITER_NF7, 0x33 }, 490 { STV090x_NBITER_NF8, 0x31 }, 491 { STV090x_NBITER_NF9, 0x2f }, 492 { STV090x_NBITER_NF10, 0x39 }, 493 { STV090x_NBITER_NF11, 0x3a }, 494 { STV090x_NBITER_NF12, 0x29 }, 495 { STV090x_NBITER_NF13, 0x37 }, 496 { STV090x_NBITER_NF14, 0x33 }, 497 { STV090x_NBITER_NF15, 0x2f }, 498 { STV090x_NBITER_NF16, 0x39 }, 499 { STV090x_NBITER_NF17, 0x3a }, 500 { STV090x_NBITERNOERR, 0x04 }, 501 { STV090x_GAINLLR_NF4, 0x0C }, 502 { STV090x_GAINLLR_NF5, 0x0F }, 503 { STV090x_GAINLLR_NF6, 0x11 }, 504 { STV090x_GAINLLR_NF7, 0x14 }, 505 { STV090x_GAINLLR_NF8, 0x17 }, 506 { STV090x_GAINLLR_NF9, 0x19 }, 507 { STV090x_GAINLLR_NF10, 0x20 }, 508 { STV090x_GAINLLR_NF11, 0x21 }, 509 { STV090x_GAINLLR_NF12, 0x0D }, 510 { STV090x_GAINLLR_NF13, 0x0F }, 511 { STV090x_GAINLLR_NF14, 0x13 }, 512 { STV090x_GAINLLR_NF15, 0x1A }, 513 { STV090x_GAINLLR_NF16, 0x1F }, 514 { STV090x_GAINLLR_NF17, 0x21 }, 515 { STV090x_RCCFGH, 0x20 }, 516 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */ 517 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/ 518}; 519 520static struct stv090x_reg stv0900_cut20_val[] = { 521 522 { STV090x_P2_DMDCFG3, 0xe8 }, 523 { STV090x_P2_DMDCFG4, 0x10 }, 524 { STV090x_P2_CARFREQ, 0x38 }, 525 { STV090x_P2_CARHDR, 0x20 }, 526 { STV090x_P2_KREFTMG, 0x5a }, 527 { STV090x_P2_SMAPCOEF7, 0x06 }, 528 { STV090x_P2_SMAPCOEF6, 0x00 }, 529 { STV090x_P2_SMAPCOEF5, 0x04 }, 530 { STV090x_P2_NOSCFG, 0x0c }, 531 { STV090x_P1_DMDCFG3, 0xe8 }, 532 { STV090x_P1_DMDCFG4, 0x10 }, 533 { STV090x_P1_CARFREQ, 0x38 }, 534 { STV090x_P1_CARHDR, 0x20 }, 535 { STV090x_P1_KREFTMG, 0x5a }, 536 { STV090x_P1_SMAPCOEF7, 0x06 }, 537 { STV090x_P1_SMAPCOEF6, 0x00 }, 538 { STV090x_P1_SMAPCOEF5, 0x04 }, 539 { STV090x_P1_NOSCFG, 0x0c }, 540 { STV090x_GAINLLR_NF4, 0x21 }, 541 { STV090x_GAINLLR_NF5, 0x21 }, 542 { STV090x_GAINLLR_NF6, 0x20 }, 543 { STV090x_GAINLLR_NF7, 0x1F }, 544 { STV090x_GAINLLR_NF8, 0x1E }, 545 { STV090x_GAINLLR_NF9, 0x1E }, 546 { STV090x_GAINLLR_NF10, 0x1D }, 547 { STV090x_GAINLLR_NF11, 0x1B }, 548 { STV090x_GAINLLR_NF12, 0x20 }, 549 { STV090x_GAINLLR_NF13, 0x20 }, 550 { STV090x_GAINLLR_NF14, 0x20 }, 551 { STV090x_GAINLLR_NF15, 0x20 }, 552 { STV090x_GAINLLR_NF16, 0x20 }, 553 { STV090x_GAINLLR_NF17, 0x21 }, 554}; 555 556static struct stv090x_reg stv0903_cut20_val[] = { 557 { STV090x_P1_DMDCFG3, 0xe8 }, 558 { STV090x_P1_DMDCFG4, 0x10 }, 559 { STV090x_P1_CARFREQ, 0x38 }, 560 { STV090x_P1_CARHDR, 0x20 }, 561 { STV090x_P1_KREFTMG, 0x5a }, 562 { STV090x_P1_SMAPCOEF7, 0x06 }, 563 { STV090x_P1_SMAPCOEF6, 0x00 }, 564 { STV090x_P1_SMAPCOEF5, 0x04 }, 565 { STV090x_P1_NOSCFG, 0x0c }, 566 { STV090x_GAINLLR_NF4, 0x21 }, 567 { STV090x_GAINLLR_NF5, 0x21 }, 568 { STV090x_GAINLLR_NF6, 0x20 }, 569 { STV090x_GAINLLR_NF7, 0x1F }, 570 { STV090x_GAINLLR_NF8, 0x1E }, 571 { STV090x_GAINLLR_NF9, 0x1E }, 572 { STV090x_GAINLLR_NF10, 0x1D }, 573 { STV090x_GAINLLR_NF11, 0x1B }, 574 { STV090x_GAINLLR_NF12, 0x20 }, 575 { STV090x_GAINLLR_NF13, 0x20 }, 576 { STV090x_GAINLLR_NF14, 0x20 }, 577 { STV090x_GAINLLR_NF15, 0x20 }, 578 { STV090x_GAINLLR_NF16, 0x20 }, 579 { STV090x_GAINLLR_NF17, 0x21 } 580}; 581 582/* Cut 2.0 Long Frame Tracking CR loop */ 583static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = { 584 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 585 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e }, 586 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e }, 587 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d }, 588 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 589 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 590 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 591 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 592 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d }, 593 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d }, 594 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d }, 595 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d }, 596 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d }, 597 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d }, 598 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d } 599}; 600 601/* Cut 3.0 Long Frame Tracking CR loop */ 602static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = { 603 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 604 { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b }, 605 { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, 606 { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, 607 { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b }, 608 { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, 609 { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, 610 { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, 611 { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b }, 612 { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 }, 613 { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a }, 614 { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a }, 615 { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b }, 616 { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b }, 617 { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b } 618}; 619 620/* Cut 2.0 Long Frame Tracking CR Loop */ 621static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = { 622 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 623 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c }, 624 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c }, 625 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c }, 626 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c }, 627 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c }, 628 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c }, 629 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, 630 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, 631 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, 632 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }, 633 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c } 634}; 635 636/* Cut 3.0 Long Frame Tracking CR Loop */ 637static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = { 638 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 639 { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a }, 640 { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a }, 641 { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a }, 642 { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a }, 643 { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a }, 644 { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a }, 645 { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, 646 { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, 647 { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, 648 { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }, 649 { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } 650}; 651 652static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = { 653 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 654 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e }, 655 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e }, 656 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e } 657}; 658 659static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = { 660 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 661 { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b }, 662 { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b }, 663 { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b } 664}; 665 666/* Cut 2.0 Short Frame Tracking CR Loop */ 667static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = { 668 /* MODCOD 2M 5M 10M 20M 30M */ 669 { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d }, 670 { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c }, 671 { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }, 672 { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d } 673}; 674 675/* Cut 3.0 Short Frame Tracking CR Loop */ 676static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = { 677 /* MODCOD 2M 5M 10M 20M 30M */ 678 { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A }, 679 { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 }, 680 { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }, 681 { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A } 682}; 683 684static inline s32 comp2(s32 __x, s32 __width) 685{ 686 if (__width == 32) 687 return __x; 688 else 689 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x; 690} 691 692static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg) 693{ 694 const struct stv090x_config *config = state->config; 695 int ret; 696 697 u8 b0[] = { reg >> 8, reg & 0xff }; 698 u8 buf; 699 700 struct i2c_msg msg[] = { 701 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 }, 702 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 } 703 }; 704 705 ret = i2c_transfer(state->i2c, msg, 2); 706 if (ret != 2) { 707 if (ret != -ERESTARTSYS) 708 dprintk(FE_ERROR, 1, 709 "Read error, Reg=[0x%02x], Status=%d", 710 reg, ret); 711 712 return ret < 0 ? ret : -EREMOTEIO; 713 } 714 if (unlikely(*state->verbose >= FE_DEBUGREG)) 715 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x", 716 reg, buf); 717 718 return (unsigned int) buf; 719} 720 721static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count) 722{ 723 const struct stv090x_config *config = state->config; 724 int ret; 725 u8 buf[2 + count]; 726 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count }; 727 728 buf[0] = reg >> 8; 729 buf[1] = reg & 0xff; 730 memcpy(&buf[2], data, count); 731 732 if (unlikely(*state->verbose >= FE_DEBUGREG)) { 733 int i; 734 735 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg); 736 for (i = 0; i < count; i++) 737 printk(" %02x", data[i]); 738 printk("\n"); 739 } 740 741 ret = i2c_transfer(state->i2c, &i2c_msg, 1); 742 if (ret != 1) { 743 if (ret != -ERESTARTSYS) 744 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d", 745 reg, data[0], count, ret); 746 return ret < 0 ? ret : -EREMOTEIO; 747 } 748 749 return 0; 750} 751 752static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data) 753{ 754 return stv090x_write_regs(state, reg, &data, 1); 755} 756 757static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable) 758{ 759 u32 reg; 760 761 /* 762 * NOTE! A lock is used as a FSM to control the state in which 763 * access is serialized between two tuners on the same demod. 764 * This has nothing to do with a lock to protect a critical section 765 * which may in some other cases be confused with protecting I/O 766 * access to the demodulator gate. 767 * In case of any error, the lock is unlocked and exit within the 768 * relevant operations themselves. 769 */ 770 if (enable) 771 mutex_lock(&state->internal->tuner_lock); 772 773 reg = STV090x_READ_DEMOD(state, I2CRPT); 774 if (enable) { 775 dprintk(FE_DEBUG, 1, "Enable Gate"); 776 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1); 777 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) 778 goto err; 779 780 } else { 781 dprintk(FE_DEBUG, 1, "Disable Gate"); 782 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0); 783 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0) 784 goto err; 785 } 786 787 if (!enable) 788 mutex_unlock(&state->internal->tuner_lock); 789 790 return 0; 791err: 792 dprintk(FE_ERROR, 1, "I/O error"); 793 mutex_unlock(&state->internal->tuner_lock); 794 return -1; 795} 796 797static void stv090x_get_lock_tmg(struct stv090x_state *state) 798{ 799 switch (state->algo) { 800 case STV090x_BLIND_SEARCH: 801 dprintk(FE_DEBUG, 1, "Blind Search"); 802 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/ 803 state->DemodTimeout = 1500; 804 state->FecTimeout = 400; 805 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/ 806 state->DemodTimeout = 1000; 807 state->FecTimeout = 300; 808 } else { /*SR >20Msps*/ 809 state->DemodTimeout = 700; 810 state->FecTimeout = 100; 811 } 812 break; 813 814 case STV090x_COLD_SEARCH: 815 case STV090x_WARM_SEARCH: 816 default: 817 dprintk(FE_DEBUG, 1, "Normal Search"); 818 if (state->srate <= 1000000) { /*SR <=1Msps*/ 819 state->DemodTimeout = 4500; 820 state->FecTimeout = 1700; 821 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */ 822 state->DemodTimeout = 2500; 823 state->FecTimeout = 1100; 824 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */ 825 state->DemodTimeout = 1000; 826 state->FecTimeout = 550; 827 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */ 828 state->DemodTimeout = 700; 829 state->FecTimeout = 250; 830 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */ 831 state->DemodTimeout = 400; 832 state->FecTimeout = 130; 833 } else { /*SR >20Msps*/ 834 state->DemodTimeout = 300; 835 state->FecTimeout = 100; 836 } 837 break; 838 } 839 840 if (state->algo == STV090x_WARM_SEARCH) 841 state->DemodTimeout /= 2; 842} 843 844static int stv090x_set_srate(struct stv090x_state *state, u32 srate) 845{ 846 u32 sym; 847 848 if (srate > 60000000) { 849 sym = (srate << 4); /* SR * 2^16 / master_clk */ 850 sym /= (state->internal->mclk >> 12); 851 } else if (srate > 6000000) { 852 sym = (srate << 6); 853 sym /= (state->internal->mclk >> 10); 854 } else { 855 sym = (srate << 9); 856 sym /= (state->internal->mclk >> 7); 857 } 858 859 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */ 860 goto err; 861 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */ 862 goto err; 863 864 return 0; 865err: 866 dprintk(FE_ERROR, 1, "I/O error"); 867 return -1; 868} 869 870static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate) 871{ 872 u32 sym; 873 874 srate = 105 * (srate / 100); 875 if (srate > 60000000) { 876 sym = (srate << 4); /* SR * 2^16 / master_clk */ 877 sym /= (state->internal->mclk >> 12); 878 } else if (srate > 6000000) { 879 sym = (srate << 6); 880 sym /= (state->internal->mclk >> 10); 881 } else { 882 sym = (srate << 9); 883 sym /= (state->internal->mclk >> 7); 884 } 885 886 if (sym < 0x7fff) { 887 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */ 888 goto err; 889 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */ 890 goto err; 891 } else { 892 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */ 893 goto err; 894 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */ 895 goto err; 896 } 897 898 return 0; 899err: 900 dprintk(FE_ERROR, 1, "I/O error"); 901 return -1; 902} 903 904static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate) 905{ 906 u32 sym; 907 908 srate = 95 * (srate / 100); 909 if (srate > 60000000) { 910 sym = (srate << 4); /* SR * 2^16 / master_clk */ 911 sym /= (state->internal->mclk >> 12); 912 } else if (srate > 6000000) { 913 sym = (srate << 6); 914 sym /= (state->internal->mclk >> 10); 915 } else { 916 sym = (srate << 9); 917 sym /= (state->internal->mclk >> 7); 918 } 919 920 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */ 921 goto err; 922 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */ 923 goto err; 924 return 0; 925err: 926 dprintk(FE_ERROR, 1, "I/O error"); 927 return -1; 928} 929 930static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff) 931{ 932 u32 ro; 933 934 switch (rolloff) { 935 case STV090x_RO_20: 936 ro = 20; 937 break; 938 case STV090x_RO_25: 939 ro = 25; 940 break; 941 case STV090x_RO_35: 942 default: 943 ro = 35; 944 break; 945 } 946 947 return srate + (srate * ro) / 100; 948} 949 950static int stv090x_set_vit_thacq(struct stv090x_state *state) 951{ 952 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0) 953 goto err; 954 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0) 955 goto err; 956 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0) 957 goto err; 958 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0) 959 goto err; 960 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0) 961 goto err; 962 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0) 963 goto err; 964 return 0; 965err: 966 dprintk(FE_ERROR, 1, "I/O error"); 967 return -1; 968} 969 970static int stv090x_set_vit_thtracq(struct stv090x_state *state) 971{ 972 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0) 973 goto err; 974 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0) 975 goto err; 976 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0) 977 goto err; 978 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0) 979 goto err; 980 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0) 981 goto err; 982 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0) 983 goto err; 984 return 0; 985err: 986 dprintk(FE_ERROR, 1, "I/O error"); 987 return -1; 988} 989 990static int stv090x_set_viterbi(struct stv090x_state *state) 991{ 992 switch (state->search_mode) { 993 case STV090x_SEARCH_AUTO: 994 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */ 995 goto err; 996 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */ 997 goto err; 998 break; 999 case STV090x_SEARCH_DVBS1: 1000 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */ 1001 goto err; 1002 switch (state->fec) { 1003 case STV090x_PR12: 1004 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0) 1005 goto err; 1006 break; 1007 1008 case STV090x_PR23: 1009 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0) 1010 goto err; 1011 break; 1012 1013 case STV090x_PR34: 1014 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0) 1015 goto err; 1016 break; 1017 1018 case STV090x_PR56: 1019 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0) 1020 goto err; 1021 break; 1022 1023 case STV090x_PR78: 1024 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0) 1025 goto err; 1026 break; 1027 1028 default: 1029 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */ 1030 goto err; 1031 break; 1032 } 1033 break; 1034 case STV090x_SEARCH_DSS: 1035 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0) 1036 goto err; 1037 switch (state->fec) { 1038 case STV090x_PR12: 1039 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0) 1040 goto err; 1041 break; 1042 1043 case STV090x_PR23: 1044 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0) 1045 goto err; 1046 break; 1047 1048 case STV090x_PR67: 1049 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0) 1050 goto err; 1051 break; 1052 1053 default: 1054 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */ 1055 goto err; 1056 break; 1057 } 1058 break; 1059 default: 1060 break; 1061 } 1062 return 0; 1063err: 1064 dprintk(FE_ERROR, 1, "I/O error"); 1065 return -1; 1066} 1067 1068static int stv090x_stop_modcod(struct stv090x_state *state) 1069{ 1070 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) 1071 goto err; 1072 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0) 1073 goto err; 1074 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0) 1075 goto err; 1076 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0) 1077 goto err; 1078 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0) 1079 goto err; 1080 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0) 1081 goto err; 1082 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0) 1083 goto err; 1084 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0) 1085 goto err; 1086 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0) 1087 goto err; 1088 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0) 1089 goto err; 1090 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0) 1091 goto err; 1092 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0) 1093 goto err; 1094 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0) 1095 goto err; 1096 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0) 1097 goto err; 1098 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0) 1099 goto err; 1100 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0) 1101 goto err; 1102 return 0; 1103err: 1104 dprintk(FE_ERROR, 1, "I/O error"); 1105 return -1; 1106} 1107 1108static int stv090x_activate_modcod(struct stv090x_state *state) 1109{ 1110 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) 1111 goto err; 1112 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0) 1113 goto err; 1114 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0) 1115 goto err; 1116 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0) 1117 goto err; 1118 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0) 1119 goto err; 1120 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0) 1121 goto err; 1122 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0) 1123 goto err; 1124 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0) 1125 goto err; 1126 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0) 1127 goto err; 1128 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0) 1129 goto err; 1130 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0) 1131 goto err; 1132 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0) 1133 goto err; 1134 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0) 1135 goto err; 1136 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0) 1137 goto err; 1138 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0) 1139 goto err; 1140 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0) 1141 goto err; 1142 1143 return 0; 1144err: 1145 dprintk(FE_ERROR, 1, "I/O error"); 1146 return -1; 1147} 1148 1149static int stv090x_activate_modcod_single(struct stv090x_state *state) 1150{ 1151 1152 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) 1153 goto err; 1154 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0) 1155 goto err; 1156 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0) 1157 goto err; 1158 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0) 1159 goto err; 1160 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0) 1161 goto err; 1162 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0) 1163 goto err; 1164 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0) 1165 goto err; 1166 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0) 1167 goto err; 1168 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0) 1169 goto err; 1170 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0) 1171 goto err; 1172 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0) 1173 goto err; 1174 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0) 1175 goto err; 1176 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0) 1177 goto err; 1178 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0) 1179 goto err; 1180 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0) 1181 goto err; 1182 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0) 1183 goto err; 1184 1185 return 0; 1186 1187err: 1188 dprintk(FE_ERROR, 1, "I/O error"); 1189 return -1; 1190} 1191 1192static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable) 1193{ 1194 u32 reg; 1195 1196 switch (state->demod) { 1197 case STV090x_DEMODULATOR_0: 1198 mutex_lock(&state->internal->demod_lock); 1199 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 1200 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable); 1201 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 1202 goto err; 1203 mutex_unlock(&state->internal->demod_lock); 1204 break; 1205 1206 case STV090x_DEMODULATOR_1: 1207 mutex_lock(&state->internal->demod_lock); 1208 reg = stv090x_read_reg(state, STV090x_STOPCLK2); 1209 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable); 1210 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) 1211 goto err; 1212 mutex_unlock(&state->internal->demod_lock); 1213 break; 1214 1215 default: 1216 dprintk(FE_ERROR, 1, "Wrong demodulator!"); 1217 break; 1218 } 1219 return 0; 1220err: 1221 mutex_unlock(&state->internal->demod_lock); 1222 dprintk(FE_ERROR, 1, "I/O error"); 1223 return -1; 1224} 1225 1226static int stv090x_dvbs_track_crl(struct stv090x_state *state) 1227{ 1228 if (state->internal->dev_ver >= 0x30) { 1229 /* Set ACLC BCLC optimised value vs SR */ 1230 if (state->srate >= 15000000) { 1231 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0) 1232 goto err; 1233 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0) 1234 goto err; 1235 } else if ((state->srate >= 7000000) && (15000000 > state->srate)) { 1236 if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0) 1237 goto err; 1238 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0) 1239 goto err; 1240 } else if (state->srate < 7000000) { 1241 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0) 1242 goto err; 1243 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0) 1244 goto err; 1245 } 1246 1247 } else { 1248 /* Cut 2.0 */ 1249 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) 1250 goto err; 1251 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0) 1252 goto err; 1253 } 1254 return 0; 1255err: 1256 dprintk(FE_ERROR, 1, "I/O error"); 1257 return -1; 1258} 1259 1260static int stv090x_delivery_search(struct stv090x_state *state) 1261{ 1262 u32 reg; 1263 1264 switch (state->search_mode) { 1265 case STV090x_SEARCH_DVBS1: 1266 case STV090x_SEARCH_DSS: 1267 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1268 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 1269 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); 1270 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1271 goto err; 1272 1273 /* Activate Viterbi decoder in legacy search, 1274 * do not use FRESVIT1, might impact VITERBI2 1275 */ 1276 if (stv090x_vitclk_ctl(state, 0) < 0) 1277 goto err; 1278 1279 if (stv090x_dvbs_track_crl(state) < 0) 1280 goto err; 1281 1282 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */ 1283 goto err; 1284 1285 if (stv090x_set_vit_thacq(state) < 0) 1286 goto err; 1287 if (stv090x_set_viterbi(state) < 0) 1288 goto err; 1289 break; 1290 1291 case STV090x_SEARCH_DVBS2: 1292 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1293 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); 1294 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); 1295 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1296 goto err; 1297 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 1298 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); 1299 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1300 goto err; 1301 1302 if (stv090x_vitclk_ctl(state, 1) < 0) 1303 goto err; 1304 1305 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */ 1306 goto err; 1307 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0) 1308 goto err; 1309 1310 if (state->internal->dev_ver <= 0x20) { 1311 /* enable S2 carrier loop */ 1312 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0) 1313 goto err; 1314 } else { 1315 /* > Cut 3: Stop carrier 3 */ 1316 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0) 1317 goto err; 1318 } 1319 1320 if (state->demod_mode != STV090x_SINGLE) { 1321 /* Cut 2: enable link during search */ 1322 if (stv090x_activate_modcod(state) < 0) 1323 goto err; 1324 } else { 1325 /* Single demodulator 1326 * Authorize SHORT and LONG frames, 1327 * QPSK, 8PSK, 16APSK and 32APSK 1328 */ 1329 if (stv090x_activate_modcod_single(state) < 0) 1330 goto err; 1331 } 1332 1333 if (stv090x_set_vit_thtracq(state) < 0) 1334 goto err; 1335 break; 1336 1337 case STV090x_SEARCH_AUTO: 1338 default: 1339 /* enable DVB-S2 and DVB-S2 in Auto MODE */ 1340 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1341 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); 1342 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); 1343 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1344 goto err; 1345 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 1346 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); 1347 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1348 goto err; 1349 1350 if (stv090x_vitclk_ctl(state, 0) < 0) 1351 goto err; 1352 1353 if (stv090x_dvbs_track_crl(state) < 0) 1354 goto err; 1355 1356 if (state->internal->dev_ver <= 0x20) { 1357 /* enable S2 carrier loop */ 1358 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0) 1359 goto err; 1360 } else { 1361 /* > Cut 3: Stop carrier 3 */ 1362 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0) 1363 goto err; 1364 } 1365 1366 if (state->demod_mode != STV090x_SINGLE) { 1367 /* Cut 2: enable link during search */ 1368 if (stv090x_activate_modcod(state) < 0) 1369 goto err; 1370 } else { 1371 /* Single demodulator 1372 * Authorize SHORT and LONG frames, 1373 * QPSK, 8PSK, 16APSK and 32APSK 1374 */ 1375 if (stv090x_activate_modcod_single(state) < 0) 1376 goto err; 1377 } 1378 1379 if (stv090x_set_vit_thacq(state) < 0) 1380 goto err; 1381 1382 if (stv090x_set_viterbi(state) < 0) 1383 goto err; 1384 break; 1385 } 1386 return 0; 1387err: 1388 dprintk(FE_ERROR, 1, "I/O error"); 1389 return -1; 1390} 1391 1392static int stv090x_start_search(struct stv090x_state *state) 1393{ 1394 u32 reg, freq_abs; 1395 s16 freq; 1396 1397 /* Reset demodulator */ 1398 reg = STV090x_READ_DEMOD(state, DMDISTATE); 1399 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); 1400 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) 1401 goto err; 1402 1403 if (state->internal->dev_ver <= 0x20) { 1404 if (state->srate <= 5000000) { 1405 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0) 1406 goto err; 1407 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0) 1408 goto err; 1409 if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0) 1410 goto err; 1411 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0) 1412 goto err; 1413 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0) 1414 goto err; 1415 1416 /*enlarge the timing bandwith for Low SR*/ 1417 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) 1418 goto err; 1419 } else { 1420 /* If the symbol rate is >5 Msps 1421 Set The carrier search up and low to auto mode */ 1422 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0) 1423 goto err; 1424 /*reduce the timing bandwith for high SR*/ 1425 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0) 1426 goto err; 1427 } 1428 } else { 1429 /* >= Cut 3 */ 1430 if (state->srate <= 5000000) { 1431 /* enlarge the timing bandwith for Low SR */ 1432 STV090x_WRITE_DEMOD(state, RTCS2, 0x68); 1433 } else { 1434 /* reduce timing bandwith for high SR */ 1435 STV090x_WRITE_DEMOD(state, RTCS2, 0x44); 1436 } 1437 1438 /* Set CFR min and max to manual mode */ 1439 STV090x_WRITE_DEMOD(state, CARCFG, 0x46); 1440 1441 if (state->algo == STV090x_WARM_SEARCH) { 1442 /* WARM Start 1443 * CFR min = -1MHz, 1444 * CFR max = +1MHz 1445 */ 1446 freq_abs = 1000 << 16; 1447 freq_abs /= (state->internal->mclk / 1000); 1448 freq = (s16) freq_abs; 1449 } else { 1450 /* COLD Start 1451 * CFR min =- (SearchRange / 2 + 600KHz) 1452 * CFR max = +(SearchRange / 2 + 600KHz) 1453 * (600KHz for the tuner step size) 1454 */ 1455 freq_abs = (state->search_range / 2000) + 600; 1456 freq_abs = freq_abs << 16; 1457 freq_abs /= (state->internal->mclk / 1000); 1458 freq = (s16) freq_abs; 1459 } 1460 1461 if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0) 1462 goto err; 1463 if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0) 1464 goto err; 1465 1466 freq *= -1; 1467 1468 if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0) 1469 goto err; 1470 if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0) 1471 goto err; 1472 1473 } 1474 1475 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0) 1476 goto err; 1477 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0) 1478 goto err; 1479 1480 if (state->internal->dev_ver >= 0x20) { 1481 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0) 1482 goto err; 1483 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0) 1484 goto err; 1485 1486 if ((state->search_mode == STV090x_DVBS1) || 1487 (state->search_mode == STV090x_DSS) || 1488 (state->search_mode == STV090x_SEARCH_AUTO)) { 1489 1490 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0) 1491 goto err; 1492 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) 1493 goto err; 1494 } 1495 } 1496 1497 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0) 1498 goto err; 1499 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0) 1500 goto err; 1501 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0) 1502 goto err; 1503 1504 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1505 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0); 1506 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); 1507 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1508 goto err; 1509 reg = STV090x_READ_DEMOD(state, DMDCFG2); 1510 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0); 1511 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0) 1512 goto err; 1513 1514 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) 1515 goto err; 1516 1517 if (state->internal->dev_ver >= 0x20) { 1518 /*Frequency offset detector setting*/ 1519 if (state->srate < 2000000) { 1520 if (state->internal->dev_ver <= 0x20) { 1521 /* Cut 2 */ 1522 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0) 1523 goto err; 1524 } else { 1525 /* Cut 3 */ 1526 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0) 1527 goto err; 1528 } 1529 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0) 1530 goto err; 1531 } else if (state->srate < 10000000) { 1532 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0) 1533 goto err; 1534 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0) 1535 goto err; 1536 } else { 1537 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0) 1538 goto err; 1539 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0) 1540 goto err; 1541 } 1542 } else { 1543 if (state->srate < 10000000) { 1544 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0) 1545 goto err; 1546 } else { 1547 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0) 1548 goto err; 1549 } 1550 } 1551 1552 switch (state->algo) { 1553 case STV090x_WARM_SEARCH: 1554 /* The symbol rate and the exact 1555 * carrier Frequency are known 1556 */ 1557 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 1558 goto err; 1559 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) 1560 goto err; 1561 break; 1562 1563 case STV090x_COLD_SEARCH: 1564 /* The symbol rate is known */ 1565 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 1566 goto err; 1567 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) 1568 goto err; 1569 break; 1570 1571 default: 1572 break; 1573 } 1574 return 0; 1575err: 1576 dprintk(FE_ERROR, 1, "I/O error"); 1577 return -1; 1578} 1579 1580static int stv090x_get_agc2_min_level(struct stv090x_state *state) 1581{ 1582 u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg; 1583 s32 i, j, steps, dir; 1584 1585 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 1586 goto err; 1587 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1588 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0); 1589 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); 1590 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1591 goto err; 1592 1593 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */ 1594 goto err; 1595 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0) 1596 goto err; 1597 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */ 1598 goto err; 1599 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0) 1600 goto err; 1601 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */ 1602 goto err; 1603 if (stv090x_set_srate(state, 1000000) < 0) 1604 goto err; 1605 1606 steps = state->search_range / 1000000; 1607 if (steps <= 0) 1608 steps = 1; 1609 1610 dir = 1; 1611 freq_step = (1000000 * 256) / (state->internal->mclk / 256); 1612 freq_init = 0; 1613 1614 for (i = 0; i < steps; i++) { 1615 if (dir > 0) 1616 freq_init = freq_init + (freq_step * i); 1617 else 1618 freq_init = freq_init - (freq_step * i); 1619 1620 dir *= -1; 1621 1622 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */ 1623 goto err; 1624 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0) 1625 goto err; 1626 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0) 1627 goto err; 1628 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */ 1629 goto err; 1630 msleep(10); 1631 1632 agc2 = 0; 1633 for (j = 0; j < 10; j++) { 1634 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | 1635 STV090x_READ_DEMOD(state, AGC2I0); 1636 } 1637 agc2 /= 10; 1638 if (agc2 < agc2_min) 1639 agc2_min = agc2; 1640 } 1641 1642 return agc2_min; 1643err: 1644 dprintk(FE_ERROR, 1, "I/O error"); 1645 return -1; 1646} 1647 1648static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk) 1649{ 1650 u8 r3, r2, r1, r0; 1651 s32 srate, int_1, int_2, tmp_1, tmp_2; 1652 1653 r3 = STV090x_READ_DEMOD(state, SFR3); 1654 r2 = STV090x_READ_DEMOD(state, SFR2); 1655 r1 = STV090x_READ_DEMOD(state, SFR1); 1656 r0 = STV090x_READ_DEMOD(state, SFR0); 1657 1658 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0); 1659 1660 int_1 = clk >> 16; 1661 int_2 = srate >> 16; 1662 1663 tmp_1 = clk % 0x10000; 1664 tmp_2 = srate % 0x10000; 1665 1666 srate = (int_1 * int_2) + 1667 ((int_1 * tmp_2) >> 16) + 1668 ((int_2 * tmp_1) >> 16); 1669 1670 return srate; 1671} 1672 1673static u32 stv090x_srate_srch_coarse(struct stv090x_state *state) 1674{ 1675 struct dvb_frontend *fe = &state->frontend; 1676 1677 int tmg_lock = 0, i; 1678 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq; 1679 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg; 1680 u32 agc2th; 1681 1682 if (state->internal->dev_ver >= 0x30) 1683 agc2th = 0x2e00; 1684 else 1685 agc2th = 0x1f00; 1686 1687 reg = STV090x_READ_DEMOD(state, DMDISTATE); 1688 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */ 1689 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) 1690 goto err; 1691 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0) 1692 goto err; 1693 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) 1694 goto err; 1695 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0) 1696 goto err; 1697 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0) 1698 goto err; 1699 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1700 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1); 1701 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); 1702 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1703 goto err; 1704 1705 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) 1706 goto err; 1707 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0) 1708 goto err; 1709 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) 1710 goto err; 1711 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0) 1712 goto err; 1713 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) 1714 goto err; 1715 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0) 1716 goto err; 1717 1718 if (state->internal->dev_ver >= 0x30) { 1719 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0) 1720 goto err; 1721 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0) 1722 goto err; 1723 1724 } else if (state->internal->dev_ver >= 0x20) { 1725 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0) 1726 goto err; 1727 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0) 1728 goto err; 1729 } 1730 1731 if (state->srate <= 2000000) 1732 car_step = 1000; 1733 else if (state->srate <= 5000000) 1734 car_step = 2000; 1735 else if (state->srate <= 12000000) 1736 car_step = 3000; 1737 else 1738 car_step = 5000; 1739 1740 steps = -1 + ((state->search_range / 1000) / car_step); 1741 steps /= 2; 1742 steps = (2 * steps) + 1; 1743 if (steps < 0) 1744 steps = 1; 1745 else if (steps > 10) { 1746 steps = 11; 1747 car_step = (state->search_range / 1000) / 10; 1748 } 1749 cur_step = 0; 1750 dir = 1; 1751 freq = state->frequency; 1752 1753 while ((!tmg_lock) && (cur_step < steps)) { 1754 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */ 1755 goto err; 1756 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) 1757 goto err; 1758 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) 1759 goto err; 1760 if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0) 1761 goto err; 1762 if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0) 1763 goto err; 1764 /* trigger acquisition */ 1765 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0) 1766 goto err; 1767 msleep(50); 1768 for (i = 0; i < 10; i++) { 1769 reg = STV090x_READ_DEMOD(state, DSTATUS); 1770 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2) 1771 tmg_cpt++; 1772 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | 1773 STV090x_READ_DEMOD(state, AGC2I0); 1774 } 1775 agc2 /= 10; 1776 srate_coarse = stv090x_get_srate(state, state->internal->mclk); 1777 cur_step++; 1778 dir *= -1; 1779 if ((tmg_cpt >= 5) && (agc2 < agc2th) && 1780 (srate_coarse < 50000000) && (srate_coarse > 850000)) 1781 tmg_lock = 1; 1782 else if (cur_step < steps) { 1783 if (dir > 0) 1784 freq += cur_step * car_step; 1785 else 1786 freq -= cur_step * car_step; 1787 1788 /* Setup tuner */ 1789 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 1790 goto err; 1791 1792 if (state->config->tuner_set_frequency) { 1793 if (state->config->tuner_set_frequency(fe, freq) < 0) 1794 goto err_gateoff; 1795 } 1796 1797 if (state->config->tuner_set_bandwidth) { 1798 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) 1799 goto err_gateoff; 1800 } 1801 1802 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 1803 goto err; 1804 1805 msleep(50); 1806 1807 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 1808 goto err; 1809 1810 if (state->config->tuner_get_status) { 1811 if (state->config->tuner_get_status(fe, ®) < 0) 1812 goto err_gateoff; 1813 } 1814 1815 if (reg) 1816 dprintk(FE_DEBUG, 1, "Tuner phase locked"); 1817 else 1818 dprintk(FE_DEBUG, 1, "Tuner unlocked"); 1819 1820 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 1821 goto err; 1822 1823 } 1824 } 1825 if (!tmg_lock) 1826 srate_coarse = 0; 1827 else 1828 srate_coarse = stv090x_get_srate(state, state->internal->mclk); 1829 1830 return srate_coarse; 1831 1832err_gateoff: 1833 stv090x_i2c_gate_ctrl(state, 0); 1834err: 1835 dprintk(FE_ERROR, 1, "I/O error"); 1836 return -1; 1837} 1838 1839static u32 stv090x_srate_srch_fine(struct stv090x_state *state) 1840{ 1841 u32 srate_coarse, freq_coarse, sym, reg; 1842 1843 srate_coarse = stv090x_get_srate(state, state->internal->mclk); 1844 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8; 1845 freq_coarse |= STV090x_READ_DEMOD(state, CFR1); 1846 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ 1847 1848 if (sym < state->srate) 1849 srate_coarse = 0; 1850 else { 1851 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */ 1852 goto err; 1853 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) 1854 goto err; 1855 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0) 1856 goto err; 1857 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0) 1858 goto err; 1859 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0) 1860 goto err; 1861 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1862 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); 1863 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1864 goto err; 1865 1866 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 1867 goto err; 1868 1869 if (state->internal->dev_ver >= 0x30) { 1870 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0) 1871 goto err; 1872 } else if (state->internal->dev_ver >= 0x20) { 1873 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) 1874 goto err; 1875 } 1876 1877 if (srate_coarse > 3000000) { 1878 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ 1879 sym = (sym / 1000) * 65536; 1880 sym /= (state->internal->mclk / 1000); 1881 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) 1882 goto err; 1883 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) 1884 goto err; 1885 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */ 1886 sym = (sym / 1000) * 65536; 1887 sym /= (state->internal->mclk / 1000); 1888 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0) 1889 goto err; 1890 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0) 1891 goto err; 1892 sym = (srate_coarse / 1000) * 65536; 1893 sym /= (state->internal->mclk / 1000); 1894 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) 1895 goto err; 1896 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0) 1897 goto err; 1898 } else { 1899 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */ 1900 sym = (sym / 100) * 65536; 1901 sym /= (state->internal->mclk / 100); 1902 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) 1903 goto err; 1904 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) 1905 goto err; 1906 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */ 1907 sym = (sym / 100) * 65536; 1908 sym /= (state->internal->mclk / 100); 1909 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0) 1910 goto err; 1911 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0) 1912 goto err; 1913 sym = (srate_coarse / 100) * 65536; 1914 sym /= (state->internal->mclk / 100); 1915 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) 1916 goto err; 1917 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0) 1918 goto err; 1919 } 1920 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0) 1921 goto err; 1922 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0) 1923 goto err; 1924 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0) 1925 goto err; 1926 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */ 1927 goto err; 1928 } 1929 1930 return srate_coarse; 1931 1932err: 1933 dprintk(FE_ERROR, 1, "I/O error"); 1934 return -1; 1935} 1936 1937static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout) 1938{ 1939 s32 timer = 0, lock = 0; 1940 u32 reg; 1941 u8 stat; 1942 1943 while ((timer < timeout) && (!lock)) { 1944 reg = STV090x_READ_DEMOD(state, DMDSTATE); 1945 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); 1946 1947 switch (stat) { 1948 case 0: /* searching */ 1949 case 1: /* first PLH detected */ 1950 default: 1951 dprintk(FE_DEBUG, 1, "Demodulator searching .."); 1952 lock = 0; 1953 break; 1954 case 2: /* DVB-S2 mode */ 1955 case 3: /* DVB-S1/legacy mode */ 1956 reg = STV090x_READ_DEMOD(state, DSTATUS); 1957 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); 1958 break; 1959 } 1960 1961 if (!lock) 1962 msleep(10); 1963 else 1964 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK"); 1965 1966 timer += 10; 1967 } 1968 return lock; 1969} 1970 1971static int stv090x_blind_search(struct stv090x_state *state) 1972{ 1973 u32 agc2, reg, srate_coarse; 1974 s32 cpt_fail, agc2_ovflw, i; 1975 u8 k_ref, k_max, k_min; 1976 int coarse_fail = 0; 1977 int lock; 1978 1979 k_max = 110; 1980 k_min = 10; 1981 1982 agc2 = stv090x_get_agc2_min_level(state); 1983 1984 if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) { 1985 lock = 0; 1986 } else { 1987 1988 if (state->internal->dev_ver <= 0x20) { 1989 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0) 1990 goto err; 1991 } else { 1992 /* > Cut 3 */ 1993 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0) 1994 goto err; 1995 } 1996 1997 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0) 1998 goto err; 1999 2000 if (state->internal->dev_ver >= 0x20) { 2001 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0) 2002 goto err; 2003 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0) 2004 goto err; 2005 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0) 2006 goto err; 2007 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */ 2008 goto err; 2009 } 2010 2011 k_ref = k_max; 2012 do { 2013 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0) 2014 goto err; 2015 if (stv090x_srate_srch_coarse(state) != 0) { 2016 srate_coarse = stv090x_srate_srch_fine(state); 2017 if (srate_coarse != 0) { 2018 stv090x_get_lock_tmg(state); 2019 lock = stv090x_get_dmdlock(state, 2020 state->DemodTimeout); 2021 } else { 2022 lock = 0; 2023 } 2024 } else { 2025 cpt_fail = 0; 2026 agc2_ovflw = 0; 2027 for (i = 0; i < 10; i++) { 2028 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) | 2029 STV090x_READ_DEMOD(state, AGC2I0); 2030 if (agc2 >= 0xff00) 2031 agc2_ovflw++; 2032 reg = STV090x_READ_DEMOD(state, DSTATUS2); 2033 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) && 2034 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01)) 2035 2036 cpt_fail++; 2037 } 2038 if ((cpt_fail > 7) || (agc2_ovflw > 7)) 2039 coarse_fail = 1; 2040 2041 lock = 0; 2042 } 2043 k_ref -= 20; 2044 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail)); 2045 } 2046 2047 return lock; 2048 2049err: 2050 dprintk(FE_ERROR, 1, "I/O error"); 2051 return -1; 2052} 2053 2054static int stv090x_chk_tmg(struct stv090x_state *state) 2055{ 2056 u32 reg; 2057 s32 tmg_cpt = 0, i; 2058 u8 freq, tmg_thh, tmg_thl; 2059 int tmg_lock = 0; 2060 2061 freq = STV090x_READ_DEMOD(state, CARFREQ); 2062 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE); 2063 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL); 2064 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0) 2065 goto err; 2066 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0) 2067 goto err; 2068 2069 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2070 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */ 2071 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2072 goto err; 2073 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0) 2074 goto err; 2075 2076 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0) 2077 goto err; 2078 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0) 2079 goto err; 2080 2081 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */ 2082 goto err; 2083 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) 2084 goto err; 2085 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0) 2086 goto err; 2087 2088 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */ 2089 goto err; 2090 msleep(10); 2091 2092 for (i = 0; i < 10; i++) { 2093 reg = STV090x_READ_DEMOD(state, DSTATUS); 2094 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2) 2095 tmg_cpt++; 2096 msleep(1); 2097 } 2098 if (tmg_cpt >= 3) 2099 tmg_lock = 1; 2100 2101 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 2102 goto err; 2103 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */ 2104 goto err; 2105 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */ 2106 goto err; 2107 2108 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0) 2109 goto err; 2110 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0) 2111 goto err; 2112 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0) 2113 goto err; 2114 2115 return tmg_lock; 2116 2117err: 2118 dprintk(FE_ERROR, 1, "I/O error"); 2119 return -1; 2120} 2121 2122static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd) 2123{ 2124 struct dvb_frontend *fe = &state->frontend; 2125 2126 u32 reg; 2127 s32 car_step, steps, cur_step, dir, freq, timeout_lock; 2128 int lock = 0; 2129 2130 if (state->srate >= 10000000) 2131 timeout_lock = timeout_dmd / 3; 2132 else 2133 timeout_lock = timeout_dmd / 2; 2134 2135 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */ 2136 if (!lock) { 2137 if (state->srate >= 10000000) { 2138 if (stv090x_chk_tmg(state)) { 2139 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 2140 goto err; 2141 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) 2142 goto err; 2143 lock = stv090x_get_dmdlock(state, timeout_dmd); 2144 } else { 2145 lock = 0; 2146 } 2147 } else { 2148 if (state->srate <= 4000000) 2149 car_step = 1000; 2150 else if (state->srate <= 7000000) 2151 car_step = 2000; 2152 else if (state->srate <= 10000000) 2153 car_step = 3000; 2154 else 2155 car_step = 5000; 2156 2157 steps = (state->search_range / 1000) / car_step; 2158 steps /= 2; 2159 steps = 2 * (steps + 1); 2160 if (steps < 0) 2161 steps = 2; 2162 else if (steps > 12) 2163 steps = 12; 2164 2165 cur_step = 1; 2166 dir = 1; 2167 2168 if (!lock) { 2169 freq = state->frequency; 2170 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate; 2171 while ((cur_step <= steps) && (!lock)) { 2172 if (dir > 0) 2173 freq += cur_step * car_step; 2174 else 2175 freq -= cur_step * car_step; 2176 2177 /* Setup tuner */ 2178 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 2179 goto err; 2180 2181 if (state->config->tuner_set_frequency) { 2182 if (state->config->tuner_set_frequency(fe, freq) < 0) 2183 goto err_gateoff; 2184 } 2185 2186 if (state->config->tuner_set_bandwidth) { 2187 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) 2188 goto err_gateoff; 2189 } 2190 2191 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 2192 goto err; 2193 2194 msleep(50); 2195 2196 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 2197 goto err; 2198 2199 if (state->config->tuner_get_status) { 2200 if (state->config->tuner_get_status(fe, ®) < 0) 2201 goto err_gateoff; 2202 } 2203 2204 if (reg) 2205 dprintk(FE_DEBUG, 1, "Tuner phase locked"); 2206 else 2207 dprintk(FE_DEBUG, 1, "Tuner unlocked"); 2208 2209 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 2210 goto err; 2211 2212 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c); 2213 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) 2214 goto err; 2215 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) 2216 goto err; 2217 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 2218 goto err; 2219 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) 2220 goto err; 2221 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3)); 2222 2223 dir *= -1; 2224 cur_step++; 2225 } 2226 } 2227 } 2228 } 2229 2230 return lock; 2231 2232err_gateoff: 2233 stv090x_i2c_gate_ctrl(state, 0); 2234err: 2235 dprintk(FE_ERROR, 1, "I/O error"); 2236 return -1; 2237} 2238 2239static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps) 2240{ 2241 s32 timeout, inc, steps_max, srate, car_max; 2242 2243 srate = state->srate; 2244 car_max = state->search_range / 1000; 2245 car_max += car_max / 10; 2246 car_max = 65536 * (car_max / 2); 2247 car_max /= (state->internal->mclk / 1000); 2248 2249 if (car_max > 0x4000) 2250 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */ 2251 2252 inc = srate; 2253 inc /= state->internal->mclk / 1000; 2254 inc *= 256; 2255 inc *= 256; 2256 inc /= 1000; 2257 2258 switch (state->search_mode) { 2259 case STV090x_SEARCH_DVBS1: 2260 case STV090x_SEARCH_DSS: 2261 inc *= 3; /* freq step = 3% of srate */ 2262 timeout = 20; 2263 break; 2264 2265 case STV090x_SEARCH_DVBS2: 2266 inc *= 4; 2267 timeout = 25; 2268 break; 2269 2270 case STV090x_SEARCH_AUTO: 2271 default: 2272 inc *= 3; 2273 timeout = 25; 2274 break; 2275 } 2276 inc /= 100; 2277 if ((inc > car_max) || (inc < 0)) 2278 inc = car_max / 2; /* increment <= 1/8 Mclk */ 2279 2280 timeout *= 27500; /* 27.5 Msps reference */ 2281 if (srate > 0) 2282 timeout /= (srate / 1000); 2283 2284 if ((timeout > 100) || (timeout < 0)) 2285 timeout = 100; 2286 2287 steps_max = (car_max / inc) + 1; /* min steps = 3 */ 2288 if ((steps_max > 100) || (steps_max < 0)) { 2289 steps_max = 100; /* max steps <= 100 */ 2290 inc = car_max / steps_max; 2291 } 2292 *freq_inc = inc; 2293 *timeout_sw = timeout; 2294 *steps = steps_max; 2295 2296 return 0; 2297} 2298 2299static int stv090x_chk_signal(struct stv090x_state *state) 2300{ 2301 s32 offst_car, agc2, car_max; 2302 int no_signal; 2303 2304 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8; 2305 offst_car |= STV090x_READ_DEMOD(state, CFR1); 2306 offst_car = comp2(offst_car, 16); 2307 2308 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8; 2309 agc2 |= STV090x_READ_DEMOD(state, AGC2I0); 2310 car_max = state->search_range / 1000; 2311 2312 car_max += (car_max / 10); /* 10% margin */ 2313 car_max = (65536 * car_max / 2); 2314 car_max /= state->internal->mclk / 1000; 2315 2316 if (car_max > 0x4000) 2317 car_max = 0x4000; 2318 2319 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) { 2320 no_signal = 1; 2321 dprintk(FE_DEBUG, 1, "No Signal"); 2322 } else { 2323 no_signal = 0; 2324 dprintk(FE_DEBUG, 1, "Found Signal"); 2325 } 2326 2327 return no_signal; 2328} 2329 2330static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max) 2331{ 2332 int no_signal, lock = 0; 2333 s32 cpt_step = 0, offst_freq, car_max; 2334 u32 reg; 2335 2336 car_max = state->search_range / 1000; 2337 car_max += (car_max / 10); 2338 car_max = (65536 * car_max / 2); 2339 car_max /= (state->internal->mclk / 1000); 2340 if (car_max > 0x4000) 2341 car_max = 0x4000; 2342 2343 if (zigzag) 2344 offst_freq = 0; 2345 else 2346 offst_freq = -car_max + inc; 2347 2348 do { 2349 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0) 2350 goto err; 2351 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0) 2352 goto err; 2353 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0) 2354 goto err; 2355 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) 2356 goto err; 2357 2358 reg = STV090x_READ_DEMOD(state, PDELCTRL1); 2359 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */ 2360 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 2361 goto err; 2362 2363 if (zigzag) { 2364 if (offst_freq >= 0) 2365 offst_freq = -offst_freq - 2 * inc; 2366 else 2367 offst_freq = -offst_freq; 2368 } else { 2369 offst_freq += 2 * inc; 2370 } 2371 2372 cpt_step++; 2373 2374 lock = stv090x_get_dmdlock(state, timeout); 2375 no_signal = stv090x_chk_signal(state); 2376 2377 } while ((!lock) && 2378 (!no_signal) && 2379 ((offst_freq - inc) < car_max) && 2380 ((offst_freq + inc) > -car_max) && 2381 (cpt_step < steps_max)); 2382 2383 reg = STV090x_READ_DEMOD(state, PDELCTRL1); 2384 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0); 2385 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 2386 goto err; 2387 2388 return lock; 2389err: 2390 dprintk(FE_ERROR, 1, "I/O error"); 2391 return -1; 2392} 2393 2394static int stv090x_sw_algo(struct stv090x_state *state) 2395{ 2396 int no_signal, zigzag, lock = 0; 2397 u32 reg; 2398 2399 s32 dvbs2_fly_wheel; 2400 s32 inc, timeout_step, trials, steps_max; 2401 2402 /* get params */ 2403 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max); 2404 2405 switch (state->search_mode) { 2406 case STV090x_SEARCH_DVBS1: 2407 case STV090x_SEARCH_DSS: 2408 /* accelerate the frequency detector */ 2409 if (state->internal->dev_ver >= 0x20) { 2410 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0) 2411 goto err; 2412 } 2413 2414 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0) 2415 goto err; 2416 zigzag = 0; 2417 break; 2418 2419 case STV090x_SEARCH_DVBS2: 2420 if (state->internal->dev_ver >= 0x20) { 2421 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) 2422 goto err; 2423 } 2424 2425 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0) 2426 goto err; 2427 zigzag = 1; 2428 break; 2429 2430 case STV090x_SEARCH_AUTO: 2431 default: 2432 /* accelerate the frequency detector */ 2433 if (state->internal->dev_ver >= 0x20) { 2434 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0) 2435 goto err; 2436 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) 2437 goto err; 2438 } 2439 2440 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0) 2441 goto err; 2442 zigzag = 0; 2443 break; 2444 } 2445 2446 trials = 0; 2447 do { 2448 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max); 2449 no_signal = stv090x_chk_signal(state); 2450 trials++; 2451 2452 /*run the SW search 2 times maximum*/ 2453 if (lock || no_signal || (trials == 2)) { 2454 /*Check if the demod is not losing lock in DVBS2*/ 2455 if (state->internal->dev_ver >= 0x20) { 2456 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) 2457 goto err; 2458 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) 2459 goto err; 2460 } 2461 2462 reg = STV090x_READ_DEMOD(state, DMDSTATE); 2463 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) { 2464 /*Check if the demod is not losing lock in DVBS2*/ 2465 msleep(timeout_step); 2466 reg = STV090x_READ_DEMOD(state, DMDFLYW); 2467 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD); 2468 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */ 2469 msleep(timeout_step); 2470 reg = STV090x_READ_DEMOD(state, DMDFLYW); 2471 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD); 2472 } 2473 if (dvbs2_fly_wheel < 0xd) { 2474 /*FALSE lock, The demod is loosing lock */ 2475 lock = 0; 2476 if (trials < 2) { 2477 if (state->internal->dev_ver >= 0x20) { 2478 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0) 2479 goto err; 2480 } 2481 2482 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0) 2483 goto err; 2484 } 2485 } 2486 } 2487 } 2488 } while ((!lock) && (trials < 2) && (!no_signal)); 2489 2490 return lock; 2491err: 2492 dprintk(FE_ERROR, 1, "I/O error"); 2493 return -1; 2494} 2495 2496static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state) 2497{ 2498 u32 reg; 2499 enum stv090x_delsys delsys; 2500 2501 reg = STV090x_READ_DEMOD(state, DMDSTATE); 2502 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2) 2503 delsys = STV090x_DVBS2; 2504 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) { 2505 reg = STV090x_READ_DEMOD(state, FECM); 2506 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1) 2507 delsys = STV090x_DSS; 2508 else 2509 delsys = STV090x_DVBS1; 2510 } else { 2511 delsys = STV090x_ERROR; 2512 } 2513 2514 return delsys; 2515} 2516 2517/* in Hz */ 2518static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk) 2519{ 2520 s32 derot, int_1, int_2, tmp_1, tmp_2; 2521 2522 derot = STV090x_READ_DEMOD(state, CFR2) << 16; 2523 derot |= STV090x_READ_DEMOD(state, CFR1) << 8; 2524 derot |= STV090x_READ_DEMOD(state, CFR0); 2525 2526 derot = comp2(derot, 24); 2527 int_1 = mclk >> 12; 2528 int_2 = derot >> 12; 2529 2530 /* carrier_frequency = MasterClock * Reg / 2^24 */ 2531 tmp_1 = mclk % 0x1000; 2532 tmp_2 = derot % 0x1000; 2533 2534 derot = (int_1 * int_2) + 2535 ((int_1 * tmp_2) >> 12) + 2536 ((int_2 * tmp_1) >> 12); 2537 2538 return derot; 2539} 2540 2541static int stv090x_get_viterbi(struct stv090x_state *state) 2542{ 2543 u32 reg, rate; 2544 2545 reg = STV090x_READ_DEMOD(state, VITCURPUN); 2546 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD); 2547 2548 switch (rate) { 2549 case 13: 2550 state->fec = STV090x_PR12; 2551 break; 2552 2553 case 18: 2554 state->fec = STV090x_PR23; 2555 break; 2556 2557 case 21: 2558 state->fec = STV090x_PR34; 2559 break; 2560 2561 case 24: 2562 state->fec = STV090x_PR56; 2563 break; 2564 2565 case 25: 2566 state->fec = STV090x_PR67; 2567 break; 2568 2569 case 26: 2570 state->fec = STV090x_PR78; 2571 break; 2572 2573 default: 2574 state->fec = STV090x_PRERR; 2575 break; 2576 } 2577 2578 return 0; 2579} 2580 2581static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state) 2582{ 2583 struct dvb_frontend *fe = &state->frontend; 2584 2585 u8 tmg; 2586 u32 reg; 2587 s32 i = 0, offst_freq; 2588 2589 msleep(5); 2590 2591 if (state->algo == STV090x_BLIND_SEARCH) { 2592 tmg = STV090x_READ_DEMOD(state, TMGREG2); 2593 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c); 2594 while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) { 2595 tmg = STV090x_READ_DEMOD(state, TMGREG2); 2596 msleep(5); 2597 i += 5; 2598 } 2599 } 2600 state->delsys = stv090x_get_std(state); 2601 2602 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 2603 goto err; 2604 2605 if (state->config->tuner_get_frequency) { 2606 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0) 2607 goto err_gateoff; 2608 } 2609 2610 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 2611 goto err; 2612 2613 offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000; 2614 state->frequency += offst_freq; 2615 2616 if (stv090x_get_viterbi(state) < 0) 2617 goto err; 2618 2619 reg = STV090x_READ_DEMOD(state, DMDMODCOD); 2620 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD); 2621 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01; 2622 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1; 2623 reg = STV090x_READ_DEMOD(state, TMGOBS); 2624 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD); 2625 reg = STV090x_READ_DEMOD(state, FECM); 2626 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD); 2627 2628 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) { 2629 2630 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 2631 goto err; 2632 2633 if (state->config->tuner_get_frequency) { 2634 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0) 2635 goto err_gateoff; 2636 } 2637 2638 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 2639 goto err; 2640 2641 if (abs(offst_freq) <= ((state->search_range / 2000) + 500)) 2642 return STV090x_RANGEOK; 2643 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000)) 2644 return STV090x_RANGEOK; 2645 else 2646 return STV090x_OUTOFRANGE; /* Out of Range */ 2647 } else { 2648 if (abs(offst_freq) <= ((state->search_range / 2000) + 500)) 2649 return STV090x_RANGEOK; 2650 else 2651 return STV090x_OUTOFRANGE; 2652 } 2653 2654 return STV090x_OUTOFRANGE; 2655 2656err_gateoff: 2657 stv090x_i2c_gate_ctrl(state, 0); 2658err: 2659 dprintk(FE_ERROR, 1, "I/O error"); 2660 return -1; 2661} 2662 2663static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate) 2664{ 2665 s32 offst_tmg; 2666 2667 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16; 2668 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8; 2669 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0); 2670 2671 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */ 2672 if (!offst_tmg) 2673 offst_tmg = 1; 2674 2675 offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg); 2676 offst_tmg /= 320; 2677 2678 return offst_tmg; 2679} 2680 2681static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots) 2682{ 2683 u8 aclc = 0x29; 2684 s32 i; 2685 struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low; 2686 2687 if (state->internal->dev_ver == 0x20) { 2688 car_loop = stv090x_s2_crl_cut20; 2689 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20; 2690 car_loop_apsk_low = stv090x_s2_apsk_crl_cut20; 2691 } else { 2692 /* >= Cut 3 */ 2693 car_loop = stv090x_s2_crl_cut30; 2694 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30; 2695 car_loop_apsk_low = stv090x_s2_apsk_crl_cut30; 2696 } 2697 2698 if (modcod < STV090x_QPSK_12) { 2699 i = 0; 2700 while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod)) 2701 i++; 2702 2703 if (i >= 3) 2704 i = 2; 2705 2706 } else { 2707 i = 0; 2708 while ((i < 14) && (modcod != car_loop[i].modcod)) 2709 i++; 2710 2711 if (i >= 14) { 2712 i = 0; 2713 while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod)) 2714 i++; 2715 2716 if (i >= 11) 2717 i = 10; 2718 } 2719 } 2720 2721 if (modcod <= STV090x_QPSK_25) { 2722 if (pilots) { 2723 if (state->srate <= 3000000) 2724 aclc = car_loop_qpsk_low[i].crl_pilots_on_2; 2725 else if (state->srate <= 7000000) 2726 aclc = car_loop_qpsk_low[i].crl_pilots_on_5; 2727 else if (state->srate <= 15000000) 2728 aclc = car_loop_qpsk_low[i].crl_pilots_on_10; 2729 else if (state->srate <= 25000000) 2730 aclc = car_loop_qpsk_low[i].crl_pilots_on_20; 2731 else 2732 aclc = car_loop_qpsk_low[i].crl_pilots_on_30; 2733 } else { 2734 if (state->srate <= 3000000) 2735 aclc = car_loop_qpsk_low[i].crl_pilots_off_2; 2736 else if (state->srate <= 7000000) 2737 aclc = car_loop_qpsk_low[i].crl_pilots_off_5; 2738 else if (state->srate <= 15000000) 2739 aclc = car_loop_qpsk_low[i].crl_pilots_off_10; 2740 else if (state->srate <= 25000000) 2741 aclc = car_loop_qpsk_low[i].crl_pilots_off_20; 2742 else 2743 aclc = car_loop_qpsk_low[i].crl_pilots_off_30; 2744 } 2745 2746 } else if (modcod <= STV090x_8PSK_910) { 2747 if (pilots) { 2748 if (state->srate <= 3000000) 2749 aclc = car_loop[i].crl_pilots_on_2; 2750 else if (state->srate <= 7000000) 2751 aclc = car_loop[i].crl_pilots_on_5; 2752 else if (state->srate <= 15000000) 2753 aclc = car_loop[i].crl_pilots_on_10; 2754 else if (state->srate <= 25000000) 2755 aclc = car_loop[i].crl_pilots_on_20; 2756 else 2757 aclc = car_loop[i].crl_pilots_on_30; 2758 } else { 2759 if (state->srate <= 3000000) 2760 aclc = car_loop[i].crl_pilots_off_2; 2761 else if (state->srate <= 7000000) 2762 aclc = car_loop[i].crl_pilots_off_5; 2763 else if (state->srate <= 15000000) 2764 aclc = car_loop[i].crl_pilots_off_10; 2765 else if (state->srate <= 25000000) 2766 aclc = car_loop[i].crl_pilots_off_20; 2767 else 2768 aclc = car_loop[i].crl_pilots_off_30; 2769 } 2770 } else { /* 16APSK and 32APSK */ 2771 if (state->srate <= 3000000) 2772 aclc = car_loop_apsk_low[i].crl_pilots_on_2; 2773 else if (state->srate <= 7000000) 2774 aclc = car_loop_apsk_low[i].crl_pilots_on_5; 2775 else if (state->srate <= 15000000) 2776 aclc = car_loop_apsk_low[i].crl_pilots_on_10; 2777 else if (state->srate <= 25000000) 2778 aclc = car_loop_apsk_low[i].crl_pilots_on_20; 2779 else 2780 aclc = car_loop_apsk_low[i].crl_pilots_on_30; 2781 } 2782 2783 return aclc; 2784} 2785 2786static u8 stv090x_optimize_carloop_short(struct stv090x_state *state) 2787{ 2788 struct stv090x_short_frame_crloop *short_crl = NULL; 2789 s32 index = 0; 2790 u8 aclc = 0x0b; 2791 2792 switch (state->modulation) { 2793 case STV090x_QPSK: 2794 default: 2795 index = 0; 2796 break; 2797 case STV090x_8PSK: 2798 index = 1; 2799 break; 2800 case STV090x_16APSK: 2801 index = 2; 2802 break; 2803 case STV090x_32APSK: 2804 index = 3; 2805 break; 2806 } 2807 2808 if (state->internal->dev_ver >= 0x30) { 2809 /* Cut 3.0 and up */ 2810 short_crl = stv090x_s2_short_crl_cut30; 2811 } else { 2812 /* Cut 2.0 and up: we don't support cuts older than 2.0 */ 2813 short_crl = stv090x_s2_short_crl_cut20; 2814 } 2815 2816 if (state->srate <= 3000000) 2817 aclc = short_crl[index].crl_2; 2818 else if (state->srate <= 7000000) 2819 aclc = short_crl[index].crl_5; 2820 else if (state->srate <= 15000000) 2821 aclc = short_crl[index].crl_10; 2822 else if (state->srate <= 25000000) 2823 aclc = short_crl[index].crl_20; 2824 else 2825 aclc = short_crl[index].crl_30; 2826 2827 return aclc; 2828} 2829 2830static int stv090x_optimize_track(struct stv090x_state *state) 2831{ 2832 struct dvb_frontend *fe = &state->frontend; 2833 2834 enum stv090x_rolloff rolloff; 2835 enum stv090x_modcod modcod; 2836 2837 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0; 2838 u32 reg; 2839 2840 srate = stv090x_get_srate(state, state->internal->mclk); 2841 srate += stv090x_get_tmgoffst(state, srate); 2842 2843 switch (state->delsys) { 2844 case STV090x_DVBS1: 2845 case STV090x_DSS: 2846 if (state->search_mode == STV090x_SEARCH_AUTO) { 2847 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2848 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 2849 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); 2850 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2851 goto err; 2852 } 2853 reg = STV090x_READ_DEMOD(state, DEMOD); 2854 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff); 2855 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01); 2856 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 2857 goto err; 2858 2859 if (state->internal->dev_ver >= 0x30) { 2860 if (stv090x_get_viterbi(state) < 0) 2861 goto err; 2862 2863 if (state->fec == STV090x_PR12) { 2864 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0) 2865 goto err; 2866 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0) 2867 goto err; 2868 } else { 2869 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0) 2870 goto err; 2871 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0) 2872 goto err; 2873 } 2874 } 2875 2876 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0) 2877 goto err; 2878 break; 2879 2880 case STV090x_DVBS2: 2881 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2882 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); 2883 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); 2884 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2885 goto err; 2886 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0) 2887 goto err; 2888 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0) 2889 goto err; 2890 if (state->frame_len == STV090x_LONG_FRAME) { 2891 reg = STV090x_READ_DEMOD(state, DMDMODCOD); 2892 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD); 2893 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01; 2894 aclc = stv090x_optimize_carloop(state, modcod, pilots); 2895 if (modcod <= STV090x_QPSK_910) { 2896 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc); 2897 } else if (modcod <= STV090x_8PSK_910) { 2898 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2899 goto err; 2900 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0) 2901 goto err; 2902 } 2903 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) { 2904 if (modcod <= STV090x_16APSK_910) { 2905 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2906 goto err; 2907 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0) 2908 goto err; 2909 } else { 2910 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2911 goto err; 2912 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0) 2913 goto err; 2914 } 2915 } 2916 } else { 2917 /*Carrier loop setting for short frame*/ 2918 aclc = stv090x_optimize_carloop_short(state); 2919 if (state->modulation == STV090x_QPSK) { 2920 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0) 2921 goto err; 2922 } else if (state->modulation == STV090x_8PSK) { 2923 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2924 goto err; 2925 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0) 2926 goto err; 2927 } else if (state->modulation == STV090x_16APSK) { 2928 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2929 goto err; 2930 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0) 2931 goto err; 2932 } else if (state->modulation == STV090x_32APSK) { 2933 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0) 2934 goto err; 2935 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0) 2936 goto err; 2937 } 2938 } 2939 2940 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */ 2941 break; 2942 2943 case STV090x_UNKNOWN: 2944 default: 2945 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2946 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 2947 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); 2948 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2949 goto err; 2950 break; 2951 } 2952 2953 f_1 = STV090x_READ_DEMOD(state, CFR2); 2954 f_0 = STV090x_READ_DEMOD(state, CFR1); 2955 reg = STV090x_READ_DEMOD(state, TMGOBS); 2956 rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD); 2957 2958 if (state->algo == STV090x_BLIND_SEARCH) { 2959 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00); 2960 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2961 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00); 2962 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); 2963 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2964 goto err; 2965 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) 2966 goto err; 2967 2968 if (stv090x_set_srate(state, srate) < 0) 2969 goto err; 2970 blind_tune = 1; 2971 2972 if (stv090x_dvbs_track_crl(state) < 0) 2973 goto err; 2974 } 2975 2976 if (state->internal->dev_ver >= 0x20) { 2977 if ((state->search_mode == STV090x_SEARCH_DVBS1) || 2978 (state->search_mode == STV090x_SEARCH_DSS) || 2979 (state->search_mode == STV090x_SEARCH_AUTO)) { 2980 2981 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0) 2982 goto err; 2983 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0) 2984 goto err; 2985 } 2986 } 2987 2988 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 2989 goto err; 2990 2991 /* AUTO tracking MODE */ 2992 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0) 2993 goto err; 2994 /* AUTO tracking MODE */ 2995 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0) 2996 goto err; 2997 2998 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) || 2999 (state->srate < 10000000)) { 3000 /* update initial carrier freq with the found freq offset */ 3001 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) 3002 goto err; 3003 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) 3004 goto err; 3005 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000; 3006 3007 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) { 3008 3009 if (state->algo != STV090x_WARM_SEARCH) { 3010 3011 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 3012 goto err; 3013 3014 if (state->config->tuner_set_bandwidth) { 3015 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) 3016 goto err_gateoff; 3017 } 3018 3019 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 3020 goto err; 3021 3022 } 3023 } 3024 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) 3025 msleep(50); /* blind search: wait 50ms for SR stabilization */ 3026 else 3027 msleep(5); 3028 3029 stv090x_get_lock_tmg(state); 3030 3031 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) { 3032 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 3033 goto err; 3034 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) 3035 goto err; 3036 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) 3037 goto err; 3038 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) 3039 goto err; 3040 3041 i = 0; 3042 3043 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) { 3044 3045 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) 3046 goto err; 3047 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0) 3048 goto err; 3049 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0) 3050 goto err; 3051 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) 3052 goto err; 3053 i++; 3054 } 3055 } 3056 3057 } 3058 3059 if (state->internal->dev_ver >= 0x20) { 3060 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0) 3061 goto err; 3062 } 3063 3064 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS)) 3065 stv090x_set_vit_thtracq(state); 3066 3067 return 0; 3068 3069err_gateoff: 3070 stv090x_i2c_gate_ctrl(state, 0); 3071err: 3072 dprintk(FE_ERROR, 1, "I/O error"); 3073 return -1; 3074} 3075 3076static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout) 3077{ 3078 s32 timer = 0, lock = 0, stat; 3079 u32 reg; 3080 3081 while ((timer < timeout) && (!lock)) { 3082 reg = STV090x_READ_DEMOD(state, DMDSTATE); 3083 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); 3084 3085 switch (stat) { 3086 case 0: /* searching */ 3087 case 1: /* first PLH detected */ 3088 default: 3089 lock = 0; 3090 break; 3091 3092 case 2: /* DVB-S2 mode */ 3093 reg = STV090x_READ_DEMOD(state, PDELSTATUS1); 3094 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD); 3095 break; 3096 3097 case 3: /* DVB-S1/legacy mode */ 3098 reg = STV090x_READ_DEMOD(state, VSTATUSVIT); 3099 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD); 3100 break; 3101 } 3102 if (!lock) { 3103 msleep(10); 3104 timer += 10; 3105 } 3106 } 3107 return lock; 3108} 3109 3110static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec) 3111{ 3112 u32 reg; 3113 s32 timer = 0; 3114 int lock; 3115 3116 lock = stv090x_get_dmdlock(state, timeout_dmd); 3117 if (lock) 3118 lock = stv090x_get_feclock(state, timeout_fec); 3119 3120 if (lock) { 3121 lock = 0; 3122 3123 while ((timer < timeout_fec) && (!lock)) { 3124 reg = STV090x_READ_DEMOD(state, TSSTATUS); 3125 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD); 3126 msleep(1); 3127 timer++; 3128 } 3129 } 3130 3131 return lock; 3132} 3133 3134static int stv090x_set_s2rolloff(struct stv090x_state *state) 3135{ 3136 u32 reg; 3137 3138 if (state->internal->dev_ver <= 0x20) { 3139 /* rolloff to auto mode if DVBS2 */ 3140 reg = STV090x_READ_DEMOD(state, DEMOD); 3141 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00); 3142 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 3143 goto err; 3144 } else { 3145 /* DVB-S2 rolloff to auto mode if DVBS2 */ 3146 reg = STV090x_READ_DEMOD(state, DEMOD); 3147 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00); 3148 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 3149 goto err; 3150 } 3151 return 0; 3152err: 3153 dprintk(FE_ERROR, 1, "I/O error"); 3154 return -1; 3155} 3156 3157 3158static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state) 3159{ 3160 struct dvb_frontend *fe = &state->frontend; 3161 enum stv090x_signal_state signal_state = STV090x_NOCARRIER; 3162 u32 reg; 3163 s32 agc1_power, power_iq = 0, i; 3164 int lock = 0, low_sr = 0, no_signal = 0; 3165 3166 reg = STV090x_READ_DEMOD(state, TSCFGH); 3167 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */ 3168 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) 3169 goto err; 3170 3171 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */ 3172 goto err; 3173 3174 if (state->internal->dev_ver >= 0x20) { 3175 if (state->srate > 5000000) { 3176 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) 3177 goto err; 3178 } else { 3179 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0) 3180 goto err; 3181 } 3182 } 3183 3184 stv090x_get_lock_tmg(state); 3185 3186 if (state->algo == STV090x_BLIND_SEARCH) { 3187 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */ 3188 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */ 3189 goto err; 3190 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0) 3191 goto err; 3192 if (stv090x_set_srate(state, 1000000) < 0) /* inital srate = 1Msps */ 3193 goto err; 3194 } else { 3195 /* known srate */ 3196 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0) 3197 goto err; 3198 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0) 3199 goto err; 3200 3201 if (state->srate < 2000000) { 3202 /* SR < 2MSPS */ 3203 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0) 3204 goto err; 3205 } else { 3206 /* SR >= 2Msps */ 3207 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0) 3208 goto err; 3209 } 3210 3211 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 3212 goto err; 3213 3214 if (state->internal->dev_ver >= 0x20) { 3215 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0) 3216 goto err; 3217 if (state->algo == STV090x_COLD_SEARCH) 3218 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10; 3219 else if (state->algo == STV090x_WARM_SEARCH) 3220 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000; 3221 } 3222 3223 /* if cold start or warm (Symbolrate is known) 3224 * use a Narrow symbol rate scan range 3225 */ 3226 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */ 3227 goto err; 3228 3229 if (stv090x_set_srate(state, state->srate) < 0) 3230 goto err; 3231 3232 if (stv090x_set_max_srate(state, state->internal->mclk, 3233 state->srate) < 0) 3234 goto err; 3235 if (stv090x_set_min_srate(state, state->internal->mclk, 3236 state->srate) < 0) 3237 goto err; 3238 3239 if (state->srate >= 10000000) 3240 low_sr = 0; 3241 else 3242 low_sr = 1; 3243 } 3244 3245 /* Setup tuner */ 3246 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 3247 goto err; 3248 3249 if (state->config->tuner_set_bbgain) { 3250 reg = state->config->tuner_bbgain; 3251 if (reg == 0) 3252 reg = 10; /* default: 10dB */ 3253 if (state->config->tuner_set_bbgain(fe, reg) < 0) 3254 goto err_gateoff; 3255 } 3256 3257 if (state->config->tuner_set_frequency) { 3258 if (state->config->tuner_set_frequency(fe, state->frequency) < 0) 3259 goto err_gateoff; 3260 } 3261 3262 if (state->config->tuner_set_bandwidth) { 3263 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0) 3264 goto err_gateoff; 3265 } 3266 3267 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 3268 goto err; 3269 3270 msleep(50); 3271 3272 if (state->config->tuner_get_status) { 3273 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 3274 goto err; 3275 if (state->config->tuner_get_status(fe, ®) < 0) 3276 goto err_gateoff; 3277 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 3278 goto err; 3279 3280 if (reg) 3281 dprintk(FE_DEBUG, 1, "Tuner phase locked"); 3282 else { 3283 dprintk(FE_DEBUG, 1, "Tuner unlocked"); 3284 return STV090x_NOCARRIER; 3285 } 3286 } 3287 3288 msleep(10); 3289 agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1), 3290 STV090x_READ_DEMOD(state, AGCIQIN0)); 3291 3292 if (agc1_power == 0) { 3293 /* If AGC1 integrator value is 0 3294 * then read POWERI, POWERQ 3295 */ 3296 for (i = 0; i < 5; i++) { 3297 power_iq += (STV090x_READ_DEMOD(state, POWERI) + 3298 STV090x_READ_DEMOD(state, POWERQ)) >> 1; 3299 } 3300 power_iq /= 5; 3301 } 3302 3303 if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) { 3304 dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq); 3305 lock = 0; 3306 signal_state = STV090x_NOAGC1; 3307 } else { 3308 reg = STV090x_READ_DEMOD(state, DEMOD); 3309 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion); 3310 3311 if (state->internal->dev_ver <= 0x20) { 3312 /* rolloff to auto mode if DVBS2 */ 3313 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1); 3314 } else { 3315 /* DVB-S2 rolloff to auto mode if DVBS2 */ 3316 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1); 3317 } 3318 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 3319 goto err; 3320 3321 if (stv090x_delivery_search(state) < 0) 3322 goto err; 3323 3324 if (state->algo != STV090x_BLIND_SEARCH) { 3325 if (stv090x_start_search(state) < 0) 3326 goto err; 3327 } 3328 } 3329 3330 if (signal_state == STV090x_NOAGC1) 3331 return signal_state; 3332 3333 if (state->algo == STV090x_BLIND_SEARCH) 3334 lock = stv090x_blind_search(state); 3335 3336 else if (state->algo == STV090x_COLD_SEARCH) 3337 lock = stv090x_get_coldlock(state, state->DemodTimeout); 3338 3339 else if (state->algo == STV090x_WARM_SEARCH) 3340 lock = stv090x_get_dmdlock(state, state->DemodTimeout); 3341 3342 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) { 3343 if (!low_sr) { 3344 if (stv090x_chk_tmg(state)) 3345 lock = stv090x_sw_algo(state); 3346 } 3347 } 3348 3349 if (lock) 3350 signal_state = stv090x_get_sig_params(state); 3351 3352 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */ 3353 stv090x_optimize_track(state); 3354 3355 if (state->internal->dev_ver >= 0x20) { 3356 /* >= Cut 2.0 :release TS reset after 3357 * demod lock and optimized Tracking 3358 */ 3359 reg = STV090x_READ_DEMOD(state, TSCFGH); 3360 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */ 3361 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) 3362 goto err; 3363 3364 msleep(3); 3365 3366 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */ 3367 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) 3368 goto err; 3369 3370 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */ 3371 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) 3372 goto err; 3373 } 3374 3375 lock = stv090x_get_lock(state, state->FecTimeout, 3376 state->FecTimeout); 3377 if (lock) { 3378 if (state->delsys == STV090x_DVBS2) { 3379 stv090x_set_s2rolloff(state); 3380 3381 reg = STV090x_READ_DEMOD(state, PDELCTRL2); 3382 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1); 3383 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0) 3384 goto err; 3385 /* Reset DVBS2 packet delinator error counter */ 3386 reg = STV090x_READ_DEMOD(state, PDELCTRL2); 3387 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0); 3388 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0) 3389 goto err; 3390 3391 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */ 3392 goto err; 3393 } else { 3394 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0) 3395 goto err; 3396 } 3397 /* Reset the Total packet counter */ 3398 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0) 3399 goto err; 3400 /* Reset the packet Error counter2 */ 3401 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0) 3402 goto err; 3403 } else { 3404 signal_state = STV090x_NODATA; 3405 no_signal = stv090x_chk_signal(state); 3406 } 3407 } 3408 return signal_state; 3409 3410err_gateoff: 3411 stv090x_i2c_gate_ctrl(state, 0); 3412err: 3413 dprintk(FE_ERROR, 1, "I/O error"); 3414 return -1; 3415} 3416 3417static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) 3418{ 3419 struct stv090x_state *state = fe->demodulator_priv; 3420 struct dtv_frontend_properties *props = &fe->dtv_property_cache; 3421 3422 if (p->frequency == 0) 3423 return DVBFE_ALGO_SEARCH_INVALID; 3424 3425 state->delsys = props->delivery_system; 3426 state->frequency = p->frequency; 3427 state->srate = p->u.qpsk.symbol_rate; 3428 state->search_mode = STV090x_SEARCH_AUTO; 3429 state->algo = STV090x_COLD_SEARCH; 3430 state->fec = STV090x_PRERR; 3431 if (state->srate > 10000000) { 3432 dprintk(FE_DEBUG, 1, "Search range: 10 MHz"); 3433 state->search_range = 10000000; 3434 } else { 3435 dprintk(FE_DEBUG, 1, "Search range: 5 MHz"); 3436 state->search_range = 5000000; 3437 } 3438 3439 if (stv090x_algo(state) == STV090x_RANGEOK) { 3440 dprintk(FE_DEBUG, 1, "Search success!"); 3441 return DVBFE_ALGO_SEARCH_SUCCESS; 3442 } else { 3443 dprintk(FE_DEBUG, 1, "Search failed!"); 3444 return DVBFE_ALGO_SEARCH_FAILED; 3445 } 3446 3447 return DVBFE_ALGO_SEARCH_ERROR; 3448} 3449 3450static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status) 3451{ 3452 struct stv090x_state *state = fe->demodulator_priv; 3453 u32 reg; 3454 u8 search_state; 3455 3456 reg = STV090x_READ_DEMOD(state, DMDSTATE); 3457 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); 3458 3459 switch (search_state) { 3460 case 0: /* searching */ 3461 case 1: /* first PLH detected */ 3462 default: 3463 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)"); 3464 *status = 0; 3465 break; 3466 3467 case 2: /* DVB-S2 mode */ 3468 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2"); 3469 reg = STV090x_READ_DEMOD(state, DSTATUS); 3470 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) { 3471 reg = STV090x_READ_DEMOD(state, PDELSTATUS1); 3472 if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) { 3473 reg = STV090x_READ_DEMOD(state, TSSTATUS); 3474 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) { 3475 *status = FE_HAS_SIGNAL | 3476 FE_HAS_CARRIER | 3477 FE_HAS_VITERBI | 3478 FE_HAS_SYNC | 3479 FE_HAS_LOCK; 3480 } 3481 } 3482 } 3483 break; 3484 3485 case 3: /* DVB-S1/legacy mode */ 3486 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S"); 3487 reg = STV090x_READ_DEMOD(state, DSTATUS); 3488 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) { 3489 reg = STV090x_READ_DEMOD(state, VSTATUSVIT); 3490 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) { 3491 reg = STV090x_READ_DEMOD(state, TSSTATUS); 3492 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) { 3493 *status = FE_HAS_SIGNAL | 3494 FE_HAS_CARRIER | 3495 FE_HAS_VITERBI | 3496 FE_HAS_SYNC | 3497 FE_HAS_LOCK; 3498 } 3499 } 3500 } 3501 break; 3502 } 3503 3504 return 0; 3505} 3506 3507static int stv090x_read_per(struct dvb_frontend *fe, u32 *per) 3508{ 3509 struct stv090x_state *state = fe->demodulator_priv; 3510 3511 s32 count_4, count_3, count_2, count_1, count_0, count; 3512 u32 reg, h, m, l; 3513 enum fe_status status; 3514 3515 stv090x_read_status(fe, &status); 3516 if (!(status & FE_HAS_LOCK)) { 3517 *per = 1 << 23; /* Max PER */ 3518 } else { 3519 /* Counter 2 */ 3520 reg = STV090x_READ_DEMOD(state, ERRCNT22); 3521 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD); 3522 3523 reg = STV090x_READ_DEMOD(state, ERRCNT21); 3524 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD); 3525 3526 reg = STV090x_READ_DEMOD(state, ERRCNT20); 3527 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD); 3528 3529 *per = ((h << 16) | (m << 8) | l); 3530 3531 count_4 = STV090x_READ_DEMOD(state, FBERCPT4); 3532 count_3 = STV090x_READ_DEMOD(state, FBERCPT3); 3533 count_2 = STV090x_READ_DEMOD(state, FBERCPT2); 3534 count_1 = STV090x_READ_DEMOD(state, FBERCPT1); 3535 count_0 = STV090x_READ_DEMOD(state, FBERCPT0); 3536 3537 if ((!count_4) && (!count_3)) { 3538 count = (count_2 & 0xff) << 16; 3539 count |= (count_1 & 0xff) << 8; 3540 count |= count_0 & 0xff; 3541 } else { 3542 count = 1 << 24; 3543 } 3544 if (count == 0) 3545 *per = 1; 3546 } 3547 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0) 3548 goto err; 3549 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0) 3550 goto err; 3551 3552 return 0; 3553err: 3554 dprintk(FE_ERROR, 1, "I/O error"); 3555 return -1; 3556} 3557 3558static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val) 3559{ 3560 int res = 0; 3561 int min = 0, med; 3562 3563 if ((val >= tab[min].read && val < tab[max].read) || 3564 (val >= tab[max].read && val < tab[min].read)) { 3565 while ((max - min) > 1) { 3566 med = (max + min) / 2; 3567 if ((val >= tab[min].read && val < tab[med].read) || 3568 (val >= tab[med].read && val < tab[min].read)) 3569 max = med; 3570 else 3571 min = med; 3572 } 3573 res = ((val - tab[min].read) * 3574 (tab[max].real - tab[min].real) / 3575 (tab[max].read - tab[min].read)) + 3576 tab[min].real; 3577 } else { 3578 if (tab[min].read < tab[max].read) { 3579 if (val < tab[min].read) 3580 res = tab[min].real; 3581 else if (val >= tab[max].read) 3582 res = tab[max].real; 3583 } else { 3584 if (val >= tab[min].read) 3585 res = tab[min].real; 3586 else if (val < tab[max].read) 3587 res = tab[max].real; 3588 } 3589 } 3590 3591 return res; 3592} 3593 3594static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 3595{ 3596 struct stv090x_state *state = fe->demodulator_priv; 3597 u32 reg; 3598 s32 agc_0, agc_1, agc; 3599 s32 str; 3600 3601 reg = STV090x_READ_DEMOD(state, AGCIQIN1); 3602 agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD); 3603 reg = STV090x_READ_DEMOD(state, AGCIQIN0); 3604 agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD); 3605 agc = MAKEWORD16(agc_1, agc_0); 3606 3607 str = stv090x_table_lookup(stv090x_rf_tab, 3608 ARRAY_SIZE(stv090x_rf_tab) - 1, agc); 3609 if (agc > stv090x_rf_tab[0].read) 3610 str = 0; 3611 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read) 3612 str = -100; 3613 *strength = (str + 100) * 0xFFFF / 100; 3614 3615 return 0; 3616} 3617 3618static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr) 3619{ 3620 struct stv090x_state *state = fe->demodulator_priv; 3621 u32 reg_0, reg_1, reg, i; 3622 s32 val_0, val_1, val = 0; 3623 u8 lock_f; 3624 s32 div; 3625 u32 last; 3626 3627 switch (state->delsys) { 3628 case STV090x_DVBS2: 3629 reg = STV090x_READ_DEMOD(state, DSTATUS); 3630 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); 3631 if (lock_f) { 3632 msleep(5); 3633 for (i = 0; i < 16; i++) { 3634 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1); 3635 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD); 3636 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0); 3637 val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD); 3638 val += MAKEWORD16(val_1, val_0); 3639 msleep(1); 3640 } 3641 val /= 16; 3642 last = ARRAY_SIZE(stv090x_s2cn_tab) - 1; 3643 div = stv090x_s2cn_tab[0].read - 3644 stv090x_s2cn_tab[last].read; 3645 *cnr = 0xFFFF - ((val * 0xFFFF) / div); 3646 } 3647 break; 3648 3649 case STV090x_DVBS1: 3650 case STV090x_DSS: 3651 reg = STV090x_READ_DEMOD(state, DSTATUS); 3652 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); 3653 if (lock_f) { 3654 msleep(5); 3655 for (i = 0; i < 16; i++) { 3656 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1); 3657 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD); 3658 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0); 3659 val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD); 3660 val += MAKEWORD16(val_1, val_0); 3661 msleep(1); 3662 } 3663 val /= 16; 3664 last = ARRAY_SIZE(stv090x_s1cn_tab) - 1; 3665 div = stv090x_s1cn_tab[0].read - 3666 stv090x_s1cn_tab[last].read; 3667 *cnr = 0xFFFF - ((val * 0xFFFF) / div); 3668 } 3669 break; 3670 default: 3671 break; 3672 } 3673 3674 return 0; 3675} 3676 3677static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) 3678{ 3679 struct stv090x_state *state = fe->demodulator_priv; 3680 u32 reg; 3681 3682 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3683 switch (tone) { 3684 case SEC_TONE_ON: 3685 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0); 3686 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); 3687 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3688 goto err; 3689 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); 3690 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3691 goto err; 3692 break; 3693 3694 case SEC_TONE_OFF: 3695 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0); 3696 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); 3697 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3698 goto err; 3699 break; 3700 default: 3701 return -EINVAL; 3702 } 3703 3704 return 0; 3705err: 3706 dprintk(FE_ERROR, 1, "I/O error"); 3707 return -1; 3708} 3709 3710 3711static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe) 3712{ 3713 return DVBFE_ALGO_CUSTOM; 3714} 3715 3716static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd) 3717{ 3718 struct stv090x_state *state = fe->demodulator_priv; 3719 u32 reg, idle = 0, fifo_full = 1; 3720 int i; 3721 3722 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3723 3724 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 3725 (state->config->diseqc_envelope_mode) ? 4 : 2); 3726 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); 3727 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3728 goto err; 3729 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); 3730 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3731 goto err; 3732 3733 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1); 3734 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3735 goto err; 3736 3737 for (i = 0; i < cmd->msg_len; i++) { 3738 3739 while (fifo_full) { 3740 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); 3741 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD); 3742 } 3743 3744 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0) 3745 goto err; 3746 } 3747 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3748 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0); 3749 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3750 goto err; 3751 3752 i = 0; 3753 3754 while ((!idle) && (i < 10)) { 3755 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); 3756 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD); 3757 msleep(10); 3758 i++; 3759 } 3760 3761 return 0; 3762err: 3763 dprintk(FE_ERROR, 1, "I/O error"); 3764 return -1; 3765} 3766 3767static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst) 3768{ 3769 struct stv090x_state *state = fe->demodulator_priv; 3770 u32 reg, idle = 0, fifo_full = 1; 3771 u8 mode, value; 3772 int i; 3773 3774 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3775 3776 if (burst == SEC_MINI_A) { 3777 mode = (state->config->diseqc_envelope_mode) ? 5 : 3; 3778 value = 0x00; 3779 } else { 3780 mode = (state->config->diseqc_envelope_mode) ? 4 : 2; 3781 value = 0xFF; 3782 } 3783 3784 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode); 3785 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); 3786 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3787 goto err; 3788 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); 3789 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3790 goto err; 3791 3792 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1); 3793 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3794 goto err; 3795 3796 while (fifo_full) { 3797 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); 3798 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD); 3799 } 3800 3801 if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0) 3802 goto err; 3803 3804 reg = STV090x_READ_DEMOD(state, DISTXCTL); 3805 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0); 3806 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) 3807 goto err; 3808 3809 i = 0; 3810 3811 while ((!idle) && (i < 10)) { 3812 reg = STV090x_READ_DEMOD(state, DISTXSTATUS); 3813 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD); 3814 msleep(10); 3815 i++; 3816 } 3817 3818 return 0; 3819err: 3820 dprintk(FE_ERROR, 1, "I/O error"); 3821 return -1; 3822} 3823 3824static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply) 3825{ 3826 struct stv090x_state *state = fe->demodulator_priv; 3827 u32 reg = 0, i = 0, rx_end = 0; 3828 3829 while ((rx_end != 1) && (i < 10)) { 3830 msleep(10); 3831 i++; 3832 reg = STV090x_READ_DEMOD(state, DISRX_ST0); 3833 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD); 3834 } 3835 3836 if (rx_end) { 3837 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD); 3838 for (i = 0; i < reply->msg_len; i++) 3839 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA); 3840 } 3841 3842 return 0; 3843} 3844 3845static int stv090x_sleep(struct dvb_frontend *fe) 3846{ 3847 struct stv090x_state *state = fe->demodulator_priv; 3848 u32 reg; 3849 3850 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 3851 goto err; 3852 3853 if (state->config->tuner_sleep) { 3854 if (state->config->tuner_sleep(fe) < 0) 3855 goto err_gateoff; 3856 } 3857 3858 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 3859 goto err; 3860 3861 dprintk(FE_DEBUG, 1, "Set %s to sleep", 3862 state->device == STV0900 ? "STV0900" : "STV0903"); 3863 3864 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); 3865 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01); 3866 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) 3867 goto err; 3868 3869 reg = stv090x_read_reg(state, STV090x_TSTTNR1); 3870 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0); 3871 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) 3872 goto err; 3873 3874 return 0; 3875 3876err_gateoff: 3877 stv090x_i2c_gate_ctrl(state, 0); 3878err: 3879 dprintk(FE_ERROR, 1, "I/O error"); 3880 return -1; 3881} 3882 3883static int stv090x_wakeup(struct dvb_frontend *fe) 3884{ 3885 struct stv090x_state *state = fe->demodulator_priv; 3886 u32 reg; 3887 3888 dprintk(FE_DEBUG, 1, "Wake %s from standby", 3889 state->device == STV0900 ? "STV0900" : "STV0903"); 3890 3891 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); 3892 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00); 3893 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) 3894 goto err; 3895 3896 reg = stv090x_read_reg(state, STV090x_TSTTNR1); 3897 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1); 3898 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) 3899 goto err; 3900 3901 return 0; 3902err: 3903 dprintk(FE_ERROR, 1, "I/O error"); 3904 return -1; 3905} 3906 3907static void stv090x_release(struct dvb_frontend *fe) 3908{ 3909 struct stv090x_state *state = fe->demodulator_priv; 3910 3911 state->internal->num_used--; 3912 if (state->internal->num_used <= 0) { 3913 3914 dprintk(FE_ERROR, 1, "Actually removing"); 3915 3916 remove_dev(state->internal); 3917 kfree(state->internal); 3918 } 3919 3920 kfree(state); 3921} 3922 3923static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode) 3924{ 3925 u32 reg = 0; 3926 3927 reg = stv090x_read_reg(state, STV090x_GENCFG); 3928 3929 switch (ldpc_mode) { 3930 case STV090x_DUAL: 3931 default: 3932 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) { 3933 /* set LDPC to dual mode */ 3934 if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0) 3935 goto err; 3936 3937 state->demod_mode = STV090x_DUAL; 3938 3939 reg = stv090x_read_reg(state, STV090x_TSTRES0); 3940 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1); 3941 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) 3942 goto err; 3943 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0); 3944 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) 3945 goto err; 3946 3947 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0) 3948 goto err; 3949 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0) 3950 goto err; 3951 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0) 3952 goto err; 3953 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0) 3954 goto err; 3955 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0) 3956 goto err; 3957 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0) 3958 goto err; 3959 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0) 3960 goto err; 3961 3962 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0) 3963 goto err; 3964 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0) 3965 goto err; 3966 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0) 3967 goto err; 3968 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0) 3969 goto err; 3970 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0) 3971 goto err; 3972 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0) 3973 goto err; 3974 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0) 3975 goto err; 3976 3977 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0) 3978 goto err; 3979 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0) 3980 goto err; 3981 } 3982 break; 3983 3984 case STV090x_SINGLE: 3985 if (stv090x_stop_modcod(state) < 0) 3986 goto err; 3987 if (stv090x_activate_modcod_single(state) < 0) 3988 goto err; 3989 3990 if (state->demod == STV090x_DEMODULATOR_1) { 3991 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */ 3992 goto err; 3993 } else { 3994 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */ 3995 goto err; 3996 } 3997 3998 reg = stv090x_read_reg(state, STV090x_TSTRES0); 3999 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1); 4000 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) 4001 goto err; 4002 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0); 4003 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) 4004 goto err; 4005 4006 reg = STV090x_READ_DEMOD(state, PDELCTRL1); 4007 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01); 4008 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 4009 goto err; 4010 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00); 4011 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) 4012 goto err; 4013 break; 4014 } 4015 4016 return 0; 4017err: 4018 dprintk(FE_ERROR, 1, "I/O error"); 4019 return -1; 4020} 4021 4022/* return (Hz), clk in Hz*/ 4023static u32 stv090x_get_mclk(struct stv090x_state *state) 4024{ 4025 const struct stv090x_config *config = state->config; 4026 u32 div, reg; 4027 u8 ratio; 4028 4029 div = stv090x_read_reg(state, STV090x_NCOARSE); 4030 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); 4031 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6; 4032 4033 return (div + 1) * config->xtal / ratio; /* kHz */ 4034} 4035 4036static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk) 4037{ 4038 const struct stv090x_config *config = state->config; 4039 u32 reg, div, clk_sel; 4040 4041 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); 4042 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6); 4043 4044 div = ((clk_sel * mclk) / config->xtal) - 1; 4045 4046 reg = stv090x_read_reg(state, STV090x_NCOARSE); 4047 STV090x_SETFIELD(reg, M_DIV_FIELD, div); 4048 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0) 4049 goto err; 4050 4051 state->internal->mclk = stv090x_get_mclk(state); 4052 4053 /*Set the DiseqC frequency to 22KHz */ 4054 div = state->internal->mclk / 704000; 4055 if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0) 4056 goto err; 4057 if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0) 4058 goto err; 4059 4060 return 0; 4061err: 4062 dprintk(FE_ERROR, 1, "I/O error"); 4063 return -1; 4064} 4065 4066static int stv090x_set_tspath(struct stv090x_state *state) 4067{ 4068 u32 reg; 4069 4070 if (state->internal->dev_ver >= 0x20) { 4071 switch (state->config->ts1_mode) { 4072 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4073 case STV090x_TSMODE_DVBCI: 4074 switch (state->config->ts2_mode) { 4075 case STV090x_TSMODE_SERIAL_PUNCTURED: 4076 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4077 default: 4078 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00); 4079 break; 4080 4081 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4082 case STV090x_TSMODE_DVBCI: 4083 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */ 4084 goto err; 4085 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4086 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4087 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4088 goto err; 4089 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM); 4090 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4091 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0) 4092 goto err; 4093 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0) 4094 goto err; 4095 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0) 4096 goto err; 4097 break; 4098 } 4099 break; 4100 4101 case STV090x_TSMODE_SERIAL_PUNCTURED: 4102 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4103 default: 4104 switch (state->config->ts2_mode) { 4105 case STV090x_TSMODE_SERIAL_PUNCTURED: 4106 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4107 default: 4108 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0) 4109 goto err; 4110 break; 4111 4112 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4113 case STV090x_TSMODE_DVBCI: 4114 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0) 4115 goto err; 4116 break; 4117 } 4118 break; 4119 } 4120 } else { 4121 switch (state->config->ts1_mode) { 4122 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4123 case STV090x_TSMODE_DVBCI: 4124 switch (state->config->ts2_mode) { 4125 case STV090x_TSMODE_SERIAL_PUNCTURED: 4126 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4127 default: 4128 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10); 4129 break; 4130 4131 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4132 case STV090x_TSMODE_DVBCI: 4133 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16); 4134 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4135 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4136 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4137 goto err; 4138 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4139 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0); 4140 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4141 goto err; 4142 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0) 4143 goto err; 4144 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0) 4145 goto err; 4146 break; 4147 } 4148 break; 4149 4150 case STV090x_TSMODE_SERIAL_PUNCTURED: 4151 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4152 default: 4153 switch (state->config->ts2_mode) { 4154 case STV090x_TSMODE_SERIAL_PUNCTURED: 4155 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4156 default: 4157 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14); 4158 break; 4159 4160 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4161 case STV090x_TSMODE_DVBCI: 4162 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12); 4163 break; 4164 } 4165 break; 4166 } 4167 } 4168 4169 switch (state->config->ts1_mode) { 4170 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4171 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4172 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4173 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4174 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4175 goto err; 4176 break; 4177 4178 case STV090x_TSMODE_DVBCI: 4179 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4180 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4181 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4182 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4183 goto err; 4184 break; 4185 4186 case STV090x_TSMODE_SERIAL_PUNCTURED: 4187 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4188 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4189 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4190 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4191 goto err; 4192 break; 4193 4194 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4195 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4196 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4197 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4198 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4199 goto err; 4200 break; 4201 4202 default: 4203 break; 4204 } 4205 4206 switch (state->config->ts2_mode) { 4207 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4208 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4209 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4210 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4211 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4212 goto err; 4213 break; 4214 4215 case STV090x_TSMODE_DVBCI: 4216 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4217 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4218 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4219 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4220 goto err; 4221 break; 4222 4223 case STV090x_TSMODE_SERIAL_PUNCTURED: 4224 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4225 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4226 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4227 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4228 goto err; 4229 break; 4230 4231 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4232 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4233 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4234 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4235 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4236 goto err; 4237 break; 4238 4239 default: 4240 break; 4241 } 4242 4243 if (state->config->ts1_clk > 0) { 4244 u32 speed; 4245 4246 switch (state->config->ts1_mode) { 4247 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4248 case STV090x_TSMODE_DVBCI: 4249 default: 4250 speed = state->internal->mclk / 4251 (state->config->ts1_clk / 4); 4252 if (speed < 0x08) 4253 speed = 0x08; 4254 if (speed > 0xFF) 4255 speed = 0xFF; 4256 break; 4257 case STV090x_TSMODE_SERIAL_PUNCTURED: 4258 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4259 speed = state->internal->mclk / 4260 (state->config->ts1_clk / 32); 4261 if (speed < 0x20) 4262 speed = 0x20; 4263 if (speed > 0xFF) 4264 speed = 0xFF; 4265 break; 4266 } 4267 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); 4268 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4269 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) 4270 goto err; 4271 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0) 4272 goto err; 4273 } 4274 4275 if (state->config->ts2_clk > 0) { 4276 u32 speed; 4277 4278 switch (state->config->ts2_mode) { 4279 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4280 case STV090x_TSMODE_DVBCI: 4281 default: 4282 speed = state->internal->mclk / 4283 (state->config->ts2_clk / 4); 4284 if (speed < 0x08) 4285 speed = 0x08; 4286 if (speed > 0xFF) 4287 speed = 0xFF; 4288 break; 4289 case STV090x_TSMODE_SERIAL_PUNCTURED: 4290 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4291 speed = state->internal->mclk / 4292 (state->config->ts2_clk / 32); 4293 if (speed < 0x20) 4294 speed = 0x20; 4295 if (speed > 0xFF) 4296 speed = 0xFF; 4297 break; 4298 } 4299 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM); 4300 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); 4301 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0) 4302 goto err; 4303 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0) 4304 goto err; 4305 } 4306 4307 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4308 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); 4309 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4310 goto err; 4311 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); 4312 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4313 goto err; 4314 4315 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4316 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); 4317 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4318 goto err; 4319 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); 4320 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4321 goto err; 4322 4323 return 0; 4324err: 4325 dprintk(FE_ERROR, 1, "I/O error"); 4326 return -1; 4327} 4328 4329static int stv090x_init(struct dvb_frontend *fe) 4330{ 4331 struct stv090x_state *state = fe->demodulator_priv; 4332 const struct stv090x_config *config = state->config; 4333 u32 reg; 4334 4335 if (state->internal->mclk == 0) { 4336 /* call tuner init to configure the tuner's clock output 4337 divider directly before setting up the master clock of 4338 the stv090x. */ 4339 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 4340 goto err; 4341 4342 if (config->tuner_init) { 4343 if (config->tuner_init(fe) < 0) 4344 goto err_gateoff; 4345 } 4346 4347 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 4348 goto err; 4349 4350 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */ 4351 msleep(5); 4352 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 4353 0x20 | config->clk_mode) < 0) 4354 goto err; 4355 stv090x_get_mclk(state); 4356 } 4357 4358 if (stv090x_wakeup(fe) < 0) { 4359 dprintk(FE_ERROR, 1, "Error waking device"); 4360 goto err; 4361 } 4362 4363 if (stv090x_ldpc_mode(state, state->demod_mode) < 0) 4364 goto err; 4365 4366 reg = STV090x_READ_DEMOD(state, TNRCFG2); 4367 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion); 4368 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0) 4369 goto err; 4370 reg = STV090x_READ_DEMOD(state, DEMOD); 4371 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff); 4372 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) 4373 goto err; 4374 4375 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 4376 goto err; 4377 4378 if (config->tuner_set_mode) { 4379 if (config->tuner_set_mode(fe, TUNER_WAKE) < 0) 4380 goto err_gateoff; 4381 } 4382 4383 if (config->tuner_init) { 4384 if (config->tuner_init(fe) < 0) 4385 goto err_gateoff; 4386 } 4387 4388 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 4389 goto err; 4390 4391 if (stv090x_set_tspath(state) < 0) 4392 goto err; 4393 4394 return 0; 4395 4396err_gateoff: 4397 stv090x_i2c_gate_ctrl(state, 0); 4398err: 4399 dprintk(FE_ERROR, 1, "I/O error"); 4400 return -1; 4401} 4402 4403static int stv090x_setup(struct dvb_frontend *fe) 4404{ 4405 struct stv090x_state *state = fe->demodulator_priv; 4406 const struct stv090x_config *config = state->config; 4407 const struct stv090x_reg *stv090x_initval = NULL; 4408 const struct stv090x_reg *stv090x_cut20_val = NULL; 4409 unsigned long t1_size = 0, t2_size = 0; 4410 u32 reg = 0; 4411 4412 int i; 4413 4414 if (state->device == STV0900) { 4415 dprintk(FE_DEBUG, 1, "Initializing STV0900"); 4416 stv090x_initval = stv0900_initval; 4417 t1_size = ARRAY_SIZE(stv0900_initval); 4418 stv090x_cut20_val = stv0900_cut20_val; 4419 t2_size = ARRAY_SIZE(stv0900_cut20_val); 4420 } else if (state->device == STV0903) { 4421 dprintk(FE_DEBUG, 1, "Initializing STV0903"); 4422 stv090x_initval = stv0903_initval; 4423 t1_size = ARRAY_SIZE(stv0903_initval); 4424 stv090x_cut20_val = stv0903_cut20_val; 4425 t2_size = ARRAY_SIZE(stv0903_cut20_val); 4426 } 4427 4428 /* STV090x init */ 4429 4430 /* Stop Demod */ 4431 if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0) 4432 goto err; 4433 if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0) 4434 goto err; 4435 4436 msleep(5); 4437 4438 /* Set No Tuner Mode */ 4439 if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0) 4440 goto err; 4441 if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0) 4442 goto err; 4443 4444 /* I2C repeater OFF */ 4445 STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level); 4446 if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0) 4447 goto err; 4448 if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0) 4449 goto err; 4450 4451 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */ 4452 goto err; 4453 msleep(5); 4454 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */ 4455 goto err; 4456 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */ 4457 goto err; 4458 msleep(5); 4459 4460 /* write initval */ 4461 dprintk(FE_DEBUG, 1, "Setting up initial values"); 4462 for (i = 0; i < t1_size; i++) { 4463 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0) 4464 goto err; 4465 } 4466 4467 state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID); 4468 if (state->internal->dev_ver >= 0x20) { 4469 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0) 4470 goto err; 4471 4472 /* write cut20_val*/ 4473 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values"); 4474 for (i = 0; i < t2_size; i++) { 4475 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0) 4476 goto err; 4477 } 4478 4479 } else if (state->internal->dev_ver < 0x20) { 4480 dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!", 4481 state->internal->dev_ver); 4482 4483 goto err; 4484 } else if (state->internal->dev_ver > 0x30) { 4485 /* we shouldn't bail out from here */ 4486 dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!", 4487 state->internal->dev_ver); 4488 } 4489 4490 /* ADC1 range */ 4491 reg = stv090x_read_reg(state, STV090x_TSTTNR1); 4492 STV090x_SETFIELD(reg, ADC1_INMODE_FIELD, 4493 (config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1); 4494 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) 4495 goto err; 4496 4497 /* ADC2 range */ 4498 reg = stv090x_read_reg(state, STV090x_TSTTNR3); 4499 STV090x_SETFIELD(reg, ADC2_INMODE_FIELD, 4500 (config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1); 4501 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) 4502 goto err; 4503 4504 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0) 4505 goto err; 4506 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0) 4507 goto err; 4508 4509 if (config->diseqc_envelope_mode) 4510 stv090x_send_diseqc_burst(fe, SEC_MINI_A); 4511 4512 return 0; 4513err: 4514 dprintk(FE_ERROR, 1, "I/O error"); 4515 return -1; 4516} 4517 4518static struct dvb_frontend_ops stv090x_ops = { 4519 4520 .info = { 4521 .name = "STV090x Multistandard", 4522 .type = FE_QPSK, 4523 .frequency_min = 950000, 4524 .frequency_max = 2150000, 4525 .frequency_stepsize = 0, 4526 .frequency_tolerance = 0, 4527 .symbol_rate_min = 1000000, 4528 .symbol_rate_max = 45000000, 4529 .caps = FE_CAN_INVERSION_AUTO | 4530 FE_CAN_FEC_AUTO | 4531 FE_CAN_QPSK | 4532 FE_CAN_2G_MODULATION 4533 }, 4534 4535 .release = stv090x_release, 4536 .init = stv090x_init, 4537 4538 .sleep = stv090x_sleep, 4539 .get_frontend_algo = stv090x_frontend_algo, 4540 4541 .diseqc_send_master_cmd = stv090x_send_diseqc_msg, 4542 .diseqc_send_burst = stv090x_send_diseqc_burst, 4543 .diseqc_recv_slave_reply = stv090x_recv_slave_reply, 4544 .set_tone = stv090x_set_tone, 4545 4546 .search = stv090x_search, 4547 .read_status = stv090x_read_status, 4548 .read_ber = stv090x_read_per, 4549 .read_signal_strength = stv090x_read_signal_strength, 4550 .read_snr = stv090x_read_cnr 4551}; 4552 4553 4554struct dvb_frontend *stv090x_attach(const struct stv090x_config *config, 4555 struct i2c_adapter *i2c, 4556 enum stv090x_demodulator demod) 4557{ 4558 struct stv090x_state *state = NULL; 4559 struct stv090x_dev *temp_int; 4560 4561 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL); 4562 if (state == NULL) 4563 goto error; 4564 4565 state->verbose = &verbose; 4566 state->config = config; 4567 state->i2c = i2c; 4568 state->frontend.ops = stv090x_ops; 4569 state->frontend.demodulator_priv = state; 4570 state->demod = demod; 4571 state->demod_mode = config->demod_mode; /* Single or Dual mode */ 4572 state->device = config->device; 4573 state->rolloff = STV090x_RO_35; /* default */ 4574 4575 temp_int = find_dev(state->i2c, 4576 state->config->address); 4577 4578 if ((temp_int != NULL) && (state->demod_mode == STV090x_DUAL)) { 4579 state->internal = temp_int->internal; 4580 state->internal->num_used++; 4581 dprintk(FE_INFO, 1, "Found Internal Structure!"); 4582 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x", 4583 state->device == STV0900 ? "STV0900" : "STV0903", 4584 demod, 4585 state->internal->dev_ver); 4586 return &state->frontend; 4587 } else { 4588 state->internal = kmalloc(sizeof(struct stv090x_internal), 4589 GFP_KERNEL); 4590 temp_int = append_internal(state->internal); 4591 state->internal->num_used = 1; 4592 state->internal->mclk = 0; 4593 state->internal->dev_ver = 0; 4594 state->internal->i2c_adap = state->i2c; 4595 state->internal->i2c_addr = state->config->address; 4596 dprintk(FE_INFO, 1, "Create New Internal Structure!"); 4597 } 4598 4599 mutex_init(&state->internal->demod_lock); 4600 mutex_init(&state->internal->tuner_lock); 4601 4602 if (stv090x_sleep(&state->frontend) < 0) { 4603 dprintk(FE_ERROR, 1, "Error putting device to sleep"); 4604 goto error; 4605 } 4606 4607 if (stv090x_setup(&state->frontend) < 0) { 4608 dprintk(FE_ERROR, 1, "Error setting up device"); 4609 goto error; 4610 } 4611 if (stv090x_wakeup(&state->frontend) < 0) { 4612 dprintk(FE_ERROR, 1, "Error waking device"); 4613 goto error; 4614 } 4615 4616 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x", 4617 state->device == STV0900 ? "STV0900" : "STV0903", 4618 demod, 4619 state->internal->dev_ver); 4620 4621 return &state->frontend; 4622 4623error: 4624 kfree(state); 4625 return NULL; 4626} 4627EXPORT_SYMBOL(stv090x_attach); 4628MODULE_PARM_DESC(verbose, "Set Verbosity level"); 4629MODULE_AUTHOR("Manu Abraham"); 4630MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend"); 4631MODULE_LICENSE("GPL"); 4632