1/* 2 driver for LSI L64781 COFDM demodulator 3 4 Copyright (C) 2001 Holger Waechtler for Convergence Integrated Media GmbH 5 Marko Kohtala <marko.kohtala@luukku.com> 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 21*/ 22 23#include <linux/init.h> 24#include <linux/kernel.h> 25#include <linux/module.h> 26#include <linux/string.h> 27#include <linux/slab.h> 28#include "dvb_frontend.h" 29#include "l64781.h" 30 31 32struct l64781_state { 33 struct i2c_adapter* i2c; 34 const struct l64781_config* config; 35 struct dvb_frontend frontend; 36 37 /* private demodulator data */ 38 unsigned int first:1; 39}; 40 41#define dprintk(args...) \ 42 do { \ 43 if (debug) printk(KERN_DEBUG "l64781: " args); \ 44 } while (0) 45 46static int debug; 47 48module_param(debug, int, 0644); 49MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); 50 51 52static int l64781_writereg (struct l64781_state* state, u8 reg, u8 data) 53{ 54 int ret; 55 u8 buf [] = { reg, data }; 56 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; 57 58 if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1) 59 dprintk ("%s: write_reg error (reg == %02x) = %02x!\n", 60 __func__, reg, ret); 61 62 return (ret != 1) ? -1 : 0; 63} 64 65static int l64781_readreg (struct l64781_state* state, u8 reg) 66{ 67 int ret; 68 u8 b0 [] = { reg }; 69 u8 b1 [] = { 0 }; 70 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 }, 71 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; 72 73 ret = i2c_transfer(state->i2c, msg, 2); 74 75 if (ret != 2) return ret; 76 77 return b1[0]; 78} 79 80static void apply_tps (struct l64781_state* state) 81{ 82 l64781_writereg (state, 0x2a, 0x00); 83 l64781_writereg (state, 0x2a, 0x01); 84 85 /* This here is a little bit questionable because it enables 86 the automatic update of TPS registers. I think we'd need to 87 handle the IRQ from FE to update some other registers as 88 well, or at least implement some magic to tuning to correct 89 to the TPS received from transmission. */ 90 l64781_writereg (state, 0x2a, 0x02); 91} 92 93 94static void reset_afc (struct l64781_state* state) 95{ 96 /* Set AFC stall for the AFC_INIT_FRQ setting, TIM_STALL for 97 timing offset */ 98 l64781_writereg (state, 0x07, 0x9e); /* stall AFC */ 99 l64781_writereg (state, 0x08, 0); /* AFC INIT FREQ */ 100 l64781_writereg (state, 0x09, 0); 101 l64781_writereg (state, 0x0a, 0); 102 l64781_writereg (state, 0x07, 0x8e); 103 l64781_writereg (state, 0x0e, 0); /* AGC gain to zero in beginning */ 104 l64781_writereg (state, 0x11, 0x80); /* stall TIM */ 105 l64781_writereg (state, 0x10, 0); /* TIM_OFFSET_LSB */ 106 l64781_writereg (state, 0x12, 0); 107 l64781_writereg (state, 0x13, 0); 108 l64781_writereg (state, 0x11, 0x00); 109} 110 111static int reset_and_configure (struct l64781_state* state) 112{ 113 u8 buf [] = { 0x06 }; 114 struct i2c_msg msg = { .addr = 0x00, .flags = 0, .buf = buf, .len = 1 }; 115 // NOTE: this is correct in writing to address 0x00 116 117 return (i2c_transfer(state->i2c, &msg, 1) == 1) ? 0 : -ENODEV; 118} 119 120static int apply_frontend_param (struct dvb_frontend* fe, struct dvb_frontend_parameters *param) 121{ 122 struct l64781_state* state = fe->demodulator_priv; 123 /* The coderates for FEC_NONE, FEC_4_5 and FEC_FEC_6_7 are arbitrary */ 124 static const u8 fec_tab[] = { 7, 0, 1, 2, 9, 3, 10, 4 }; 125 /* QPSK, QAM_16, QAM_64 */ 126 static const u8 qam_tab [] = { 2, 4, 0, 6 }; 127 static const u8 bw_tab [] = { 8, 7, 6 }; /* 8Mhz, 7MHz, 6MHz */ 128 static const u8 guard_tab [] = { 1, 2, 4, 8 }; 129 /* The Grundig 29504-401.04 Tuner comes with 18.432MHz crystal. */ 130 static const u32 ppm = 8000; 131 struct dvb_ofdm_parameters *p = ¶m->u.ofdm; 132 u32 ddfs_offset_fixed; 133/* u32 ddfs_offset_variable = 0x6000-((1000000UL+ppm)/ */ 134/* bw_tab[p->bandWidth]<<10)/15625; */ 135 u32 init_freq; 136 u32 spi_bias; 137 u8 val0x04; 138 u8 val0x05; 139 u8 val0x06; 140 int bw = p->bandwidth - BANDWIDTH_8_MHZ; 141 142 if (fe->ops.tuner_ops.set_params) { 143 fe->ops.tuner_ops.set_params(fe, param); 144 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 145 } 146 147 if (param->inversion != INVERSION_ON && 148 param->inversion != INVERSION_OFF) 149 return -EINVAL; 150 151 if (bw < 0 || bw > 2) 152 return -EINVAL; 153 154 if (p->code_rate_HP != FEC_1_2 && p->code_rate_HP != FEC_2_3 && 155 p->code_rate_HP != FEC_3_4 && p->code_rate_HP != FEC_5_6 && 156 p->code_rate_HP != FEC_7_8) 157 return -EINVAL; 158 159 if (p->hierarchy_information != HIERARCHY_NONE && 160 (p->code_rate_LP != FEC_1_2 && p->code_rate_LP != FEC_2_3 && 161 p->code_rate_LP != FEC_3_4 && p->code_rate_LP != FEC_5_6 && 162 p->code_rate_LP != FEC_7_8)) 163 return -EINVAL; 164 165 if (p->constellation != QPSK && p->constellation != QAM_16 && 166 p->constellation != QAM_64) 167 return -EINVAL; 168 169 if (p->transmission_mode != TRANSMISSION_MODE_2K && 170 p->transmission_mode != TRANSMISSION_MODE_8K) 171 return -EINVAL; 172 173 if (p->guard_interval < GUARD_INTERVAL_1_32 || 174 p->guard_interval > GUARD_INTERVAL_1_4) 175 return -EINVAL; 176 177 if (p->hierarchy_information < HIERARCHY_NONE || 178 p->hierarchy_information > HIERARCHY_4) 179 return -EINVAL; 180 181 ddfs_offset_fixed = 0x4000-(ppm<<16)/bw_tab[p->bandwidth]/1000000; 182 183 /* This works up to 20000 ppm, it overflows if too large ppm! */ 184 init_freq = (((8UL<<25) + (8UL<<19) / 25*ppm / (15625/25)) / 185 bw_tab[p->bandwidth] & 0xFFFFFF); 186 187 /* SPI bias calculation is slightly modified to fit in 32bit */ 188 /* will work for high ppm only... */ 189 spi_bias = 378 * (1 << 10); 190 spi_bias *= 16; 191 spi_bias *= bw_tab[p->bandwidth]; 192 spi_bias *= qam_tab[p->constellation]; 193 spi_bias /= p->code_rate_HP + 1; 194 spi_bias /= (guard_tab[p->guard_interval] + 32); 195 spi_bias *= 1000; 196 spi_bias /= 1000 + ppm/1000; 197 spi_bias *= p->code_rate_HP; 198 199 val0x04 = (p->transmission_mode << 2) | p->guard_interval; 200 val0x05 = fec_tab[p->code_rate_HP]; 201 202 if (p->hierarchy_information != HIERARCHY_NONE) 203 val0x05 |= (p->code_rate_LP - FEC_1_2) << 3; 204 205 val0x06 = (p->hierarchy_information << 2) | p->constellation; 206 207 l64781_writereg (state, 0x04, val0x04); 208 l64781_writereg (state, 0x05, val0x05); 209 l64781_writereg (state, 0x06, val0x06); 210 211 reset_afc (state); 212 213 /* Technical manual section 2.6.1, TIM_IIR_GAIN optimal values */ 214 l64781_writereg (state, 0x15, 215 p->transmission_mode == TRANSMISSION_MODE_2K ? 1 : 3); 216 l64781_writereg (state, 0x16, init_freq & 0xff); 217 l64781_writereg (state, 0x17, (init_freq >> 8) & 0xff); 218 l64781_writereg (state, 0x18, (init_freq >> 16) & 0xff); 219 220 l64781_writereg (state, 0x1b, spi_bias & 0xff); 221 l64781_writereg (state, 0x1c, (spi_bias >> 8) & 0xff); 222 l64781_writereg (state, 0x1d, ((spi_bias >> 16) & 0x7f) | 223 (param->inversion == INVERSION_ON ? 0x80 : 0x00)); 224 225 l64781_writereg (state, 0x22, ddfs_offset_fixed & 0xff); 226 l64781_writereg (state, 0x23, (ddfs_offset_fixed >> 8) & 0x3f); 227 228 l64781_readreg (state, 0x00); /* clear interrupt registers... */ 229 l64781_readreg (state, 0x01); /* dto. */ 230 231 apply_tps (state); 232 233 return 0; 234} 235 236static int get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters* param) 237{ 238 struct l64781_state* state = fe->demodulator_priv; 239 int tmp; 240 241 242 tmp = l64781_readreg(state, 0x04); 243 switch(tmp & 3) { 244 case 0: 245 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; 246 break; 247 case 1: 248 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; 249 break; 250 case 2: 251 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; 252 break; 253 case 3: 254 param->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; 255 break; 256 } 257 switch((tmp >> 2) & 3) { 258 case 0: 259 param->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; 260 break; 261 case 1: 262 param->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; 263 break; 264 default: 265 printk("Unexpected value for transmission_mode\n"); 266 } 267 268 269 270 tmp = l64781_readreg(state, 0x05); 271 switch(tmp & 7) { 272 case 0: 273 param->u.ofdm.code_rate_HP = FEC_1_2; 274 break; 275 case 1: 276 param->u.ofdm.code_rate_HP = FEC_2_3; 277 break; 278 case 2: 279 param->u.ofdm.code_rate_HP = FEC_3_4; 280 break; 281 case 3: 282 param->u.ofdm.code_rate_HP = FEC_5_6; 283 break; 284 case 4: 285 param->u.ofdm.code_rate_HP = FEC_7_8; 286 break; 287 default: 288 printk("Unexpected value for code_rate_HP\n"); 289 } 290 switch((tmp >> 3) & 7) { 291 case 0: 292 param->u.ofdm.code_rate_LP = FEC_1_2; 293 break; 294 case 1: 295 param->u.ofdm.code_rate_LP = FEC_2_3; 296 break; 297 case 2: 298 param->u.ofdm.code_rate_LP = FEC_3_4; 299 break; 300 case 3: 301 param->u.ofdm.code_rate_LP = FEC_5_6; 302 break; 303 case 4: 304 param->u.ofdm.code_rate_LP = FEC_7_8; 305 break; 306 default: 307 printk("Unexpected value for code_rate_LP\n"); 308 } 309 310 311 tmp = l64781_readreg(state, 0x06); 312 switch(tmp & 3) { 313 case 0: 314 param->u.ofdm.constellation = QPSK; 315 break; 316 case 1: 317 param->u.ofdm.constellation = QAM_16; 318 break; 319 case 2: 320 param->u.ofdm.constellation = QAM_64; 321 break; 322 default: 323 printk("Unexpected value for constellation\n"); 324 } 325 switch((tmp >> 2) & 7) { 326 case 0: 327 param->u.ofdm.hierarchy_information = HIERARCHY_NONE; 328 break; 329 case 1: 330 param->u.ofdm.hierarchy_information = HIERARCHY_1; 331 break; 332 case 2: 333 param->u.ofdm.hierarchy_information = HIERARCHY_2; 334 break; 335 case 3: 336 param->u.ofdm.hierarchy_information = HIERARCHY_4; 337 break; 338 default: 339 printk("Unexpected value for hierarchy\n"); 340 } 341 342 343 tmp = l64781_readreg (state, 0x1d); 344 param->inversion = (tmp & 0x80) ? INVERSION_ON : INVERSION_OFF; 345 346 tmp = (int) (l64781_readreg (state, 0x08) | 347 (l64781_readreg (state, 0x09) << 8) | 348 (l64781_readreg (state, 0x0a) << 16)); 349 param->frequency += tmp; 350 351 return 0; 352} 353 354static int l64781_read_status(struct dvb_frontend* fe, fe_status_t* status) 355{ 356 struct l64781_state* state = fe->demodulator_priv; 357 int sync = l64781_readreg (state, 0x32); 358 int gain = l64781_readreg (state, 0x0e); 359 360 l64781_readreg (state, 0x00); /* clear interrupt registers... */ 361 l64781_readreg (state, 0x01); /* dto. */ 362 363 *status = 0; 364 365 if (gain > 5) 366 *status |= FE_HAS_SIGNAL; 367 368 if (sync & 0x02) /* VCXO locked, this criteria should be ok */ 369 *status |= FE_HAS_CARRIER; 370 371 if (sync & 0x20) 372 *status |= FE_HAS_VITERBI; 373 374 if (sync & 0x40) 375 *status |= FE_HAS_SYNC; 376 377 if (sync == 0x7f) 378 *status |= FE_HAS_LOCK; 379 380 return 0; 381} 382 383static int l64781_read_ber(struct dvb_frontend* fe, u32* ber) 384{ 385 struct l64781_state* state = fe->demodulator_priv; 386 387 *ber = l64781_readreg (state, 0x39) 388 | (l64781_readreg (state, 0x3a) << 8); 389 390 return 0; 391} 392 393static int l64781_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength) 394{ 395 struct l64781_state* state = fe->demodulator_priv; 396 397 u8 gain = l64781_readreg (state, 0x0e); 398 *signal_strength = (gain << 8) | gain; 399 400 return 0; 401} 402 403static int l64781_read_snr(struct dvb_frontend* fe, u16* snr) 404{ 405 struct l64781_state* state = fe->demodulator_priv; 406 407 u8 avg_quality = 0xff - l64781_readreg (state, 0x33); 408 *snr = (avg_quality << 8) | avg_quality; /* not exact, but...*/ 409 410 return 0; 411} 412 413static int l64781_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) 414{ 415 struct l64781_state* state = fe->demodulator_priv; 416 417 *ucblocks = l64781_readreg (state, 0x37) 418 | (l64781_readreg (state, 0x38) << 8); 419 420 return 0; 421} 422 423static int l64781_sleep(struct dvb_frontend* fe) 424{ 425 struct l64781_state* state = fe->demodulator_priv; 426 427 /* Power down */ 428 return l64781_writereg (state, 0x3e, 0x5a); 429} 430 431static int l64781_init(struct dvb_frontend* fe) 432{ 433 struct l64781_state* state = fe->demodulator_priv; 434 435 reset_and_configure (state); 436 437 /* Power up */ 438 l64781_writereg (state, 0x3e, 0xa5); 439 440 /* Reset hard */ 441 l64781_writereg (state, 0x2a, 0x04); 442 l64781_writereg (state, 0x2a, 0x00); 443 444 /* Set tuner specific things */ 445 /* AFC_POL, set also in reset_afc */ 446 l64781_writereg (state, 0x07, 0x8e); 447 448 /* Use internal ADC */ 449 l64781_writereg (state, 0x0b, 0x81); 450 451 /* AGC loop gain, and polarity is positive */ 452 l64781_writereg (state, 0x0c, 0x84); 453 454 /* Internal ADC outputs two's complement */ 455 l64781_writereg (state, 0x0d, 0x8c); 456 457 /* With ppm=8000, it seems the DTR_SENSITIVITY will result in 458 value of 2 with all possible bandwidths and guard 459 intervals, which is the initial value anyway. */ 460 /*l64781_writereg (state, 0x19, 0x92);*/ 461 462 /* Everything is two's complement, soft bit and CSI_OUT too */ 463 l64781_writereg (state, 0x1e, 0x09); 464 465 /* delay a bit after first init attempt */ 466 if (state->first) { 467 state->first = 0; 468 msleep(200); 469 } 470 471 return 0; 472} 473 474static int l64781_get_tune_settings(struct dvb_frontend* fe, 475 struct dvb_frontend_tune_settings* fesettings) 476{ 477 fesettings->min_delay_ms = 4000; 478 fesettings->step_size = 0; 479 fesettings->max_drift = 0; 480 return 0; 481} 482 483static void l64781_release(struct dvb_frontend* fe) 484{ 485 struct l64781_state* state = fe->demodulator_priv; 486 kfree(state); 487} 488 489static struct dvb_frontend_ops l64781_ops; 490 491struct dvb_frontend* l64781_attach(const struct l64781_config* config, 492 struct i2c_adapter* i2c) 493{ 494 struct l64781_state* state = NULL; 495 int reg0x3e = -1; 496 u8 b0 [] = { 0x1a }; 497 u8 b1 [] = { 0x00 }; 498 struct i2c_msg msg [] = { { .addr = config->demod_address, .flags = 0, .buf = b0, .len = 1 }, 499 { .addr = config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; 500 501 /* allocate memory for the internal state */ 502 state = kzalloc(sizeof(struct l64781_state), GFP_KERNEL); 503 if (state == NULL) goto error; 504 505 /* setup the state */ 506 state->config = config; 507 state->i2c = i2c; 508 state->first = 1; 509 510 /** 511 * the L64781 won't show up before we send the reset_and_configure() 512 * broadcast. If nothing responds there is no L64781 on the bus... 513 */ 514 if (reset_and_configure(state) < 0) { 515 dprintk("No response to reset and configure broadcast...\n"); 516 goto error; 517 } 518 519 /* The chip always responds to reads */ 520 if (i2c_transfer(state->i2c, msg, 2) != 2) { 521 dprintk("No response to read on I2C bus\n"); 522 goto error; 523 } 524 525 /* Save current register contents for bailout */ 526 reg0x3e = l64781_readreg(state, 0x3e); 527 528 /* Reading the POWER_DOWN register always returns 0 */ 529 if (reg0x3e != 0) { 530 dprintk("Device doesn't look like L64781\n"); 531 goto error; 532 } 533 534 /* Turn the chip off */ 535 l64781_writereg (state, 0x3e, 0x5a); 536 537 /* Responds to all reads with 0 */ 538 if (l64781_readreg(state, 0x1a) != 0) { 539 dprintk("Read 1 returned unexpcted value\n"); 540 goto error; 541 } 542 543 /* Turn the chip on */ 544 l64781_writereg (state, 0x3e, 0xa5); 545 546 /* Responds with register default value */ 547 if (l64781_readreg(state, 0x1a) != 0xa1) { 548 dprintk("Read 2 returned unexpcted value\n"); 549 goto error; 550 } 551 552 /* create dvb_frontend */ 553 memcpy(&state->frontend.ops, &l64781_ops, sizeof(struct dvb_frontend_ops)); 554 state->frontend.demodulator_priv = state; 555 return &state->frontend; 556 557error: 558 if (reg0x3e >= 0) 559 l64781_writereg (state, 0x3e, reg0x3e); /* restore reg 0x3e */ 560 kfree(state); 561 return NULL; 562} 563 564static struct dvb_frontend_ops l64781_ops = { 565 566 .info = { 567 .name = "LSI L64781 DVB-T", 568 .type = FE_OFDM, 569 /* .frequency_min = ???,*/ 570 /* .frequency_max = ???,*/ 571 .frequency_stepsize = 166666, 572 /* .frequency_tolerance = ???,*/ 573 /* .symbol_rate_tolerance = ???,*/ 574 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 575 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | 576 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | 577 FE_CAN_MUTE_TS 578 }, 579 580 .release = l64781_release, 581 582 .init = l64781_init, 583 .sleep = l64781_sleep, 584 585 .set_frontend = apply_frontend_param, 586 .get_frontend = get_frontend, 587 .get_tune_settings = l64781_get_tune_settings, 588 589 .read_status = l64781_read_status, 590 .read_ber = l64781_read_ber, 591 .read_signal_strength = l64781_read_signal_strength, 592 .read_snr = l64781_read_snr, 593 .read_ucblocks = l64781_read_ucblocks, 594}; 595 596MODULE_DESCRIPTION("LSI L64781 DVB-T Demodulator driver"); 597MODULE_AUTHOR("Holger Waechtler, Marko Kohtala"); 598MODULE_LICENSE("GPL"); 599 600EXPORT_SYMBOL(l64781_attach); 601