1/* 2 cx24110 - Single Chip Satellite Channel Receiver driver module 3 4 Copyright (C) 2002 Peter Hettkamp <peter.hettkamp@htp-tel.de> based on 5 work 6 Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de> 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 23*/ 24 25#include <linux/slab.h> 26#include <linux/kernel.h> 27#include <linux/module.h> 28#include <linux/init.h> 29 30#include "dvb_frontend.h" 31#include "cx24110.h" 32 33 34struct cx24110_state { 35 36 struct i2c_adapter* i2c; 37 38 const struct cx24110_config* config; 39 40 struct dvb_frontend frontend; 41 42 u32 lastber; 43 u32 lastbler; 44 u32 lastesn0; 45}; 46 47static int debug; 48#define dprintk(args...) \ 49 do { \ 50 if (debug) printk(KERN_DEBUG "cx24110: " args); \ 51 } while (0) 52 53static struct {u8 reg; u8 data;} cx24110_regdata[]= 54 /* Comments beginning with @ denote this value should 55 be the default */ 56 {{0x09,0x01}, /* SoftResetAll */ 57 {0x09,0x00}, /* release reset */ 58 {0x01,0xe8}, /* MSB of code rate 27.5MS/s */ 59 {0x02,0x17}, /* middle byte " */ 60 {0x03,0x29}, /* LSB " */ 61 {0x05,0x03}, /* @ DVB mode, standard code rate 3/4 */ 62 {0x06,0xa5}, /* @ PLL 60MHz */ 63 {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */ 64 {0x0a,0x00}, /* @ partial chip disables, do not set */ 65 {0x0b,0x01}, /* set output clock in gapped mode, start signal low 66 active for first byte */ 67 {0x0c,0x11}, /* no parity bytes, large hold time, serial data out */ 68 {0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */ 69 {0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1 70 to avoid starting the BER counter. Reset the 71 CRC test bit. Finite counting selected */ 72 {0x15,0xff}, /* @ size of the limited time window for RS BER 73 estimation. It is <value>*256 RS blocks, this 74 gives approx. 2.6 sec at 27.5MS/s, rate 3/4 */ 75 {0x16,0x00}, /* @ enable all RS output ports */ 76 {0x17,0x04}, /* @ time window allowed for the RS to sync */ 77 {0x18,0xae}, /* @ allow all standard DVB code rates to be scanned 78 for automatically */ 79 /* leave the current code rate and normalization 80 registers as they are after reset... */ 81 {0x21,0x10}, /* @ during AutoAcq, search each viterbi setting 82 only once */ 83 {0x23,0x18}, /* @ size of the limited time window for Viterbi BER 84 estimation. It is <value>*65536 channel bits, i.e. 85 approx. 38ms at 27.5MS/s, rate 3/4 */ 86 {0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */ 87 /* leave front-end AGC parameters at default values */ 88 /* leave decimation AGC parameters at default values */ 89 {0x35,0x40}, /* disable all interrupts. They are not connected anyway */ 90 {0x36,0xff}, /* clear all interrupt pending flags */ 91 {0x37,0x00}, /* @ fully enable AutoAcqq state machine */ 92 {0x38,0x07}, /* @ enable fade recovery, but not autostart AutoAcq */ 93 /* leave the equalizer parameters on their default values */ 94 /* leave the final AGC parameters on their default values */ 95 {0x41,0x00}, /* @ MSB of front-end derotator frequency */ 96 {0x42,0x00}, /* @ middle bytes " */ 97 {0x43,0x00}, /* @ LSB " */ 98 /* leave the carrier tracking loop parameters on default */ 99 /* leave the bit timing loop parameters at default */ 100 {0x56,0x4d}, /* set the filtune voltage to 2.7V, as recommended by */ 101 /* the cx24108 data sheet for symbol rates above 15MS/s */ 102 {0x57,0x00}, /* @ Filter sigma delta enabled, positive */ 103 {0x61,0x95}, /* GPIO pins 1-4 have special function */ 104 {0x62,0x05}, /* GPIO pin 5 has special function, pin 6 is GPIO */ 105 {0x63,0x00}, /* All GPIO pins use CMOS output characteristics */ 106 {0x64,0x20}, /* GPIO 6 is input, all others are outputs */ 107 {0x6d,0x30}, /* tuner auto mode clock freq 62kHz */ 108 {0x70,0x15}, /* use auto mode, tuner word is 21 bits long */ 109 {0x73,0x00}, /* @ disable several demod bypasses */ 110 {0x74,0x00}, /* @ " */ 111 {0x75,0x00} /* @ " */ 112 /* the remaining registers are for SEC */ 113 }; 114 115 116static int cx24110_writereg (struct cx24110_state* state, int reg, int data) 117{ 118 u8 buf [] = { reg, data }; 119 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; 120 int err; 121 122 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) { 123 dprintk ("%s: writereg error (err == %i, reg == 0x%02x," 124 " data == 0x%02x)\n", __func__, err, reg, data); 125 return -EREMOTEIO; 126 } 127 128 return 0; 129} 130 131static int cx24110_readreg (struct cx24110_state* state, u8 reg) 132{ 133 int ret; 134 u8 b0 [] = { reg }; 135 u8 b1 [] = { 0 }; 136 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 }, 137 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; 138 139 ret = i2c_transfer(state->i2c, msg, 2); 140 141 if (ret != 2) return ret; 142 143 return b1[0]; 144} 145 146static int cx24110_set_inversion (struct cx24110_state* state, fe_spectral_inversion_t inversion) 147{ 148 149 switch (inversion) { 150 case INVERSION_OFF: 151 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1); 152 /* AcqSpectrInvDis on. No idea why someone should want this */ 153 cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)&0xf7); 154 /* Initial value 0 at start of acq */ 155 cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)&0xef); 156 /* current value 0 */ 157 /* The cx24110 manual tells us this reg is read-only. 158 But what the heck... set it ayways */ 159 break; 160 case INVERSION_ON: 161 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1); 162 /* AcqSpectrInvDis on. No idea why someone should want this */ 163 cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)|0x08); 164 /* Initial value 1 at start of acq */ 165 cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)|0x10); 166 /* current value 1 */ 167 break; 168 case INVERSION_AUTO: 169 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xfe); 170 /* AcqSpectrInvDis off. Leave initial & current states as is */ 171 break; 172 default: 173 return -EINVAL; 174 } 175 176 return 0; 177} 178 179static int cx24110_set_fec (struct cx24110_state* state, fe_code_rate_t fec) 180{ 181 182 static const int rate[]={-1,1,2,3,5,7,-1}; 183 static const int g1[]={-1,0x01,0x02,0x05,0x15,0x45,-1}; 184 static const int g2[]={-1,0x01,0x03,0x06,0x1a,0x7a,-1}; 185 186 /* Well, the AutoAcq engine of the cx24106 and 24110 automatically 187 searches all enabled viterbi rates, and can handle non-standard 188 rates as well. */ 189 190 if (fec>FEC_AUTO) 191 fec=FEC_AUTO; 192 193 if (fec==FEC_AUTO) { /* (re-)establish AutoAcq behaviour */ 194 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xdf); 195 /* clear AcqVitDis bit */ 196 cx24110_writereg(state,0x18,0xae); 197 /* allow all DVB standard code rates */ 198 cx24110_writereg(state,0x05,(cx24110_readreg(state,0x05)&0xf0)|0x3); 199 /* set nominal Viterbi rate 3/4 */ 200 cx24110_writereg(state,0x22,(cx24110_readreg(state,0x22)&0xf0)|0x3); 201 /* set current Viterbi rate 3/4 */ 202 cx24110_writereg(state,0x1a,0x05); cx24110_writereg(state,0x1b,0x06); 203 /* set the puncture registers for code rate 3/4 */ 204 return 0; 205 } else { 206 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x20); 207 /* set AcqVitDis bit */ 208 if(rate[fec]>0) { 209 cx24110_writereg(state,0x05,(cx24110_readreg(state,0x05)&0xf0)|rate[fec]); 210 /* set nominal Viterbi rate */ 211 cx24110_writereg(state,0x22,(cx24110_readreg(state,0x22)&0xf0)|rate[fec]); 212 /* set current Viterbi rate */ 213 cx24110_writereg(state,0x1a,g1[fec]); 214 cx24110_writereg(state,0x1b,g2[fec]); 215 /* not sure if this is the right way: I always used AutoAcq mode */ 216 } else 217 return -EOPNOTSUPP; 218 }; 219 return 0; 220} 221 222static fe_code_rate_t cx24110_get_fec (struct cx24110_state* state) 223{ 224 int i; 225 226 i=cx24110_readreg(state,0x22)&0x0f; 227 if(!(i&0x08)) { 228 return FEC_1_2 + i - 1; 229 } else { 230 return FEC_NONE; 231 } 232} 233 234static int cx24110_set_symbolrate (struct cx24110_state* state, u32 srate) 235{ 236 u32 ratio; 237 u32 tmp, fclk, BDRI; 238 239 static const u32 bands[]={5000000UL,15000000UL,90999000UL/2}; 240 int i; 241 242 dprintk("cx24110 debug: entering %s(%d)\n",__func__,srate); 243 if (srate>90999000UL/2) 244 srate=90999000UL/2; 245 if (srate<500000) 246 srate=500000; 247 248 for(i = 0; (i < ARRAY_SIZE(bands)) && (srate>bands[i]); i++) 249 ; 250 /* first, check which sample rate is appropriate: 45, 60 80 or 90 MHz, 251 and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult, 252 R06[3:0] PLLphaseDetGain */ 253 tmp=cx24110_readreg(state,0x07)&0xfc; 254 if(srate<90999000UL/4) { /* sample rate 45MHz*/ 255 cx24110_writereg(state,0x07,tmp); 256 cx24110_writereg(state,0x06,0x78); 257 fclk=90999000UL/2; 258 } else if(srate<60666000UL/2) { /* sample rate 60MHz */ 259 cx24110_writereg(state,0x07,tmp|0x1); 260 cx24110_writereg(state,0x06,0xa5); 261 fclk=60666000UL; 262 } else if(srate<80888000UL/2) { /* sample rate 80MHz */ 263 cx24110_writereg(state,0x07,tmp|0x2); 264 cx24110_writereg(state,0x06,0x87); 265 fclk=80888000UL; 266 } else { /* sample rate 90MHz */ 267 cx24110_writereg(state,0x07,tmp|0x3); 268 cx24110_writereg(state,0x06,0x78); 269 fclk=90999000UL; 270 }; 271 dprintk("cx24110 debug: fclk %d Hz\n",fclk); 272 /* we need to divide two integers with approx. 27 bits in 32 bit 273 arithmetic giving a 25 bit result */ 274 /* the maximum dividend is 90999000/2, 0x02b6446c, this number is 275 also the most complex divisor. Hence, the dividend has, 276 assuming 32bit unsigned arithmetic, 6 clear bits on top, the 277 divisor 2 unused bits at the bottom. Also, the quotient is 278 always less than 1/2. Borrowed from VES1893.c, of course */ 279 280 tmp=srate<<6; 281 BDRI=fclk>>2; 282 ratio=(tmp/BDRI); 283 284 tmp=(tmp%BDRI)<<8; 285 ratio=(ratio<<8)+(tmp/BDRI); 286 287 tmp=(tmp%BDRI)<<8; 288 ratio=(ratio<<8)+(tmp/BDRI); 289 290 tmp=(tmp%BDRI)<<1; 291 ratio=(ratio<<1)+(tmp/BDRI); 292 293 dprintk("srate= %d (range %d, up to %d)\n", srate,i,bands[i]); 294 dprintk("fclk = %d\n", fclk); 295 dprintk("ratio= %08x\n", ratio); 296 297 cx24110_writereg(state, 0x1, (ratio>>16)&0xff); 298 cx24110_writereg(state, 0x2, (ratio>>8)&0xff); 299 cx24110_writereg(state, 0x3, (ratio)&0xff); 300 301 return 0; 302 303} 304 305static int _cx24110_pll_write (struct dvb_frontend* fe, u8 *buf, int len) 306{ 307 struct cx24110_state *state = fe->demodulator_priv; 308 309 if (len != 3) 310 return -EINVAL; 311 312/* tuner data is 21 bits long, must be left-aligned in data */ 313/* tuner cx24108 is written through a dedicated 3wire interface on the demod chip */ 314 315 cx24110_writereg(state,0x6d,0x30); /* auto mode at 62kHz */ 316 cx24110_writereg(state,0x70,0x15); /* auto mode 21 bits */ 317 318 /* if the auto tuner writer is still busy, clear it out */ 319 while (cx24110_readreg(state,0x6d)&0x80) 320 cx24110_writereg(state,0x72,0); 321 322 /* write the topmost 8 bits */ 323 cx24110_writereg(state,0x72,buf[0]); 324 325 /* wait for the send to be completed */ 326 while ((cx24110_readreg(state,0x6d)&0xc0)==0x80) 327 ; 328 329 /* send another 8 bytes */ 330 cx24110_writereg(state,0x72,buf[1]); 331 while ((cx24110_readreg(state,0x6d)&0xc0)==0x80) 332 ; 333 334 /* and the topmost 5 bits of this byte */ 335 cx24110_writereg(state,0x72,buf[2]); 336 while ((cx24110_readreg(state,0x6d)&0xc0)==0x80) 337 ; 338 339 /* now strobe the enable line once */ 340 cx24110_writereg(state,0x6d,0x32); 341 cx24110_writereg(state,0x6d,0x30); 342 343 return 0; 344} 345 346static int cx24110_initfe(struct dvb_frontend* fe) 347{ 348 struct cx24110_state *state = fe->demodulator_priv; 349 int i; 350 351 dprintk("%s: init chip\n", __func__); 352 353 for(i = 0; i < ARRAY_SIZE(cx24110_regdata); i++) { 354 cx24110_writereg(state, cx24110_regdata[i].reg, cx24110_regdata[i].data); 355 }; 356 357 return 0; 358} 359 360static int cx24110_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage) 361{ 362 struct cx24110_state *state = fe->demodulator_priv; 363 364 switch (voltage) { 365 case SEC_VOLTAGE_13: 366 return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0xc0); 367 case SEC_VOLTAGE_18: 368 return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0x40); 369 default: 370 return -EINVAL; 371 }; 372} 373 374static int cx24110_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t burst) 375{ 376 int rv, bit; 377 struct cx24110_state *state = fe->demodulator_priv; 378 unsigned long timeout; 379 380 if (burst == SEC_MINI_A) 381 bit = 0x00; 382 else if (burst == SEC_MINI_B) 383 bit = 0x08; 384 else 385 return -EINVAL; 386 387 rv = cx24110_readreg(state, 0x77); 388 if (!(rv & 0x04)) 389 cx24110_writereg(state, 0x77, rv | 0x04); 390 391 rv = cx24110_readreg(state, 0x76); 392 cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40 | bit)); 393 timeout = jiffies + msecs_to_jiffies(100); 394 while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40)) 395 ; /* wait for LNB ready */ 396 397 return 0; 398} 399 400static int cx24110_send_diseqc_msg(struct dvb_frontend* fe, 401 struct dvb_diseqc_master_cmd *cmd) 402{ 403 int i, rv; 404 struct cx24110_state *state = fe->demodulator_priv; 405 unsigned long timeout; 406 407 if (cmd->msg_len < 3 || cmd->msg_len > 6) 408 return -EINVAL; /* not implemented */ 409 410 for (i = 0; i < cmd->msg_len; i++) 411 cx24110_writereg(state, 0x79 + i, cmd->msg[i]); 412 413 rv = cx24110_readreg(state, 0x77); 414 if (rv & 0x04) { 415 cx24110_writereg(state, 0x77, rv & ~0x04); 416 msleep(30); /* reportedly fixes switching problems */ 417 } 418 419 rv = cx24110_readreg(state, 0x76); 420 421 cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40) | ((cmd->msg_len-3) & 3)); 422 timeout = jiffies + msecs_to_jiffies(100); 423 while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40)) 424 ; /* wait for LNB ready */ 425 426 return 0; 427} 428 429static int cx24110_read_status(struct dvb_frontend* fe, fe_status_t* status) 430{ 431 struct cx24110_state *state = fe->demodulator_priv; 432 433 int sync = cx24110_readreg (state, 0x55); 434 435 *status = 0; 436 437 if (sync & 0x10) 438 *status |= FE_HAS_SIGNAL; 439 440 if (sync & 0x08) 441 *status |= FE_HAS_CARRIER; 442 443 sync = cx24110_readreg (state, 0x08); 444 445 if (sync & 0x40) 446 *status |= FE_HAS_VITERBI; 447 448 if (sync & 0x20) 449 *status |= FE_HAS_SYNC; 450 451 if ((sync & 0x60) == 0x60) 452 *status |= FE_HAS_LOCK; 453 454 return 0; 455} 456 457static int cx24110_read_ber(struct dvb_frontend* fe, u32* ber) 458{ 459 struct cx24110_state *state = fe->demodulator_priv; 460 461 if(cx24110_readreg(state,0x24)&0x10) { 462 /* the Viterbi error counter has finished one counting window */ 463 cx24110_writereg(state,0x24,0x04); /* select the ber reg */ 464 state->lastber=cx24110_readreg(state,0x25)| 465 (cx24110_readreg(state,0x26)<<8); 466 cx24110_writereg(state,0x24,0x04); /* start new count window */ 467 cx24110_writereg(state,0x24,0x14); 468 } 469 *ber = state->lastber; 470 471 return 0; 472} 473 474static int cx24110_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength) 475{ 476 struct cx24110_state *state = fe->demodulator_priv; 477 478/* no provision in hardware. Read the frontend AGC accumulator. No idea how to scale this, but I know it is 2s complement */ 479 u8 signal = cx24110_readreg (state, 0x27)+128; 480 *signal_strength = (signal << 8) | signal; 481 482 return 0; 483} 484 485static int cx24110_read_snr(struct dvb_frontend* fe, u16* snr) 486{ 487 struct cx24110_state *state = fe->demodulator_priv; 488 489 /* no provision in hardware. Can be computed from the Es/N0 estimator, but I don't know how. */ 490 if(cx24110_readreg(state,0x6a)&0x80) { 491 /* the Es/N0 error counter has finished one counting window */ 492 state->lastesn0=cx24110_readreg(state,0x69)| 493 (cx24110_readreg(state,0x68)<<8); 494 cx24110_writereg(state,0x6a,0x84); /* start new count window */ 495 } 496 *snr = state->lastesn0; 497 498 return 0; 499} 500 501static int cx24110_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) 502{ 503 struct cx24110_state *state = fe->demodulator_priv; 504 u32 lastbyer; 505 506 if(cx24110_readreg(state,0x10)&0x40) { 507 /* the RS error counter has finished one counting window */ 508 cx24110_writereg(state,0x10,0x60); /* select the byer reg */ 509 lastbyer=cx24110_readreg(state,0x12)| 510 (cx24110_readreg(state,0x13)<<8)| 511 (cx24110_readreg(state,0x14)<<16); 512 cx24110_writereg(state,0x10,0x70); /* select the bler reg */ 513 state->lastbler=cx24110_readreg(state,0x12)| 514 (cx24110_readreg(state,0x13)<<8)| 515 (cx24110_readreg(state,0x14)<<16); 516 cx24110_writereg(state,0x10,0x20); /* start new count window */ 517 } 518 *ucblocks = state->lastbler; 519 520 return 0; 521} 522 523static int cx24110_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 524{ 525 struct cx24110_state *state = fe->demodulator_priv; 526 527 528 if (fe->ops.tuner_ops.set_params) { 529 fe->ops.tuner_ops.set_params(fe, p); 530 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 531 } 532 533 cx24110_set_inversion (state, p->inversion); 534 cx24110_set_fec (state, p->u.qpsk.fec_inner); 535 cx24110_set_symbolrate (state, p->u.qpsk.symbol_rate); 536 cx24110_writereg(state,0x04,0x05); /* start aquisition */ 537 538 return 0; 539} 540 541static int cx24110_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) 542{ 543 struct cx24110_state *state = fe->demodulator_priv; 544 s32 afc; unsigned sclk; 545 546/* cannot read back tuner settings (freq). Need to have some private storage */ 547 548 sclk = cx24110_readreg (state, 0x07) & 0x03; 549/* ok, real AFC (FEDR) freq. is afc/2^24*fsamp, fsamp=45/60/80/90MHz. 550 * Need 64 bit arithmetic. Is thiss possible in the kernel? */ 551 if (sclk==0) sclk=90999000L/2L; 552 else if (sclk==1) sclk=60666000L; 553 else if (sclk==2) sclk=80888000L; 554 else sclk=90999000L; 555 sclk>>=8; 556 afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+ 557 ((sclk*cx24110_readreg (state, 0x45))>>8)+ 558 ((sclk*cx24110_readreg (state, 0x46))>>16); 559 560 p->frequency += afc; 561 p->inversion = (cx24110_readreg (state, 0x22) & 0x10) ? 562 INVERSION_ON : INVERSION_OFF; 563 p->u.qpsk.fec_inner = cx24110_get_fec (state); 564 565 return 0; 566} 567 568static int cx24110_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone) 569{ 570 struct cx24110_state *state = fe->demodulator_priv; 571 572 return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&~0x10)|(((tone==SEC_TONE_ON))?0x10:0)); 573} 574 575static void cx24110_release(struct dvb_frontend* fe) 576{ 577 struct cx24110_state* state = fe->demodulator_priv; 578 kfree(state); 579} 580 581static struct dvb_frontend_ops cx24110_ops; 582 583struct dvb_frontend* cx24110_attach(const struct cx24110_config* config, 584 struct i2c_adapter* i2c) 585{ 586 struct cx24110_state* state = NULL; 587 int ret; 588 589 /* allocate memory for the internal state */ 590 state = kzalloc(sizeof(struct cx24110_state), GFP_KERNEL); 591 if (state == NULL) goto error; 592 593 /* setup the state */ 594 state->config = config; 595 state->i2c = i2c; 596 state->lastber = 0; 597 state->lastbler = 0; 598 state->lastesn0 = 0; 599 600 /* check if the demod is there */ 601 ret = cx24110_readreg(state, 0x00); 602 if ((ret != 0x5a) && (ret != 0x69)) goto error; 603 604 /* create dvb_frontend */ 605 memcpy(&state->frontend.ops, &cx24110_ops, sizeof(struct dvb_frontend_ops)); 606 state->frontend.demodulator_priv = state; 607 return &state->frontend; 608 609error: 610 kfree(state); 611 return NULL; 612} 613 614static struct dvb_frontend_ops cx24110_ops = { 615 616 .info = { 617 .name = "Conexant CX24110 DVB-S", 618 .type = FE_QPSK, 619 .frequency_min = 950000, 620 .frequency_max = 2150000, 621 .frequency_stepsize = 1011, /* kHz for QPSK frontends */ 622 .frequency_tolerance = 29500, 623 .symbol_rate_min = 1000000, 624 .symbol_rate_max = 45000000, 625 .caps = FE_CAN_INVERSION_AUTO | 626 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 627 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 628 FE_CAN_QPSK | FE_CAN_RECOVER 629 }, 630 631 .release = cx24110_release, 632 633 .init = cx24110_initfe, 634 .write = _cx24110_pll_write, 635 .set_frontend = cx24110_set_frontend, 636 .get_frontend = cx24110_get_frontend, 637 .read_status = cx24110_read_status, 638 .read_ber = cx24110_read_ber, 639 .read_signal_strength = cx24110_read_signal_strength, 640 .read_snr = cx24110_read_snr, 641 .read_ucblocks = cx24110_read_ucblocks, 642 643 .diseqc_send_master_cmd = cx24110_send_diseqc_msg, 644 .set_tone = cx24110_set_tone, 645 .set_voltage = cx24110_set_voltage, 646 .diseqc_send_burst = cx24110_diseqc_send_burst, 647}; 648 649module_param(debug, int, 0644); 650MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); 651 652MODULE_DESCRIPTION("Conexant CX24110 DVB-S Demodulator driver"); 653MODULE_AUTHOR("Peter Hettkamp"); 654MODULE_LICENSE("GPL"); 655 656EXPORT_SYMBOL(cx24110_attach); 657