1/* 2 * dme1737.c - Driver for the SMSC DME1737, Asus A8000, SMSC SCH311x, SCH5027, 3 * and SCH5127 Super-I/O chips integrated hardware monitoring 4 * features. 5 * Copyright (c) 2007, 2008, 2009, 2010 Juerg Haefliger <juergh@gmail.com> 6 * 7 * This driver is an I2C/ISA hybrid, meaning that it uses the I2C bus to access 8 * the chip registers if a DME1737, A8000, or SCH5027 is found and the ISA bus 9 * if a SCH311x or SCH5127 chip is found. Both types of chips have very 10 * similar hardware monitoring capabilities but differ in the way they can be 11 * accessed. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 26 */ 27 28#include <linux/module.h> 29#include <linux/init.h> 30#include <linux/slab.h> 31#include <linux/jiffies.h> 32#include <linux/i2c.h> 33#include <linux/platform_device.h> 34#include <linux/hwmon.h> 35#include <linux/hwmon-sysfs.h> 36#include <linux/hwmon-vid.h> 37#include <linux/err.h> 38#include <linux/mutex.h> 39#include <linux/acpi.h> 40#include <linux/io.h> 41 42/* ISA device, if found */ 43static struct platform_device *pdev; 44 45/* Module load parameters */ 46static int force_start; 47module_param(force_start, bool, 0); 48MODULE_PARM_DESC(force_start, "Force the chip to start monitoring inputs"); 49 50static unsigned short force_id; 51module_param(force_id, ushort, 0); 52MODULE_PARM_DESC(force_id, "Override the detected device ID"); 53 54static int probe_all_addr; 55module_param(probe_all_addr, bool, 0); 56MODULE_PARM_DESC(probe_all_addr, "Include probing of non-standard LPC " 57 "addresses"); 58 59/* Addresses to scan */ 60static const unsigned short normal_i2c[] = {0x2c, 0x2d, 0x2e, I2C_CLIENT_END}; 61 62enum chips { dme1737, sch5027, sch311x, sch5127 }; 63 64/* --------------------------------------------------------------------- 65 * Registers 66 * 67 * The sensors are defined as follows: 68 * 69 * Voltages Temperatures 70 * -------- ------------ 71 * in0 +5VTR (+5V stdby) temp1 Remote diode 1 72 * in1 Vccp (proc core) temp2 Internal temp 73 * in2 VCC (internal +3.3V) temp3 Remote diode 2 74 * in3 +5V 75 * in4 +12V 76 * in5 VTR (+3.3V stby) 77 * in6 Vbat 78 * 79 * --------------------------------------------------------------------- */ 80 81/* Voltages (in) numbered 0-6 (ix) */ 82#define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) \ 83 : 0x94 + (ix)) 84#define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \ 85 : 0x91 + (ix) * 2) 86#define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \ 87 : 0x92 + (ix) * 2) 88 89/* Temperatures (temp) numbered 0-2 (ix) */ 90#define DME1737_REG_TEMP(ix) (0x25 + (ix)) 91#define DME1737_REG_TEMP_MIN(ix) (0x4e + (ix) * 2) 92#define DME1737_REG_TEMP_MAX(ix) (0x4f + (ix) * 2) 93#define DME1737_REG_TEMP_OFFSET(ix) ((ix) == 0 ? 0x1f \ 94 : 0x1c + (ix)) 95 96/* Voltage and temperature LSBs 97 * The LSBs (4 bits each) are stored in 5 registers with the following layouts: 98 * IN_TEMP_LSB(0) = [in5, in6] 99 * IN_TEMP_LSB(1) = [temp3, temp1] 100 * IN_TEMP_LSB(2) = [in4, temp2] 101 * IN_TEMP_LSB(3) = [in3, in0] 102 * IN_TEMP_LSB(4) = [in2, in1] */ 103#define DME1737_REG_IN_TEMP_LSB(ix) (0x84 + (ix)) 104static const u8 DME1737_REG_IN_LSB[] = {3, 4, 4, 3, 2, 0, 0}; 105static const u8 DME1737_REG_IN_LSB_SHL[] = {4, 4, 0, 0, 0, 0, 4}; 106static const u8 DME1737_REG_TEMP_LSB[] = {1, 2, 1}; 107static const u8 DME1737_REG_TEMP_LSB_SHL[] = {4, 4, 0}; 108 109/* Fans numbered 0-5 (ix) */ 110#define DME1737_REG_FAN(ix) ((ix) < 4 ? 0x28 + (ix) * 2 \ 111 : 0xa1 + (ix) * 2) 112#define DME1737_REG_FAN_MIN(ix) ((ix) < 4 ? 0x54 + (ix) * 2 \ 113 : 0xa5 + (ix) * 2) 114#define DME1737_REG_FAN_OPT(ix) ((ix) < 4 ? 0x90 + (ix) \ 115 : 0xb2 + (ix)) 116#define DME1737_REG_FAN_MAX(ix) (0xb4 + (ix)) /* only for fan[4-5] */ 117 118/* PWMs numbered 0-2, 4-5 (ix) */ 119#define DME1737_REG_PWM(ix) ((ix) < 3 ? 0x30 + (ix) \ 120 : 0xa1 + (ix)) 121#define DME1737_REG_PWM_CONFIG(ix) (0x5c + (ix)) /* only for pwm[0-2] */ 122#define DME1737_REG_PWM_MIN(ix) (0x64 + (ix)) /* only for pwm[0-2] */ 123#define DME1737_REG_PWM_FREQ(ix) ((ix) < 3 ? 0x5f + (ix) \ 124 : 0xa3 + (ix)) 125/* The layout of the ramp rate registers is different from the other pwm 126 * registers. The bits for the 3 PWMs are stored in 2 registers: 127 * PWM_RR(0) = [OFF3, OFF2, OFF1, RES, RR1E, RR1-2, RR1-1, RR1-0] 128 * PWM_RR(1) = [RR2E, RR2-2, RR2-1, RR2-0, RR3E, RR3-2, RR3-1, RR3-0] */ 129#define DME1737_REG_PWM_RR(ix) (0x62 + (ix)) /* only for pwm[0-2] */ 130 131/* Thermal zones 0-2 */ 132#define DME1737_REG_ZONE_LOW(ix) (0x67 + (ix)) 133#define DME1737_REG_ZONE_ABS(ix) (0x6a + (ix)) 134/* The layout of the hysteresis registers is different from the other zone 135 * registers. The bits for the 3 zones are stored in 2 registers: 136 * ZONE_HYST(0) = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0] 137 * ZONE_HYST(1) = [H3-3, H3-2, H3-1, H3-0, RES, RES, RES, RES] */ 138#define DME1737_REG_ZONE_HYST(ix) (0x6d + (ix)) 139 140/* Alarm registers and bit mapping 141 * The 3 8-bit alarm registers will be concatenated to a single 32-bit 142 * alarm value [0, ALARM3, ALARM2, ALARM1]. */ 143#define DME1737_REG_ALARM1 0x41 144#define DME1737_REG_ALARM2 0x42 145#define DME1737_REG_ALARM3 0x83 146static const u8 DME1737_BIT_ALARM_IN[] = {0, 1, 2, 3, 8, 16, 17}; 147static const u8 DME1737_BIT_ALARM_TEMP[] = {4, 5, 6}; 148static const u8 DME1737_BIT_ALARM_FAN[] = {10, 11, 12, 13, 22, 23}; 149 150/* Miscellaneous registers */ 151#define DME1737_REG_DEVICE 0x3d 152#define DME1737_REG_COMPANY 0x3e 153#define DME1737_REG_VERSTEP 0x3f 154#define DME1737_REG_CONFIG 0x40 155#define DME1737_REG_CONFIG2 0x7f 156#define DME1737_REG_VID 0x43 157#define DME1737_REG_TACH_PWM 0x81 158 159/* --------------------------------------------------------------------- 160 * Misc defines 161 * --------------------------------------------------------------------- */ 162 163/* Chip identification */ 164#define DME1737_COMPANY_SMSC 0x5c 165#define DME1737_VERSTEP 0x88 166#define DME1737_VERSTEP_MASK 0xf8 167#define SCH311X_DEVICE 0x8c 168#define SCH5027_VERSTEP 0x69 169#define SCH5127_DEVICE 0x8e 170 171/* Device ID values (global configuration register index 0x20) */ 172#define DME1737_ID_1 0x77 173#define DME1737_ID_2 0x78 174#define SCH3112_ID 0x7c 175#define SCH3114_ID 0x7d 176#define SCH3116_ID 0x7f 177#define SCH5027_ID 0x89 178#define SCH5127_ID 0x86 179 180/* Length of ISA address segment */ 181#define DME1737_EXTENT 2 182 183/* chip-dependent features */ 184#define HAS_TEMP_OFFSET (1 << 0) /* bit 0 */ 185#define HAS_VID (1 << 1) /* bit 1 */ 186#define HAS_ZONE3 (1 << 2) /* bit 2 */ 187#define HAS_ZONE_HYST (1 << 3) /* bit 3 */ 188#define HAS_PWM_MIN (1 << 4) /* bit 4 */ 189#define HAS_FAN(ix) (1 << ((ix) + 5)) /* bits 5-10 */ 190#define HAS_PWM(ix) (1 << ((ix) + 11)) /* bits 11-16 */ 191 192/* --------------------------------------------------------------------- 193 * Data structures and manipulation thereof 194 * --------------------------------------------------------------------- */ 195 196struct dme1737_data { 197 struct i2c_client *client; /* for I2C devices only */ 198 struct device *hwmon_dev; 199 const char *name; 200 unsigned int addr; /* for ISA devices only */ 201 202 struct mutex update_lock; 203 int valid; /* !=0 if following fields are valid */ 204 unsigned long last_update; /* in jiffies */ 205 unsigned long last_vbat; /* in jiffies */ 206 enum chips type; 207 const int *in_nominal; /* pointer to IN_NOMINAL array */ 208 209 u8 vid; 210 u8 pwm_rr_en; 211 u32 has_features; 212 213 /* Register values */ 214 u16 in[7]; 215 u8 in_min[7]; 216 u8 in_max[7]; 217 s16 temp[3]; 218 s8 temp_min[3]; 219 s8 temp_max[3]; 220 s8 temp_offset[3]; 221 u8 config; 222 u8 config2; 223 u8 vrm; 224 u16 fan[6]; 225 u16 fan_min[6]; 226 u8 fan_max[2]; 227 u8 fan_opt[6]; 228 u8 pwm[6]; 229 u8 pwm_min[3]; 230 u8 pwm_config[3]; 231 u8 pwm_acz[3]; 232 u8 pwm_freq[6]; 233 u8 pwm_rr[2]; 234 u8 zone_low[3]; 235 u8 zone_abs[3]; 236 u8 zone_hyst[2]; 237 u32 alarms; 238}; 239 240/* Nominal voltage values */ 241static const int IN_NOMINAL_DME1737[] = {5000, 2250, 3300, 5000, 12000, 3300, 242 3300}; 243static const int IN_NOMINAL_SCH311x[] = {2500, 1500, 3300, 5000, 12000, 3300, 244 3300}; 245static const int IN_NOMINAL_SCH5027[] = {5000, 2250, 3300, 1125, 1125, 3300, 246 3300}; 247static const int IN_NOMINAL_SCH5127[] = {2500, 2250, 3300, 1125, 1125, 3300, 248 3300}; 249#define IN_NOMINAL(type) ((type) == sch311x ? IN_NOMINAL_SCH311x : \ 250 (type) == sch5027 ? IN_NOMINAL_SCH5027 : \ 251 (type) == sch5127 ? IN_NOMINAL_SCH5127 : \ 252 IN_NOMINAL_DME1737) 253 254/* Voltage input 255 * Voltage inputs have 16 bits resolution, limit values have 8 bits 256 * resolution. */ 257static inline int IN_FROM_REG(int reg, int nominal, int res) 258{ 259 return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2)); 260} 261 262static inline int IN_TO_REG(int val, int nominal) 263{ 264 return SENSORS_LIMIT((val * 192 + nominal / 2) / nominal, 0, 255); 265} 266 267/* Temperature input 268 * The register values represent temperatures in 2's complement notation from 269 * -127 degrees C to +127 degrees C. Temp inputs have 16 bits resolution, limit 270 * values have 8 bits resolution. */ 271static inline int TEMP_FROM_REG(int reg, int res) 272{ 273 return (reg * 1000) >> (res - 8); 274} 275 276static inline int TEMP_TO_REG(int val) 277{ 278 return SENSORS_LIMIT((val < 0 ? val - 500 : val + 500) / 1000, 279 -128, 127); 280} 281 282/* Temperature range */ 283static const int TEMP_RANGE[] = {2000, 2500, 3333, 4000, 5000, 6666, 8000, 284 10000, 13333, 16000, 20000, 26666, 32000, 285 40000, 53333, 80000}; 286 287static inline int TEMP_RANGE_FROM_REG(int reg) 288{ 289 return TEMP_RANGE[(reg >> 4) & 0x0f]; 290} 291 292static int TEMP_RANGE_TO_REG(int val, int reg) 293{ 294 int i; 295 296 for (i = 15; i > 0; i--) { 297 if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2) { 298 break; 299 } 300 } 301 302 return (reg & 0x0f) | (i << 4); 303} 304 305static inline int TEMP_HYST_FROM_REG(int reg, int ix) 306{ 307 return (((ix == 1) ? reg : reg >> 4) & 0x0f) * 1000; 308} 309 310static inline int TEMP_HYST_TO_REG(int val, int ix, int reg) 311{ 312 int hyst = SENSORS_LIMIT((val + 500) / 1000, 0, 15); 313 314 return (ix == 1) ? (reg & 0xf0) | hyst : (reg & 0x0f) | (hyst << 4); 315} 316 317/* Fan input RPM */ 318static inline int FAN_FROM_REG(int reg, int tpc) 319{ 320 if (tpc) { 321 return tpc * reg; 322 } else { 323 return (reg == 0 || reg == 0xffff) ? 0 : 90000 * 60 / reg; 324 } 325} 326 327static inline int FAN_TO_REG(int val, int tpc) 328{ 329 if (tpc) { 330 return SENSORS_LIMIT(val / tpc, 0, 0xffff); 331 } else { 332 return (val <= 0) ? 0xffff : 333 SENSORS_LIMIT(90000 * 60 / val, 0, 0xfffe); 334 } 335} 336 337/* Fan TPC (tach pulse count) 338 * Converts a register value to a TPC multiplier or returns 0 if the tachometer 339 * is configured in legacy (non-tpc) mode */ 340static inline int FAN_TPC_FROM_REG(int reg) 341{ 342 return (reg & 0x20) ? 0 : 60 >> (reg & 0x03); 343} 344 345/* Fan type 346 * The type of a fan is expressed in number of pulses-per-revolution that it 347 * emits */ 348static inline int FAN_TYPE_FROM_REG(int reg) 349{ 350 int edge = (reg >> 1) & 0x03; 351 352 return (edge > 0) ? 1 << (edge - 1) : 0; 353} 354 355static inline int FAN_TYPE_TO_REG(int val, int reg) 356{ 357 int edge = (val == 4) ? 3 : val; 358 359 return (reg & 0xf9) | (edge << 1); 360} 361 362/* Fan max RPM */ 363static const int FAN_MAX[] = {0x54, 0x38, 0x2a, 0x21, 0x1c, 0x18, 0x15, 0x12, 364 0x11, 0x0f, 0x0e}; 365 366static int FAN_MAX_FROM_REG(int reg) 367{ 368 int i; 369 370 for (i = 10; i > 0; i--) { 371 if (reg == FAN_MAX[i]) { 372 break; 373 } 374 } 375 376 return 1000 + i * 500; 377} 378 379static int FAN_MAX_TO_REG(int val) 380{ 381 int i; 382 383 for (i = 10; i > 0; i--) { 384 if (val > (1000 + (i - 1) * 500)) { 385 break; 386 } 387 } 388 389 return FAN_MAX[i]; 390} 391 392/* PWM enable 393 * Register to enable mapping: 394 * 000: 2 fan on zone 1 auto 395 * 001: 2 fan on zone 2 auto 396 * 010: 2 fan on zone 3 auto 397 * 011: 0 fan full on 398 * 100: -1 fan disabled 399 * 101: 2 fan on hottest of zones 2,3 auto 400 * 110: 2 fan on hottest of zones 1,2,3 auto 401 * 111: 1 fan in manual mode */ 402static inline int PWM_EN_FROM_REG(int reg) 403{ 404 static const int en[] = {2, 2, 2, 0, -1, 2, 2, 1}; 405 406 return en[(reg >> 5) & 0x07]; 407} 408 409static inline int PWM_EN_TO_REG(int val, int reg) 410{ 411 int en = (val == 1) ? 7 : 3; 412 413 return (reg & 0x1f) | ((en & 0x07) << 5); 414} 415 416/* PWM auto channels zone 417 * Register to auto channels zone mapping (ACZ is a bitfield with bit x 418 * corresponding to zone x+1): 419 * 000: 001 fan on zone 1 auto 420 * 001: 010 fan on zone 2 auto 421 * 010: 100 fan on zone 3 auto 422 * 011: 000 fan full on 423 * 100: 000 fan disabled 424 * 101: 110 fan on hottest of zones 2,3 auto 425 * 110: 111 fan on hottest of zones 1,2,3 auto 426 * 111: 000 fan in manual mode */ 427static inline int PWM_ACZ_FROM_REG(int reg) 428{ 429 static const int acz[] = {1, 2, 4, 0, 0, 6, 7, 0}; 430 431 return acz[(reg >> 5) & 0x07]; 432} 433 434static inline int PWM_ACZ_TO_REG(int val, int reg) 435{ 436 int acz = (val == 4) ? 2 : val - 1; 437 438 return (reg & 0x1f) | ((acz & 0x07) << 5); 439} 440 441/* PWM frequency */ 442static const int PWM_FREQ[] = {11, 15, 22, 29, 35, 44, 59, 88, 443 15000, 20000, 30000, 25000, 0, 0, 0, 0}; 444 445static inline int PWM_FREQ_FROM_REG(int reg) 446{ 447 return PWM_FREQ[reg & 0x0f]; 448} 449 450static int PWM_FREQ_TO_REG(int val, int reg) 451{ 452 int i; 453 454 /* the first two cases are special - stupid chip design! */ 455 if (val > 27500) { 456 i = 10; 457 } else if (val > 22500) { 458 i = 11; 459 } else { 460 for (i = 9; i > 0; i--) { 461 if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2) { 462 break; 463 } 464 } 465 } 466 467 return (reg & 0xf0) | i; 468} 469 470/* PWM ramp rate 471 * Register layout: 472 * reg[0] = [OFF3, OFF2, OFF1, RES, RR1-E, RR1-2, RR1-1, RR1-0] 473 * reg[1] = [RR2-E, RR2-2, RR2-1, RR2-0, RR3-E, RR3-2, RR3-1, RR3-0] */ 474static const u8 PWM_RR[] = {206, 104, 69, 41, 26, 18, 10, 5}; 475 476static inline int PWM_RR_FROM_REG(int reg, int ix) 477{ 478 int rr = (ix == 1) ? reg >> 4 : reg; 479 480 return (rr & 0x08) ? PWM_RR[rr & 0x07] : 0; 481} 482 483static int PWM_RR_TO_REG(int val, int ix, int reg) 484{ 485 int i; 486 487 for (i = 0; i < 7; i++) { 488 if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2) { 489 break; 490 } 491 } 492 493 return (ix == 1) ? (reg & 0x8f) | (i << 4) : (reg & 0xf8) | i; 494} 495 496/* PWM ramp rate enable */ 497static inline int PWM_RR_EN_FROM_REG(int reg, int ix) 498{ 499 return PWM_RR_FROM_REG(reg, ix) ? 1 : 0; 500} 501 502static inline int PWM_RR_EN_TO_REG(int val, int ix, int reg) 503{ 504 int en = (ix == 1) ? 0x80 : 0x08; 505 506 return val ? reg | en : reg & ~en; 507} 508 509/* PWM min/off 510 * The PWM min/off bits are part of the PMW ramp rate register 0 (see above for 511 * the register layout). */ 512static inline int PWM_OFF_FROM_REG(int reg, int ix) 513{ 514 return (reg >> (ix + 5)) & 0x01; 515} 516 517static inline int PWM_OFF_TO_REG(int val, int ix, int reg) 518{ 519 return (reg & ~(1 << (ix + 5))) | ((val & 0x01) << (ix + 5)); 520} 521 522/* --------------------------------------------------------------------- 523 * Device I/O access 524 * 525 * ISA access is performed through an index/data register pair and needs to 526 * be protected by a mutex during runtime (not required for initialization). 527 * We use data->update_lock for this and need to ensure that we acquire it 528 * before calling dme1737_read or dme1737_write. 529 * --------------------------------------------------------------------- */ 530 531static u8 dme1737_read(const struct dme1737_data *data, u8 reg) 532{ 533 struct i2c_client *client = data->client; 534 s32 val; 535 536 if (client) { /* I2C device */ 537 val = i2c_smbus_read_byte_data(client, reg); 538 539 if (val < 0) { 540 dev_warn(&client->dev, "Read from register " 541 "0x%02x failed! Please report to the driver " 542 "maintainer.\n", reg); 543 } 544 } else { /* ISA device */ 545 outb(reg, data->addr); 546 val = inb(data->addr + 1); 547 } 548 549 return val; 550} 551 552static s32 dme1737_write(const struct dme1737_data *data, u8 reg, u8 val) 553{ 554 struct i2c_client *client = data->client; 555 s32 res = 0; 556 557 if (client) { /* I2C device */ 558 res = i2c_smbus_write_byte_data(client, reg, val); 559 560 if (res < 0) { 561 dev_warn(&client->dev, "Write to register " 562 "0x%02x failed! Please report to the driver " 563 "maintainer.\n", reg); 564 } 565 } else { /* ISA device */ 566 outb(reg, data->addr); 567 outb(val, data->addr + 1); 568 } 569 570 return res; 571} 572 573static struct dme1737_data *dme1737_update_device(struct device *dev) 574{ 575 struct dme1737_data *data = dev_get_drvdata(dev); 576 int ix; 577 u8 lsb[5]; 578 579 mutex_lock(&data->update_lock); 580 581 /* Enable a Vbat monitoring cycle every 10 mins */ 582 if (time_after(jiffies, data->last_vbat + 600 * HZ) || !data->valid) { 583 dme1737_write(data, DME1737_REG_CONFIG, dme1737_read(data, 584 DME1737_REG_CONFIG) | 0x10); 585 data->last_vbat = jiffies; 586 } 587 588 /* Sample register contents every 1 sec */ 589 if (time_after(jiffies, data->last_update + HZ) || !data->valid) { 590 if (data->has_features & HAS_VID) { 591 data->vid = dme1737_read(data, DME1737_REG_VID) & 592 0x3f; 593 } 594 595 /* In (voltage) registers */ 596 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) { 597 /* Voltage inputs are stored as 16 bit values even 598 * though they have only 12 bits resolution. This is 599 * to make it consistent with the temp inputs. */ 600 data->in[ix] = dme1737_read(data, 601 DME1737_REG_IN(ix)) << 8; 602 data->in_min[ix] = dme1737_read(data, 603 DME1737_REG_IN_MIN(ix)); 604 data->in_max[ix] = dme1737_read(data, 605 DME1737_REG_IN_MAX(ix)); 606 } 607 608 /* Temp registers */ 609 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) { 610 /* Temp inputs are stored as 16 bit values even 611 * though they have only 12 bits resolution. This is 612 * to take advantage of implicit conversions between 613 * register values (2's complement) and temp values 614 * (signed decimal). */ 615 data->temp[ix] = dme1737_read(data, 616 DME1737_REG_TEMP(ix)) << 8; 617 data->temp_min[ix] = dme1737_read(data, 618 DME1737_REG_TEMP_MIN(ix)); 619 data->temp_max[ix] = dme1737_read(data, 620 DME1737_REG_TEMP_MAX(ix)); 621 if (data->has_features & HAS_TEMP_OFFSET) { 622 data->temp_offset[ix] = dme1737_read(data, 623 DME1737_REG_TEMP_OFFSET(ix)); 624 } 625 } 626 627 /* In and temp LSB registers 628 * The LSBs are latched when the MSBs are read, so the order in 629 * which the registers are read (MSB first, then LSB) is 630 * important! */ 631 for (ix = 0; ix < ARRAY_SIZE(lsb); ix++) { 632 lsb[ix] = dme1737_read(data, 633 DME1737_REG_IN_TEMP_LSB(ix)); 634 } 635 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) { 636 data->in[ix] |= (lsb[DME1737_REG_IN_LSB[ix]] << 637 DME1737_REG_IN_LSB_SHL[ix]) & 0xf0; 638 } 639 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) { 640 data->temp[ix] |= (lsb[DME1737_REG_TEMP_LSB[ix]] << 641 DME1737_REG_TEMP_LSB_SHL[ix]) & 0xf0; 642 } 643 644 /* Fan registers */ 645 for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) { 646 /* Skip reading registers if optional fans are not 647 * present */ 648 if (!(data->has_features & HAS_FAN(ix))) { 649 continue; 650 } 651 data->fan[ix] = dme1737_read(data, 652 DME1737_REG_FAN(ix)); 653 data->fan[ix] |= dme1737_read(data, 654 DME1737_REG_FAN(ix) + 1) << 8; 655 data->fan_min[ix] = dme1737_read(data, 656 DME1737_REG_FAN_MIN(ix)); 657 data->fan_min[ix] |= dme1737_read(data, 658 DME1737_REG_FAN_MIN(ix) + 1) << 8; 659 data->fan_opt[ix] = dme1737_read(data, 660 DME1737_REG_FAN_OPT(ix)); 661 /* fan_max exists only for fan[5-6] */ 662 if (ix > 3) { 663 data->fan_max[ix - 4] = dme1737_read(data, 664 DME1737_REG_FAN_MAX(ix)); 665 } 666 } 667 668 /* PWM registers */ 669 for (ix = 0; ix < ARRAY_SIZE(data->pwm); ix++) { 670 /* Skip reading registers if optional PWMs are not 671 * present */ 672 if (!(data->has_features & HAS_PWM(ix))) { 673 continue; 674 } 675 data->pwm[ix] = dme1737_read(data, 676 DME1737_REG_PWM(ix)); 677 data->pwm_freq[ix] = dme1737_read(data, 678 DME1737_REG_PWM_FREQ(ix)); 679 /* pwm_config and pwm_min exist only for pwm[1-3] */ 680 if (ix < 3) { 681 data->pwm_config[ix] = dme1737_read(data, 682 DME1737_REG_PWM_CONFIG(ix)); 683 data->pwm_min[ix] = dme1737_read(data, 684 DME1737_REG_PWM_MIN(ix)); 685 } 686 } 687 for (ix = 0; ix < ARRAY_SIZE(data->pwm_rr); ix++) { 688 data->pwm_rr[ix] = dme1737_read(data, 689 DME1737_REG_PWM_RR(ix)); 690 } 691 692 /* Thermal zone registers */ 693 for (ix = 0; ix < ARRAY_SIZE(data->zone_low); ix++) { 694 /* Skip reading registers if zone3 is not present */ 695 if ((ix == 2) && !(data->has_features & HAS_ZONE3)) { 696 continue; 697 } 698 /* sch5127 zone2 registers are special */ 699 if ((ix == 1) && (data->type == sch5127)) { 700 data->zone_low[1] = dme1737_read(data, 701 DME1737_REG_ZONE_LOW(2)); 702 data->zone_abs[1] = dme1737_read(data, 703 DME1737_REG_ZONE_ABS(2)); 704 } else { 705 data->zone_low[ix] = dme1737_read(data, 706 DME1737_REG_ZONE_LOW(ix)); 707 data->zone_abs[ix] = dme1737_read(data, 708 DME1737_REG_ZONE_ABS(ix)); 709 } 710 } 711 if (data->has_features & HAS_ZONE_HYST) { 712 for (ix = 0; ix < ARRAY_SIZE(data->zone_hyst); ix++) { 713 data->zone_hyst[ix] = dme1737_read(data, 714 DME1737_REG_ZONE_HYST(ix)); 715 } 716 } 717 718 /* Alarm registers */ 719 data->alarms = dme1737_read(data, 720 DME1737_REG_ALARM1); 721 /* Bit 7 tells us if the other alarm registers are non-zero and 722 * therefore also need to be read */ 723 if (data->alarms & 0x80) { 724 data->alarms |= dme1737_read(data, 725 DME1737_REG_ALARM2) << 8; 726 data->alarms |= dme1737_read(data, 727 DME1737_REG_ALARM3) << 16; 728 } 729 730 /* The ISA chips require explicit clearing of alarm bits. 731 * Don't worry, an alarm will come back if the condition 732 * that causes it still exists */ 733 if (!data->client) { 734 if (data->alarms & 0xff0000) { 735 dme1737_write(data, DME1737_REG_ALARM3, 736 0xff); 737 } 738 if (data->alarms & 0xff00) { 739 dme1737_write(data, DME1737_REG_ALARM2, 740 0xff); 741 } 742 if (data->alarms & 0xff) { 743 dme1737_write(data, DME1737_REG_ALARM1, 744 0xff); 745 } 746 } 747 748 data->last_update = jiffies; 749 data->valid = 1; 750 } 751 752 mutex_unlock(&data->update_lock); 753 754 return data; 755} 756 757/* --------------------------------------------------------------------- 758 * Voltage sysfs attributes 759 * ix = [0-5] 760 * --------------------------------------------------------------------- */ 761 762#define SYS_IN_INPUT 0 763#define SYS_IN_MIN 1 764#define SYS_IN_MAX 2 765#define SYS_IN_ALARM 3 766 767static ssize_t show_in(struct device *dev, struct device_attribute *attr, 768 char *buf) 769{ 770 struct dme1737_data *data = dme1737_update_device(dev); 771 struct sensor_device_attribute_2 772 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 773 int ix = sensor_attr_2->index; 774 int fn = sensor_attr_2->nr; 775 int res; 776 777 switch (fn) { 778 case SYS_IN_INPUT: 779 res = IN_FROM_REG(data->in[ix], data->in_nominal[ix], 16); 780 break; 781 case SYS_IN_MIN: 782 res = IN_FROM_REG(data->in_min[ix], data->in_nominal[ix], 8); 783 break; 784 case SYS_IN_MAX: 785 res = IN_FROM_REG(data->in_max[ix], data->in_nominal[ix], 8); 786 break; 787 case SYS_IN_ALARM: 788 res = (data->alarms >> DME1737_BIT_ALARM_IN[ix]) & 0x01; 789 break; 790 default: 791 res = 0; 792 dev_dbg(dev, "Unknown function %d.\n", fn); 793 } 794 795 return sprintf(buf, "%d\n", res); 796} 797 798static ssize_t set_in(struct device *dev, struct device_attribute *attr, 799 const char *buf, size_t count) 800{ 801 struct dme1737_data *data = dev_get_drvdata(dev); 802 struct sensor_device_attribute_2 803 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 804 int ix = sensor_attr_2->index; 805 int fn = sensor_attr_2->nr; 806 long val = simple_strtol(buf, NULL, 10); 807 808 mutex_lock(&data->update_lock); 809 switch (fn) { 810 case SYS_IN_MIN: 811 data->in_min[ix] = IN_TO_REG(val, data->in_nominal[ix]); 812 dme1737_write(data, DME1737_REG_IN_MIN(ix), 813 data->in_min[ix]); 814 break; 815 case SYS_IN_MAX: 816 data->in_max[ix] = IN_TO_REG(val, data->in_nominal[ix]); 817 dme1737_write(data, DME1737_REG_IN_MAX(ix), 818 data->in_max[ix]); 819 break; 820 default: 821 dev_dbg(dev, "Unknown function %d.\n", fn); 822 } 823 mutex_unlock(&data->update_lock); 824 825 return count; 826} 827 828/* --------------------------------------------------------------------- 829 * Temperature sysfs attributes 830 * ix = [0-2] 831 * --------------------------------------------------------------------- */ 832 833#define SYS_TEMP_INPUT 0 834#define SYS_TEMP_MIN 1 835#define SYS_TEMP_MAX 2 836#define SYS_TEMP_OFFSET 3 837#define SYS_TEMP_ALARM 4 838#define SYS_TEMP_FAULT 5 839 840static ssize_t show_temp(struct device *dev, struct device_attribute *attr, 841 char *buf) 842{ 843 struct dme1737_data *data = dme1737_update_device(dev); 844 struct sensor_device_attribute_2 845 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 846 int ix = sensor_attr_2->index; 847 int fn = sensor_attr_2->nr; 848 int res; 849 850 switch (fn) { 851 case SYS_TEMP_INPUT: 852 res = TEMP_FROM_REG(data->temp[ix], 16); 853 break; 854 case SYS_TEMP_MIN: 855 res = TEMP_FROM_REG(data->temp_min[ix], 8); 856 break; 857 case SYS_TEMP_MAX: 858 res = TEMP_FROM_REG(data->temp_max[ix], 8); 859 break; 860 case SYS_TEMP_OFFSET: 861 res = TEMP_FROM_REG(data->temp_offset[ix], 8); 862 break; 863 case SYS_TEMP_ALARM: 864 res = (data->alarms >> DME1737_BIT_ALARM_TEMP[ix]) & 0x01; 865 break; 866 case SYS_TEMP_FAULT: 867 res = (((u16)data->temp[ix] & 0xff00) == 0x8000); 868 break; 869 default: 870 res = 0; 871 dev_dbg(dev, "Unknown function %d.\n", fn); 872 } 873 874 return sprintf(buf, "%d\n", res); 875} 876 877static ssize_t set_temp(struct device *dev, struct device_attribute *attr, 878 const char *buf, size_t count) 879{ 880 struct dme1737_data *data = dev_get_drvdata(dev); 881 struct sensor_device_attribute_2 882 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 883 int ix = sensor_attr_2->index; 884 int fn = sensor_attr_2->nr; 885 long val = simple_strtol(buf, NULL, 10); 886 887 mutex_lock(&data->update_lock); 888 switch (fn) { 889 case SYS_TEMP_MIN: 890 data->temp_min[ix] = TEMP_TO_REG(val); 891 dme1737_write(data, DME1737_REG_TEMP_MIN(ix), 892 data->temp_min[ix]); 893 break; 894 case SYS_TEMP_MAX: 895 data->temp_max[ix] = TEMP_TO_REG(val); 896 dme1737_write(data, DME1737_REG_TEMP_MAX(ix), 897 data->temp_max[ix]); 898 break; 899 case SYS_TEMP_OFFSET: 900 data->temp_offset[ix] = TEMP_TO_REG(val); 901 dme1737_write(data, DME1737_REG_TEMP_OFFSET(ix), 902 data->temp_offset[ix]); 903 break; 904 default: 905 dev_dbg(dev, "Unknown function %d.\n", fn); 906 } 907 mutex_unlock(&data->update_lock); 908 909 return count; 910} 911 912/* --------------------------------------------------------------------- 913 * Zone sysfs attributes 914 * ix = [0-2] 915 * --------------------------------------------------------------------- */ 916 917#define SYS_ZONE_AUTO_CHANNELS_TEMP 0 918#define SYS_ZONE_AUTO_POINT1_TEMP_HYST 1 919#define SYS_ZONE_AUTO_POINT1_TEMP 2 920#define SYS_ZONE_AUTO_POINT2_TEMP 3 921#define SYS_ZONE_AUTO_POINT3_TEMP 4 922 923static ssize_t show_zone(struct device *dev, struct device_attribute *attr, 924 char *buf) 925{ 926 struct dme1737_data *data = dme1737_update_device(dev); 927 struct sensor_device_attribute_2 928 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 929 int ix = sensor_attr_2->index; 930 int fn = sensor_attr_2->nr; 931 int res; 932 933 switch (fn) { 934 case SYS_ZONE_AUTO_CHANNELS_TEMP: 935 /* check config2 for non-standard temp-to-zone mapping */ 936 if ((ix == 1) && (data->config2 & 0x02)) { 937 res = 4; 938 } else { 939 res = 1 << ix; 940 } 941 break; 942 case SYS_ZONE_AUTO_POINT1_TEMP_HYST: 943 res = TEMP_FROM_REG(data->zone_low[ix], 8) - 944 TEMP_HYST_FROM_REG(data->zone_hyst[ix == 2], ix); 945 break; 946 case SYS_ZONE_AUTO_POINT1_TEMP: 947 res = TEMP_FROM_REG(data->zone_low[ix], 8); 948 break; 949 case SYS_ZONE_AUTO_POINT2_TEMP: 950 /* pwm_freq holds the temp range bits in the upper nibble */ 951 res = TEMP_FROM_REG(data->zone_low[ix], 8) + 952 TEMP_RANGE_FROM_REG(data->pwm_freq[ix]); 953 break; 954 case SYS_ZONE_AUTO_POINT3_TEMP: 955 res = TEMP_FROM_REG(data->zone_abs[ix], 8); 956 break; 957 default: 958 res = 0; 959 dev_dbg(dev, "Unknown function %d.\n", fn); 960 } 961 962 return sprintf(buf, "%d\n", res); 963} 964 965static ssize_t set_zone(struct device *dev, struct device_attribute *attr, 966 const char *buf, size_t count) 967{ 968 struct dme1737_data *data = dev_get_drvdata(dev); 969 struct sensor_device_attribute_2 970 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 971 int ix = sensor_attr_2->index; 972 int fn = sensor_attr_2->nr; 973 long val = simple_strtol(buf, NULL, 10); 974 975 mutex_lock(&data->update_lock); 976 switch (fn) { 977 case SYS_ZONE_AUTO_POINT1_TEMP_HYST: 978 /* Refresh the cache */ 979 data->zone_low[ix] = dme1737_read(data, 980 DME1737_REG_ZONE_LOW(ix)); 981 /* Modify the temp hyst value */ 982 data->zone_hyst[ix == 2] = TEMP_HYST_TO_REG( 983 TEMP_FROM_REG(data->zone_low[ix], 8) - 984 val, ix, dme1737_read(data, 985 DME1737_REG_ZONE_HYST(ix == 2))); 986 dme1737_write(data, DME1737_REG_ZONE_HYST(ix == 2), 987 data->zone_hyst[ix == 2]); 988 break; 989 case SYS_ZONE_AUTO_POINT1_TEMP: 990 data->zone_low[ix] = TEMP_TO_REG(val); 991 dme1737_write(data, DME1737_REG_ZONE_LOW(ix), 992 data->zone_low[ix]); 993 break; 994 case SYS_ZONE_AUTO_POINT2_TEMP: 995 /* Refresh the cache */ 996 data->zone_low[ix] = dme1737_read(data, 997 DME1737_REG_ZONE_LOW(ix)); 998 /* Modify the temp range value (which is stored in the upper 999 * nibble of the pwm_freq register) */ 1000 data->pwm_freq[ix] = TEMP_RANGE_TO_REG(val - 1001 TEMP_FROM_REG(data->zone_low[ix], 8), 1002 dme1737_read(data, 1003 DME1737_REG_PWM_FREQ(ix))); 1004 dme1737_write(data, DME1737_REG_PWM_FREQ(ix), 1005 data->pwm_freq[ix]); 1006 break; 1007 case SYS_ZONE_AUTO_POINT3_TEMP: 1008 data->zone_abs[ix] = TEMP_TO_REG(val); 1009 dme1737_write(data, DME1737_REG_ZONE_ABS(ix), 1010 data->zone_abs[ix]); 1011 break; 1012 default: 1013 dev_dbg(dev, "Unknown function %d.\n", fn); 1014 } 1015 mutex_unlock(&data->update_lock); 1016 1017 return count; 1018} 1019 1020/* --------------------------------------------------------------------- 1021 * Fan sysfs attributes 1022 * ix = [0-5] 1023 * --------------------------------------------------------------------- */ 1024 1025#define SYS_FAN_INPUT 0 1026#define SYS_FAN_MIN 1 1027#define SYS_FAN_MAX 2 1028#define SYS_FAN_ALARM 3 1029#define SYS_FAN_TYPE 4 1030 1031static ssize_t show_fan(struct device *dev, struct device_attribute *attr, 1032 char *buf) 1033{ 1034 struct dme1737_data *data = dme1737_update_device(dev); 1035 struct sensor_device_attribute_2 1036 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1037 int ix = sensor_attr_2->index; 1038 int fn = sensor_attr_2->nr; 1039 int res; 1040 1041 switch (fn) { 1042 case SYS_FAN_INPUT: 1043 res = FAN_FROM_REG(data->fan[ix], 1044 ix < 4 ? 0 : 1045 FAN_TPC_FROM_REG(data->fan_opt[ix])); 1046 break; 1047 case SYS_FAN_MIN: 1048 res = FAN_FROM_REG(data->fan_min[ix], 1049 ix < 4 ? 0 : 1050 FAN_TPC_FROM_REG(data->fan_opt[ix])); 1051 break; 1052 case SYS_FAN_MAX: 1053 /* only valid for fan[5-6] */ 1054 res = FAN_MAX_FROM_REG(data->fan_max[ix - 4]); 1055 break; 1056 case SYS_FAN_ALARM: 1057 res = (data->alarms >> DME1737_BIT_ALARM_FAN[ix]) & 0x01; 1058 break; 1059 case SYS_FAN_TYPE: 1060 /* only valid for fan[1-4] */ 1061 res = FAN_TYPE_FROM_REG(data->fan_opt[ix]); 1062 break; 1063 default: 1064 res = 0; 1065 dev_dbg(dev, "Unknown function %d.\n", fn); 1066 } 1067 1068 return sprintf(buf, "%d\n", res); 1069} 1070 1071static ssize_t set_fan(struct device *dev, struct device_attribute *attr, 1072 const char *buf, size_t count) 1073{ 1074 struct dme1737_data *data = dev_get_drvdata(dev); 1075 struct sensor_device_attribute_2 1076 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1077 int ix = sensor_attr_2->index; 1078 int fn = sensor_attr_2->nr; 1079 long val = simple_strtol(buf, NULL, 10); 1080 1081 mutex_lock(&data->update_lock); 1082 switch (fn) { 1083 case SYS_FAN_MIN: 1084 if (ix < 4) { 1085 data->fan_min[ix] = FAN_TO_REG(val, 0); 1086 } else { 1087 /* Refresh the cache */ 1088 data->fan_opt[ix] = dme1737_read(data, 1089 DME1737_REG_FAN_OPT(ix)); 1090 /* Modify the fan min value */ 1091 data->fan_min[ix] = FAN_TO_REG(val, 1092 FAN_TPC_FROM_REG(data->fan_opt[ix])); 1093 } 1094 dme1737_write(data, DME1737_REG_FAN_MIN(ix), 1095 data->fan_min[ix] & 0xff); 1096 dme1737_write(data, DME1737_REG_FAN_MIN(ix) + 1, 1097 data->fan_min[ix] >> 8); 1098 break; 1099 case SYS_FAN_MAX: 1100 /* Only valid for fan[5-6] */ 1101 data->fan_max[ix - 4] = FAN_MAX_TO_REG(val); 1102 dme1737_write(data, DME1737_REG_FAN_MAX(ix), 1103 data->fan_max[ix - 4]); 1104 break; 1105 case SYS_FAN_TYPE: 1106 /* Only valid for fan[1-4] */ 1107 if (!(val == 1 || val == 2 || val == 4)) { 1108 count = -EINVAL; 1109 dev_warn(dev, "Fan type value %ld not " 1110 "supported. Choose one of 1, 2, or 4.\n", 1111 val); 1112 goto exit; 1113 } 1114 data->fan_opt[ix] = FAN_TYPE_TO_REG(val, dme1737_read(data, 1115 DME1737_REG_FAN_OPT(ix))); 1116 dme1737_write(data, DME1737_REG_FAN_OPT(ix), 1117 data->fan_opt[ix]); 1118 break; 1119 default: 1120 dev_dbg(dev, "Unknown function %d.\n", fn); 1121 } 1122exit: 1123 mutex_unlock(&data->update_lock); 1124 1125 return count; 1126} 1127 1128/* --------------------------------------------------------------------- 1129 * PWM sysfs attributes 1130 * ix = [0-4] 1131 * --------------------------------------------------------------------- */ 1132 1133#define SYS_PWM 0 1134#define SYS_PWM_FREQ 1 1135#define SYS_PWM_ENABLE 2 1136#define SYS_PWM_RAMP_RATE 3 1137#define SYS_PWM_AUTO_CHANNELS_ZONE 4 1138#define SYS_PWM_AUTO_PWM_MIN 5 1139#define SYS_PWM_AUTO_POINT1_PWM 6 1140#define SYS_PWM_AUTO_POINT2_PWM 7 1141 1142static ssize_t show_pwm(struct device *dev, struct device_attribute *attr, 1143 char *buf) 1144{ 1145 struct dme1737_data *data = dme1737_update_device(dev); 1146 struct sensor_device_attribute_2 1147 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1148 int ix = sensor_attr_2->index; 1149 int fn = sensor_attr_2->nr; 1150 int res; 1151 1152 switch (fn) { 1153 case SYS_PWM: 1154 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 0) { 1155 res = 255; 1156 } else { 1157 res = data->pwm[ix]; 1158 } 1159 break; 1160 case SYS_PWM_FREQ: 1161 res = PWM_FREQ_FROM_REG(data->pwm_freq[ix]); 1162 break; 1163 case SYS_PWM_ENABLE: 1164 if (ix >= 3) { 1165 res = 1; /* pwm[5-6] hard-wired to manual mode */ 1166 } else { 1167 res = PWM_EN_FROM_REG(data->pwm_config[ix]); 1168 } 1169 break; 1170 case SYS_PWM_RAMP_RATE: 1171 /* Only valid for pwm[1-3] */ 1172 res = PWM_RR_FROM_REG(data->pwm_rr[ix > 0], ix); 1173 break; 1174 case SYS_PWM_AUTO_CHANNELS_ZONE: 1175 /* Only valid for pwm[1-3] */ 1176 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1177 res = PWM_ACZ_FROM_REG(data->pwm_config[ix]); 1178 } else { 1179 res = data->pwm_acz[ix]; 1180 } 1181 break; 1182 case SYS_PWM_AUTO_PWM_MIN: 1183 /* Only valid for pwm[1-3] */ 1184 if (PWM_OFF_FROM_REG(data->pwm_rr[0], ix)) { 1185 res = data->pwm_min[ix]; 1186 } else { 1187 res = 0; 1188 } 1189 break; 1190 case SYS_PWM_AUTO_POINT1_PWM: 1191 /* Only valid for pwm[1-3] */ 1192 res = data->pwm_min[ix]; 1193 break; 1194 case SYS_PWM_AUTO_POINT2_PWM: 1195 /* Only valid for pwm[1-3] */ 1196 res = 255; /* hard-wired */ 1197 break; 1198 default: 1199 res = 0; 1200 dev_dbg(dev, "Unknown function %d.\n", fn); 1201 } 1202 1203 return sprintf(buf, "%d\n", res); 1204} 1205 1206static struct attribute *dme1737_pwm_chmod_attr[]; 1207static void dme1737_chmod_file(struct device*, struct attribute*, mode_t); 1208 1209static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, 1210 const char *buf, size_t count) 1211{ 1212 struct dme1737_data *data = dev_get_drvdata(dev); 1213 struct sensor_device_attribute_2 1214 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1215 int ix = sensor_attr_2->index; 1216 int fn = sensor_attr_2->nr; 1217 long val = simple_strtol(buf, NULL, 10); 1218 1219 mutex_lock(&data->update_lock); 1220 switch (fn) { 1221 case SYS_PWM: 1222 data->pwm[ix] = SENSORS_LIMIT(val, 0, 255); 1223 dme1737_write(data, DME1737_REG_PWM(ix), data->pwm[ix]); 1224 break; 1225 case SYS_PWM_FREQ: 1226 data->pwm_freq[ix] = PWM_FREQ_TO_REG(val, dme1737_read(data, 1227 DME1737_REG_PWM_FREQ(ix))); 1228 dme1737_write(data, DME1737_REG_PWM_FREQ(ix), 1229 data->pwm_freq[ix]); 1230 break; 1231 case SYS_PWM_ENABLE: 1232 /* Only valid for pwm[1-3] */ 1233 if (val < 0 || val > 2) { 1234 count = -EINVAL; 1235 dev_warn(dev, "PWM enable %ld not " 1236 "supported. Choose one of 0, 1, or 2.\n", 1237 val); 1238 goto exit; 1239 } 1240 /* Refresh the cache */ 1241 data->pwm_config[ix] = dme1737_read(data, 1242 DME1737_REG_PWM_CONFIG(ix)); 1243 if (val == PWM_EN_FROM_REG(data->pwm_config[ix])) { 1244 /* Bail out if no change */ 1245 goto exit; 1246 } 1247 /* Do some housekeeping if we are currently in auto mode */ 1248 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1249 /* Save the current zone channel assignment */ 1250 data->pwm_acz[ix] = PWM_ACZ_FROM_REG( 1251 data->pwm_config[ix]); 1252 /* Save the current ramp rate state and disable it */ 1253 data->pwm_rr[ix > 0] = dme1737_read(data, 1254 DME1737_REG_PWM_RR(ix > 0)); 1255 data->pwm_rr_en &= ~(1 << ix); 1256 if (PWM_RR_EN_FROM_REG(data->pwm_rr[ix > 0], ix)) { 1257 data->pwm_rr_en |= (1 << ix); 1258 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(0, ix, 1259 data->pwm_rr[ix > 0]); 1260 dme1737_write(data, 1261 DME1737_REG_PWM_RR(ix > 0), 1262 data->pwm_rr[ix > 0]); 1263 } 1264 } 1265 /* Set the new PWM mode */ 1266 switch (val) { 1267 case 0: 1268 /* Change permissions of pwm[ix] to read-only */ 1269 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], 1270 S_IRUGO); 1271 /* Turn fan fully on */ 1272 data->pwm_config[ix] = PWM_EN_TO_REG(0, 1273 data->pwm_config[ix]); 1274 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix), 1275 data->pwm_config[ix]); 1276 break; 1277 case 1: 1278 /* Turn on manual mode */ 1279 data->pwm_config[ix] = PWM_EN_TO_REG(1, 1280 data->pwm_config[ix]); 1281 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix), 1282 data->pwm_config[ix]); 1283 /* Change permissions of pwm[ix] to read-writeable */ 1284 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], 1285 S_IRUGO | S_IWUSR); 1286 break; 1287 case 2: 1288 /* Change permissions of pwm[ix] to read-only */ 1289 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], 1290 S_IRUGO); 1291 /* Turn on auto mode using the saved zone channel 1292 * assignment */ 1293 data->pwm_config[ix] = PWM_ACZ_TO_REG( 1294 data->pwm_acz[ix], 1295 data->pwm_config[ix]); 1296 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix), 1297 data->pwm_config[ix]); 1298 /* Enable PWM ramp rate if previously enabled */ 1299 if (data->pwm_rr_en & (1 << ix)) { 1300 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(1, ix, 1301 dme1737_read(data, 1302 DME1737_REG_PWM_RR(ix > 0))); 1303 dme1737_write(data, 1304 DME1737_REG_PWM_RR(ix > 0), 1305 data->pwm_rr[ix > 0]); 1306 } 1307 break; 1308 } 1309 break; 1310 case SYS_PWM_RAMP_RATE: 1311 /* Only valid for pwm[1-3] */ 1312 /* Refresh the cache */ 1313 data->pwm_config[ix] = dme1737_read(data, 1314 DME1737_REG_PWM_CONFIG(ix)); 1315 data->pwm_rr[ix > 0] = dme1737_read(data, 1316 DME1737_REG_PWM_RR(ix > 0)); 1317 /* Set the ramp rate value */ 1318 if (val > 0) { 1319 data->pwm_rr[ix > 0] = PWM_RR_TO_REG(val, ix, 1320 data->pwm_rr[ix > 0]); 1321 } 1322 /* Enable/disable the feature only if the associated PWM 1323 * output is in automatic mode. */ 1324 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1325 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(val > 0, ix, 1326 data->pwm_rr[ix > 0]); 1327 } 1328 dme1737_write(data, DME1737_REG_PWM_RR(ix > 0), 1329 data->pwm_rr[ix > 0]); 1330 break; 1331 case SYS_PWM_AUTO_CHANNELS_ZONE: 1332 /* Only valid for pwm[1-3] */ 1333 if (!(val == 1 || val == 2 || val == 4 || 1334 val == 6 || val == 7)) { 1335 count = -EINVAL; 1336 dev_warn(dev, "PWM auto channels zone %ld " 1337 "not supported. Choose one of 1, 2, 4, 6, " 1338 "or 7.\n", val); 1339 goto exit; 1340 } 1341 /* Refresh the cache */ 1342 data->pwm_config[ix] = dme1737_read(data, 1343 DME1737_REG_PWM_CONFIG(ix)); 1344 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1345 /* PWM is already in auto mode so update the temp 1346 * channel assignment */ 1347 data->pwm_config[ix] = PWM_ACZ_TO_REG(val, 1348 data->pwm_config[ix]); 1349 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix), 1350 data->pwm_config[ix]); 1351 } else { 1352 /* PWM is not in auto mode so we save the temp 1353 * channel assignment for later use */ 1354 data->pwm_acz[ix] = val; 1355 } 1356 break; 1357 case SYS_PWM_AUTO_PWM_MIN: 1358 /* Only valid for pwm[1-3] */ 1359 /* Refresh the cache */ 1360 data->pwm_min[ix] = dme1737_read(data, 1361 DME1737_REG_PWM_MIN(ix)); 1362 /* There are only 2 values supported for the auto_pwm_min 1363 * value: 0 or auto_point1_pwm. So if the temperature drops 1364 * below the auto_point1_temp_hyst value, the fan either turns 1365 * off or runs at auto_point1_pwm duty-cycle. */ 1366 if (val > ((data->pwm_min[ix] + 1) / 2)) { 1367 data->pwm_rr[0] = PWM_OFF_TO_REG(1, ix, 1368 dme1737_read(data, 1369 DME1737_REG_PWM_RR(0))); 1370 } else { 1371 data->pwm_rr[0] = PWM_OFF_TO_REG(0, ix, 1372 dme1737_read(data, 1373 DME1737_REG_PWM_RR(0))); 1374 } 1375 dme1737_write(data, DME1737_REG_PWM_RR(0), 1376 data->pwm_rr[0]); 1377 break; 1378 case SYS_PWM_AUTO_POINT1_PWM: 1379 /* Only valid for pwm[1-3] */ 1380 data->pwm_min[ix] = SENSORS_LIMIT(val, 0, 255); 1381 dme1737_write(data, DME1737_REG_PWM_MIN(ix), 1382 data->pwm_min[ix]); 1383 break; 1384 default: 1385 dev_dbg(dev, "Unknown function %d.\n", fn); 1386 } 1387exit: 1388 mutex_unlock(&data->update_lock); 1389 1390 return count; 1391} 1392 1393/* --------------------------------------------------------------------- 1394 * Miscellaneous sysfs attributes 1395 * --------------------------------------------------------------------- */ 1396 1397static ssize_t show_vrm(struct device *dev, struct device_attribute *attr, 1398 char *buf) 1399{ 1400 struct i2c_client *client = to_i2c_client(dev); 1401 struct dme1737_data *data = i2c_get_clientdata(client); 1402 1403 return sprintf(buf, "%d\n", data->vrm); 1404} 1405 1406static ssize_t set_vrm(struct device *dev, struct device_attribute *attr, 1407 const char *buf, size_t count) 1408{ 1409 struct dme1737_data *data = dev_get_drvdata(dev); 1410 long val = simple_strtol(buf, NULL, 10); 1411 1412 data->vrm = val; 1413 return count; 1414} 1415 1416static ssize_t show_vid(struct device *dev, struct device_attribute *attr, 1417 char *buf) 1418{ 1419 struct dme1737_data *data = dme1737_update_device(dev); 1420 1421 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm)); 1422} 1423 1424static ssize_t show_name(struct device *dev, struct device_attribute *attr, 1425 char *buf) 1426{ 1427 struct dme1737_data *data = dev_get_drvdata(dev); 1428 1429 return sprintf(buf, "%s\n", data->name); 1430} 1431 1432/* --------------------------------------------------------------------- 1433 * Sysfs device attribute defines and structs 1434 * --------------------------------------------------------------------- */ 1435 1436/* Voltages 0-6 */ 1437 1438#define SENSOR_DEVICE_ATTR_IN(ix) \ 1439static SENSOR_DEVICE_ATTR_2(in##ix##_input, S_IRUGO, \ 1440 show_in, NULL, SYS_IN_INPUT, ix); \ 1441static SENSOR_DEVICE_ATTR_2(in##ix##_min, S_IRUGO | S_IWUSR, \ 1442 show_in, set_in, SYS_IN_MIN, ix); \ 1443static SENSOR_DEVICE_ATTR_2(in##ix##_max, S_IRUGO | S_IWUSR, \ 1444 show_in, set_in, SYS_IN_MAX, ix); \ 1445static SENSOR_DEVICE_ATTR_2(in##ix##_alarm, S_IRUGO, \ 1446 show_in, NULL, SYS_IN_ALARM, ix) 1447 1448SENSOR_DEVICE_ATTR_IN(0); 1449SENSOR_DEVICE_ATTR_IN(1); 1450SENSOR_DEVICE_ATTR_IN(2); 1451SENSOR_DEVICE_ATTR_IN(3); 1452SENSOR_DEVICE_ATTR_IN(4); 1453SENSOR_DEVICE_ATTR_IN(5); 1454SENSOR_DEVICE_ATTR_IN(6); 1455 1456/* Temperatures 1-3 */ 1457 1458#define SENSOR_DEVICE_ATTR_TEMP(ix) \ 1459static SENSOR_DEVICE_ATTR_2(temp##ix##_input, S_IRUGO, \ 1460 show_temp, NULL, SYS_TEMP_INPUT, ix-1); \ 1461static SENSOR_DEVICE_ATTR_2(temp##ix##_min, S_IRUGO | S_IWUSR, \ 1462 show_temp, set_temp, SYS_TEMP_MIN, ix-1); \ 1463static SENSOR_DEVICE_ATTR_2(temp##ix##_max, S_IRUGO | S_IWUSR, \ 1464 show_temp, set_temp, SYS_TEMP_MAX, ix-1); \ 1465static SENSOR_DEVICE_ATTR_2(temp##ix##_offset, S_IRUGO, \ 1466 show_temp, set_temp, SYS_TEMP_OFFSET, ix-1); \ 1467static SENSOR_DEVICE_ATTR_2(temp##ix##_alarm, S_IRUGO, \ 1468 show_temp, NULL, SYS_TEMP_ALARM, ix-1); \ 1469static SENSOR_DEVICE_ATTR_2(temp##ix##_fault, S_IRUGO, \ 1470 show_temp, NULL, SYS_TEMP_FAULT, ix-1) 1471 1472SENSOR_DEVICE_ATTR_TEMP(1); 1473SENSOR_DEVICE_ATTR_TEMP(2); 1474SENSOR_DEVICE_ATTR_TEMP(3); 1475 1476/* Zones 1-3 */ 1477 1478#define SENSOR_DEVICE_ATTR_ZONE(ix) \ 1479static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_channels_temp, S_IRUGO, \ 1480 show_zone, NULL, SYS_ZONE_AUTO_CHANNELS_TEMP, ix-1); \ 1481static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp_hyst, S_IRUGO, \ 1482 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP_HYST, ix-1); \ 1483static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp, S_IRUGO, \ 1484 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP, ix-1); \ 1485static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point2_temp, S_IRUGO, \ 1486 show_zone, set_zone, SYS_ZONE_AUTO_POINT2_TEMP, ix-1); \ 1487static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point3_temp, S_IRUGO, \ 1488 show_zone, set_zone, SYS_ZONE_AUTO_POINT3_TEMP, ix-1) 1489 1490SENSOR_DEVICE_ATTR_ZONE(1); 1491SENSOR_DEVICE_ATTR_ZONE(2); 1492SENSOR_DEVICE_ATTR_ZONE(3); 1493 1494/* Fans 1-4 */ 1495 1496#define SENSOR_DEVICE_ATTR_FAN_1TO4(ix) \ 1497static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \ 1498 show_fan, NULL, SYS_FAN_INPUT, ix-1); \ 1499static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \ 1500 show_fan, set_fan, SYS_FAN_MIN, ix-1); \ 1501static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \ 1502 show_fan, NULL, SYS_FAN_ALARM, ix-1); \ 1503static SENSOR_DEVICE_ATTR_2(fan##ix##_type, S_IRUGO | S_IWUSR, \ 1504 show_fan, set_fan, SYS_FAN_TYPE, ix-1) 1505 1506SENSOR_DEVICE_ATTR_FAN_1TO4(1); 1507SENSOR_DEVICE_ATTR_FAN_1TO4(2); 1508SENSOR_DEVICE_ATTR_FAN_1TO4(3); 1509SENSOR_DEVICE_ATTR_FAN_1TO4(4); 1510 1511/* Fans 5-6 */ 1512 1513#define SENSOR_DEVICE_ATTR_FAN_5TO6(ix) \ 1514static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \ 1515 show_fan, NULL, SYS_FAN_INPUT, ix-1); \ 1516static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \ 1517 show_fan, set_fan, SYS_FAN_MIN, ix-1); \ 1518static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \ 1519 show_fan, NULL, SYS_FAN_ALARM, ix-1); \ 1520static SENSOR_DEVICE_ATTR_2(fan##ix##_max, S_IRUGO | S_IWUSR, \ 1521 show_fan, set_fan, SYS_FAN_MAX, ix-1) 1522 1523SENSOR_DEVICE_ATTR_FAN_5TO6(5); 1524SENSOR_DEVICE_ATTR_FAN_5TO6(6); 1525 1526/* PWMs 1-3 */ 1527 1528#define SENSOR_DEVICE_ATTR_PWM_1TO3(ix) \ 1529static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \ 1530 show_pwm, set_pwm, SYS_PWM, ix-1); \ 1531static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \ 1532 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \ 1533static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \ 1534 show_pwm, set_pwm, SYS_PWM_ENABLE, ix-1); \ 1535static SENSOR_DEVICE_ATTR_2(pwm##ix##_ramp_rate, S_IRUGO, \ 1536 show_pwm, set_pwm, SYS_PWM_RAMP_RATE, ix-1); \ 1537static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_channels_zone, S_IRUGO, \ 1538 show_pwm, set_pwm, SYS_PWM_AUTO_CHANNELS_ZONE, ix-1); \ 1539static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_pwm_min, S_IRUGO, \ 1540 show_pwm, set_pwm, SYS_PWM_AUTO_PWM_MIN, ix-1); \ 1541static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point1_pwm, S_IRUGO, \ 1542 show_pwm, set_pwm, SYS_PWM_AUTO_POINT1_PWM, ix-1); \ 1543static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point2_pwm, S_IRUGO, \ 1544 show_pwm, NULL, SYS_PWM_AUTO_POINT2_PWM, ix-1) 1545 1546SENSOR_DEVICE_ATTR_PWM_1TO3(1); 1547SENSOR_DEVICE_ATTR_PWM_1TO3(2); 1548SENSOR_DEVICE_ATTR_PWM_1TO3(3); 1549 1550/* PWMs 5-6 */ 1551 1552#define SENSOR_DEVICE_ATTR_PWM_5TO6(ix) \ 1553static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \ 1554 show_pwm, set_pwm, SYS_PWM, ix-1); \ 1555static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \ 1556 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \ 1557static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \ 1558 show_pwm, NULL, SYS_PWM_ENABLE, ix-1) 1559 1560SENSOR_DEVICE_ATTR_PWM_5TO6(5); 1561SENSOR_DEVICE_ATTR_PWM_5TO6(6); 1562 1563/* Misc */ 1564 1565static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm, set_vrm); 1566static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL); 1567static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); /* for ISA devices */ 1568 1569/* This struct holds all the attributes that are always present and need to be 1570 * created unconditionally. The attributes that need modification of their 1571 * permissions are created read-only and write permissions are added or removed 1572 * on the fly when required */ 1573static struct attribute *dme1737_attr[] ={ 1574 /* Voltages */ 1575 &sensor_dev_attr_in0_input.dev_attr.attr, 1576 &sensor_dev_attr_in0_min.dev_attr.attr, 1577 &sensor_dev_attr_in0_max.dev_attr.attr, 1578 &sensor_dev_attr_in0_alarm.dev_attr.attr, 1579 &sensor_dev_attr_in1_input.dev_attr.attr, 1580 &sensor_dev_attr_in1_min.dev_attr.attr, 1581 &sensor_dev_attr_in1_max.dev_attr.attr, 1582 &sensor_dev_attr_in1_alarm.dev_attr.attr, 1583 &sensor_dev_attr_in2_input.dev_attr.attr, 1584 &sensor_dev_attr_in2_min.dev_attr.attr, 1585 &sensor_dev_attr_in2_max.dev_attr.attr, 1586 &sensor_dev_attr_in2_alarm.dev_attr.attr, 1587 &sensor_dev_attr_in3_input.dev_attr.attr, 1588 &sensor_dev_attr_in3_min.dev_attr.attr, 1589 &sensor_dev_attr_in3_max.dev_attr.attr, 1590 &sensor_dev_attr_in3_alarm.dev_attr.attr, 1591 &sensor_dev_attr_in4_input.dev_attr.attr, 1592 &sensor_dev_attr_in4_min.dev_attr.attr, 1593 &sensor_dev_attr_in4_max.dev_attr.attr, 1594 &sensor_dev_attr_in4_alarm.dev_attr.attr, 1595 &sensor_dev_attr_in5_input.dev_attr.attr, 1596 &sensor_dev_attr_in5_min.dev_attr.attr, 1597 &sensor_dev_attr_in5_max.dev_attr.attr, 1598 &sensor_dev_attr_in5_alarm.dev_attr.attr, 1599 &sensor_dev_attr_in6_input.dev_attr.attr, 1600 &sensor_dev_attr_in6_min.dev_attr.attr, 1601 &sensor_dev_attr_in6_max.dev_attr.attr, 1602 &sensor_dev_attr_in6_alarm.dev_attr.attr, 1603 /* Temperatures */ 1604 &sensor_dev_attr_temp1_input.dev_attr.attr, 1605 &sensor_dev_attr_temp1_min.dev_attr.attr, 1606 &sensor_dev_attr_temp1_max.dev_attr.attr, 1607 &sensor_dev_attr_temp1_alarm.dev_attr.attr, 1608 &sensor_dev_attr_temp1_fault.dev_attr.attr, 1609 &sensor_dev_attr_temp2_input.dev_attr.attr, 1610 &sensor_dev_attr_temp2_min.dev_attr.attr, 1611 &sensor_dev_attr_temp2_max.dev_attr.attr, 1612 &sensor_dev_attr_temp2_alarm.dev_attr.attr, 1613 &sensor_dev_attr_temp2_fault.dev_attr.attr, 1614 &sensor_dev_attr_temp3_input.dev_attr.attr, 1615 &sensor_dev_attr_temp3_min.dev_attr.attr, 1616 &sensor_dev_attr_temp3_max.dev_attr.attr, 1617 &sensor_dev_attr_temp3_alarm.dev_attr.attr, 1618 &sensor_dev_attr_temp3_fault.dev_attr.attr, 1619 /* Zones */ 1620 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr, 1621 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr, 1622 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr, 1623 &sensor_dev_attr_zone1_auto_channels_temp.dev_attr.attr, 1624 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr, 1625 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr, 1626 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr, 1627 &sensor_dev_attr_zone2_auto_channels_temp.dev_attr.attr, 1628 NULL 1629}; 1630 1631static const struct attribute_group dme1737_group = { 1632 .attrs = dme1737_attr, 1633}; 1634 1635/* The following struct holds temp offset attributes, which are not available 1636 * in all chips. The following chips support them: 1637 * DME1737, SCH311x */ 1638static struct attribute *dme1737_temp_offset_attr[] = { 1639 &sensor_dev_attr_temp1_offset.dev_attr.attr, 1640 &sensor_dev_attr_temp2_offset.dev_attr.attr, 1641 &sensor_dev_attr_temp3_offset.dev_attr.attr, 1642 NULL 1643}; 1644 1645static const struct attribute_group dme1737_temp_offset_group = { 1646 .attrs = dme1737_temp_offset_attr, 1647}; 1648 1649/* The following struct holds VID related attributes, which are not available 1650 * in all chips. The following chips support them: 1651 * DME1737 */ 1652static struct attribute *dme1737_vid_attr[] = { 1653 &dev_attr_vrm.attr, 1654 &dev_attr_cpu0_vid.attr, 1655 NULL 1656}; 1657 1658static const struct attribute_group dme1737_vid_group = { 1659 .attrs = dme1737_vid_attr, 1660}; 1661 1662/* The following struct holds temp zone 3 related attributes, which are not 1663 * available in all chips. The following chips support them: 1664 * DME1737, SCH311x, SCH5027 */ 1665static struct attribute *dme1737_zone3_attr[] = { 1666 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr, 1667 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr, 1668 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr, 1669 &sensor_dev_attr_zone3_auto_channels_temp.dev_attr.attr, 1670 NULL 1671}; 1672 1673static const struct attribute_group dme1737_zone3_group = { 1674 .attrs = dme1737_zone3_attr, 1675}; 1676 1677 1678/* The following struct holds temp zone hysteresis related attributes, which 1679 * are not available in all chips. The following chips support them: 1680 * DME1737, SCH311x */ 1681static struct attribute *dme1737_zone_hyst_attr[] = { 1682 &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr, 1683 &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr, 1684 &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr, 1685 NULL 1686}; 1687 1688static const struct attribute_group dme1737_zone_hyst_group = { 1689 .attrs = dme1737_zone_hyst_attr, 1690}; 1691 1692/* The following structs hold the PWM attributes, some of which are optional. 1693 * Their creation depends on the chip configuration which is determined during 1694 * module load. */ 1695static struct attribute *dme1737_pwm1_attr[] = { 1696 &sensor_dev_attr_pwm1.dev_attr.attr, 1697 &sensor_dev_attr_pwm1_freq.dev_attr.attr, 1698 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 1699 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr, 1700 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr, 1701 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, 1702 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, 1703 NULL 1704}; 1705static struct attribute *dme1737_pwm2_attr[] = { 1706 &sensor_dev_attr_pwm2.dev_attr.attr, 1707 &sensor_dev_attr_pwm2_freq.dev_attr.attr, 1708 &sensor_dev_attr_pwm2_enable.dev_attr.attr, 1709 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr, 1710 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr, 1711 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, 1712 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, 1713 NULL 1714}; 1715static struct attribute *dme1737_pwm3_attr[] = { 1716 &sensor_dev_attr_pwm3.dev_attr.attr, 1717 &sensor_dev_attr_pwm3_freq.dev_attr.attr, 1718 &sensor_dev_attr_pwm3_enable.dev_attr.attr, 1719 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr, 1720 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr, 1721 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, 1722 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, 1723 NULL 1724}; 1725static struct attribute *dme1737_pwm5_attr[] = { 1726 &sensor_dev_attr_pwm5.dev_attr.attr, 1727 &sensor_dev_attr_pwm5_freq.dev_attr.attr, 1728 &sensor_dev_attr_pwm5_enable.dev_attr.attr, 1729 NULL 1730}; 1731static struct attribute *dme1737_pwm6_attr[] = { 1732 &sensor_dev_attr_pwm6.dev_attr.attr, 1733 &sensor_dev_attr_pwm6_freq.dev_attr.attr, 1734 &sensor_dev_attr_pwm6_enable.dev_attr.attr, 1735 NULL 1736}; 1737 1738static const struct attribute_group dme1737_pwm_group[] = { 1739 { .attrs = dme1737_pwm1_attr }, 1740 { .attrs = dme1737_pwm2_attr }, 1741 { .attrs = dme1737_pwm3_attr }, 1742 { .attrs = NULL }, 1743 { .attrs = dme1737_pwm5_attr }, 1744 { .attrs = dme1737_pwm6_attr }, 1745}; 1746 1747/* The following struct holds auto PWM min attributes, which are not available 1748 * in all chips. Their creation depends on the chip type which is determined 1749 * during module load. */ 1750static struct attribute *dme1737_auto_pwm_min_attr[] = { 1751 &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr, 1752 &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr, 1753 &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr, 1754}; 1755 1756/* The following structs hold the fan attributes, some of which are optional. 1757 * Their creation depends on the chip configuration which is determined during 1758 * module load. */ 1759static struct attribute *dme1737_fan1_attr[] = { 1760 &sensor_dev_attr_fan1_input.dev_attr.attr, 1761 &sensor_dev_attr_fan1_min.dev_attr.attr, 1762 &sensor_dev_attr_fan1_alarm.dev_attr.attr, 1763 &sensor_dev_attr_fan1_type.dev_attr.attr, 1764 NULL 1765}; 1766static struct attribute *dme1737_fan2_attr[] = { 1767 &sensor_dev_attr_fan2_input.dev_attr.attr, 1768 &sensor_dev_attr_fan2_min.dev_attr.attr, 1769 &sensor_dev_attr_fan2_alarm.dev_attr.attr, 1770 &sensor_dev_attr_fan2_type.dev_attr.attr, 1771 NULL 1772}; 1773static struct attribute *dme1737_fan3_attr[] = { 1774 &sensor_dev_attr_fan3_input.dev_attr.attr, 1775 &sensor_dev_attr_fan3_min.dev_attr.attr, 1776 &sensor_dev_attr_fan3_alarm.dev_attr.attr, 1777 &sensor_dev_attr_fan3_type.dev_attr.attr, 1778 NULL 1779}; 1780static struct attribute *dme1737_fan4_attr[] = { 1781 &sensor_dev_attr_fan4_input.dev_attr.attr, 1782 &sensor_dev_attr_fan4_min.dev_attr.attr, 1783 &sensor_dev_attr_fan4_alarm.dev_attr.attr, 1784 &sensor_dev_attr_fan4_type.dev_attr.attr, 1785 NULL 1786}; 1787static struct attribute *dme1737_fan5_attr[] = { 1788 &sensor_dev_attr_fan5_input.dev_attr.attr, 1789 &sensor_dev_attr_fan5_min.dev_attr.attr, 1790 &sensor_dev_attr_fan5_alarm.dev_attr.attr, 1791 &sensor_dev_attr_fan5_max.dev_attr.attr, 1792 NULL 1793}; 1794static struct attribute *dme1737_fan6_attr[] = { 1795 &sensor_dev_attr_fan6_input.dev_attr.attr, 1796 &sensor_dev_attr_fan6_min.dev_attr.attr, 1797 &sensor_dev_attr_fan6_alarm.dev_attr.attr, 1798 &sensor_dev_attr_fan6_max.dev_attr.attr, 1799 NULL 1800}; 1801 1802static const struct attribute_group dme1737_fan_group[] = { 1803 { .attrs = dme1737_fan1_attr }, 1804 { .attrs = dme1737_fan2_attr }, 1805 { .attrs = dme1737_fan3_attr }, 1806 { .attrs = dme1737_fan4_attr }, 1807 { .attrs = dme1737_fan5_attr }, 1808 { .attrs = dme1737_fan6_attr }, 1809}; 1810 1811/* The permissions of the following zone attributes are changed to read- 1812 * writeable if the chip is *not* locked. Otherwise they stay read-only. */ 1813static struct attribute *dme1737_zone_chmod_attr[] = { 1814 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr, 1815 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr, 1816 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr, 1817 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr, 1818 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr, 1819 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr, 1820 NULL 1821}; 1822 1823static const struct attribute_group dme1737_zone_chmod_group = { 1824 .attrs = dme1737_zone_chmod_attr, 1825}; 1826 1827 1828/* The permissions of the following zone 3 attributes are changed to read- 1829 * writeable if the chip is *not* locked. Otherwise they stay read-only. */ 1830static struct attribute *dme1737_zone3_chmod_attr[] = { 1831 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr, 1832 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr, 1833 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr, 1834 NULL 1835}; 1836 1837static const struct attribute_group dme1737_zone3_chmod_group = { 1838 .attrs = dme1737_zone3_chmod_attr, 1839}; 1840 1841/* The permissions of the following PWM attributes are changed to read- 1842 * writeable if the chip is *not* locked and the respective PWM is available. 1843 * Otherwise they stay read-only. */ 1844static struct attribute *dme1737_pwm1_chmod_attr[] = { 1845 &sensor_dev_attr_pwm1_freq.dev_attr.attr, 1846 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 1847 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr, 1848 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr, 1849 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, 1850 NULL 1851}; 1852static struct attribute *dme1737_pwm2_chmod_attr[] = { 1853 &sensor_dev_attr_pwm2_freq.dev_attr.attr, 1854 &sensor_dev_attr_pwm2_enable.dev_attr.attr, 1855 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr, 1856 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr, 1857 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, 1858 NULL 1859}; 1860static struct attribute *dme1737_pwm3_chmod_attr[] = { 1861 &sensor_dev_attr_pwm3_freq.dev_attr.attr, 1862 &sensor_dev_attr_pwm3_enable.dev_attr.attr, 1863 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr, 1864 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr, 1865 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, 1866 NULL 1867}; 1868static struct attribute *dme1737_pwm5_chmod_attr[] = { 1869 &sensor_dev_attr_pwm5.dev_attr.attr, 1870 &sensor_dev_attr_pwm5_freq.dev_attr.attr, 1871 NULL 1872}; 1873static struct attribute *dme1737_pwm6_chmod_attr[] = { 1874 &sensor_dev_attr_pwm6.dev_attr.attr, 1875 &sensor_dev_attr_pwm6_freq.dev_attr.attr, 1876 NULL 1877}; 1878 1879static const struct attribute_group dme1737_pwm_chmod_group[] = { 1880 { .attrs = dme1737_pwm1_chmod_attr }, 1881 { .attrs = dme1737_pwm2_chmod_attr }, 1882 { .attrs = dme1737_pwm3_chmod_attr }, 1883 { .attrs = NULL }, 1884 { .attrs = dme1737_pwm5_chmod_attr }, 1885 { .attrs = dme1737_pwm6_chmod_attr }, 1886}; 1887 1888/* Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the 1889 * chip is not locked. Otherwise they are read-only. */ 1890static struct attribute *dme1737_pwm_chmod_attr[] = { 1891 &sensor_dev_attr_pwm1.dev_attr.attr, 1892 &sensor_dev_attr_pwm2.dev_attr.attr, 1893 &sensor_dev_attr_pwm3.dev_attr.attr, 1894}; 1895 1896/* --------------------------------------------------------------------- 1897 * Super-IO functions 1898 * --------------------------------------------------------------------- */ 1899 1900static inline void dme1737_sio_enter(int sio_cip) 1901{ 1902 outb(0x55, sio_cip); 1903} 1904 1905static inline void dme1737_sio_exit(int sio_cip) 1906{ 1907 outb(0xaa, sio_cip); 1908} 1909 1910static inline int dme1737_sio_inb(int sio_cip, int reg) 1911{ 1912 outb(reg, sio_cip); 1913 return inb(sio_cip + 1); 1914} 1915 1916static inline void dme1737_sio_outb(int sio_cip, int reg, int val) 1917{ 1918 outb(reg, sio_cip); 1919 outb(val, sio_cip + 1); 1920} 1921 1922/* --------------------------------------------------------------------- 1923 * Device initialization 1924 * --------------------------------------------------------------------- */ 1925 1926static int dme1737_i2c_get_features(int, struct dme1737_data*); 1927 1928static void dme1737_chmod_file(struct device *dev, 1929 struct attribute *attr, mode_t mode) 1930{ 1931 if (sysfs_chmod_file(&dev->kobj, attr, mode)) { 1932 dev_warn(dev, "Failed to change permissions of %s.\n", 1933 attr->name); 1934 } 1935} 1936 1937static void dme1737_chmod_group(struct device *dev, 1938 const struct attribute_group *group, 1939 mode_t mode) 1940{ 1941 struct attribute **attr; 1942 1943 for (attr = group->attrs; *attr; attr++) { 1944 dme1737_chmod_file(dev, *attr, mode); 1945 } 1946} 1947 1948static void dme1737_remove_files(struct device *dev) 1949{ 1950 struct dme1737_data *data = dev_get_drvdata(dev); 1951 int ix; 1952 1953 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) { 1954 if (data->has_features & HAS_FAN(ix)) { 1955 sysfs_remove_group(&dev->kobj, 1956 &dme1737_fan_group[ix]); 1957 } 1958 } 1959 1960 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) { 1961 if (data->has_features & HAS_PWM(ix)) { 1962 sysfs_remove_group(&dev->kobj, 1963 &dme1737_pwm_group[ix]); 1964 if ((data->has_features & HAS_PWM_MIN) && ix < 3) { 1965 sysfs_remove_file(&dev->kobj, 1966 dme1737_auto_pwm_min_attr[ix]); 1967 } 1968 } 1969 } 1970 1971 if (data->has_features & HAS_TEMP_OFFSET) { 1972 sysfs_remove_group(&dev->kobj, &dme1737_temp_offset_group); 1973 } 1974 if (data->has_features & HAS_VID) { 1975 sysfs_remove_group(&dev->kobj, &dme1737_vid_group); 1976 } 1977 if (data->has_features & HAS_ZONE3) { 1978 sysfs_remove_group(&dev->kobj, &dme1737_zone3_group); 1979 } 1980 if (data->has_features & HAS_ZONE_HYST) { 1981 sysfs_remove_group(&dev->kobj, &dme1737_zone_hyst_group); 1982 } 1983 sysfs_remove_group(&dev->kobj, &dme1737_group); 1984 1985 if (!data->client) { 1986 sysfs_remove_file(&dev->kobj, &dev_attr_name.attr); 1987 } 1988} 1989 1990static int dme1737_create_files(struct device *dev) 1991{ 1992 struct dme1737_data *data = dev_get_drvdata(dev); 1993 int err, ix; 1994 1995 /* Create a name attribute for ISA devices */ 1996 if (!data->client && 1997 (err = sysfs_create_file(&dev->kobj, &dev_attr_name.attr))) { 1998 goto exit; 1999 } 2000 2001 /* Create standard sysfs attributes */ 2002 if ((err = sysfs_create_group(&dev->kobj, &dme1737_group))) { 2003 goto exit_remove; 2004 } 2005 2006 /* Create chip-dependent sysfs attributes */ 2007 if ((data->has_features & HAS_TEMP_OFFSET) && 2008 (err = sysfs_create_group(&dev->kobj, 2009 &dme1737_temp_offset_group))) { 2010 goto exit_remove; 2011 } 2012 if ((data->has_features & HAS_VID) && 2013 (err = sysfs_create_group(&dev->kobj, 2014 &dme1737_vid_group))) { 2015 goto exit_remove; 2016 } 2017 if ((data->has_features & HAS_ZONE3) && 2018 (err = sysfs_create_group(&dev->kobj, 2019 &dme1737_zone3_group))) { 2020 goto exit_remove; 2021 } 2022 if ((data->has_features & HAS_ZONE_HYST) && 2023 (err = sysfs_create_group(&dev->kobj, 2024 &dme1737_zone_hyst_group))) { 2025 goto exit_remove; 2026 } 2027 2028 /* Create fan sysfs attributes */ 2029 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) { 2030 if (data->has_features & HAS_FAN(ix)) { 2031 if ((err = sysfs_create_group(&dev->kobj, 2032 &dme1737_fan_group[ix]))) { 2033 goto exit_remove; 2034 } 2035 } 2036 } 2037 2038 /* Create PWM sysfs attributes */ 2039 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) { 2040 if (data->has_features & HAS_PWM(ix)) { 2041 if ((err = sysfs_create_group(&dev->kobj, 2042 &dme1737_pwm_group[ix]))) { 2043 goto exit_remove; 2044 } 2045 if ((data->has_features & HAS_PWM_MIN) && ix < 3 && 2046 (err = sysfs_create_file(&dev->kobj, 2047 dme1737_auto_pwm_min_attr[ix]))) { 2048 goto exit_remove; 2049 } 2050 } 2051 } 2052 2053 /* Inform if the device is locked. Otherwise change the permissions of 2054 * selected attributes from read-only to read-writeable. */ 2055 if (data->config & 0x02) { 2056 dev_info(dev, "Device is locked. Some attributes " 2057 "will be read-only.\n"); 2058 } else { 2059 /* Change permissions of zone sysfs attributes */ 2060 dme1737_chmod_group(dev, &dme1737_zone_chmod_group, 2061 S_IRUGO | S_IWUSR); 2062 2063 /* Change permissions of chip-dependent sysfs attributes */ 2064 if (data->has_features & HAS_TEMP_OFFSET) { 2065 dme1737_chmod_group(dev, &dme1737_temp_offset_group, 2066 S_IRUGO | S_IWUSR); 2067 } 2068 if (data->has_features & HAS_ZONE3) { 2069 dme1737_chmod_group(dev, &dme1737_zone3_chmod_group, 2070 S_IRUGO | S_IWUSR); 2071 } 2072 if (data->has_features & HAS_ZONE_HYST) { 2073 dme1737_chmod_group(dev, &dme1737_zone_hyst_group, 2074 S_IRUGO | S_IWUSR); 2075 } 2076 2077 /* Change permissions of PWM sysfs attributes */ 2078 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_chmod_group); ix++) { 2079 if (data->has_features & HAS_PWM(ix)) { 2080 dme1737_chmod_group(dev, 2081 &dme1737_pwm_chmod_group[ix], 2082 S_IRUGO | S_IWUSR); 2083 if ((data->has_features & HAS_PWM_MIN) && 2084 ix < 3) { 2085 dme1737_chmod_file(dev, 2086 dme1737_auto_pwm_min_attr[ix], 2087 S_IRUGO | S_IWUSR); 2088 } 2089 } 2090 } 2091 2092 /* Change permissions of pwm[1-3] if in manual mode */ 2093 for (ix = 0; ix < 3; ix++) { 2094 if ((data->has_features & HAS_PWM(ix)) && 2095 (PWM_EN_FROM_REG(data->pwm_config[ix]) == 1)) { 2096 dme1737_chmod_file(dev, 2097 dme1737_pwm_chmod_attr[ix], 2098 S_IRUGO | S_IWUSR); 2099 } 2100 } 2101 } 2102 2103 return 0; 2104 2105exit_remove: 2106 dme1737_remove_files(dev); 2107exit: 2108 return err; 2109} 2110 2111static int dme1737_init_device(struct device *dev) 2112{ 2113 struct dme1737_data *data = dev_get_drvdata(dev); 2114 struct i2c_client *client = data->client; 2115 int ix; 2116 u8 reg; 2117 2118 /* Point to the right nominal voltages array */ 2119 data->in_nominal = IN_NOMINAL(data->type); 2120 2121 data->config = dme1737_read(data, DME1737_REG_CONFIG); 2122 /* Inform if part is not monitoring/started */ 2123 if (!(data->config & 0x01)) { 2124 if (!force_start) { 2125 dev_err(dev, "Device is not monitoring. " 2126 "Use the force_start load parameter to " 2127 "override.\n"); 2128 return -EFAULT; 2129 } 2130 2131 /* Force monitoring */ 2132 data->config |= 0x01; 2133 dme1737_write(data, DME1737_REG_CONFIG, data->config); 2134 } 2135 /* Inform if part is not ready */ 2136 if (!(data->config & 0x04)) { 2137 dev_err(dev, "Device is not ready.\n"); 2138 return -EFAULT; 2139 } 2140 2141 /* Determine which optional fan and pwm features are enabled (only 2142 * valid for I2C devices) */ 2143 if (client) { /* I2C chip */ 2144 data->config2 = dme1737_read(data, DME1737_REG_CONFIG2); 2145 /* Check if optional fan3 input is enabled */ 2146 if (data->config2 & 0x04) { 2147 data->has_features |= HAS_FAN(2); 2148 } 2149 2150 /* Fan4 and pwm3 are only available if the client's I2C address 2151 * is the default 0x2e. Otherwise the I/Os associated with 2152 * these functions are used for addr enable/select. */ 2153 if (client->addr == 0x2e) { 2154 data->has_features |= HAS_FAN(3) | HAS_PWM(2); 2155 } 2156 2157 /* Determine which of the optional fan[5-6] and pwm[5-6] 2158 * features are enabled. For this, we need to query the runtime 2159 * registers through the Super-IO LPC interface. Try both 2160 * config ports 0x2e and 0x4e. */ 2161 if (dme1737_i2c_get_features(0x2e, data) && 2162 dme1737_i2c_get_features(0x4e, data)) { 2163 dev_warn(dev, "Failed to query Super-IO for optional " 2164 "features.\n"); 2165 } 2166 } 2167 2168 /* Fan[1-2] and pwm[1-2] are present in all chips */ 2169 data->has_features |= HAS_FAN(0) | HAS_FAN(1) | HAS_PWM(0) | HAS_PWM(1); 2170 2171 /* Chip-dependent features */ 2172 switch (data->type) { 2173 case dme1737: 2174 data->has_features |= HAS_TEMP_OFFSET | HAS_VID | HAS_ZONE3 | 2175 HAS_ZONE_HYST | HAS_PWM_MIN; 2176 break; 2177 case sch311x: 2178 data->has_features |= HAS_TEMP_OFFSET | HAS_ZONE3 | 2179 HAS_ZONE_HYST | HAS_PWM_MIN | HAS_FAN(2) | HAS_PWM(2); 2180 break; 2181 case sch5027: 2182 data->has_features |= HAS_ZONE3; 2183 break; 2184 case sch5127: 2185 data->has_features |= HAS_FAN(2) | HAS_PWM(2); 2186 break; 2187 default: 2188 break; 2189 } 2190 2191 dev_info(dev, "Optional features: pwm3=%s, pwm5=%s, pwm6=%s, " 2192 "fan3=%s, fan4=%s, fan5=%s, fan6=%s.\n", 2193 (data->has_features & HAS_PWM(2)) ? "yes" : "no", 2194 (data->has_features & HAS_PWM(4)) ? "yes" : "no", 2195 (data->has_features & HAS_PWM(5)) ? "yes" : "no", 2196 (data->has_features & HAS_FAN(2)) ? "yes" : "no", 2197 (data->has_features & HAS_FAN(3)) ? "yes" : "no", 2198 (data->has_features & HAS_FAN(4)) ? "yes" : "no", 2199 (data->has_features & HAS_FAN(5)) ? "yes" : "no"); 2200 2201 reg = dme1737_read(data, DME1737_REG_TACH_PWM); 2202 /* Inform if fan-to-pwm mapping differs from the default */ 2203 if (client && reg != 0xa4) { /* I2C chip */ 2204 dev_warn(dev, "Non-standard fan to pwm mapping: " 2205 "fan1->pwm%d, fan2->pwm%d, fan3->pwm%d, " 2206 "fan4->pwm%d. Please report to the driver " 2207 "maintainer.\n", 2208 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1, 2209 ((reg >> 4) & 0x03) + 1, ((reg >> 6) & 0x03) + 1); 2210 } else if (!client && reg != 0x24) { /* ISA chip */ 2211 dev_warn(dev, "Non-standard fan to pwm mapping: " 2212 "fan1->pwm%d, fan2->pwm%d, fan3->pwm%d. " 2213 "Please report to the driver maintainer.\n", 2214 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1, 2215 ((reg >> 4) & 0x03) + 1); 2216 } 2217 2218 /* Switch pwm[1-3] to manual mode if they are currently disabled and 2219 * set the duty-cycles to 0% (which is identical to the PWMs being 2220 * disabled). */ 2221 if (!(data->config & 0x02)) { 2222 for (ix = 0; ix < 3; ix++) { 2223 data->pwm_config[ix] = dme1737_read(data, 2224 DME1737_REG_PWM_CONFIG(ix)); 2225 if ((data->has_features & HAS_PWM(ix)) && 2226 (PWM_EN_FROM_REG(data->pwm_config[ix]) == -1)) { 2227 dev_info(dev, "Switching pwm%d to " 2228 "manual mode.\n", ix + 1); 2229 data->pwm_config[ix] = PWM_EN_TO_REG(1, 2230 data->pwm_config[ix]); 2231 dme1737_write(data, DME1737_REG_PWM(ix), 0); 2232 dme1737_write(data, 2233 DME1737_REG_PWM_CONFIG(ix), 2234 data->pwm_config[ix]); 2235 } 2236 } 2237 } 2238 2239 /* Initialize the default PWM auto channels zone (acz) assignments */ 2240 data->pwm_acz[0] = 1; /* pwm1 -> zone1 */ 2241 data->pwm_acz[1] = 2; /* pwm2 -> zone2 */ 2242 data->pwm_acz[2] = 4; /* pwm3 -> zone3 */ 2243 2244 /* Set VRM */ 2245 if (data->has_features & HAS_VID) { 2246 data->vrm = vid_which_vrm(); 2247 } 2248 2249 return 0; 2250} 2251 2252/* --------------------------------------------------------------------- 2253 * I2C device detection and registration 2254 * --------------------------------------------------------------------- */ 2255 2256static struct i2c_driver dme1737_i2c_driver; 2257 2258static int dme1737_i2c_get_features(int sio_cip, struct dme1737_data *data) 2259{ 2260 int err = 0, reg; 2261 u16 addr; 2262 2263 dme1737_sio_enter(sio_cip); 2264 2265 /* Check device ID 2266 * We currently know about two kinds of DME1737 and SCH5027. */ 2267 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20); 2268 if (!(reg == DME1737_ID_1 || reg == DME1737_ID_2 || 2269 reg == SCH5027_ID)) { 2270 err = -ENODEV; 2271 goto exit; 2272 } 2273 2274 /* Select logical device A (runtime registers) */ 2275 dme1737_sio_outb(sio_cip, 0x07, 0x0a); 2276 2277 /* Get the base address of the runtime registers */ 2278 if (!(addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) | 2279 dme1737_sio_inb(sio_cip, 0x61))) { 2280 err = -ENODEV; 2281 goto exit; 2282 } 2283 2284 /* Read the runtime registers to determine which optional features 2285 * are enabled and available. Bits [3:2] of registers 0x43-0x46 are set 2286 * to '10' if the respective feature is enabled. */ 2287 if ((inb(addr + 0x43) & 0x0c) == 0x08) { /* fan6 */ 2288 data->has_features |= HAS_FAN(5); 2289 } 2290 if ((inb(addr + 0x44) & 0x0c) == 0x08) { /* pwm6 */ 2291 data->has_features |= HAS_PWM(5); 2292 } 2293 if ((inb(addr + 0x45) & 0x0c) == 0x08) { /* fan5 */ 2294 data->has_features |= HAS_FAN(4); 2295 } 2296 if ((inb(addr + 0x46) & 0x0c) == 0x08) { /* pwm5 */ 2297 data->has_features |= HAS_PWM(4); 2298 } 2299 2300exit: 2301 dme1737_sio_exit(sio_cip); 2302 2303 return err; 2304} 2305 2306/* Return 0 if detection is successful, -ENODEV otherwise */ 2307static int dme1737_i2c_detect(struct i2c_client *client, 2308 struct i2c_board_info *info) 2309{ 2310 struct i2c_adapter *adapter = client->adapter; 2311 struct device *dev = &adapter->dev; 2312 u8 company, verstep = 0; 2313 const char *name; 2314 2315 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { 2316 return -ENODEV; 2317 } 2318 2319 company = i2c_smbus_read_byte_data(client, DME1737_REG_COMPANY); 2320 verstep = i2c_smbus_read_byte_data(client, DME1737_REG_VERSTEP); 2321 2322 if (company == DME1737_COMPANY_SMSC && 2323 verstep == SCH5027_VERSTEP) { 2324 name = "sch5027"; 2325 } else if (company == DME1737_COMPANY_SMSC && 2326 (verstep & DME1737_VERSTEP_MASK) == DME1737_VERSTEP) { 2327 name = "dme1737"; 2328 } else { 2329 return -ENODEV; 2330 } 2331 2332 dev_info(dev, "Found a %s chip at 0x%02x (rev 0x%02x).\n", 2333 verstep == SCH5027_VERSTEP ? "SCH5027" : "DME1737", 2334 client->addr, verstep); 2335 strlcpy(info->type, name, I2C_NAME_SIZE); 2336 2337 return 0; 2338} 2339 2340static int dme1737_i2c_probe(struct i2c_client *client, 2341 const struct i2c_device_id *id) 2342{ 2343 struct dme1737_data *data; 2344 struct device *dev = &client->dev; 2345 int err; 2346 2347 data = kzalloc(sizeof(struct dme1737_data), GFP_KERNEL); 2348 if (!data) { 2349 err = -ENOMEM; 2350 goto exit; 2351 } 2352 2353 i2c_set_clientdata(client, data); 2354 data->type = id->driver_data; 2355 data->client = client; 2356 data->name = client->name; 2357 mutex_init(&data->update_lock); 2358 2359 /* Initialize the DME1737 chip */ 2360 if ((err = dme1737_init_device(dev))) { 2361 dev_err(dev, "Failed to initialize device.\n"); 2362 goto exit_kfree; 2363 } 2364 2365 /* Create sysfs files */ 2366 if ((err = dme1737_create_files(dev))) { 2367 dev_err(dev, "Failed to create sysfs files.\n"); 2368 goto exit_kfree; 2369 } 2370 2371 /* Register device */ 2372 data->hwmon_dev = hwmon_device_register(dev); 2373 if (IS_ERR(data->hwmon_dev)) { 2374 dev_err(dev, "Failed to register device.\n"); 2375 err = PTR_ERR(data->hwmon_dev); 2376 goto exit_remove; 2377 } 2378 2379 return 0; 2380 2381exit_remove: 2382 dme1737_remove_files(dev); 2383exit_kfree: 2384 kfree(data); 2385exit: 2386 return err; 2387} 2388 2389static int dme1737_i2c_remove(struct i2c_client *client) 2390{ 2391 struct dme1737_data *data = i2c_get_clientdata(client); 2392 2393 hwmon_device_unregister(data->hwmon_dev); 2394 dme1737_remove_files(&client->dev); 2395 2396 kfree(data); 2397 return 0; 2398} 2399 2400static const struct i2c_device_id dme1737_id[] = { 2401 { "dme1737", dme1737 }, 2402 { "sch5027", sch5027 }, 2403 { } 2404}; 2405MODULE_DEVICE_TABLE(i2c, dme1737_id); 2406 2407static struct i2c_driver dme1737_i2c_driver = { 2408 .class = I2C_CLASS_HWMON, 2409 .driver = { 2410 .name = "dme1737", 2411 }, 2412 .probe = dme1737_i2c_probe, 2413 .remove = dme1737_i2c_remove, 2414 .id_table = dme1737_id, 2415 .detect = dme1737_i2c_detect, 2416 .address_list = normal_i2c, 2417}; 2418 2419/* --------------------------------------------------------------------- 2420 * ISA device detection and registration 2421 * --------------------------------------------------------------------- */ 2422 2423static int __init dme1737_isa_detect(int sio_cip, unsigned short *addr) 2424{ 2425 int err = 0, reg; 2426 unsigned short base_addr; 2427 2428 dme1737_sio_enter(sio_cip); 2429 2430 /* Check device ID 2431 * We currently know about SCH3112, SCH3114, SCH3116, and SCH5127 */ 2432 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20); 2433 if (!(reg == SCH3112_ID || reg == SCH3114_ID || reg == SCH3116_ID || 2434 reg == SCH5127_ID)) { 2435 err = -ENODEV; 2436 goto exit; 2437 } 2438 2439 /* Select logical device A (runtime registers) */ 2440 dme1737_sio_outb(sio_cip, 0x07, 0x0a); 2441 2442 /* Get the base address of the runtime registers */ 2443 if (!(base_addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) | 2444 dme1737_sio_inb(sio_cip, 0x61))) { 2445 printk(KERN_ERR "dme1737: Base address not set.\n"); 2446 err = -ENODEV; 2447 goto exit; 2448 } 2449 2450 /* Access to the hwmon registers is through an index/data register 2451 * pair located at offset 0x70/0x71. */ 2452 *addr = base_addr + 0x70; 2453 2454exit: 2455 dme1737_sio_exit(sio_cip); 2456 return err; 2457} 2458 2459static int __init dme1737_isa_device_add(unsigned short addr) 2460{ 2461 struct resource res = { 2462 .start = addr, 2463 .end = addr + DME1737_EXTENT - 1, 2464 .name = "dme1737", 2465 .flags = IORESOURCE_IO, 2466 }; 2467 int err; 2468 2469 err = acpi_check_resource_conflict(&res); 2470 if (err) 2471 goto exit; 2472 2473 if (!(pdev = platform_device_alloc("dme1737", addr))) { 2474 printk(KERN_ERR "dme1737: Failed to allocate device.\n"); 2475 err = -ENOMEM; 2476 goto exit; 2477 } 2478 2479 if ((err = platform_device_add_resources(pdev, &res, 1))) { 2480 printk(KERN_ERR "dme1737: Failed to add device resource " 2481 "(err = %d).\n", err); 2482 goto exit_device_put; 2483 } 2484 2485 if ((err = platform_device_add(pdev))) { 2486 printk(KERN_ERR "dme1737: Failed to add device (err = %d).\n", 2487 err); 2488 goto exit_device_put; 2489 } 2490 2491 return 0; 2492 2493exit_device_put: 2494 platform_device_put(pdev); 2495 pdev = NULL; 2496exit: 2497 return err; 2498} 2499 2500static int __devinit dme1737_isa_probe(struct platform_device *pdev) 2501{ 2502 u8 company, device; 2503 struct resource *res; 2504 struct dme1737_data *data; 2505 struct device *dev = &pdev->dev; 2506 int err; 2507 2508 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 2509 if (!request_region(res->start, DME1737_EXTENT, "dme1737")) { 2510 dev_err(dev, "Failed to request region 0x%04x-0x%04x.\n", 2511 (unsigned short)res->start, 2512 (unsigned short)res->start + DME1737_EXTENT - 1); 2513 err = -EBUSY; 2514 goto exit; 2515 } 2516 2517 if (!(data = kzalloc(sizeof(struct dme1737_data), GFP_KERNEL))) { 2518 err = -ENOMEM; 2519 goto exit_release_region; 2520 } 2521 2522 data->addr = res->start; 2523 platform_set_drvdata(pdev, data); 2524 2525 /* Skip chip detection if module is loaded with force_id parameter */ 2526 switch (force_id) { 2527 case SCH3112_ID: 2528 case SCH3114_ID: 2529 case SCH3116_ID: 2530 data->type = sch311x; 2531 break; 2532 case SCH5127_ID: 2533 data->type = sch5127; 2534 break; 2535 default: 2536 company = dme1737_read(data, DME1737_REG_COMPANY); 2537 device = dme1737_read(data, DME1737_REG_DEVICE); 2538 2539 if ((company == DME1737_COMPANY_SMSC) && 2540 (device == SCH311X_DEVICE)) { 2541 data->type = sch311x; 2542 } else if ((company == DME1737_COMPANY_SMSC) && 2543 (device == SCH5127_DEVICE)) { 2544 data->type = sch5127; 2545 } else { 2546 err = -ENODEV; 2547 goto exit_kfree; 2548 } 2549 } 2550 2551 if (data->type == sch5127) { 2552 data->name = "sch5127"; 2553 } else { 2554 data->name = "sch311x"; 2555 } 2556 2557 /* Initialize the mutex */ 2558 mutex_init(&data->update_lock); 2559 2560 dev_info(dev, "Found a %s chip at 0x%04x\n", 2561 data->type == sch5127 ? "SCH5127" : "SCH311x", data->addr); 2562 2563 /* Initialize the chip */ 2564 if ((err = dme1737_init_device(dev))) { 2565 dev_err(dev, "Failed to initialize device.\n"); 2566 goto exit_kfree; 2567 } 2568 2569 /* Create sysfs files */ 2570 if ((err = dme1737_create_files(dev))) { 2571 dev_err(dev, "Failed to create sysfs files.\n"); 2572 goto exit_kfree; 2573 } 2574 2575 /* Register device */ 2576 data->hwmon_dev = hwmon_device_register(dev); 2577 if (IS_ERR(data->hwmon_dev)) { 2578 dev_err(dev, "Failed to register device.\n"); 2579 err = PTR_ERR(data->hwmon_dev); 2580 goto exit_remove_files; 2581 } 2582 2583 return 0; 2584 2585exit_remove_files: 2586 dme1737_remove_files(dev); 2587exit_kfree: 2588 platform_set_drvdata(pdev, NULL); 2589 kfree(data); 2590exit_release_region: 2591 release_region(res->start, DME1737_EXTENT); 2592exit: 2593 return err; 2594} 2595 2596static int __devexit dme1737_isa_remove(struct platform_device *pdev) 2597{ 2598 struct dme1737_data *data = platform_get_drvdata(pdev); 2599 2600 hwmon_device_unregister(data->hwmon_dev); 2601 dme1737_remove_files(&pdev->dev); 2602 release_region(data->addr, DME1737_EXTENT); 2603 platform_set_drvdata(pdev, NULL); 2604 kfree(data); 2605 2606 return 0; 2607} 2608 2609static struct platform_driver dme1737_isa_driver = { 2610 .driver = { 2611 .owner = THIS_MODULE, 2612 .name = "dme1737", 2613 }, 2614 .probe = dme1737_isa_probe, 2615 .remove = __devexit_p(dme1737_isa_remove), 2616}; 2617 2618/* --------------------------------------------------------------------- 2619 * Module initialization and cleanup 2620 * --------------------------------------------------------------------- */ 2621 2622static int __init dme1737_init(void) 2623{ 2624 int err; 2625 unsigned short addr; 2626 2627 if ((err = i2c_add_driver(&dme1737_i2c_driver))) { 2628 goto exit; 2629 } 2630 2631 if (dme1737_isa_detect(0x2e, &addr) && 2632 dme1737_isa_detect(0x4e, &addr) && 2633 (!probe_all_addr || 2634 (dme1737_isa_detect(0x162e, &addr) && 2635 dme1737_isa_detect(0x164e, &addr)))) { 2636 /* Return 0 if we didn't find an ISA device */ 2637 return 0; 2638 } 2639 2640 if ((err = platform_driver_register(&dme1737_isa_driver))) { 2641 goto exit_del_i2c_driver; 2642 } 2643 2644 /* Sets global pdev as a side effect */ 2645 if ((err = dme1737_isa_device_add(addr))) { 2646 goto exit_del_isa_driver; 2647 } 2648 2649 return 0; 2650 2651exit_del_isa_driver: 2652 platform_driver_unregister(&dme1737_isa_driver); 2653exit_del_i2c_driver: 2654 i2c_del_driver(&dme1737_i2c_driver); 2655exit: 2656 return err; 2657} 2658 2659static void __exit dme1737_exit(void) 2660{ 2661 if (pdev) { 2662 platform_device_unregister(pdev); 2663 platform_driver_unregister(&dme1737_isa_driver); 2664 } 2665 2666 i2c_del_driver(&dme1737_i2c_driver); 2667} 2668 2669MODULE_AUTHOR("Juerg Haefliger <juergh@gmail.com>"); 2670MODULE_DESCRIPTION("DME1737 sensors"); 2671MODULE_LICENSE("GPL"); 2672 2673module_init(dme1737_init); 2674module_exit(dme1737_exit); 2675