1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#include <linux/seq_file.h> 29#include <linux/slab.h> 30#include "drmP.h" 31#include "rv515d.h" 32#include "radeon.h" 33#include "radeon_asic.h" 34#include "atom.h" 35#include "rv515_reg_safe.h" 36 37/* This files gather functions specifics to: rv515 */ 38int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); 39int rv515_debugfs_ga_info_init(struct radeon_device *rdev); 40void rv515_gpu_init(struct radeon_device *rdev); 41int rv515_mc_wait_for_idle(struct radeon_device *rdev); 42 43void rv515_debugfs(struct radeon_device *rdev) 44{ 45 if (r100_debugfs_rbbm_init(rdev)) { 46 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 47 } 48 if (rv515_debugfs_pipes_info_init(rdev)) { 49 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 50 } 51 if (rv515_debugfs_ga_info_init(rdev)) { 52 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 53 } 54} 55 56void rv515_ring_start(struct radeon_device *rdev) 57{ 58 int r; 59 60 r = radeon_ring_lock(rdev, 64); 61 if (r) { 62 return; 63 } 64 radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0)); 65 radeon_ring_write(rdev, 66 ISYNC_ANY2D_IDLE3D | 67 ISYNC_ANY3D_IDLE2D | 68 ISYNC_WAIT_IDLEGUI | 69 ISYNC_CPSCRATCH_IDLEGUI); 70 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); 71 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 72 radeon_ring_write(rdev, PACKET0(0x170C, 0)); 73 radeon_ring_write(rdev, 1 << 31); 74 radeon_ring_write(rdev, PACKET0(GB_SELECT, 0)); 75 radeon_ring_write(rdev, 0); 76 radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0)); 77 radeon_ring_write(rdev, 0); 78 radeon_ring_write(rdev, PACKET0(0x42C8, 0)); 79 radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1); 80 radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0)); 81 radeon_ring_write(rdev, 0); 82 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 83 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); 84 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 85 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); 86 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); 87 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 88 radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0)); 89 radeon_ring_write(rdev, 0); 90 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 91 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); 92 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 93 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); 94 radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0)); 95 radeon_ring_write(rdev, 96 ((6 << MS_X0_SHIFT) | 97 (6 << MS_Y0_SHIFT) | 98 (6 << MS_X1_SHIFT) | 99 (6 << MS_Y1_SHIFT) | 100 (6 << MS_X2_SHIFT) | 101 (6 << MS_Y2_SHIFT) | 102 (6 << MSBD0_Y_SHIFT) | 103 (6 << MSBD0_X_SHIFT))); 104 radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0)); 105 radeon_ring_write(rdev, 106 ((6 << MS_X3_SHIFT) | 107 (6 << MS_Y3_SHIFT) | 108 (6 << MS_X4_SHIFT) | 109 (6 << MS_Y4_SHIFT) | 110 (6 << MS_X5_SHIFT) | 111 (6 << MS_Y5_SHIFT) | 112 (6 << MSBD1_SHIFT))); 113 radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0)); 114 radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); 115 radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0)); 116 radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); 117 radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0)); 118 radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); 119 radeon_ring_write(rdev, PACKET0(0x20C8, 0)); 120 radeon_ring_write(rdev, 0); 121 radeon_ring_unlock_commit(rdev); 122} 123 124int rv515_mc_wait_for_idle(struct radeon_device *rdev) 125{ 126 unsigned i; 127 uint32_t tmp; 128 129 for (i = 0; i < rdev->usec_timeout; i++) { 130 /* read MC_STATUS */ 131 tmp = RREG32_MC(MC_STATUS); 132 if (tmp & MC_STATUS_IDLE) { 133 return 0; 134 } 135 DRM_UDELAY(1); 136 } 137 return -1; 138} 139 140void rv515_vga_render_disable(struct radeon_device *rdev) 141{ 142 WREG32(R_000300_VGA_RENDER_CONTROL, 143 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); 144} 145 146void rv515_gpu_init(struct radeon_device *rdev) 147{ 148 unsigned pipe_select_current, gb_pipe_select, tmp; 149 150 if (r100_gui_wait_for_idle(rdev)) { 151 printk(KERN_WARNING "Failed to wait GUI idle while " 152 "reseting GPU. Bad things might happen.\n"); 153 } 154 rv515_vga_render_disable(rdev); 155 r420_pipes_init(rdev); 156 gb_pipe_select = RREG32(0x402C); 157 tmp = RREG32(0x170C); 158 pipe_select_current = (tmp >> 2) & 3; 159 tmp = (1 << pipe_select_current) | 160 (((gb_pipe_select >> 8) & 0xF) << 4); 161 WREG32_PLL(0x000D, tmp); 162 if (r100_gui_wait_for_idle(rdev)) { 163 printk(KERN_WARNING "Failed to wait GUI idle while " 164 "reseting GPU. Bad things might happen.\n"); 165 } 166 if (rv515_mc_wait_for_idle(rdev)) { 167 printk(KERN_WARNING "Failed to wait MC idle while " 168 "programming pipes. Bad things might happen.\n"); 169 } 170} 171 172static void rv515_vram_get_type(struct radeon_device *rdev) 173{ 174 uint32_t tmp; 175 176 rdev->mc.vram_width = 128; 177 rdev->mc.vram_is_ddr = true; 178 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; 179 switch (tmp) { 180 case 0: 181 rdev->mc.vram_width = 64; 182 break; 183 case 1: 184 rdev->mc.vram_width = 128; 185 break; 186 default: 187 rdev->mc.vram_width = 128; 188 break; 189 } 190} 191 192void rv515_mc_init(struct radeon_device *rdev) 193{ 194 195 rv515_vram_get_type(rdev); 196 r100_vram_init_sizes(rdev); 197 radeon_vram_location(rdev, &rdev->mc, 0); 198 rdev->mc.gtt_base_align = 0; 199 if (!(rdev->flags & RADEON_IS_AGP)) 200 radeon_gtt_location(rdev, &rdev->mc); 201 radeon_update_bandwidth_info(rdev); 202} 203 204uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) 205{ 206 uint32_t r; 207 208 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); 209 r = RREG32(MC_IND_DATA); 210 WREG32(MC_IND_INDEX, 0); 211 return r; 212} 213 214void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 215{ 216 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); 217 WREG32(MC_IND_DATA, (v)); 218 WREG32(MC_IND_INDEX, 0); 219} 220 221#if defined(CONFIG_DEBUG_FS) 222static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) 223{ 224 struct drm_info_node *node = (struct drm_info_node *) m->private; 225 struct drm_device *dev = node->minor->dev; 226 struct radeon_device *rdev = dev->dev_private; 227 uint32_t tmp; 228 229 tmp = RREG32(GB_PIPE_SELECT); 230 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 231 tmp = RREG32(SU_REG_DEST); 232 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); 233 tmp = RREG32(GB_TILE_CONFIG); 234 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 235 tmp = RREG32(DST_PIPE_CONFIG); 236 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 237 return 0; 238} 239 240static int rv515_debugfs_ga_info(struct seq_file *m, void *data) 241{ 242 struct drm_info_node *node = (struct drm_info_node *) m->private; 243 struct drm_device *dev = node->minor->dev; 244 struct radeon_device *rdev = dev->dev_private; 245 uint32_t tmp; 246 247 tmp = RREG32(0x2140); 248 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); 249 radeon_asic_reset(rdev); 250 tmp = RREG32(0x425C); 251 seq_printf(m, "GA_IDLE 0x%08x\n", tmp); 252 return 0; 253} 254 255static struct drm_info_list rv515_pipes_info_list[] = { 256 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, 257}; 258 259static struct drm_info_list rv515_ga_info_list[] = { 260 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, 261}; 262#endif 263 264int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) 265{ 266#if defined(CONFIG_DEBUG_FS) 267 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); 268#else 269 return 0; 270#endif 271} 272 273int rv515_debugfs_ga_info_init(struct radeon_device *rdev) 274{ 275#if defined(CONFIG_DEBUG_FS) 276 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); 277#else 278 return 0; 279#endif 280} 281 282void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) 283{ 284 save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL); 285 save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL); 286 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); 287 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); 288 save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL); 289 save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); 290 291 /* Stop all video */ 292 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 293 WREG32(R_000300_VGA_RENDER_CONTROL, 0); 294 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); 295 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); 296 WREG32(R_006080_D1CRTC_CONTROL, 0); 297 WREG32(R_006880_D2CRTC_CONTROL, 0); 298 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); 299 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 300 WREG32(R_000330_D1VGA_CONTROL, 0); 301 WREG32(R_000338_D2VGA_CONTROL, 0); 302} 303 304void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 305{ 306 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); 307 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); 308 WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); 309 WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); 310 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); 311 /* Unlock host access */ 312 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); 313 mdelay(1); 314 /* Restore video state */ 315 WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control); 316 WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control); 317 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); 318 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); 319 WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); 320 WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); 321 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); 322 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 323 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); 324} 325 326void rv515_mc_program(struct radeon_device *rdev) 327{ 328 struct rv515_mc_save save; 329 330 /* Stops all mc clients */ 331 rv515_mc_stop(rdev, &save); 332 333 /* Wait for mc idle */ 334 if (rv515_mc_wait_for_idle(rdev)) 335 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 336 /* Write VRAM size in case we are limiting it */ 337 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 338 /* Program MC, should be a 32bits limited address space */ 339 WREG32_MC(R_000001_MC_FB_LOCATION, 340 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | 341 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); 342 WREG32(R_000134_HDP_FB_LOCATION, 343 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 344 if (rdev->flags & RADEON_IS_AGP) { 345 WREG32_MC(R_000002_MC_AGP_LOCATION, 346 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | 347 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 348 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 349 WREG32_MC(R_000004_MC_AGP_BASE_2, 350 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 351 } else { 352 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); 353 WREG32_MC(R_000003_MC_AGP_BASE, 0); 354 WREG32_MC(R_000004_MC_AGP_BASE_2, 0); 355 } 356 357 rv515_mc_resume(rdev, &save); 358} 359 360void rv515_clock_startup(struct radeon_device *rdev) 361{ 362 if (radeon_dynclks != -1 && radeon_dynclks) 363 radeon_atom_set_clock_gating(rdev, 1); 364 /* We need to force on some of the block */ 365 WREG32_PLL(R_00000F_CP_DYN_CNTL, 366 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); 367 WREG32_PLL(R_000011_E2_DYN_CNTL, 368 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); 369 WREG32_PLL(R_000013_IDCT_DYN_CNTL, 370 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); 371} 372 373static int rv515_startup(struct radeon_device *rdev) 374{ 375 int r; 376 377 rv515_mc_program(rdev); 378 /* Resume clock */ 379 rv515_clock_startup(rdev); 380 /* Initialize GPU configuration (# pipes, ...) */ 381 rv515_gpu_init(rdev); 382 /* Initialize GART (initialize after TTM so we can allocate 383 * memory through TTM but finalize after TTM) */ 384 if (rdev->flags & RADEON_IS_PCIE) { 385 r = rv370_pcie_gart_enable(rdev); 386 if (r) 387 return r; 388 } 389 /* Enable IRQ */ 390 rs600_irq_set(rdev); 391 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 392 /* 1M ring buffer */ 393 r = r100_cp_init(rdev, 1024 * 1024); 394 if (r) { 395 dev_err(rdev->dev, "failled initializing CP (%d).\n", r); 396 return r; 397 } 398 r = r100_wb_init(rdev); 399 if (r) 400 dev_err(rdev->dev, "failled initializing WB (%d).\n", r); 401 r = r100_ib_init(rdev); 402 if (r) { 403 dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 404 return r; 405 } 406 return 0; 407} 408 409int rv515_resume(struct radeon_device *rdev) 410{ 411 /* Make sur GART are not working */ 412 if (rdev->flags & RADEON_IS_PCIE) 413 rv370_pcie_gart_disable(rdev); 414 /* Resume clock before doing reset */ 415 rv515_clock_startup(rdev); 416 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 417 if (radeon_asic_reset(rdev)) { 418 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 419 RREG32(R_000E40_RBBM_STATUS), 420 RREG32(R_0007C0_CP_STAT)); 421 } 422 /* post */ 423 atom_asic_init(rdev->mode_info.atom_context); 424 /* Resume clock after posting */ 425 rv515_clock_startup(rdev); 426 /* Initialize surface registers */ 427 radeon_surface_init(rdev); 428 return rv515_startup(rdev); 429} 430 431int rv515_suspend(struct radeon_device *rdev) 432{ 433 r100_cp_disable(rdev); 434 r100_wb_disable(rdev); 435 rs600_irq_disable(rdev); 436 if (rdev->flags & RADEON_IS_PCIE) 437 rv370_pcie_gart_disable(rdev); 438 return 0; 439} 440 441void rv515_set_safe_registers(struct radeon_device *rdev) 442{ 443 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; 444 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); 445} 446 447void rv515_fini(struct radeon_device *rdev) 448{ 449 r100_cp_fini(rdev); 450 r100_wb_fini(rdev); 451 r100_ib_fini(rdev); 452 radeon_gem_fini(rdev); 453 rv370_pcie_gart_fini(rdev); 454 radeon_agp_fini(rdev); 455 radeon_irq_kms_fini(rdev); 456 radeon_fence_driver_fini(rdev); 457 radeon_bo_fini(rdev); 458 radeon_atombios_fini(rdev); 459 kfree(rdev->bios); 460 rdev->bios = NULL; 461} 462 463int rv515_init(struct radeon_device *rdev) 464{ 465 int r; 466 467 /* Initialize scratch registers */ 468 radeon_scratch_init(rdev); 469 /* Initialize surface registers */ 470 radeon_surface_init(rdev); 471 /* TODO: disable VGA need to use VGA request */ 472 /* restore some register to sane defaults */ 473 r100_restore_sanity(rdev); 474 /* BIOS*/ 475 if (!radeon_get_bios(rdev)) { 476 if (ASIC_IS_AVIVO(rdev)) 477 return -EINVAL; 478 } 479 if (rdev->is_atom_bios) { 480 r = radeon_atombios_init(rdev); 481 if (r) 482 return r; 483 } else { 484 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 485 return -EINVAL; 486 } 487 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 488 if (radeon_asic_reset(rdev)) { 489 dev_warn(rdev->dev, 490 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 491 RREG32(R_000E40_RBBM_STATUS), 492 RREG32(R_0007C0_CP_STAT)); 493 } 494 /* check if cards are posted or not */ 495 if (radeon_boot_test_post_card(rdev) == false) 496 return -EINVAL; 497 /* Initialize clocks */ 498 radeon_get_clock_info(rdev->ddev); 499 /* initialize AGP */ 500 if (rdev->flags & RADEON_IS_AGP) { 501 r = radeon_agp_init(rdev); 502 if (r) { 503 radeon_agp_disable(rdev); 504 } 505 } 506 /* initialize memory controller */ 507 rv515_mc_init(rdev); 508 rv515_debugfs(rdev); 509 /* Fence driver */ 510 r = radeon_fence_driver_init(rdev); 511 if (r) 512 return r; 513 r = radeon_irq_kms_init(rdev); 514 if (r) 515 return r; 516 /* Memory manager */ 517 r = radeon_bo_init(rdev); 518 if (r) 519 return r; 520 r = rv370_pcie_gart_init(rdev); 521 if (r) 522 return r; 523 rv515_set_safe_registers(rdev); 524 rdev->accel_working = true; 525 r = rv515_startup(rdev); 526 if (r) { 527 /* Somethings want wront with the accel init stop accel */ 528 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 529 r100_cp_fini(rdev); 530 r100_wb_fini(rdev); 531 r100_ib_fini(rdev); 532 radeon_irq_kms_fini(rdev); 533 rv370_pcie_gart_fini(rdev); 534 radeon_agp_fini(rdev); 535 rdev->accel_working = false; 536 } 537 return 0; 538} 539 540void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) 541{ 542 int index_reg = 0x6578 + crtc->crtc_offset; 543 int data_reg = 0x657c + crtc->crtc_offset; 544 545 WREG32(0x659C + crtc->crtc_offset, 0x0); 546 WREG32(0x6594 + crtc->crtc_offset, 0x705); 547 WREG32(0x65A4 + crtc->crtc_offset, 0x10001); 548 WREG32(0x65D8 + crtc->crtc_offset, 0x0); 549 WREG32(0x65B0 + crtc->crtc_offset, 0x0); 550 WREG32(0x65C0 + crtc->crtc_offset, 0x0); 551 WREG32(0x65D4 + crtc->crtc_offset, 0x0); 552 WREG32(index_reg, 0x0); 553 WREG32(data_reg, 0x841880A8); 554 WREG32(index_reg, 0x1); 555 WREG32(data_reg, 0x84208680); 556 WREG32(index_reg, 0x2); 557 WREG32(data_reg, 0xBFF880B0); 558 WREG32(index_reg, 0x100); 559 WREG32(data_reg, 0x83D88088); 560 WREG32(index_reg, 0x101); 561 WREG32(data_reg, 0x84608680); 562 WREG32(index_reg, 0x102); 563 WREG32(data_reg, 0xBFF080D0); 564 WREG32(index_reg, 0x200); 565 WREG32(data_reg, 0x83988068); 566 WREG32(index_reg, 0x201); 567 WREG32(data_reg, 0x84A08680); 568 WREG32(index_reg, 0x202); 569 WREG32(data_reg, 0xBFF080F8); 570 WREG32(index_reg, 0x300); 571 WREG32(data_reg, 0x83588058); 572 WREG32(index_reg, 0x301); 573 WREG32(data_reg, 0x84E08660); 574 WREG32(index_reg, 0x302); 575 WREG32(data_reg, 0xBFF88120); 576 WREG32(index_reg, 0x400); 577 WREG32(data_reg, 0x83188040); 578 WREG32(index_reg, 0x401); 579 WREG32(data_reg, 0x85008660); 580 WREG32(index_reg, 0x402); 581 WREG32(data_reg, 0xBFF88150); 582 WREG32(index_reg, 0x500); 583 WREG32(data_reg, 0x82D88030); 584 WREG32(index_reg, 0x501); 585 WREG32(data_reg, 0x85408640); 586 WREG32(index_reg, 0x502); 587 WREG32(data_reg, 0xBFF88180); 588 WREG32(index_reg, 0x600); 589 WREG32(data_reg, 0x82A08018); 590 WREG32(index_reg, 0x601); 591 WREG32(data_reg, 0x85808620); 592 WREG32(index_reg, 0x602); 593 WREG32(data_reg, 0xBFF081B8); 594 WREG32(index_reg, 0x700); 595 WREG32(data_reg, 0x82608010); 596 WREG32(index_reg, 0x701); 597 WREG32(data_reg, 0x85A08600); 598 WREG32(index_reg, 0x702); 599 WREG32(data_reg, 0x800081F0); 600 WREG32(index_reg, 0x800); 601 WREG32(data_reg, 0x8228BFF8); 602 WREG32(index_reg, 0x801); 603 WREG32(data_reg, 0x85E085E0); 604 WREG32(index_reg, 0x802); 605 WREG32(data_reg, 0xBFF88228); 606 WREG32(index_reg, 0x10000); 607 WREG32(data_reg, 0x82A8BF00); 608 WREG32(index_reg, 0x10001); 609 WREG32(data_reg, 0x82A08CC0); 610 WREG32(index_reg, 0x10002); 611 WREG32(data_reg, 0x8008BEF8); 612 WREG32(index_reg, 0x10100); 613 WREG32(data_reg, 0x81F0BF28); 614 WREG32(index_reg, 0x10101); 615 WREG32(data_reg, 0x83608CA0); 616 WREG32(index_reg, 0x10102); 617 WREG32(data_reg, 0x8018BED0); 618 WREG32(index_reg, 0x10200); 619 WREG32(data_reg, 0x8148BF38); 620 WREG32(index_reg, 0x10201); 621 WREG32(data_reg, 0x84408C80); 622 WREG32(index_reg, 0x10202); 623 WREG32(data_reg, 0x8008BEB8); 624 WREG32(index_reg, 0x10300); 625 WREG32(data_reg, 0x80B0BF78); 626 WREG32(index_reg, 0x10301); 627 WREG32(data_reg, 0x85008C20); 628 WREG32(index_reg, 0x10302); 629 WREG32(data_reg, 0x8020BEA0); 630 WREG32(index_reg, 0x10400); 631 WREG32(data_reg, 0x8028BF90); 632 WREG32(index_reg, 0x10401); 633 WREG32(data_reg, 0x85E08BC0); 634 WREG32(index_reg, 0x10402); 635 WREG32(data_reg, 0x8018BE90); 636 WREG32(index_reg, 0x10500); 637 WREG32(data_reg, 0xBFB8BFB0); 638 WREG32(index_reg, 0x10501); 639 WREG32(data_reg, 0x86C08B40); 640 WREG32(index_reg, 0x10502); 641 WREG32(data_reg, 0x8010BE90); 642 WREG32(index_reg, 0x10600); 643 WREG32(data_reg, 0xBF58BFC8); 644 WREG32(index_reg, 0x10601); 645 WREG32(data_reg, 0x87A08AA0); 646 WREG32(index_reg, 0x10602); 647 WREG32(data_reg, 0x8010BE98); 648 WREG32(index_reg, 0x10700); 649 WREG32(data_reg, 0xBF10BFF0); 650 WREG32(index_reg, 0x10701); 651 WREG32(data_reg, 0x886089E0); 652 WREG32(index_reg, 0x10702); 653 WREG32(data_reg, 0x8018BEB0); 654 WREG32(index_reg, 0x10800); 655 WREG32(data_reg, 0xBED8BFE8); 656 WREG32(index_reg, 0x10801); 657 WREG32(data_reg, 0x89408940); 658 WREG32(index_reg, 0x10802); 659 WREG32(data_reg, 0xBFE8BED8); 660 WREG32(index_reg, 0x20000); 661 WREG32(data_reg, 0x80008000); 662 WREG32(index_reg, 0x20001); 663 WREG32(data_reg, 0x90008000); 664 WREG32(index_reg, 0x20002); 665 WREG32(data_reg, 0x80008000); 666 WREG32(index_reg, 0x20003); 667 WREG32(data_reg, 0x80008000); 668 WREG32(index_reg, 0x20100); 669 WREG32(data_reg, 0x80108000); 670 WREG32(index_reg, 0x20101); 671 WREG32(data_reg, 0x8FE0BF70); 672 WREG32(index_reg, 0x20102); 673 WREG32(data_reg, 0xBFE880C0); 674 WREG32(index_reg, 0x20103); 675 WREG32(data_reg, 0x80008000); 676 WREG32(index_reg, 0x20200); 677 WREG32(data_reg, 0x8018BFF8); 678 WREG32(index_reg, 0x20201); 679 WREG32(data_reg, 0x8F80BF08); 680 WREG32(index_reg, 0x20202); 681 WREG32(data_reg, 0xBFD081A0); 682 WREG32(index_reg, 0x20203); 683 WREG32(data_reg, 0xBFF88000); 684 WREG32(index_reg, 0x20300); 685 WREG32(data_reg, 0x80188000); 686 WREG32(index_reg, 0x20301); 687 WREG32(data_reg, 0x8EE0BEC0); 688 WREG32(index_reg, 0x20302); 689 WREG32(data_reg, 0xBFB082A0); 690 WREG32(index_reg, 0x20303); 691 WREG32(data_reg, 0x80008000); 692 WREG32(index_reg, 0x20400); 693 WREG32(data_reg, 0x80188000); 694 WREG32(index_reg, 0x20401); 695 WREG32(data_reg, 0x8E00BEA0); 696 WREG32(index_reg, 0x20402); 697 WREG32(data_reg, 0xBF8883C0); 698 WREG32(index_reg, 0x20403); 699 WREG32(data_reg, 0x80008000); 700 WREG32(index_reg, 0x20500); 701 WREG32(data_reg, 0x80188000); 702 WREG32(index_reg, 0x20501); 703 WREG32(data_reg, 0x8D00BE90); 704 WREG32(index_reg, 0x20502); 705 WREG32(data_reg, 0xBF588500); 706 WREG32(index_reg, 0x20503); 707 WREG32(data_reg, 0x80008008); 708 WREG32(index_reg, 0x20600); 709 WREG32(data_reg, 0x80188000); 710 WREG32(index_reg, 0x20601); 711 WREG32(data_reg, 0x8BC0BE98); 712 WREG32(index_reg, 0x20602); 713 WREG32(data_reg, 0xBF308660); 714 WREG32(index_reg, 0x20603); 715 WREG32(data_reg, 0x80008008); 716 WREG32(index_reg, 0x20700); 717 WREG32(data_reg, 0x80108000); 718 WREG32(index_reg, 0x20701); 719 WREG32(data_reg, 0x8A80BEB0); 720 WREG32(index_reg, 0x20702); 721 WREG32(data_reg, 0xBF0087C0); 722 WREG32(index_reg, 0x20703); 723 WREG32(data_reg, 0x80008008); 724 WREG32(index_reg, 0x20800); 725 WREG32(data_reg, 0x80108000); 726 WREG32(index_reg, 0x20801); 727 WREG32(data_reg, 0x8920BED0); 728 WREG32(index_reg, 0x20802); 729 WREG32(data_reg, 0xBED08920); 730 WREG32(index_reg, 0x20803); 731 WREG32(data_reg, 0x80008010); 732 WREG32(index_reg, 0x30000); 733 WREG32(data_reg, 0x90008000); 734 WREG32(index_reg, 0x30001); 735 WREG32(data_reg, 0x80008000); 736 WREG32(index_reg, 0x30100); 737 WREG32(data_reg, 0x8FE0BF90); 738 WREG32(index_reg, 0x30101); 739 WREG32(data_reg, 0xBFF880A0); 740 WREG32(index_reg, 0x30200); 741 WREG32(data_reg, 0x8F60BF40); 742 WREG32(index_reg, 0x30201); 743 WREG32(data_reg, 0xBFE88180); 744 WREG32(index_reg, 0x30300); 745 WREG32(data_reg, 0x8EC0BF00); 746 WREG32(index_reg, 0x30301); 747 WREG32(data_reg, 0xBFC88280); 748 WREG32(index_reg, 0x30400); 749 WREG32(data_reg, 0x8DE0BEE0); 750 WREG32(index_reg, 0x30401); 751 WREG32(data_reg, 0xBFA083A0); 752 WREG32(index_reg, 0x30500); 753 WREG32(data_reg, 0x8CE0BED0); 754 WREG32(index_reg, 0x30501); 755 WREG32(data_reg, 0xBF7884E0); 756 WREG32(index_reg, 0x30600); 757 WREG32(data_reg, 0x8BA0BED8); 758 WREG32(index_reg, 0x30601); 759 WREG32(data_reg, 0xBF508640); 760 WREG32(index_reg, 0x30700); 761 WREG32(data_reg, 0x8A60BEE8); 762 WREG32(index_reg, 0x30701); 763 WREG32(data_reg, 0xBF2087A0); 764 WREG32(index_reg, 0x30800); 765 WREG32(data_reg, 0x8900BF00); 766 WREG32(index_reg, 0x30801); 767 WREG32(data_reg, 0xBF008900); 768} 769 770struct rv515_watermark { 771 u32 lb_request_fifo_depth; 772 fixed20_12 num_line_pair; 773 fixed20_12 estimated_width; 774 fixed20_12 worst_case_latency; 775 fixed20_12 consumption_rate; 776 fixed20_12 active_time; 777 fixed20_12 dbpp; 778 fixed20_12 priority_mark_max; 779 fixed20_12 priority_mark; 780 fixed20_12 sclk; 781}; 782 783void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, 784 struct radeon_crtc *crtc, 785 struct rv515_watermark *wm) 786{ 787 struct drm_display_mode *mode = &crtc->base.mode; 788 fixed20_12 a, b, c; 789 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 790 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 791 792 if (!crtc->base.enabled) { 793 wm->lb_request_fifo_depth = 4; 794 return; 795 } 796 797 if (crtc->vsc.full > dfixed_const(2)) 798 wm->num_line_pair.full = dfixed_const(2); 799 else 800 wm->num_line_pair.full = dfixed_const(1); 801 802 b.full = dfixed_const(mode->crtc_hdisplay); 803 c.full = dfixed_const(256); 804 a.full = dfixed_div(b, c); 805 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 806 request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 807 if (a.full < dfixed_const(4)) { 808 wm->lb_request_fifo_depth = 4; 809 } else { 810 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 811 } 812 813 /* Determine consumption rate 814 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 815 * vtaps = number of vertical taps, 816 * vsc = vertical scaling ratio, defined as source/destination 817 * hsc = horizontal scaling ration, defined as source/destination 818 */ 819 a.full = dfixed_const(mode->clock); 820 b.full = dfixed_const(1000); 821 a.full = dfixed_div(a, b); 822 pclk.full = dfixed_div(b, a); 823 if (crtc->rmx_type != RMX_OFF) { 824 b.full = dfixed_const(2); 825 if (crtc->vsc.full > b.full) 826 b.full = crtc->vsc.full; 827 b.full = dfixed_mul(b, crtc->hsc); 828 c.full = dfixed_const(2); 829 b.full = dfixed_div(b, c); 830 consumption_time.full = dfixed_div(pclk, b); 831 } else { 832 consumption_time.full = pclk.full; 833 } 834 a.full = dfixed_const(1); 835 wm->consumption_rate.full = dfixed_div(a, consumption_time); 836 837 838 /* Determine line time 839 * LineTime = total time for one line of displayhtotal 840 * LineTime = total number of horizontal pixels 841 * pclk = pixel clock period(ns) 842 */ 843 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 844 line_time.full = dfixed_mul(a, pclk); 845 846 /* Determine active time 847 * ActiveTime = time of active region of display within one line, 848 * hactive = total number of horizontal active pixels 849 * htotal = total number of horizontal pixels 850 */ 851 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 852 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 853 wm->active_time.full = dfixed_mul(line_time, b); 854 wm->active_time.full = dfixed_div(wm->active_time, a); 855 856 /* Determine chunk time 857 * ChunkTime = the time it takes the DCP to send one chunk of data 858 * to the LB which consists of pipeline delay and inter chunk gap 859 * sclk = system clock(Mhz) 860 */ 861 a.full = dfixed_const(600 * 1000); 862 chunk_time.full = dfixed_div(a, rdev->pm.sclk); 863 read_delay_latency.full = dfixed_const(1000); 864 865 /* Determine the worst case latency 866 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 867 * WorstCaseLatency = worst case time from urgent to when the MC starts 868 * to return data 869 * READ_DELAY_IDLE_MAX = constant of 1us 870 * ChunkTime = time it takes the DCP to send one chunk of data to the LB 871 * which consists of pipeline delay and inter chunk gap 872 */ 873 if (dfixed_trunc(wm->num_line_pair) > 1) { 874 a.full = dfixed_const(3); 875 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 876 wm->worst_case_latency.full += read_delay_latency.full; 877 } else { 878 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; 879 } 880 881 /* Determine the tolerable latency 882 * TolerableLatency = Any given request has only 1 line time 883 * for the data to be returned 884 * LBRequestFifoDepth = Number of chunk requests the LB can 885 * put into the request FIFO for a display 886 * LineTime = total time for one line of display 887 * ChunkTime = the time it takes the DCP to send one chunk 888 * of data to the LB which consists of 889 * pipeline delay and inter chunk gap 890 */ 891 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 892 tolerable_latency.full = line_time.full; 893 } else { 894 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 895 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 896 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 897 tolerable_latency.full = line_time.full - tolerable_latency.full; 898 } 899 /* We assume worst case 32bits (4 bytes) */ 900 wm->dbpp.full = dfixed_const(2 * 16); 901 902 /* Determine the maximum priority mark 903 * width = viewport width in pixels 904 */ 905 a.full = dfixed_const(16); 906 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 907 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 908 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 909 910 /* Determine estimated width */ 911 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 912 estimated_width.full = dfixed_div(estimated_width, consumption_time); 913 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 914 wm->priority_mark.full = wm->priority_mark_max.full; 915 } else { 916 a.full = dfixed_const(16); 917 wm->priority_mark.full = dfixed_div(estimated_width, a); 918 wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 919 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 920 } 921} 922 923void rv515_bandwidth_avivo_update(struct radeon_device *rdev) 924{ 925 struct drm_display_mode *mode0 = NULL; 926 struct drm_display_mode *mode1 = NULL; 927 struct rv515_watermark wm0; 928 struct rv515_watermark wm1; 929 u32 tmp; 930 u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF; 931 u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF; 932 fixed20_12 priority_mark02, priority_mark12, fill_rate; 933 fixed20_12 a, b; 934 935 if (rdev->mode_info.crtcs[0]->base.enabled) 936 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 937 if (rdev->mode_info.crtcs[1]->base.enabled) 938 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 939 rs690_line_buffer_adjust(rdev, mode0, mode1); 940 941 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); 942 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); 943 944 tmp = wm0.lb_request_fifo_depth; 945 tmp |= wm1.lb_request_fifo_depth << 16; 946 WREG32(LB_MAX_REQ_OUTSTANDING, tmp); 947 948 if (mode0 && mode1) { 949 if (dfixed_trunc(wm0.dbpp) > 64) 950 a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); 951 else 952 a.full = wm0.num_line_pair.full; 953 if (dfixed_trunc(wm1.dbpp) > 64) 954 b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); 955 else 956 b.full = wm1.num_line_pair.full; 957 a.full += b.full; 958 fill_rate.full = dfixed_div(wm0.sclk, a); 959 if (wm0.consumption_rate.full > fill_rate.full) { 960 b.full = wm0.consumption_rate.full - fill_rate.full; 961 b.full = dfixed_mul(b, wm0.active_time); 962 a.full = dfixed_const(16); 963 b.full = dfixed_div(b, a); 964 a.full = dfixed_mul(wm0.worst_case_latency, 965 wm0.consumption_rate); 966 priority_mark02.full = a.full + b.full; 967 } else { 968 a.full = dfixed_mul(wm0.worst_case_latency, 969 wm0.consumption_rate); 970 b.full = dfixed_const(16 * 1000); 971 priority_mark02.full = dfixed_div(a, b); 972 } 973 if (wm1.consumption_rate.full > fill_rate.full) { 974 b.full = wm1.consumption_rate.full - fill_rate.full; 975 b.full = dfixed_mul(b, wm1.active_time); 976 a.full = dfixed_const(16); 977 b.full = dfixed_div(b, a); 978 a.full = dfixed_mul(wm1.worst_case_latency, 979 wm1.consumption_rate); 980 priority_mark12.full = a.full + b.full; 981 } else { 982 a.full = dfixed_mul(wm1.worst_case_latency, 983 wm1.consumption_rate); 984 b.full = dfixed_const(16 * 1000); 985 priority_mark12.full = dfixed_div(a, b); 986 } 987 if (wm0.priority_mark.full > priority_mark02.full) 988 priority_mark02.full = wm0.priority_mark.full; 989 if (dfixed_trunc(priority_mark02) < 0) 990 priority_mark02.full = 0; 991 if (wm0.priority_mark_max.full > priority_mark02.full) 992 priority_mark02.full = wm0.priority_mark_max.full; 993 if (wm1.priority_mark.full > priority_mark12.full) 994 priority_mark12.full = wm1.priority_mark.full; 995 if (dfixed_trunc(priority_mark12) < 0) 996 priority_mark12.full = 0; 997 if (wm1.priority_mark_max.full > priority_mark12.full) 998 priority_mark12.full = wm1.priority_mark_max.full; 999 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1000 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1001 if (rdev->disp_priority == 2) { 1002 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1003 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1004 } 1005 } else if (mode0) { 1006 if (dfixed_trunc(wm0.dbpp) > 64) 1007 a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); 1008 else 1009 a.full = wm0.num_line_pair.full; 1010 fill_rate.full = dfixed_div(wm0.sclk, a); 1011 if (wm0.consumption_rate.full > fill_rate.full) { 1012 b.full = wm0.consumption_rate.full - fill_rate.full; 1013 b.full = dfixed_mul(b, wm0.active_time); 1014 a.full = dfixed_const(16); 1015 b.full = dfixed_div(b, a); 1016 a.full = dfixed_mul(wm0.worst_case_latency, 1017 wm0.consumption_rate); 1018 priority_mark02.full = a.full + b.full; 1019 } else { 1020 a.full = dfixed_mul(wm0.worst_case_latency, 1021 wm0.consumption_rate); 1022 b.full = dfixed_const(16); 1023 priority_mark02.full = dfixed_div(a, b); 1024 } 1025 if (wm0.priority_mark.full > priority_mark02.full) 1026 priority_mark02.full = wm0.priority_mark.full; 1027 if (dfixed_trunc(priority_mark02) < 0) 1028 priority_mark02.full = 0; 1029 if (wm0.priority_mark_max.full > priority_mark02.full) 1030 priority_mark02.full = wm0.priority_mark_max.full; 1031 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 1032 if (rdev->disp_priority == 2) 1033 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1034 } else if (mode1) { 1035 if (dfixed_trunc(wm1.dbpp) > 64) 1036 a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); 1037 else 1038 a.full = wm1.num_line_pair.full; 1039 fill_rate.full = dfixed_div(wm1.sclk, a); 1040 if (wm1.consumption_rate.full > fill_rate.full) { 1041 b.full = wm1.consumption_rate.full - fill_rate.full; 1042 b.full = dfixed_mul(b, wm1.active_time); 1043 a.full = dfixed_const(16); 1044 b.full = dfixed_div(b, a); 1045 a.full = dfixed_mul(wm1.worst_case_latency, 1046 wm1.consumption_rate); 1047 priority_mark12.full = a.full + b.full; 1048 } else { 1049 a.full = dfixed_mul(wm1.worst_case_latency, 1050 wm1.consumption_rate); 1051 b.full = dfixed_const(16 * 1000); 1052 priority_mark12.full = dfixed_div(a, b); 1053 } 1054 if (wm1.priority_mark.full > priority_mark12.full) 1055 priority_mark12.full = wm1.priority_mark.full; 1056 if (dfixed_trunc(priority_mark12) < 0) 1057 priority_mark12.full = 0; 1058 if (wm1.priority_mark_max.full > priority_mark12.full) 1059 priority_mark12.full = wm1.priority_mark_max.full; 1060 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 1061 if (rdev->disp_priority == 2) 1062 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1063 } 1064 1065 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 1066 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 1067 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 1068 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 1069} 1070 1071void rv515_bandwidth_update(struct radeon_device *rdev) 1072{ 1073 uint32_t tmp; 1074 struct drm_display_mode *mode0 = NULL; 1075 struct drm_display_mode *mode1 = NULL; 1076 1077 radeon_update_display_priority(rdev); 1078 1079 if (rdev->mode_info.crtcs[0]->base.enabled) 1080 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1081 if (rdev->mode_info.crtcs[1]->base.enabled) 1082 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1083 /* 1084 * Set display0/1 priority up in the memory controller for 1085 * modes if the user specifies HIGH for displaypriority 1086 * option. 1087 */ 1088 if ((rdev->disp_priority == 2) && 1089 (rdev->family == CHIP_RV515)) { 1090 tmp = RREG32_MC(MC_MISC_LAT_TIMER); 1091 tmp &= ~MC_DISP1R_INIT_LAT_MASK; 1092 tmp &= ~MC_DISP0R_INIT_LAT_MASK; 1093 if (mode1) 1094 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); 1095 if (mode0) 1096 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); 1097 WREG32_MC(MC_MISC_LAT_TIMER, tmp); 1098 } 1099 rv515_bandwidth_avivo_update(rdev); 1100} 1101