1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#include "drmP.h" 29#include "radeon.h" 30#include "radeon_asic.h" 31#include "atom.h" 32#include "rs690d.h" 33 34static int rs690_mc_wait_for_idle(struct radeon_device *rdev) 35{ 36 unsigned i; 37 uint32_t tmp; 38 39 for (i = 0; i < rdev->usec_timeout; i++) { 40 /* read MC_STATUS */ 41 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS); 42 if (G_000090_MC_SYSTEM_IDLE(tmp)) 43 return 0; 44 udelay(1); 45 } 46 return -1; 47} 48 49static void rs690_gpu_init(struct radeon_device *rdev) 50{ 51 r420_pipes_init(rdev); 52 if (rs690_mc_wait_for_idle(rdev)) { 53 printk(KERN_WARNING "Failed to wait MC idle while " 54 "programming pipes. Bad things might happen.\n"); 55 } 56} 57 58union igp_info { 59 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 60 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2; 61}; 62 63void rs690_pm_info(struct radeon_device *rdev) 64{ 65 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 66 union igp_info *info; 67 uint16_t data_offset; 68 uint8_t frev, crev; 69 fixed20_12 tmp; 70 71 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, 72 &frev, &crev, &data_offset)) { 73 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset); 74 75 /* Get various system informations from bios */ 76 switch (crev) { 77 case 1: 78 tmp.full = dfixed_const(100); 79 rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info.ulBootUpMemoryClock); 80 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); 81 if (info->info.usK8MemoryClock) 82 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); 83 else if (rdev->clock.default_mclk) { 84 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); 85 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); 86 } else 87 rdev->pm.igp_system_mclk.full = dfixed_const(400); 88 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock)); 89 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth); 90 break; 91 case 2: 92 tmp.full = dfixed_const(100); 93 rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info_v2.ulBootUpSidePortClock); 94 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); 95 if (info->info_v2.ulBootUpUMAClock) 96 rdev->pm.igp_system_mclk.full = dfixed_const(info->info_v2.ulBootUpUMAClock); 97 else if (rdev->clock.default_mclk) 98 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); 99 else 100 rdev->pm.igp_system_mclk.full = dfixed_const(66700); 101 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); 102 rdev->pm.igp_ht_link_clk.full = dfixed_const(info->info_v2.ulHTLinkFreq); 103 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp); 104 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); 105 break; 106 default: 107 /* We assume the slower possible clock ie worst case */ 108 rdev->pm.igp_sideport_mclk.full = dfixed_const(200); 109 rdev->pm.igp_system_mclk.full = dfixed_const(200); 110 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); 111 rdev->pm.igp_ht_link_width.full = dfixed_const(8); 112 DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 113 break; 114 } 115 } else { 116 /* We assume the slower possible clock ie worst case */ 117 rdev->pm.igp_sideport_mclk.full = dfixed_const(200); 118 rdev->pm.igp_system_mclk.full = dfixed_const(200); 119 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); 120 rdev->pm.igp_ht_link_width.full = dfixed_const(8); 121 DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 122 } 123 /* Compute various bandwidth */ 124 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ 125 tmp.full = dfixed_const(4); 126 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp); 127 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 128 * = ht_clk * ht_width / 5 129 */ 130 tmp.full = dfixed_const(5); 131 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk, 132 rdev->pm.igp_ht_link_width); 133 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp); 134 if (tmp.full < rdev->pm.max_bandwidth.full) { 135 /* HT link is a limiting factor */ 136 rdev->pm.max_bandwidth.full = tmp.full; 137 } 138 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 139 * = (sideport_clk * 14) / 10 140 */ 141 tmp.full = dfixed_const(14); 142 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp); 143 tmp.full = dfixed_const(10); 144 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp); 145} 146 147void rs690_mc_init(struct radeon_device *rdev) 148{ 149 u64 base; 150 151 rs400_gart_adjust_size(rdev); 152 rdev->mc.vram_is_ddr = true; 153 rdev->mc.vram_width = 128; 154 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 155 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 156 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 157 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 158 rdev->mc.visible_vram_size = rdev->mc.aper_size; 159 rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 160 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 161 base = G_000100_MC_FB_START(base) << 16; 162 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 163 rs690_pm_info(rdev); 164 radeon_vram_location(rdev, &rdev->mc, base); 165 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 166 radeon_gtt_location(rdev, &rdev->mc); 167 radeon_update_bandwidth_info(rdev); 168} 169 170void rs690_line_buffer_adjust(struct radeon_device *rdev, 171 struct drm_display_mode *mode1, 172 struct drm_display_mode *mode2) 173{ 174 u32 tmp; 175 176 /* 177 * Line Buffer Setup 178 * There is a single line buffer shared by both display controllers. 179 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 180 * the display controllers. The paritioning can either be done 181 * manually or via one of four preset allocations specified in bits 1:0: 182 * 0 - line buffer is divided in half and shared between crtc 183 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 184 * 2 - D1 gets the whole buffer 185 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 186 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual 187 * allocation mode. In manual allocation mode, D1 always starts at 0, 188 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1. 189 */ 190 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT; 191 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE; 192 /* auto */ 193 if (mode1 && mode2) { 194 if (mode1->hdisplay > mode2->hdisplay) { 195 if (mode1->hdisplay > 2560) 196 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; 197 else 198 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 199 } else if (mode2->hdisplay > mode1->hdisplay) { 200 if (mode2->hdisplay > 2560) 201 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 202 else 203 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 204 } else 205 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 206 } else if (mode1) { 207 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY; 208 } else if (mode2) { 209 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 210 } 211 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp); 212} 213 214struct rs690_watermark { 215 u32 lb_request_fifo_depth; 216 fixed20_12 num_line_pair; 217 fixed20_12 estimated_width; 218 fixed20_12 worst_case_latency; 219 fixed20_12 consumption_rate; 220 fixed20_12 active_time; 221 fixed20_12 dbpp; 222 fixed20_12 priority_mark_max; 223 fixed20_12 priority_mark; 224 fixed20_12 sclk; 225}; 226 227void rs690_crtc_bandwidth_compute(struct radeon_device *rdev, 228 struct radeon_crtc *crtc, 229 struct rs690_watermark *wm) 230{ 231 struct drm_display_mode *mode = &crtc->base.mode; 232 fixed20_12 a, b, c; 233 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 234 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 235 236 if (!crtc->base.enabled) { 237 wm->lb_request_fifo_depth = 4; 238 return; 239 } 240 241 if (crtc->vsc.full > dfixed_const(2)) 242 wm->num_line_pair.full = dfixed_const(2); 243 else 244 wm->num_line_pair.full = dfixed_const(1); 245 246 b.full = dfixed_const(mode->crtc_hdisplay); 247 c.full = dfixed_const(256); 248 a.full = dfixed_div(b, c); 249 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 250 request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 251 if (a.full < dfixed_const(4)) { 252 wm->lb_request_fifo_depth = 4; 253 } else { 254 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 255 } 256 257 /* Determine consumption rate 258 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 259 * vtaps = number of vertical taps, 260 * vsc = vertical scaling ratio, defined as source/destination 261 * hsc = horizontal scaling ration, defined as source/destination 262 */ 263 a.full = dfixed_const(mode->clock); 264 b.full = dfixed_const(1000); 265 a.full = dfixed_div(a, b); 266 pclk.full = dfixed_div(b, a); 267 if (crtc->rmx_type != RMX_OFF) { 268 b.full = dfixed_const(2); 269 if (crtc->vsc.full > b.full) 270 b.full = crtc->vsc.full; 271 b.full = dfixed_mul(b, crtc->hsc); 272 c.full = dfixed_const(2); 273 b.full = dfixed_div(b, c); 274 consumption_time.full = dfixed_div(pclk, b); 275 } else { 276 consumption_time.full = pclk.full; 277 } 278 a.full = dfixed_const(1); 279 wm->consumption_rate.full = dfixed_div(a, consumption_time); 280 281 282 /* Determine line time 283 * LineTime = total time for one line of displayhtotal 284 * LineTime = total number of horizontal pixels 285 * pclk = pixel clock period(ns) 286 */ 287 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 288 line_time.full = dfixed_mul(a, pclk); 289 290 /* Determine active time 291 * ActiveTime = time of active region of display within one line, 292 * hactive = total number of horizontal active pixels 293 * htotal = total number of horizontal pixels 294 */ 295 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 296 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 297 wm->active_time.full = dfixed_mul(line_time, b); 298 wm->active_time.full = dfixed_div(wm->active_time, a); 299 300 /* Maximun bandwidth is the minimun bandwidth of all component */ 301 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth; 302 if (rdev->mc.igp_sideport_enabled) { 303 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full && 304 rdev->pm.sideport_bandwidth.full) 305 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth; 306 read_delay_latency.full = dfixed_const(370 * 800 * 1000); 307 read_delay_latency.full = dfixed_div(read_delay_latency, 308 rdev->pm.igp_sideport_mclk); 309 } else { 310 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full && 311 rdev->pm.k8_bandwidth.full) 312 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth; 313 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full && 314 rdev->pm.ht_bandwidth.full) 315 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth; 316 read_delay_latency.full = dfixed_const(5000); 317 } 318 319 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ 320 a.full = dfixed_const(16); 321 rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a); 322 a.full = dfixed_const(1000); 323 rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk); 324 /* Determine chunk time 325 * ChunkTime = the time it takes the DCP to send one chunk of data 326 * to the LB which consists of pipeline delay and inter chunk gap 327 * sclk = system clock(ns) 328 */ 329 a.full = dfixed_const(256 * 13); 330 chunk_time.full = dfixed_mul(rdev->pm.sclk, a); 331 a.full = dfixed_const(10); 332 chunk_time.full = dfixed_div(chunk_time, a); 333 334 /* Determine the worst case latency 335 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 336 * WorstCaseLatency = worst case time from urgent to when the MC starts 337 * to return data 338 * READ_DELAY_IDLE_MAX = constant of 1us 339 * ChunkTime = time it takes the DCP to send one chunk of data to the LB 340 * which consists of pipeline delay and inter chunk gap 341 */ 342 if (dfixed_trunc(wm->num_line_pair) > 1) { 343 a.full = dfixed_const(3); 344 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 345 wm->worst_case_latency.full += read_delay_latency.full; 346 } else { 347 a.full = dfixed_const(2); 348 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 349 wm->worst_case_latency.full += read_delay_latency.full; 350 } 351 352 /* Determine the tolerable latency 353 * TolerableLatency = Any given request has only 1 line time 354 * for the data to be returned 355 * LBRequestFifoDepth = Number of chunk requests the LB can 356 * put into the request FIFO for a display 357 * LineTime = total time for one line of display 358 * ChunkTime = the time it takes the DCP to send one chunk 359 * of data to the LB which consists of 360 * pipeline delay and inter chunk gap 361 */ 362 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 363 tolerable_latency.full = line_time.full; 364 } else { 365 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 366 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 367 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 368 tolerable_latency.full = line_time.full - tolerable_latency.full; 369 } 370 /* We assume worst case 32bits (4 bytes) */ 371 wm->dbpp.full = dfixed_const(4 * 8); 372 373 /* Determine the maximum priority mark 374 * width = viewport width in pixels 375 */ 376 a.full = dfixed_const(16); 377 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 378 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 379 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 380 381 /* Determine estimated width */ 382 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 383 estimated_width.full = dfixed_div(estimated_width, consumption_time); 384 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 385 wm->priority_mark.full = dfixed_const(10); 386 } else { 387 a.full = dfixed_const(16); 388 wm->priority_mark.full = dfixed_div(estimated_width, a); 389 wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 390 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 391 } 392} 393 394void rs690_bandwidth_update(struct radeon_device *rdev) 395{ 396 struct drm_display_mode *mode0 = NULL; 397 struct drm_display_mode *mode1 = NULL; 398 struct rs690_watermark wm0; 399 struct rs690_watermark wm1; 400 u32 tmp; 401 u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); 402 u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); 403 fixed20_12 priority_mark02, priority_mark12, fill_rate; 404 fixed20_12 a, b; 405 406 radeon_update_display_priority(rdev); 407 408 if (rdev->mode_info.crtcs[0]->base.enabled) 409 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 410 if (rdev->mode_info.crtcs[1]->base.enabled) 411 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 412 /* 413 * Set display0/1 priority up in the memory controller for 414 * modes if the user specifies HIGH for displaypriority 415 * option. 416 */ 417 if ((rdev->disp_priority == 2) && 418 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) { 419 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); 420 tmp &= C_000104_MC_DISP0R_INIT_LAT; 421 tmp &= C_000104_MC_DISP1R_INIT_LAT; 422 if (mode0) 423 tmp |= S_000104_MC_DISP0R_INIT_LAT(1); 424 if (mode1) 425 tmp |= S_000104_MC_DISP1R_INIT_LAT(1); 426 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp); 427 } 428 rs690_line_buffer_adjust(rdev, mode0, mode1); 429 430 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) 431 WREG32(R_006C9C_DCP_CONTROL, 0); 432 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) 433 WREG32(R_006C9C_DCP_CONTROL, 2); 434 435 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); 436 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); 437 438 tmp = (wm0.lb_request_fifo_depth - 1); 439 tmp |= (wm1.lb_request_fifo_depth - 1) << 16; 440 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); 441 442 if (mode0 && mode1) { 443 if (dfixed_trunc(wm0.dbpp) > 64) 444 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); 445 else 446 a.full = wm0.num_line_pair.full; 447 if (dfixed_trunc(wm1.dbpp) > 64) 448 b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); 449 else 450 b.full = wm1.num_line_pair.full; 451 a.full += b.full; 452 fill_rate.full = dfixed_div(wm0.sclk, a); 453 if (wm0.consumption_rate.full > fill_rate.full) { 454 b.full = wm0.consumption_rate.full - fill_rate.full; 455 b.full = dfixed_mul(b, wm0.active_time); 456 a.full = dfixed_mul(wm0.worst_case_latency, 457 wm0.consumption_rate); 458 a.full = a.full + b.full; 459 b.full = dfixed_const(16 * 1000); 460 priority_mark02.full = dfixed_div(a, b); 461 } else { 462 a.full = dfixed_mul(wm0.worst_case_latency, 463 wm0.consumption_rate); 464 b.full = dfixed_const(16 * 1000); 465 priority_mark02.full = dfixed_div(a, b); 466 } 467 if (wm1.consumption_rate.full > fill_rate.full) { 468 b.full = wm1.consumption_rate.full - fill_rate.full; 469 b.full = dfixed_mul(b, wm1.active_time); 470 a.full = dfixed_mul(wm1.worst_case_latency, 471 wm1.consumption_rate); 472 a.full = a.full + b.full; 473 b.full = dfixed_const(16 * 1000); 474 priority_mark12.full = dfixed_div(a, b); 475 } else { 476 a.full = dfixed_mul(wm1.worst_case_latency, 477 wm1.consumption_rate); 478 b.full = dfixed_const(16 * 1000); 479 priority_mark12.full = dfixed_div(a, b); 480 } 481 if (wm0.priority_mark.full > priority_mark02.full) 482 priority_mark02.full = wm0.priority_mark.full; 483 if (dfixed_trunc(priority_mark02) < 0) 484 priority_mark02.full = 0; 485 if (wm0.priority_mark_max.full > priority_mark02.full) 486 priority_mark02.full = wm0.priority_mark_max.full; 487 if (wm1.priority_mark.full > priority_mark12.full) 488 priority_mark12.full = wm1.priority_mark.full; 489 if (dfixed_trunc(priority_mark12) < 0) 490 priority_mark12.full = 0; 491 if (wm1.priority_mark_max.full > priority_mark12.full) 492 priority_mark12.full = wm1.priority_mark_max.full; 493 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 494 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 495 if (rdev->disp_priority == 2) { 496 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 497 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 498 } 499 } else if (mode0) { 500 if (dfixed_trunc(wm0.dbpp) > 64) 501 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); 502 else 503 a.full = wm0.num_line_pair.full; 504 fill_rate.full = dfixed_div(wm0.sclk, a); 505 if (wm0.consumption_rate.full > fill_rate.full) { 506 b.full = wm0.consumption_rate.full - fill_rate.full; 507 b.full = dfixed_mul(b, wm0.active_time); 508 a.full = dfixed_mul(wm0.worst_case_latency, 509 wm0.consumption_rate); 510 a.full = a.full + b.full; 511 b.full = dfixed_const(16 * 1000); 512 priority_mark02.full = dfixed_div(a, b); 513 } else { 514 a.full = dfixed_mul(wm0.worst_case_latency, 515 wm0.consumption_rate); 516 b.full = dfixed_const(16 * 1000); 517 priority_mark02.full = dfixed_div(a, b); 518 } 519 if (wm0.priority_mark.full > priority_mark02.full) 520 priority_mark02.full = wm0.priority_mark.full; 521 if (dfixed_trunc(priority_mark02) < 0) 522 priority_mark02.full = 0; 523 if (wm0.priority_mark_max.full > priority_mark02.full) 524 priority_mark02.full = wm0.priority_mark_max.full; 525 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 526 if (rdev->disp_priority == 2) 527 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 528 } else if (mode1) { 529 if (dfixed_trunc(wm1.dbpp) > 64) 530 a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); 531 else 532 a.full = wm1.num_line_pair.full; 533 fill_rate.full = dfixed_div(wm1.sclk, a); 534 if (wm1.consumption_rate.full > fill_rate.full) { 535 b.full = wm1.consumption_rate.full - fill_rate.full; 536 b.full = dfixed_mul(b, wm1.active_time); 537 a.full = dfixed_mul(wm1.worst_case_latency, 538 wm1.consumption_rate); 539 a.full = a.full + b.full; 540 b.full = dfixed_const(16 * 1000); 541 priority_mark12.full = dfixed_div(a, b); 542 } else { 543 a.full = dfixed_mul(wm1.worst_case_latency, 544 wm1.consumption_rate); 545 b.full = dfixed_const(16 * 1000); 546 priority_mark12.full = dfixed_div(a, b); 547 } 548 if (wm1.priority_mark.full > priority_mark12.full) 549 priority_mark12.full = wm1.priority_mark.full; 550 if (dfixed_trunc(priority_mark12) < 0) 551 priority_mark12.full = 0; 552 if (wm1.priority_mark_max.full > priority_mark12.full) 553 priority_mark12.full = wm1.priority_mark_max.full; 554 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 555 if (rdev->disp_priority == 2) 556 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 557 } 558 559 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 560 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 561 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 562 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 563} 564 565uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) 566{ 567 uint32_t r; 568 569 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg)); 570 r = RREG32(R_00007C_MC_DATA); 571 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR); 572 return r; 573} 574 575void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 576{ 577 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) | 578 S_000078_MC_IND_WR_EN(1)); 579 WREG32(R_00007C_MC_DATA, v); 580 WREG32(R_000078_MC_INDEX, 0x7F); 581} 582 583void rs690_mc_program(struct radeon_device *rdev) 584{ 585 struct rv515_mc_save save; 586 587 /* Stops all mc clients */ 588 rv515_mc_stop(rdev, &save); 589 590 /* Wait for mc idle */ 591 if (rs690_mc_wait_for_idle(rdev)) 592 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 593 /* Program MC, should be a 32bits limited address space */ 594 WREG32_MC(R_000100_MCCFG_FB_LOCATION, 595 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) | 596 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16)); 597 WREG32(R_000134_HDP_FB_LOCATION, 598 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 599 600 rv515_mc_resume(rdev, &save); 601} 602 603static int rs690_startup(struct radeon_device *rdev) 604{ 605 int r; 606 607 rs690_mc_program(rdev); 608 /* Resume clock */ 609 rv515_clock_startup(rdev); 610 /* Initialize GPU configuration (# pipes, ...) */ 611 rs690_gpu_init(rdev); 612 /* Initialize GART (initialize after TTM so we can allocate 613 * memory through TTM but finalize after TTM) */ 614 r = rs400_gart_enable(rdev); 615 if (r) 616 return r; 617 /* Enable IRQ */ 618 rs600_irq_set(rdev); 619 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 620 /* 1M ring buffer */ 621 r = r100_cp_init(rdev, 1024 * 1024); 622 if (r) { 623 dev_err(rdev->dev, "failled initializing CP (%d).\n", r); 624 return r; 625 } 626 r = r100_wb_init(rdev); 627 if (r) 628 dev_err(rdev->dev, "failled initializing WB (%d).\n", r); 629 r = r100_ib_init(rdev); 630 if (r) { 631 dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 632 return r; 633 } 634 635 r = r600_audio_init(rdev); 636 if (r) { 637 dev_err(rdev->dev, "failed initializing audio\n"); 638 return r; 639 } 640 641 return 0; 642} 643 644int rs690_resume(struct radeon_device *rdev) 645{ 646 /* Make sur GART are not working */ 647 rs400_gart_disable(rdev); 648 /* Resume clock before doing reset */ 649 rv515_clock_startup(rdev); 650 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 651 if (radeon_asic_reset(rdev)) { 652 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 653 RREG32(R_000E40_RBBM_STATUS), 654 RREG32(R_0007C0_CP_STAT)); 655 } 656 /* post */ 657 atom_asic_init(rdev->mode_info.atom_context); 658 /* Resume clock after posting */ 659 rv515_clock_startup(rdev); 660 /* Initialize surface registers */ 661 radeon_surface_init(rdev); 662 return rs690_startup(rdev); 663} 664 665int rs690_suspend(struct radeon_device *rdev) 666{ 667 r600_audio_fini(rdev); 668 r100_cp_disable(rdev); 669 r100_wb_disable(rdev); 670 rs600_irq_disable(rdev); 671 rs400_gart_disable(rdev); 672 return 0; 673} 674 675void rs690_fini(struct radeon_device *rdev) 676{ 677 r600_audio_fini(rdev); 678 r100_cp_fini(rdev); 679 r100_wb_fini(rdev); 680 r100_ib_fini(rdev); 681 radeon_gem_fini(rdev); 682 rs400_gart_fini(rdev); 683 radeon_irq_kms_fini(rdev); 684 radeon_fence_driver_fini(rdev); 685 radeon_bo_fini(rdev); 686 radeon_atombios_fini(rdev); 687 kfree(rdev->bios); 688 rdev->bios = NULL; 689} 690 691int rs690_init(struct radeon_device *rdev) 692{ 693 int r; 694 695 /* Disable VGA */ 696 rv515_vga_render_disable(rdev); 697 /* Initialize scratch registers */ 698 radeon_scratch_init(rdev); 699 /* Initialize surface registers */ 700 radeon_surface_init(rdev); 701 /* restore some register to sane defaults */ 702 r100_restore_sanity(rdev); 703 /* TODO: disable VGA need to use VGA request */ 704 /* BIOS*/ 705 if (!radeon_get_bios(rdev)) { 706 if (ASIC_IS_AVIVO(rdev)) 707 return -EINVAL; 708 } 709 if (rdev->is_atom_bios) { 710 r = radeon_atombios_init(rdev); 711 if (r) 712 return r; 713 } else { 714 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 715 return -EINVAL; 716 } 717 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 718 if (radeon_asic_reset(rdev)) { 719 dev_warn(rdev->dev, 720 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 721 RREG32(R_000E40_RBBM_STATUS), 722 RREG32(R_0007C0_CP_STAT)); 723 } 724 /* check if cards are posted or not */ 725 if (radeon_boot_test_post_card(rdev) == false) 726 return -EINVAL; 727 728 /* Initialize clocks */ 729 radeon_get_clock_info(rdev->ddev); 730 /* initialize memory controller */ 731 rs690_mc_init(rdev); 732 rv515_debugfs(rdev); 733 /* Fence driver */ 734 r = radeon_fence_driver_init(rdev); 735 if (r) 736 return r; 737 r = radeon_irq_kms_init(rdev); 738 if (r) 739 return r; 740 /* Memory manager */ 741 r = radeon_bo_init(rdev); 742 if (r) 743 return r; 744 r = rs400_gart_init(rdev); 745 if (r) 746 return r; 747 rs600_set_safe_registers(rdev); 748 rdev->accel_working = true; 749 r = rs690_startup(rdev); 750 if (r) { 751 /* Somethings want wront with the accel init stop accel */ 752 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 753 r100_cp_fini(rdev); 754 r100_wb_fini(rdev); 755 r100_ib_fini(rdev); 756 rs400_gart_fini(rdev); 757 radeon_irq_kms_fini(rdev); 758 rdev->accel_working = false; 759 } 760 return 0; 761} 762