1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Christian K��nig. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian K��nig 25 */ 26#include "drmP.h" 27#include "radeon_drm.h" 28#include "radeon.h" 29#include "atom.h" 30 31/* 32 * HDMI color format 33 */ 34enum r600_hdmi_color_format { 35 RGB = 0, 36 YCC_422 = 1, 37 YCC_444 = 2 38}; 39 40/* 41 * IEC60958 status bits 42 */ 43enum r600_hdmi_iec_status_bits { 44 AUDIO_STATUS_DIG_ENABLE = 0x01, 45 AUDIO_STATUS_V = 0x02, 46 AUDIO_STATUS_VCFG = 0x04, 47 AUDIO_STATUS_EMPHASIS = 0x08, 48 AUDIO_STATUS_COPYRIGHT = 0x10, 49 AUDIO_STATUS_NONAUDIO = 0x20, 50 AUDIO_STATUS_PROFESSIONAL = 0x40, 51 AUDIO_STATUS_LEVEL = 0x80 52}; 53 54struct { 55 uint32_t Clock; 56 57 int N_32kHz; 58 int CTS_32kHz; 59 60 int N_44_1kHz; 61 int CTS_44_1kHz; 62 63 int N_48kHz; 64 int CTS_48kHz; 65 66} r600_hdmi_ACR[] = { 67 /* 32kHz 44.1kHz 48kHz */ 68 /* Clock N CTS N CTS N CTS */ 69 { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ 70 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ 71 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ 72 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ 73 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ 74 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ 75 { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ 76 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ 77 { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ 78 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ 79 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ 80}; 81 82/* 83 * calculate CTS value if it's not found in the table 84 */ 85static void r600_hdmi_calc_CTS(uint32_t clock, int *CTS, int N, int freq) 86{ 87 if (*CTS == 0) 88 *CTS = clock * N / (128 * freq) * 1000; 89 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", 90 N, *CTS, freq); 91} 92 93/* 94 * update the N and CTS parameters for a given pixel clock rate 95 */ 96static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) 97{ 98 struct drm_device *dev = encoder->dev; 99 struct radeon_device *rdev = dev->dev_private; 100 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; 101 int CTS; 102 int N; 103 int i; 104 105 for (i = 0; r600_hdmi_ACR[i].Clock != clock && r600_hdmi_ACR[i].Clock != 0; i++); 106 107 CTS = r600_hdmi_ACR[i].CTS_32kHz; 108 N = r600_hdmi_ACR[i].N_32kHz; 109 r600_hdmi_calc_CTS(clock, &CTS, N, 32000); 110 WREG32(offset+R600_HDMI_32kHz_CTS, CTS << 12); 111 WREG32(offset+R600_HDMI_32kHz_N, N); 112 113 CTS = r600_hdmi_ACR[i].CTS_44_1kHz; 114 N = r600_hdmi_ACR[i].N_44_1kHz; 115 r600_hdmi_calc_CTS(clock, &CTS, N, 44100); 116 WREG32(offset+R600_HDMI_44_1kHz_CTS, CTS << 12); 117 WREG32(offset+R600_HDMI_44_1kHz_N, N); 118 119 CTS = r600_hdmi_ACR[i].CTS_48kHz; 120 N = r600_hdmi_ACR[i].N_48kHz; 121 r600_hdmi_calc_CTS(clock, &CTS, N, 48000); 122 WREG32(offset+R600_HDMI_48kHz_CTS, CTS << 12); 123 WREG32(offset+R600_HDMI_48kHz_N, N); 124} 125 126/* 127 * calculate the crc for a given info frame 128 */ 129static void r600_hdmi_infoframe_checksum(uint8_t packetType, 130 uint8_t versionNumber, 131 uint8_t length, 132 uint8_t *frame) 133{ 134 int i; 135 frame[0] = packetType + versionNumber + length; 136 for (i = 1; i <= length; i++) 137 frame[0] += frame[i]; 138 frame[0] = 0x100 - frame[0]; 139} 140 141/* 142 * build a HDMI Video Info Frame 143 */ 144static void r600_hdmi_videoinfoframe( 145 struct drm_encoder *encoder, 146 enum r600_hdmi_color_format color_format, 147 int active_information_present, 148 uint8_t active_format_aspect_ratio, 149 uint8_t scan_information, 150 uint8_t colorimetry, 151 uint8_t ex_colorimetry, 152 uint8_t quantization, 153 int ITC, 154 uint8_t picture_aspect_ratio, 155 uint8_t video_format_identification, 156 uint8_t pixel_repetition, 157 uint8_t non_uniform_picture_scaling, 158 uint8_t bar_info_data_valid, 159 uint16_t top_bar, 160 uint16_t bottom_bar, 161 uint16_t left_bar, 162 uint16_t right_bar 163) 164{ 165 struct drm_device *dev = encoder->dev; 166 struct radeon_device *rdev = dev->dev_private; 167 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; 168 169 uint8_t frame[14]; 170 171 frame[0x0] = 0; 172 frame[0x1] = 173 (scan_information & 0x3) | 174 ((bar_info_data_valid & 0x3) << 2) | 175 ((active_information_present & 0x1) << 4) | 176 ((color_format & 0x3) << 5); 177 frame[0x2] = 178 (active_format_aspect_ratio & 0xF) | 179 ((picture_aspect_ratio & 0x3) << 4) | 180 ((colorimetry & 0x3) << 6); 181 frame[0x3] = 182 (non_uniform_picture_scaling & 0x3) | 183 ((quantization & 0x3) << 2) | 184 ((ex_colorimetry & 0x7) << 4) | 185 ((ITC & 0x1) << 7); 186 frame[0x4] = (video_format_identification & 0x7F); 187 frame[0x5] = (pixel_repetition & 0xF); 188 frame[0x6] = (top_bar & 0xFF); 189 frame[0x7] = (top_bar >> 8); 190 frame[0x8] = (bottom_bar & 0xFF); 191 frame[0x9] = (bottom_bar >> 8); 192 frame[0xA] = (left_bar & 0xFF); 193 frame[0xB] = (left_bar >> 8); 194 frame[0xC] = (right_bar & 0xFF); 195 frame[0xD] = (right_bar >> 8); 196 197 r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame); 198 199 WREG32(offset+R600_HDMI_VIDEOINFOFRAME_0, 200 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 201 WREG32(offset+R600_HDMI_VIDEOINFOFRAME_1, 202 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 203 WREG32(offset+R600_HDMI_VIDEOINFOFRAME_2, 204 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 205 WREG32(offset+R600_HDMI_VIDEOINFOFRAME_3, 206 frame[0xC] | (frame[0xD] << 8)); 207} 208 209/* 210 * build a Audio Info Frame 211 */ 212static void r600_hdmi_audioinfoframe( 213 struct drm_encoder *encoder, 214 uint8_t channel_count, 215 uint8_t coding_type, 216 uint8_t sample_size, 217 uint8_t sample_frequency, 218 uint8_t format, 219 uint8_t channel_allocation, 220 uint8_t level_shift, 221 int downmix_inhibit 222) 223{ 224 struct drm_device *dev = encoder->dev; 225 struct radeon_device *rdev = dev->dev_private; 226 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; 227 228 uint8_t frame[11]; 229 230 frame[0x0] = 0; 231 frame[0x1] = (channel_count & 0x7) | ((coding_type & 0xF) << 4); 232 frame[0x2] = (sample_size & 0x3) | ((sample_frequency & 0x7) << 2); 233 frame[0x3] = format; 234 frame[0x4] = channel_allocation; 235 frame[0x5] = ((level_shift & 0xF) << 3) | ((downmix_inhibit & 0x1) << 7); 236 frame[0x6] = 0; 237 frame[0x7] = 0; 238 frame[0x8] = 0; 239 frame[0x9] = 0; 240 frame[0xA] = 0; 241 242 r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame); 243 244 WREG32(offset+R600_HDMI_AUDIOINFOFRAME_0, 245 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 246 WREG32(offset+R600_HDMI_AUDIOINFOFRAME_1, 247 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); 248} 249 250/* 251 * test if audio buffer is filled enough to start playing 252 */ 253static int r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) 254{ 255 struct drm_device *dev = encoder->dev; 256 struct radeon_device *rdev = dev->dev_private; 257 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; 258 259 return (RREG32(offset+R600_HDMI_STATUS) & 0x10) != 0; 260} 261 262/* 263 * have buffer status changed since last call? 264 */ 265int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) 266{ 267 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 268 int status, result; 269 270 if (!radeon_encoder->hdmi_offset) 271 return 0; 272 273 status = r600_hdmi_is_audio_buffer_filled(encoder); 274 result = radeon_encoder->hdmi_buffer_status != status; 275 radeon_encoder->hdmi_buffer_status = status; 276 277 return result; 278} 279 280void r600_hdmi_audio_workaround(struct drm_encoder *encoder) 281{ 282 struct drm_device *dev = encoder->dev; 283 struct radeon_device *rdev = dev->dev_private; 284 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 285 uint32_t offset = radeon_encoder->hdmi_offset; 286 287 if (!offset) 288 return; 289 290 if (!radeon_encoder->hdmi_audio_workaround || 291 r600_hdmi_is_audio_buffer_filled(encoder)) { 292 293 WREG32_P(offset+R600_HDMI_CNTL, 0x00000001, ~0x00001001); 294 295 } else { 296 WREG32_P(offset+R600_HDMI_CNTL, 0x00001001, ~0x00001001); 297 } 298} 299 300 301/* 302 * update the info frames with the data from the current display mode 303 */ 304void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) 305{ 306 struct drm_device *dev = encoder->dev; 307 struct radeon_device *rdev = dev->dev_private; 308 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; 309 310 if (ASIC_IS_DCE4(rdev)) 311 return; 312 313 if (!offset) 314 return; 315 316 r600_audio_set_clock(encoder, mode->clock); 317 318 WREG32(offset+R600_HDMI_UNKNOWN_0, 0x1000); 319 WREG32(offset+R600_HDMI_UNKNOWN_1, 0x0); 320 WREG32(offset+R600_HDMI_UNKNOWN_2, 0x1000); 321 322 r600_hdmi_update_ACR(encoder, mode->clock); 323 324 WREG32(offset+R600_HDMI_VIDEOCNTL, 0x13); 325 326 WREG32(offset+R600_HDMI_VERSION, 0x202); 327 328 r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0, 329 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 330 331 /* it's unknown what these bits do excatly, but it's indeed quite usefull for debugging */ 332 WREG32(offset+R600_HDMI_AUDIO_DEBUG_0, 0x00FFFFFF); 333 WREG32(offset+R600_HDMI_AUDIO_DEBUG_1, 0x007FFFFF); 334 WREG32(offset+R600_HDMI_AUDIO_DEBUG_2, 0x00000001); 335 WREG32(offset+R600_HDMI_AUDIO_DEBUG_3, 0x00000001); 336 337 r600_hdmi_audio_workaround(encoder); 338 339 /* audio packets per line, does anyone know how to calc this ? */ 340 WREG32_P(offset+R600_HDMI_CNTL, 0x00040000, ~0x001F0000); 341} 342 343/* 344 * update settings with current parameters from audio engine 345 */ 346void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) 347{ 348 struct drm_device *dev = encoder->dev; 349 struct radeon_device *rdev = dev->dev_private; 350 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; 351 352 int channels = r600_audio_channels(rdev); 353 int rate = r600_audio_rate(rdev); 354 int bps = r600_audio_bits_per_sample(rdev); 355 uint8_t status_bits = r600_audio_status_bits(rdev); 356 uint8_t category_code = r600_audio_category_code(rdev); 357 358 uint32_t iec; 359 360 if (!offset) 361 return; 362 363 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", 364 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", 365 channels, rate, bps); 366 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", 367 (int)status_bits, (int)category_code); 368 369 iec = 0; 370 if (status_bits & AUDIO_STATUS_PROFESSIONAL) 371 iec |= 1 << 0; 372 if (status_bits & AUDIO_STATUS_NONAUDIO) 373 iec |= 1 << 1; 374 if (status_bits & AUDIO_STATUS_COPYRIGHT) 375 iec |= 1 << 2; 376 if (status_bits & AUDIO_STATUS_EMPHASIS) 377 iec |= 1 << 3; 378 379 iec |= category_code << 8; 380 381 switch (rate) { 382 case 32000: iec |= 0x3 << 24; break; 383 case 44100: iec |= 0x0 << 24; break; 384 case 88200: iec |= 0x8 << 24; break; 385 case 176400: iec |= 0xc << 24; break; 386 case 48000: iec |= 0x2 << 24; break; 387 case 96000: iec |= 0xa << 24; break; 388 case 192000: iec |= 0xe << 24; break; 389 } 390 391 WREG32(offset+R600_HDMI_IEC60958_1, iec); 392 393 iec = 0; 394 switch (bps) { 395 case 16: iec |= 0x2; break; 396 case 20: iec |= 0x3; break; 397 case 24: iec |= 0xb; break; 398 } 399 if (status_bits & AUDIO_STATUS_V) 400 iec |= 0x5 << 16; 401 402 WREG32_P(offset+R600_HDMI_IEC60958_2, iec, ~0x5000f); 403 404 /* 0x021 or 0x031 sets the audio frame length */ 405 WREG32(offset+R600_HDMI_AUDIOCNTL, 0x31); 406 r600_hdmi_audioinfoframe(encoder, channels-1, 0, 0, 0, 0, 0, 0, 0); 407 408 r600_hdmi_audio_workaround(encoder); 409} 410 411static int r600_hdmi_find_free_block(struct drm_device *dev) 412{ 413 struct radeon_device *rdev = dev->dev_private; 414 struct drm_encoder *encoder; 415 struct radeon_encoder *radeon_encoder; 416 bool free_blocks[3] = { true, true, true }; 417 418 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 419 radeon_encoder = to_radeon_encoder(encoder); 420 switch (radeon_encoder->hdmi_offset) { 421 case R600_HDMI_BLOCK1: 422 free_blocks[0] = false; 423 break; 424 case R600_HDMI_BLOCK2: 425 free_blocks[1] = false; 426 break; 427 case R600_HDMI_BLOCK3: 428 free_blocks[2] = false; 429 break; 430 } 431 } 432 433 if (rdev->family == CHIP_RS600 || rdev->family == CHIP_RS690 || 434 rdev->family == CHIP_RS740) { 435 return free_blocks[0] ? R600_HDMI_BLOCK1 : 0; 436 } else if (rdev->family >= CHIP_R600) { 437 if (free_blocks[0]) 438 return R600_HDMI_BLOCK1; 439 else if (free_blocks[1]) 440 return R600_HDMI_BLOCK2; 441 } 442 return 0; 443} 444 445static void r600_hdmi_assign_block(struct drm_encoder *encoder) 446{ 447 struct drm_device *dev = encoder->dev; 448 struct radeon_device *rdev = dev->dev_private; 449 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 450 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 451 452 if (!dig) { 453 dev_err(rdev->dev, "Enabling HDMI on non-dig encoder\n"); 454 return; 455 } 456 457 if (ASIC_IS_DCE4(rdev)) { 458 /* TODO */ 459 } else if (ASIC_IS_DCE3(rdev)) { 460 radeon_encoder->hdmi_offset = dig->dig_encoder ? 461 R600_HDMI_BLOCK3 : R600_HDMI_BLOCK1; 462 if (ASIC_IS_DCE32(rdev)) 463 radeon_encoder->hdmi_config_offset = dig->dig_encoder ? 464 R600_HDMI_CONFIG2 : R600_HDMI_CONFIG1; 465 } else if (rdev->family >= CHIP_R600 || rdev->family == CHIP_RS600 || 466 rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 467 radeon_encoder->hdmi_offset = r600_hdmi_find_free_block(dev); 468 } 469} 470 471/* 472 * enable the HDMI engine 473 */ 474void r600_hdmi_enable(struct drm_encoder *encoder) 475{ 476 struct drm_device *dev = encoder->dev; 477 struct radeon_device *rdev = dev->dev_private; 478 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 479 uint32_t offset; 480 481 if (ASIC_IS_DCE4(rdev)) 482 return; 483 484 if (!radeon_encoder->hdmi_offset) { 485 r600_hdmi_assign_block(encoder); 486 if (!radeon_encoder->hdmi_offset) { 487 dev_warn(rdev->dev, "Could not find HDMI block for " 488 "0x%x encoder\n", radeon_encoder->encoder_id); 489 return; 490 } 491 } 492 493 offset = radeon_encoder->hdmi_offset; 494 if (ASIC_IS_DCE32(rdev) && !ASIC_IS_DCE4(rdev)) { 495 WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0x1, ~0x1); 496 } else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { 497 switch (radeon_encoder->encoder_id) { 498 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 499 WREG32_P(AVIVO_TMDSA_CNTL, 0x4, ~0x4); 500 WREG32(offset + R600_HDMI_ENABLE, 0x101); 501 break; 502 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 503 WREG32_P(AVIVO_LVTMA_CNTL, 0x4, ~0x4); 504 WREG32(offset + R600_HDMI_ENABLE, 0x105); 505 break; 506 default: 507 dev_err(rdev->dev, "Unknown HDMI output type\n"); 508 break; 509 } 510 } 511 512 if (rdev->irq.installed 513 && rdev->family != CHIP_RS600 514 && rdev->family != CHIP_RS690 515 && rdev->family != CHIP_RS740) { 516 517 /* if irq is available use it */ 518 rdev->irq.hdmi[offset == R600_HDMI_BLOCK1 ? 0 : 1] = true; 519 radeon_irq_set(rdev); 520 521 r600_audio_disable_polling(encoder); 522 } else { 523 /* if not fallback to polling */ 524 r600_audio_enable_polling(encoder); 525 } 526 527 DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n", 528 radeon_encoder->hdmi_offset, radeon_encoder->encoder_id); 529} 530 531/* 532 * disable the HDMI engine 533 */ 534void r600_hdmi_disable(struct drm_encoder *encoder) 535{ 536 struct drm_device *dev = encoder->dev; 537 struct radeon_device *rdev = dev->dev_private; 538 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 539 uint32_t offset; 540 541 if (ASIC_IS_DCE4(rdev)) 542 return; 543 544 offset = radeon_encoder->hdmi_offset; 545 if (!offset) { 546 dev_err(rdev->dev, "Disabling not enabled HDMI\n"); 547 return; 548 } 549 550 DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n", 551 offset, radeon_encoder->encoder_id); 552 553 /* disable irq */ 554 rdev->irq.hdmi[offset == R600_HDMI_BLOCK1 ? 0 : 1] = false; 555 radeon_irq_set(rdev); 556 557 /* disable polling */ 558 r600_audio_disable_polling(encoder); 559 560 if (ASIC_IS_DCE32(rdev) && !ASIC_IS_DCE4(rdev)) { 561 WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0, ~0x1); 562 } else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { 563 switch (radeon_encoder->encoder_id) { 564 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 565 WREG32_P(AVIVO_TMDSA_CNTL, 0, ~0x4); 566 WREG32(offset + R600_HDMI_ENABLE, 0); 567 break; 568 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 569 WREG32_P(AVIVO_LVTMA_CNTL, 0, ~0x4); 570 WREG32(offset + R600_HDMI_ENABLE, 0); 571 break; 572 default: 573 dev_err(rdev->dev, "Unknown HDMI output type\n"); 574 break; 575 } 576 } 577 578 radeon_encoder->hdmi_offset = 0; 579 radeon_encoder->hdmi_config_offset = 0; 580} 581