1/* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24#ifndef EVERGREEND_H 25#define EVERGREEND_H 26 27#define EVERGREEN_MAX_SH_GPRS 256 28#define EVERGREEN_MAX_TEMP_GPRS 16 29#define EVERGREEN_MAX_SH_THREADS 256 30#define EVERGREEN_MAX_SH_STACK_ENTRIES 4096 31#define EVERGREEN_MAX_FRC_EOV_CNT 16384 32#define EVERGREEN_MAX_BACKENDS 8 33#define EVERGREEN_MAX_BACKENDS_MASK 0xFF 34#define EVERGREEN_MAX_SIMDS 16 35#define EVERGREEN_MAX_SIMDS_MASK 0xFFFF 36#define EVERGREEN_MAX_PIPES 8 37#define EVERGREEN_MAX_PIPES_MASK 0xFF 38#define EVERGREEN_MAX_LDS_NUM 0xFFFF 39 40/* Registers */ 41 42#define RCU_IND_INDEX 0x100 43#define RCU_IND_DATA 0x104 44 45#define GRBM_GFX_INDEX 0x802C 46#define INSTANCE_INDEX(x) ((x) << 0) 47#define SE_INDEX(x) ((x) << 16) 48#define INSTANCE_BROADCAST_WRITES (1 << 30) 49#define SE_BROADCAST_WRITES (1 << 31) 50#define RLC_GFX_INDEX 0x3fC4 51#define CC_GC_SHADER_PIPE_CONFIG 0x8950 52#define WRITE_DIS (1 << 0) 53#define CC_RB_BACKEND_DISABLE 0x98F4 54#define BACKEND_DISABLE(x) ((x) << 16) 55#define GB_ADDR_CONFIG 0x98F8 56#define NUM_PIPES(x) ((x) << 0) 57#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 58#define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 59#define NUM_SHADER_ENGINES(x) ((x) << 12) 60#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 61#define NUM_GPUS(x) ((x) << 20) 62#define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 63#define ROW_SIZE(x) ((x) << 28) 64#define GB_BACKEND_MAP 0x98FC 65#define DMIF_ADDR_CONFIG 0xBD4 66#define HDP_ADDR_CONFIG 0x2F48 67 68#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 69#define GC_USER_RB_BACKEND_DISABLE 0x9B7C 70 71#define CGTS_SYS_TCC_DISABLE 0x3F90 72#define CGTS_TCC_DISABLE 0x9148 73#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 74#define CGTS_USER_TCC_DISABLE 0x914C 75 76#define CONFIG_MEMSIZE 0x5428 77 78#define CP_ME_CNTL 0x86D8 79#define CP_ME_HALT (1 << 28) 80#define CP_PFP_HALT (1 << 26) 81#define CP_ME_RAM_DATA 0xC160 82#define CP_ME_RAM_RADDR 0xC158 83#define CP_ME_RAM_WADDR 0xC15C 84#define CP_MEQ_THRESHOLDS 0x8764 85#define STQ_SPLIT(x) ((x) << 0) 86#define CP_PERFMON_CNTL 0x87FC 87#define CP_PFP_UCODE_ADDR 0xC150 88#define CP_PFP_UCODE_DATA 0xC154 89#define CP_QUEUE_THRESHOLDS 0x8760 90#define ROQ_IB1_START(x) ((x) << 0) 91#define ROQ_IB2_START(x) ((x) << 8) 92#define CP_RB_BASE 0xC100 93#define CP_RB_CNTL 0xC104 94#define RB_BUFSZ(x) ((x) << 0) 95#define RB_BLKSZ(x) ((x) << 8) 96#define RB_NO_UPDATE (1 << 27) 97#define RB_RPTR_WR_ENA (1 << 31) 98#define BUF_SWAP_32BIT (2 << 16) 99#define CP_RB_RPTR 0x8700 100#define CP_RB_RPTR_ADDR 0xC10C 101#define CP_RB_RPTR_ADDR_HI 0xC110 102#define CP_RB_RPTR_WR 0xC108 103#define CP_RB_WPTR 0xC114 104#define CP_RB_WPTR_ADDR 0xC118 105#define CP_RB_WPTR_ADDR_HI 0xC11C 106#define CP_RB_WPTR_DELAY 0x8704 107#define CP_SEM_WAIT_TIMER 0x85BC 108#define CP_DEBUG 0xC1FC 109 110 111#define GC_USER_SHADER_PIPE_CONFIG 0x8954 112#define INACTIVE_QD_PIPES(x) ((x) << 8) 113#define INACTIVE_QD_PIPES_MASK 0x0000FF00 114#define INACTIVE_SIMDS(x) ((x) << 16) 115#define INACTIVE_SIMDS_MASK 0x00FF0000 116 117#define GRBM_CNTL 0x8000 118#define GRBM_READ_TIMEOUT(x) ((x) << 0) 119#define GRBM_SOFT_RESET 0x8020 120#define SOFT_RESET_CP (1 << 0) 121#define SOFT_RESET_CB (1 << 1) 122#define SOFT_RESET_DB (1 << 3) 123#define SOFT_RESET_PA (1 << 5) 124#define SOFT_RESET_SC (1 << 6) 125#define SOFT_RESET_SPI (1 << 8) 126#define SOFT_RESET_SH (1 << 9) 127#define SOFT_RESET_SX (1 << 10) 128#define SOFT_RESET_TC (1 << 11) 129#define SOFT_RESET_TA (1 << 12) 130#define SOFT_RESET_VC (1 << 13) 131#define SOFT_RESET_VGT (1 << 14) 132 133#define GRBM_STATUS 0x8010 134#define CMDFIFO_AVAIL_MASK 0x0000000F 135#define SRBM_RQ_PENDING (1 << 5) 136#define CF_RQ_PENDING (1 << 7) 137#define PF_RQ_PENDING (1 << 8) 138#define GRBM_EE_BUSY (1 << 10) 139#define SX_CLEAN (1 << 11) 140#define DB_CLEAN (1 << 12) 141#define CB_CLEAN (1 << 13) 142#define TA_BUSY (1 << 14) 143#define VGT_BUSY_NO_DMA (1 << 16) 144#define VGT_BUSY (1 << 17) 145#define SX_BUSY (1 << 20) 146#define SH_BUSY (1 << 21) 147#define SPI_BUSY (1 << 22) 148#define SC_BUSY (1 << 24) 149#define PA_BUSY (1 << 25) 150#define DB_BUSY (1 << 26) 151#define CP_COHERENCY_BUSY (1 << 28) 152#define CP_BUSY (1 << 29) 153#define CB_BUSY (1 << 30) 154#define GUI_ACTIVE (1 << 31) 155#define GRBM_STATUS_SE0 0x8014 156#define GRBM_STATUS_SE1 0x8018 157#define SE_SX_CLEAN (1 << 0) 158#define SE_DB_CLEAN (1 << 1) 159#define SE_CB_CLEAN (1 << 2) 160#define SE_TA_BUSY (1 << 25) 161#define SE_SX_BUSY (1 << 26) 162#define SE_SPI_BUSY (1 << 27) 163#define SE_SH_BUSY (1 << 28) 164#define SE_SC_BUSY (1 << 29) 165#define SE_DB_BUSY (1 << 30) 166#define SE_CB_BUSY (1 << 31) 167 168#define CG_MULT_THERMAL_STATUS 0x740 169#define ASIC_T(x) ((x) << 16) 170#define ASIC_T_MASK 0x7FF0000 171#define ASIC_T_SHIFT 16 172 173#define HDP_HOST_PATH_CNTL 0x2C00 174#define HDP_NONSURFACE_BASE 0x2C04 175#define HDP_NONSURFACE_INFO 0x2C08 176#define HDP_NONSURFACE_SIZE 0x2C0C 177#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 178#define HDP_TILING_CONFIG 0x2F3C 179 180#define MC_SHARED_CHMAP 0x2004 181#define NOOFCHAN_SHIFT 12 182#define NOOFCHAN_MASK 0x00003000 183 184#define MC_ARB_RAMCFG 0x2760 185#define NOOFBANK_SHIFT 0 186#define NOOFBANK_MASK 0x00000003 187#define NOOFRANK_SHIFT 2 188#define NOOFRANK_MASK 0x00000004 189#define NOOFROWS_SHIFT 3 190#define NOOFROWS_MASK 0x00000038 191#define NOOFCOLS_SHIFT 6 192#define NOOFCOLS_MASK 0x000000C0 193#define CHANSIZE_SHIFT 8 194#define CHANSIZE_MASK 0x00000100 195#define BURSTLENGTH_SHIFT 9 196#define BURSTLENGTH_MASK 0x00000200 197#define CHANSIZE_OVERRIDE (1 << 11) 198#define MC_VM_AGP_TOP 0x2028 199#define MC_VM_AGP_BOT 0x202C 200#define MC_VM_AGP_BASE 0x2030 201#define MC_VM_FB_LOCATION 0x2024 202#define MC_VM_MB_L1_TLB0_CNTL 0x2234 203#define MC_VM_MB_L1_TLB1_CNTL 0x2238 204#define MC_VM_MB_L1_TLB2_CNTL 0x223C 205#define MC_VM_MB_L1_TLB3_CNTL 0x2240 206#define ENABLE_L1_TLB (1 << 0) 207#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 208#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 209#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 210#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 211#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 212#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 213#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 214#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 215#define MC_VM_MD_L1_TLB0_CNTL 0x2654 216#define MC_VM_MD_L1_TLB1_CNTL 0x2658 217#define MC_VM_MD_L1_TLB2_CNTL 0x265C 218#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 219#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 220#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 221 222#define PA_CL_ENHANCE 0x8A14 223#define CLIP_VTX_REORDER_ENA (1 << 0) 224#define NUM_CLIP_SEQ(x) ((x) << 1) 225#define PA_SC_AA_CONFIG 0x28C04 226#define MSAA_NUM_SAMPLES_SHIFT 0 227#define MSAA_NUM_SAMPLES_MASK 0x3 228#define PA_SC_CLIPRECT_RULE 0x2820C 229#define PA_SC_EDGERULE 0x28230 230#define PA_SC_FIFO_SIZE 0x8BCC 231#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 232#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 233#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 234#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 235#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 236#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 237#define PA_SC_LINE_STIPPLE 0x28A0C 238#define PA_SC_LINE_STIPPLE_STATE 0x8B10 239 240#define SCRATCH_REG0 0x8500 241#define SCRATCH_REG1 0x8504 242#define SCRATCH_REG2 0x8508 243#define SCRATCH_REG3 0x850C 244#define SCRATCH_REG4 0x8510 245#define SCRATCH_REG5 0x8514 246#define SCRATCH_REG6 0x8518 247#define SCRATCH_REG7 0x851C 248#define SCRATCH_UMSK 0x8540 249#define SCRATCH_ADDR 0x8544 250 251#define SMX_DC_CTL0 0xA020 252#define USE_HASH_FUNCTION (1 << 0) 253#define NUMBER_OF_SETS(x) ((x) << 1) 254#define FLUSH_ALL_ON_EVENT (1 << 10) 255#define STALL_ON_EVENT (1 << 11) 256#define SMX_EVENT_CTL 0xA02C 257#define ES_FLUSH_CTL(x) ((x) << 0) 258#define GS_FLUSH_CTL(x) ((x) << 3) 259#define ACK_FLUSH_CTL(x) ((x) << 6) 260#define SYNC_FLUSH_CTL (1 << 8) 261 262#define SPI_CONFIG_CNTL 0x9100 263#define GPR_WRITE_PRIORITY(x) ((x) << 0) 264#define SPI_CONFIG_CNTL_1 0x913C 265#define VTX_DONE_DELAY(x) ((x) << 0) 266#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 267#define SPI_INPUT_Z 0x286D8 268#define SPI_PS_IN_CONTROL_0 0x286CC 269#define NUM_INTERP(x) ((x)<<0) 270#define POSITION_ENA (1<<8) 271#define POSITION_CENTROID (1<<9) 272#define POSITION_ADDR(x) ((x)<<10) 273#define PARAM_GEN(x) ((x)<<15) 274#define PARAM_GEN_ADDR(x) ((x)<<19) 275#define BARYC_SAMPLE_CNTL(x) ((x)<<26) 276#define PERSP_GRADIENT_ENA (1<<28) 277#define LINEAR_GRADIENT_ENA (1<<29) 278#define POSITION_SAMPLE (1<<30) 279#define BARYC_AT_SAMPLE_ENA (1<<31) 280 281#define SQ_CONFIG 0x8C00 282#define VC_ENABLE (1 << 0) 283#define EXPORT_SRC_C (1 << 1) 284#define CS_PRIO(x) ((x) << 18) 285#define LS_PRIO(x) ((x) << 20) 286#define HS_PRIO(x) ((x) << 22) 287#define PS_PRIO(x) ((x) << 24) 288#define VS_PRIO(x) ((x) << 26) 289#define GS_PRIO(x) ((x) << 28) 290#define ES_PRIO(x) ((x) << 30) 291#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 292#define NUM_PS_GPRS(x) ((x) << 0) 293#define NUM_VS_GPRS(x) ((x) << 16) 294#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 295#define SQ_GPR_RESOURCE_MGMT_2 0x8C08 296#define NUM_GS_GPRS(x) ((x) << 0) 297#define NUM_ES_GPRS(x) ((x) << 16) 298#define SQ_GPR_RESOURCE_MGMT_3 0x8C0C 299#define NUM_HS_GPRS(x) ((x) << 0) 300#define NUM_LS_GPRS(x) ((x) << 16) 301#define SQ_THREAD_RESOURCE_MGMT 0x8C18 302#define NUM_PS_THREADS(x) ((x) << 0) 303#define NUM_VS_THREADS(x) ((x) << 8) 304#define NUM_GS_THREADS(x) ((x) << 16) 305#define NUM_ES_THREADS(x) ((x) << 24) 306#define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C 307#define NUM_HS_THREADS(x) ((x) << 0) 308#define NUM_LS_THREADS(x) ((x) << 8) 309#define SQ_STACK_RESOURCE_MGMT_1 0x8C20 310#define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 311#define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 312#define SQ_STACK_RESOURCE_MGMT_2 0x8C24 313#define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 314#define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 315#define SQ_STACK_RESOURCE_MGMT_3 0x8C28 316#define NUM_HS_STACK_ENTRIES(x) ((x) << 0) 317#define NUM_LS_STACK_ENTRIES(x) ((x) << 16) 318#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 319#define SQ_LDS_RESOURCE_MGMT 0x8E2C 320 321#define SQ_MS_FIFO_SIZES 0x8CF0 322#define CACHE_FIFO_SIZE(x) ((x) << 0) 323#define FETCH_FIFO_HIWATER(x) ((x) << 8) 324#define DONE_FIFO_HIWATER(x) ((x) << 16) 325#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 326 327#define SX_DEBUG_1 0x9058 328#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 329#define SX_EXPORT_BUFFER_SIZES 0x900C 330#define COLOR_BUFFER_SIZE(x) ((x) << 0) 331#define POSITION_BUFFER_SIZE(x) ((x) << 8) 332#define SMX_BUFFER_SIZE(x) ((x) << 16) 333#define SX_MISC 0x28350 334 335#define CB_PERF_CTR0_SEL_0 0x9A20 336#define CB_PERF_CTR0_SEL_1 0x9A24 337#define CB_PERF_CTR1_SEL_0 0x9A28 338#define CB_PERF_CTR1_SEL_1 0x9A2C 339#define CB_PERF_CTR2_SEL_0 0x9A30 340#define CB_PERF_CTR2_SEL_1 0x9A34 341#define CB_PERF_CTR3_SEL_0 0x9A38 342#define CB_PERF_CTR3_SEL_1 0x9A3C 343 344#define TA_CNTL_AUX 0x9508 345#define DISABLE_CUBE_WRAP (1 << 0) 346#define DISABLE_CUBE_ANISO (1 << 1) 347#define SYNC_GRADIENT (1 << 24) 348#define SYNC_WALKER (1 << 25) 349#define SYNC_ALIGNER (1 << 26) 350 351#define VGT_CACHE_INVALIDATION 0x88C4 352#define CACHE_INVALIDATION(x) ((x) << 0) 353#define VC_ONLY 0 354#define TC_ONLY 1 355#define VC_AND_TC 2 356#define AUTO_INVLD_EN(x) ((x) << 6) 357#define NO_AUTO 0 358#define ES_AUTO 1 359#define GS_AUTO 2 360#define ES_AND_GS_AUTO 3 361#define VGT_GS_VERTEX_REUSE 0x88D4 362#define VGT_NUM_INSTANCES 0x8974 363#define VGT_OUT_DEALLOC_CNTL 0x28C5C 364#define DEALLOC_DIST_MASK 0x0000007F 365#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 366#define VTX_REUSE_DEPTH_MASK 0x000000FF 367 368#define VM_CONTEXT0_CNTL 0x1410 369#define ENABLE_CONTEXT (1 << 0) 370#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 371#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 372#define VM_CONTEXT1_CNTL 0x1414 373#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 374#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 375#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 376#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 377#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 378#define REQUEST_TYPE(x) (((x) & 0xf) << 0) 379#define RESPONSE_TYPE_MASK 0x000000F0 380#define RESPONSE_TYPE_SHIFT 4 381#define VM_L2_CNTL 0x1400 382#define ENABLE_L2_CACHE (1 << 0) 383#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 384#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 385#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 386#define VM_L2_CNTL2 0x1404 387#define INVALIDATE_ALL_L1_TLBS (1 << 0) 388#define INVALIDATE_L2_CACHE (1 << 1) 389#define VM_L2_CNTL3 0x1408 390#define BANK_SELECT(x) ((x) << 0) 391#define CACHE_UPDATE_MODE(x) ((x) << 6) 392#define VM_L2_STATUS 0x140C 393#define L2_BUSY (1 << 0) 394 395#define WAIT_UNTIL 0x8040 396 397#define SRBM_STATUS 0x0E50 398#define SRBM_SOFT_RESET 0x0E60 399#define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 400#define SOFT_RESET_BIF (1 << 1) 401#define SOFT_RESET_CG (1 << 2) 402#define SOFT_RESET_DC (1 << 5) 403#define SOFT_RESET_GRBM (1 << 8) 404#define SOFT_RESET_HDP (1 << 9) 405#define SOFT_RESET_IH (1 << 10) 406#define SOFT_RESET_MC (1 << 11) 407#define SOFT_RESET_RLC (1 << 13) 408#define SOFT_RESET_ROM (1 << 14) 409#define SOFT_RESET_SEM (1 << 15) 410#define SOFT_RESET_VMC (1 << 17) 411#define SOFT_RESET_TST (1 << 21) 412#define SOFT_RESET_REGBB (1 << 22) 413#define SOFT_RESET_ORB (1 << 23) 414 415#define IH_RB_CNTL 0x3e00 416# define IH_RB_ENABLE (1 << 0) 417# define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 418# define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 419# define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 420# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 421# define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 422# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 423#define IH_RB_BASE 0x3e04 424#define IH_RB_RPTR 0x3e08 425#define IH_RB_WPTR 0x3e0c 426# define RB_OVERFLOW (1 << 0) 427# define WPTR_OFFSET_MASK 0x3fffc 428#define IH_RB_WPTR_ADDR_HI 0x3e10 429#define IH_RB_WPTR_ADDR_LO 0x3e14 430#define IH_CNTL 0x3e18 431# define ENABLE_INTR (1 << 0) 432# define IH_MC_SWAP(x) ((x) << 2) 433# define IH_MC_SWAP_NONE 0 434# define IH_MC_SWAP_16BIT 1 435# define IH_MC_SWAP_32BIT 2 436# define IH_MC_SWAP_64BIT 3 437# define RPTR_REARM (1 << 4) 438# define MC_WRREQ_CREDIT(x) ((x) << 15) 439# define MC_WR_CLEAN_CNT(x) ((x) << 20) 440 441#define CP_INT_CNTL 0xc124 442# define CNTX_BUSY_INT_ENABLE (1 << 19) 443# define CNTX_EMPTY_INT_ENABLE (1 << 20) 444# define SCRATCH_INT_ENABLE (1 << 25) 445# define TIME_STAMP_INT_ENABLE (1 << 26) 446# define IB2_INT_ENABLE (1 << 29) 447# define IB1_INT_ENABLE (1 << 30) 448# define RB_INT_ENABLE (1 << 31) 449#define CP_INT_STATUS 0xc128 450# define SCRATCH_INT_STAT (1 << 25) 451# define TIME_STAMP_INT_STAT (1 << 26) 452# define IB2_INT_STAT (1 << 29) 453# define IB1_INT_STAT (1 << 30) 454# define RB_INT_STAT (1 << 31) 455 456#define GRBM_INT_CNTL 0x8060 457# define RDERR_INT_ENABLE (1 << 0) 458# define GUI_IDLE_INT_ENABLE (1 << 19) 459 460/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 461#define CRTC_STATUS_FRAME_COUNT 0x6e98 462 463/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 464#define VLINE_STATUS 0x6bb8 465# define VLINE_OCCURRED (1 << 0) 466# define VLINE_ACK (1 << 4) 467# define VLINE_STAT (1 << 12) 468# define VLINE_INTERRUPT (1 << 16) 469# define VLINE_INTERRUPT_TYPE (1 << 17) 470/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 471#define VBLANK_STATUS 0x6bbc 472# define VBLANK_OCCURRED (1 << 0) 473# define VBLANK_ACK (1 << 4) 474# define VBLANK_STAT (1 << 12) 475# define VBLANK_INTERRUPT (1 << 16) 476# define VBLANK_INTERRUPT_TYPE (1 << 17) 477 478/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 479#define INT_MASK 0x6b40 480# define VBLANK_INT_MASK (1 << 0) 481# define VLINE_INT_MASK (1 << 4) 482 483#define DISP_INTERRUPT_STATUS 0x60f4 484# define LB_D1_VLINE_INTERRUPT (1 << 2) 485# define LB_D1_VBLANK_INTERRUPT (1 << 3) 486# define DC_HPD1_INTERRUPT (1 << 17) 487# define DC_HPD1_RX_INTERRUPT (1 << 18) 488# define DACA_AUTODETECT_INTERRUPT (1 << 22) 489# define DACB_AUTODETECT_INTERRUPT (1 << 23) 490# define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 491# define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 492#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 493# define LB_D2_VLINE_INTERRUPT (1 << 2) 494# define LB_D2_VBLANK_INTERRUPT (1 << 3) 495# define DC_HPD2_INTERRUPT (1 << 17) 496# define DC_HPD2_RX_INTERRUPT (1 << 18) 497# define DISP_TIMER_INTERRUPT (1 << 24) 498#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 499# define LB_D3_VLINE_INTERRUPT (1 << 2) 500# define LB_D3_VBLANK_INTERRUPT (1 << 3) 501# define DC_HPD3_INTERRUPT (1 << 17) 502# define DC_HPD3_RX_INTERRUPT (1 << 18) 503#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 504# define LB_D4_VLINE_INTERRUPT (1 << 2) 505# define LB_D4_VBLANK_INTERRUPT (1 << 3) 506# define DC_HPD4_INTERRUPT (1 << 17) 507# define DC_HPD4_RX_INTERRUPT (1 << 18) 508#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 509# define LB_D5_VLINE_INTERRUPT (1 << 2) 510# define LB_D5_VBLANK_INTERRUPT (1 << 3) 511# define DC_HPD5_INTERRUPT (1 << 17) 512# define DC_HPD5_RX_INTERRUPT (1 << 18) 513#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6050 514# define LB_D6_VLINE_INTERRUPT (1 << 2) 515# define LB_D6_VBLANK_INTERRUPT (1 << 3) 516# define DC_HPD6_INTERRUPT (1 << 17) 517# define DC_HPD6_RX_INTERRUPT (1 << 18) 518 519/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 520#define GRPH_INT_STATUS 0x6858 521# define GRPH_PFLIP_INT_OCCURRED (1 << 0) 522# define GRPH_PFLIP_INT_CLEAR (1 << 8) 523/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 524#define GRPH_INT_CONTROL 0x685c 525# define GRPH_PFLIP_INT_MASK (1 << 0) 526# define GRPH_PFLIP_INT_TYPE (1 << 8) 527 528#define DACA_AUTODETECT_INT_CONTROL 0x66c8 529#define DACB_AUTODETECT_INT_CONTROL 0x67c8 530 531#define DC_HPD1_INT_STATUS 0x601c 532#define DC_HPD2_INT_STATUS 0x6028 533#define DC_HPD3_INT_STATUS 0x6034 534#define DC_HPD4_INT_STATUS 0x6040 535#define DC_HPD5_INT_STATUS 0x604c 536#define DC_HPD6_INT_STATUS 0x6058 537# define DC_HPDx_INT_STATUS (1 << 0) 538# define DC_HPDx_SENSE (1 << 1) 539# define DC_HPDx_RX_INT_STATUS (1 << 8) 540 541#define DC_HPD1_INT_CONTROL 0x6020 542#define DC_HPD2_INT_CONTROL 0x602c 543#define DC_HPD3_INT_CONTROL 0x6038 544#define DC_HPD4_INT_CONTROL 0x6044 545#define DC_HPD5_INT_CONTROL 0x6050 546#define DC_HPD6_INT_CONTROL 0x605c 547# define DC_HPDx_INT_ACK (1 << 0) 548# define DC_HPDx_INT_POLARITY (1 << 8) 549# define DC_HPDx_INT_EN (1 << 16) 550# define DC_HPDx_RX_INT_ACK (1 << 20) 551# define DC_HPDx_RX_INT_EN (1 << 24) 552 553#define DC_HPD1_CONTROL 0x6024 554#define DC_HPD2_CONTROL 0x6030 555#define DC_HPD3_CONTROL 0x603c 556#define DC_HPD4_CONTROL 0x6048 557#define DC_HPD5_CONTROL 0x6054 558#define DC_HPD6_CONTROL 0x6060 559# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 560# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 561# define DC_HPDx_EN (1 << 28) 562 563/* 564 * PM4 565 */ 566#define PACKET_TYPE0 0 567#define PACKET_TYPE1 1 568#define PACKET_TYPE2 2 569#define PACKET_TYPE3 3 570 571#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 572#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 573#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 574#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 575#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 576 (((reg) >> 2) & 0xFFFF) | \ 577 ((n) & 0x3FFF) << 16) 578#define CP_PACKET2 0x80000000 579#define PACKET2_PAD_SHIFT 0 580#define PACKET2_PAD_MASK (0x3fffffff << 0) 581 582#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 583 584#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 585 (((op) & 0xFF) << 8) | \ 586 ((n) & 0x3FFF) << 16) 587 588/* Packet 3 types */ 589#define PACKET3_NOP 0x10 590#define PACKET3_SET_BASE 0x11 591#define PACKET3_CLEAR_STATE 0x12 592#define PACKET3_INDIRECT_BUFFER_SIZE 0x13 593#define PACKET3_DISPATCH_DIRECT 0x15 594#define PACKET3_DISPATCH_INDIRECT 0x16 595#define PACKET3_INDIRECT_BUFFER_END 0x17 596#define PACKET3_SET_PREDICATION 0x20 597#define PACKET3_REG_RMW 0x21 598#define PACKET3_COND_EXEC 0x22 599#define PACKET3_PRED_EXEC 0x23 600#define PACKET3_DRAW_INDIRECT 0x24 601#define PACKET3_DRAW_INDEX_INDIRECT 0x25 602#define PACKET3_INDEX_BASE 0x26 603#define PACKET3_DRAW_INDEX_2 0x27 604#define PACKET3_CONTEXT_CONTROL 0x28 605#define PACKET3_DRAW_INDEX_OFFSET 0x29 606#define PACKET3_INDEX_TYPE 0x2A 607#define PACKET3_DRAW_INDEX 0x2B 608#define PACKET3_DRAW_INDEX_AUTO 0x2D 609#define PACKET3_DRAW_INDEX_IMMD 0x2E 610#define PACKET3_NUM_INSTANCES 0x2F 611#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 612#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 613#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 614#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 615#define PACKET3_MEM_SEMAPHORE 0x39 616#define PACKET3_MPEG_INDEX 0x3A 617#define PACKET3_WAIT_REG_MEM 0x3C 618#define PACKET3_MEM_WRITE 0x3D 619#define PACKET3_INDIRECT_BUFFER 0x32 620#define PACKET3_SURFACE_SYNC 0x43 621# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 622# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 623# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 624# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 625# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 626# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 627# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 628# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 629# define PACKET3_DB_DEST_BASE_ENA (1 << 14) 630# define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 631# define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 632# define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 633# define PACKET3_CB11_DEST_BASE_ENA (1 << 17) 634# define PACKET3_FULL_CACHE_ENA (1 << 20) 635# define PACKET3_TC_ACTION_ENA (1 << 23) 636# define PACKET3_VC_ACTION_ENA (1 << 24) 637# define PACKET3_CB_ACTION_ENA (1 << 25) 638# define PACKET3_DB_ACTION_ENA (1 << 26) 639# define PACKET3_SH_ACTION_ENA (1 << 27) 640# define PACKET3_SMX_ACTION_ENA (1 << 28) 641#define PACKET3_ME_INITIALIZE 0x44 642#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 643#define PACKET3_COND_WRITE 0x45 644#define PACKET3_EVENT_WRITE 0x46 645#define PACKET3_EVENT_WRITE_EOP 0x47 646#define PACKET3_EVENT_WRITE_EOS 0x48 647#define PACKET3_PREAMBLE_CNTL 0x4A 648#define PACKET3_RB_OFFSET 0x4B 649#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 650#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 651#define PACKET3_ALU_PS_CONST_UPDATE 0x4E 652#define PACKET3_ALU_VS_CONST_UPDATE 0x4F 653#define PACKET3_ONE_REG_WRITE 0x57 654#define PACKET3_SET_CONFIG_REG 0x68 655#define PACKET3_SET_CONFIG_REG_START 0x00008000 656#define PACKET3_SET_CONFIG_REG_END 0x0000ac00 657#define PACKET3_SET_CONTEXT_REG 0x69 658#define PACKET3_SET_CONTEXT_REG_START 0x00028000 659#define PACKET3_SET_CONTEXT_REG_END 0x00029000 660#define PACKET3_SET_ALU_CONST 0x6A 661/* alu const buffers only; no reg file */ 662#define PACKET3_SET_BOOL_CONST 0x6B 663#define PACKET3_SET_BOOL_CONST_START 0x0003a500 664#define PACKET3_SET_BOOL_CONST_END 0x0003a518 665#define PACKET3_SET_LOOP_CONST 0x6C 666#define PACKET3_SET_LOOP_CONST_START 0x0003a200 667#define PACKET3_SET_LOOP_CONST_END 0x0003a500 668#define PACKET3_SET_RESOURCE 0x6D 669#define PACKET3_SET_RESOURCE_START 0x00030000 670#define PACKET3_SET_RESOURCE_END 0x00038000 671#define PACKET3_SET_SAMPLER 0x6E 672#define PACKET3_SET_SAMPLER_START 0x0003c000 673#define PACKET3_SET_SAMPLER_END 0x0003c600 674#define PACKET3_SET_CTL_CONST 0x6F 675#define PACKET3_SET_CTL_CONST_START 0x0003cff0 676#define PACKET3_SET_CTL_CONST_END 0x0003ff0c 677#define PACKET3_SET_RESOURCE_OFFSET 0x70 678#define PACKET3_SET_ALU_CONST_VS 0x71 679#define PACKET3_SET_ALU_CONST_DI 0x72 680#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 681#define PACKET3_SET_RESOURCE_INDIRECT 0x74 682#define PACKET3_SET_APPEND_CNT 0x75 683 684#define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c 685#define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30) 686#define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3) 687#define SQ_TEX_VTX_INVALID_TEXTURE 0x0 688#define SQ_TEX_VTX_INVALID_BUFFER 0x1 689#define SQ_TEX_VTX_VALID_TEXTURE 0x2 690#define SQ_TEX_VTX_VALID_BUFFER 0x3 691 692#define SQ_CONST_MEM_BASE 0x8df8 693 694#define SQ_ESGS_RING_SIZE 0x8c44 695#define SQ_GSVS_RING_SIZE 0x8c4c 696#define SQ_ESTMP_RING_SIZE 0x8c54 697#define SQ_GSTMP_RING_SIZE 0x8c5c 698#define SQ_VSTMP_RING_SIZE 0x8c64 699#define SQ_PSTMP_RING_SIZE 0x8c6c 700#define SQ_LSTMP_RING_SIZE 0x8e14 701#define SQ_HSTMP_RING_SIZE 0x8e1c 702#define VGT_TF_RING_SIZE 0x8988 703 704#define SQ_ESGS_RING_ITEMSIZE 0x28900 705#define SQ_GSVS_RING_ITEMSIZE 0x28904 706#define SQ_ESTMP_RING_ITEMSIZE 0x28908 707#define SQ_GSTMP_RING_ITEMSIZE 0x2890c 708#define SQ_VSTMP_RING_ITEMSIZE 0x28910 709#define SQ_PSTMP_RING_ITEMSIZE 0x28914 710#define SQ_LSTMP_RING_ITEMSIZE 0x28830 711#define SQ_HSTMP_RING_ITEMSIZE 0x28834 712 713#define SQ_GS_VERT_ITEMSIZE 0x2891c 714#define SQ_GS_VERT_ITEMSIZE_1 0x28920 715#define SQ_GS_VERT_ITEMSIZE_2 0x28924 716#define SQ_GS_VERT_ITEMSIZE_3 0x28928 717#define SQ_GSVS_RING_OFFSET_1 0x2892c 718#define SQ_GSVS_RING_OFFSET_2 0x28930 719#define SQ_GSVS_RING_OFFSET_3 0x28934 720 721#define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140 722#define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80 723 724#define SQ_ALU_CONST_CACHE_PS_0 0x28940 725#define SQ_ALU_CONST_CACHE_PS_1 0x28944 726#define SQ_ALU_CONST_CACHE_PS_2 0x28948 727#define SQ_ALU_CONST_CACHE_PS_3 0x2894c 728#define SQ_ALU_CONST_CACHE_PS_4 0x28950 729#define SQ_ALU_CONST_CACHE_PS_5 0x28954 730#define SQ_ALU_CONST_CACHE_PS_6 0x28958 731#define SQ_ALU_CONST_CACHE_PS_7 0x2895c 732#define SQ_ALU_CONST_CACHE_PS_8 0x28960 733#define SQ_ALU_CONST_CACHE_PS_9 0x28964 734#define SQ_ALU_CONST_CACHE_PS_10 0x28968 735#define SQ_ALU_CONST_CACHE_PS_11 0x2896c 736#define SQ_ALU_CONST_CACHE_PS_12 0x28970 737#define SQ_ALU_CONST_CACHE_PS_13 0x28974 738#define SQ_ALU_CONST_CACHE_PS_14 0x28978 739#define SQ_ALU_CONST_CACHE_PS_15 0x2897c 740#define SQ_ALU_CONST_CACHE_VS_0 0x28980 741#define SQ_ALU_CONST_CACHE_VS_1 0x28984 742#define SQ_ALU_CONST_CACHE_VS_2 0x28988 743#define SQ_ALU_CONST_CACHE_VS_3 0x2898c 744#define SQ_ALU_CONST_CACHE_VS_4 0x28990 745#define SQ_ALU_CONST_CACHE_VS_5 0x28994 746#define SQ_ALU_CONST_CACHE_VS_6 0x28998 747#define SQ_ALU_CONST_CACHE_VS_7 0x2899c 748#define SQ_ALU_CONST_CACHE_VS_8 0x289a0 749#define SQ_ALU_CONST_CACHE_VS_9 0x289a4 750#define SQ_ALU_CONST_CACHE_VS_10 0x289a8 751#define SQ_ALU_CONST_CACHE_VS_11 0x289ac 752#define SQ_ALU_CONST_CACHE_VS_12 0x289b0 753#define SQ_ALU_CONST_CACHE_VS_13 0x289b4 754#define SQ_ALU_CONST_CACHE_VS_14 0x289b8 755#define SQ_ALU_CONST_CACHE_VS_15 0x289bc 756#define SQ_ALU_CONST_CACHE_GS_0 0x289c0 757#define SQ_ALU_CONST_CACHE_GS_1 0x289c4 758#define SQ_ALU_CONST_CACHE_GS_2 0x289c8 759#define SQ_ALU_CONST_CACHE_GS_3 0x289cc 760#define SQ_ALU_CONST_CACHE_GS_4 0x289d0 761#define SQ_ALU_CONST_CACHE_GS_5 0x289d4 762#define SQ_ALU_CONST_CACHE_GS_6 0x289d8 763#define SQ_ALU_CONST_CACHE_GS_7 0x289dc 764#define SQ_ALU_CONST_CACHE_GS_8 0x289e0 765#define SQ_ALU_CONST_CACHE_GS_9 0x289e4 766#define SQ_ALU_CONST_CACHE_GS_10 0x289e8 767#define SQ_ALU_CONST_CACHE_GS_11 0x289ec 768#define SQ_ALU_CONST_CACHE_GS_12 0x289f0 769#define SQ_ALU_CONST_CACHE_GS_13 0x289f4 770#define SQ_ALU_CONST_CACHE_GS_14 0x289f8 771#define SQ_ALU_CONST_CACHE_GS_15 0x289fc 772#define SQ_ALU_CONST_CACHE_HS_0 0x28f00 773#define SQ_ALU_CONST_CACHE_HS_1 0x28f04 774#define SQ_ALU_CONST_CACHE_HS_2 0x28f08 775#define SQ_ALU_CONST_CACHE_HS_3 0x28f0c 776#define SQ_ALU_CONST_CACHE_HS_4 0x28f10 777#define SQ_ALU_CONST_CACHE_HS_5 0x28f14 778#define SQ_ALU_CONST_CACHE_HS_6 0x28f18 779#define SQ_ALU_CONST_CACHE_HS_7 0x28f1c 780#define SQ_ALU_CONST_CACHE_HS_8 0x28f20 781#define SQ_ALU_CONST_CACHE_HS_9 0x28f24 782#define SQ_ALU_CONST_CACHE_HS_10 0x28f28 783#define SQ_ALU_CONST_CACHE_HS_11 0x28f2c 784#define SQ_ALU_CONST_CACHE_HS_12 0x28f30 785#define SQ_ALU_CONST_CACHE_HS_13 0x28f34 786#define SQ_ALU_CONST_CACHE_HS_14 0x28f38 787#define SQ_ALU_CONST_CACHE_HS_15 0x28f3c 788#define SQ_ALU_CONST_CACHE_LS_0 0x28f40 789#define SQ_ALU_CONST_CACHE_LS_1 0x28f44 790#define SQ_ALU_CONST_CACHE_LS_2 0x28f48 791#define SQ_ALU_CONST_CACHE_LS_3 0x28f4c 792#define SQ_ALU_CONST_CACHE_LS_4 0x28f50 793#define SQ_ALU_CONST_CACHE_LS_5 0x28f54 794#define SQ_ALU_CONST_CACHE_LS_6 0x28f58 795#define SQ_ALU_CONST_CACHE_LS_7 0x28f5c 796#define SQ_ALU_CONST_CACHE_LS_8 0x28f60 797#define SQ_ALU_CONST_CACHE_LS_9 0x28f64 798#define SQ_ALU_CONST_CACHE_LS_10 0x28f68 799#define SQ_ALU_CONST_CACHE_LS_11 0x28f6c 800#define SQ_ALU_CONST_CACHE_LS_12 0x28f70 801#define SQ_ALU_CONST_CACHE_LS_13 0x28f74 802#define SQ_ALU_CONST_CACHE_LS_14 0x28f78 803#define SQ_ALU_CONST_CACHE_LS_15 0x28f7c 804 805#define DB_DEPTH_CONTROL 0x28800 806#define DB_DEPTH_VIEW 0x28008 807#define DB_HTILE_DATA_BASE 0x28014 808#define DB_Z_INFO 0x28040 809# define Z_ARRAY_MODE(x) ((x) << 4) 810#define DB_STENCIL_INFO 0x28044 811#define DB_Z_READ_BASE 0x28048 812#define DB_STENCIL_READ_BASE 0x2804c 813#define DB_Z_WRITE_BASE 0x28050 814#define DB_STENCIL_WRITE_BASE 0x28054 815#define DB_DEPTH_SIZE 0x28058 816 817#define SQ_PGM_START_PS 0x28840 818#define SQ_PGM_START_VS 0x2885c 819#define SQ_PGM_START_GS 0x28874 820#define SQ_PGM_START_ES 0x2888c 821#define SQ_PGM_START_FS 0x288a4 822#define SQ_PGM_START_HS 0x288b8 823#define SQ_PGM_START_LS 0x288d0 824 825#define VGT_STRMOUT_CONFIG 0x28b94 826#define VGT_STRMOUT_BUFFER_CONFIG 0x28b98 827 828#define CB_TARGET_MASK 0x28238 829#define CB_SHADER_MASK 0x2823c 830 831#define GDS_ADDR_BASE 0x28720 832 833#define CB_IMMED0_BASE 0x28b9c 834#define CB_IMMED1_BASE 0x28ba0 835#define CB_IMMED2_BASE 0x28ba4 836#define CB_IMMED3_BASE 0x28ba8 837#define CB_IMMED4_BASE 0x28bac 838#define CB_IMMED5_BASE 0x28bb0 839#define CB_IMMED6_BASE 0x28bb4 840#define CB_IMMED7_BASE 0x28bb8 841#define CB_IMMED8_BASE 0x28bbc 842#define CB_IMMED9_BASE 0x28bc0 843#define CB_IMMED10_BASE 0x28bc4 844#define CB_IMMED11_BASE 0x28bc8 845 846/* all 12 CB blocks have these regs */ 847#define CB_COLOR0_BASE 0x28c60 848#define CB_COLOR0_PITCH 0x28c64 849#define CB_COLOR0_SLICE 0x28c68 850#define CB_COLOR0_VIEW 0x28c6c 851#define CB_COLOR0_INFO 0x28c70 852# define CB_ARRAY_MODE(x) ((x) << 8) 853# define ARRAY_LINEAR_GENERAL 0 854# define ARRAY_LINEAR_ALIGNED 1 855# define ARRAY_1D_TILED_THIN1 2 856# define ARRAY_2D_TILED_THIN1 4 857#define CB_COLOR0_ATTRIB 0x28c74 858#define CB_COLOR0_DIM 0x28c78 859/* only CB0-7 blocks have these regs */ 860#define CB_COLOR0_CMASK 0x28c7c 861#define CB_COLOR0_CMASK_SLICE 0x28c80 862#define CB_COLOR0_FMASK 0x28c84 863#define CB_COLOR0_FMASK_SLICE 0x28c88 864#define CB_COLOR0_CLEAR_WORD0 0x28c8c 865#define CB_COLOR0_CLEAR_WORD1 0x28c90 866#define CB_COLOR0_CLEAR_WORD2 0x28c94 867#define CB_COLOR0_CLEAR_WORD3 0x28c98 868 869#define CB_COLOR1_BASE 0x28c9c 870#define CB_COLOR2_BASE 0x28cd8 871#define CB_COLOR3_BASE 0x28d14 872#define CB_COLOR4_BASE 0x28d50 873#define CB_COLOR5_BASE 0x28d8c 874#define CB_COLOR6_BASE 0x28dc8 875#define CB_COLOR7_BASE 0x28e04 876#define CB_COLOR8_BASE 0x28e40 877#define CB_COLOR9_BASE 0x28e5c 878#define CB_COLOR10_BASE 0x28e78 879#define CB_COLOR11_BASE 0x28e94 880 881#define CB_COLOR1_PITCH 0x28ca0 882#define CB_COLOR2_PITCH 0x28cdc 883#define CB_COLOR3_PITCH 0x28d18 884#define CB_COLOR4_PITCH 0x28d54 885#define CB_COLOR5_PITCH 0x28d90 886#define CB_COLOR6_PITCH 0x28dcc 887#define CB_COLOR7_PITCH 0x28e08 888#define CB_COLOR8_PITCH 0x28e44 889#define CB_COLOR9_PITCH 0x28e60 890#define CB_COLOR10_PITCH 0x28e7c 891#define CB_COLOR11_PITCH 0x28e98 892 893#define CB_COLOR1_SLICE 0x28ca4 894#define CB_COLOR2_SLICE 0x28ce0 895#define CB_COLOR3_SLICE 0x28d1c 896#define CB_COLOR4_SLICE 0x28d58 897#define CB_COLOR5_SLICE 0x28d94 898#define CB_COLOR6_SLICE 0x28dd0 899#define CB_COLOR7_SLICE 0x28e0c 900#define CB_COLOR8_SLICE 0x28e48 901#define CB_COLOR9_SLICE 0x28e64 902#define CB_COLOR10_SLICE 0x28e80 903#define CB_COLOR11_SLICE 0x28e9c 904 905#define CB_COLOR1_VIEW 0x28ca8 906#define CB_COLOR2_VIEW 0x28ce4 907#define CB_COLOR3_VIEW 0x28d20 908#define CB_COLOR4_VIEW 0x28d5c 909#define CB_COLOR5_VIEW 0x28d98 910#define CB_COLOR6_VIEW 0x28dd4 911#define CB_COLOR7_VIEW 0x28e10 912#define CB_COLOR8_VIEW 0x28e4c 913#define CB_COLOR9_VIEW 0x28e68 914#define CB_COLOR10_VIEW 0x28e84 915#define CB_COLOR11_VIEW 0x28ea0 916 917#define CB_COLOR1_INFO 0x28cac 918#define CB_COLOR2_INFO 0x28ce8 919#define CB_COLOR3_INFO 0x28d24 920#define CB_COLOR4_INFO 0x28d60 921#define CB_COLOR5_INFO 0x28d9c 922#define CB_COLOR6_INFO 0x28dd8 923#define CB_COLOR7_INFO 0x28e14 924#define CB_COLOR8_INFO 0x28e50 925#define CB_COLOR9_INFO 0x28e6c 926#define CB_COLOR10_INFO 0x28e88 927#define CB_COLOR11_INFO 0x28ea4 928 929#define CB_COLOR1_ATTRIB 0x28cb0 930#define CB_COLOR2_ATTRIB 0x28cec 931#define CB_COLOR3_ATTRIB 0x28d28 932#define CB_COLOR4_ATTRIB 0x28d64 933#define CB_COLOR5_ATTRIB 0x28da0 934#define CB_COLOR6_ATTRIB 0x28ddc 935#define CB_COLOR7_ATTRIB 0x28e18 936#define CB_COLOR8_ATTRIB 0x28e54 937#define CB_COLOR9_ATTRIB 0x28e70 938#define CB_COLOR10_ATTRIB 0x28e8c 939#define CB_COLOR11_ATTRIB 0x28ea8 940 941#define CB_COLOR1_DIM 0x28cb4 942#define CB_COLOR2_DIM 0x28cf0 943#define CB_COLOR3_DIM 0x28d2c 944#define CB_COLOR4_DIM 0x28d68 945#define CB_COLOR5_DIM 0x28da4 946#define CB_COLOR6_DIM 0x28de0 947#define CB_COLOR7_DIM 0x28e1c 948#define CB_COLOR8_DIM 0x28e58 949#define CB_COLOR9_DIM 0x28e74 950#define CB_COLOR10_DIM 0x28e90 951#define CB_COLOR11_DIM 0x28eac 952 953#define CB_COLOR1_CMASK 0x28cb8 954#define CB_COLOR2_CMASK 0x28cf4 955#define CB_COLOR3_CMASK 0x28d30 956#define CB_COLOR4_CMASK 0x28d6c 957#define CB_COLOR5_CMASK 0x28da8 958#define CB_COLOR6_CMASK 0x28de4 959#define CB_COLOR7_CMASK 0x28e20 960 961#define CB_COLOR1_CMASK_SLICE 0x28cbc 962#define CB_COLOR2_CMASK_SLICE 0x28cf8 963#define CB_COLOR3_CMASK_SLICE 0x28d34 964#define CB_COLOR4_CMASK_SLICE 0x28d70 965#define CB_COLOR5_CMASK_SLICE 0x28dac 966#define CB_COLOR6_CMASK_SLICE 0x28de8 967#define CB_COLOR7_CMASK_SLICE 0x28e24 968 969#define CB_COLOR1_FMASK 0x28cc0 970#define CB_COLOR2_FMASK 0x28cfc 971#define CB_COLOR3_FMASK 0x28d38 972#define CB_COLOR4_FMASK 0x28d74 973#define CB_COLOR5_FMASK 0x28db0 974#define CB_COLOR6_FMASK 0x28dec 975#define CB_COLOR7_FMASK 0x28e28 976 977#define CB_COLOR1_FMASK_SLICE 0x28cc4 978#define CB_COLOR2_FMASK_SLICE 0x28d00 979#define CB_COLOR3_FMASK_SLICE 0x28d3c 980#define CB_COLOR4_FMASK_SLICE 0x28d78 981#define CB_COLOR5_FMASK_SLICE 0x28db4 982#define CB_COLOR6_FMASK_SLICE 0x28df0 983#define CB_COLOR7_FMASK_SLICE 0x28e2c 984 985#define CB_COLOR1_CLEAR_WORD0 0x28cc8 986#define CB_COLOR2_CLEAR_WORD0 0x28d04 987#define CB_COLOR3_CLEAR_WORD0 0x28d40 988#define CB_COLOR4_CLEAR_WORD0 0x28d7c 989#define CB_COLOR5_CLEAR_WORD0 0x28db8 990#define CB_COLOR6_CLEAR_WORD0 0x28df4 991#define CB_COLOR7_CLEAR_WORD0 0x28e30 992 993#define CB_COLOR1_CLEAR_WORD1 0x28ccc 994#define CB_COLOR2_CLEAR_WORD1 0x28d08 995#define CB_COLOR3_CLEAR_WORD1 0x28d44 996#define CB_COLOR4_CLEAR_WORD1 0x28d80 997#define CB_COLOR5_CLEAR_WORD1 0x28dbc 998#define CB_COLOR6_CLEAR_WORD1 0x28df8 999#define CB_COLOR7_CLEAR_WORD1 0x28e34 1000 1001#define CB_COLOR1_CLEAR_WORD2 0x28cd0 1002#define CB_COLOR2_CLEAR_WORD2 0x28d0c 1003#define CB_COLOR3_CLEAR_WORD2 0x28d48 1004#define CB_COLOR4_CLEAR_WORD2 0x28d84 1005#define CB_COLOR5_CLEAR_WORD2 0x28dc0 1006#define CB_COLOR6_CLEAR_WORD2 0x28dfc 1007#define CB_COLOR7_CLEAR_WORD2 0x28e38 1008 1009#define CB_COLOR1_CLEAR_WORD3 0x28cd4 1010#define CB_COLOR2_CLEAR_WORD3 0x28d10 1011#define CB_COLOR3_CLEAR_WORD3 0x28d4c 1012#define CB_COLOR4_CLEAR_WORD3 0x28d88 1013#define CB_COLOR5_CLEAR_WORD3 0x28dc4 1014#define CB_COLOR6_CLEAR_WORD3 0x28e00 1015#define CB_COLOR7_CLEAR_WORD3 0x28e3c 1016 1017#define SQ_TEX_RESOURCE_WORD0_0 0x30000 1018#define SQ_TEX_RESOURCE_WORD1_0 0x30004 1019# define TEX_ARRAY_MODE(x) ((x) << 28) 1020#define SQ_TEX_RESOURCE_WORD2_0 0x30008 1021#define SQ_TEX_RESOURCE_WORD3_0 0x3000C 1022#define SQ_TEX_RESOURCE_WORD4_0 0x30010 1023#define SQ_TEX_RESOURCE_WORD5_0 0x30014 1024#define SQ_TEX_RESOURCE_WORD6_0 0x30018 1025#define SQ_TEX_RESOURCE_WORD7_0 0x3001c 1026 1027 1028#endif 1029