1/* 2 * Copyright (C) 2007 Ben Skeggs. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27#include "drmP.h" 28#include "drm.h" 29#include "nouveau_drv.h" 30#include "nouveau_grctx.h" 31 32struct nouveau_channel * 33nv40_graph_channel(struct drm_device *dev) 34{ 35 struct drm_nouveau_private *dev_priv = dev->dev_private; 36 uint32_t inst; 37 int i; 38 39 inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR); 40 if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED)) 41 return NULL; 42 inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4; 43 44 for (i = 0; i < dev_priv->engine.fifo.channels; i++) { 45 struct nouveau_channel *chan = dev_priv->fifos[i]; 46 47 if (chan && chan->ramin_grctx && 48 chan->ramin_grctx->instance == inst) 49 return chan; 50 } 51 52 return NULL; 53} 54 55int 56nv40_graph_create_context(struct nouveau_channel *chan) 57{ 58 struct drm_device *dev = chan->dev; 59 struct drm_nouveau_private *dev_priv = dev->dev_private; 60 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 61 struct nouveau_grctx ctx = {}; 62 int ret; 63 64 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size, 65 16, NVOBJ_FLAG_ZERO_ALLOC, 66 &chan->ramin_grctx); 67 if (ret) 68 return ret; 69 70 /* Initialise default context values */ 71 ctx.dev = chan->dev; 72 ctx.mode = NOUVEAU_GRCTX_VALS; 73 ctx.data = chan->ramin_grctx->gpuobj; 74 nv40_grctx_init(&ctx); 75 76 nv_wo32(dev, chan->ramin_grctx->gpuobj, 0, 77 chan->ramin_grctx->gpuobj->im_pramin->start); 78 return 0; 79} 80 81void 82nv40_graph_destroy_context(struct nouveau_channel *chan) 83{ 84 nouveau_gpuobj_ref_del(chan->dev, &chan->ramin_grctx); 85} 86 87static int 88nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save) 89{ 90 uint32_t old_cp, tv = 1000, tmp; 91 int i; 92 93 old_cp = nv_rd32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER); 94 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); 95 96 tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0310); 97 tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE : 98 NV40_PGRAPH_CTXCTL_0310_XFER_LOAD; 99 nv_wr32(dev, NV40_PGRAPH_CTXCTL_0310, tmp); 100 101 tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0304); 102 tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX; 103 nv_wr32(dev, NV40_PGRAPH_CTXCTL_0304, tmp); 104 105 nouveau_wait_for_idle(dev); 106 107 for (i = 0; i < tv; i++) { 108 if (nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C) == 0) 109 break; 110 } 111 112 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp); 113 114 if (i == tv) { 115 uint32_t ucstat = nv_rd32(dev, NV40_PGRAPH_CTXCTL_UCODE_STAT); 116 NV_ERROR(dev, "Failed: Instance=0x%08x Save=%d\n", inst, save); 117 NV_ERROR(dev, "IP: 0x%02x, Opcode: 0x%08x\n", 118 ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT, 119 ucstat & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK); 120 NV_ERROR(dev, "0x40030C = 0x%08x\n", 121 nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C)); 122 return -EBUSY; 123 } 124 125 return 0; 126} 127 128/* Restore the context for a specific channel into PGRAPH */ 129int 130nv40_graph_load_context(struct nouveau_channel *chan) 131{ 132 struct drm_device *dev = chan->dev; 133 uint32_t inst; 134 int ret; 135 136 if (!chan->ramin_grctx) 137 return -EINVAL; 138 inst = chan->ramin_grctx->instance >> 4; 139 140 ret = nv40_graph_transfer_context(dev, inst, 0); 141 if (ret) 142 return ret; 143 144 /* 0x40032C, no idea of it's exact function. Could simply be a 145 * record of the currently active PGRAPH context. It's currently 146 * unknown as to what bit 24 does. The nv ddx has it set, so we will 147 * set it here too. 148 */ 149 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); 150 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 151 (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) | 152 NV40_PGRAPH_CTXCTL_CUR_LOADED); 153 /* 0x32E0 records the instance address of the active FIFO's PGRAPH 154 * context. If at any time this doesn't match 0x40032C, you will 155 * recieve PGRAPH_INTR_CONTEXT_SWITCH 156 */ 157 nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst); 158 return 0; 159} 160 161int 162nv40_graph_unload_context(struct drm_device *dev) 163{ 164 uint32_t inst; 165 int ret; 166 167 inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR); 168 if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED)) 169 return 0; 170 inst &= NV40_PGRAPH_CTXCTL_CUR_INSTANCE; 171 172 ret = nv40_graph_transfer_context(dev, inst, 1); 173 174 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, inst); 175 return ret; 176} 177 178void 179nv40_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr, 180 uint32_t size, uint32_t pitch) 181{ 182 struct drm_nouveau_private *dev_priv = dev->dev_private; 183 uint32_t limit = max(1u, addr + size) - 1; 184 185 if (pitch) 186 addr |= 1; 187 188 switch (dev_priv->chipset) { 189 case 0x44: 190 case 0x4a: 191 case 0x4e: 192 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch); 193 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit); 194 nv_wr32(dev, NV20_PGRAPH_TILE(i), addr); 195 break; 196 197 case 0x46: 198 case 0x47: 199 case 0x49: 200 case 0x4b: 201 nv_wr32(dev, NV47_PGRAPH_TSIZE(i), pitch); 202 nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), limit); 203 nv_wr32(dev, NV47_PGRAPH_TILE(i), addr); 204 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch); 205 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit); 206 nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr); 207 break; 208 209 default: 210 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch); 211 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit); 212 nv_wr32(dev, NV20_PGRAPH_TILE(i), addr); 213 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch); 214 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit); 215 nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr); 216 break; 217 } 218} 219 220/* 221 * G70 0x47 222 * G71 0x49 223 * NV45 0x48 224 * G72[M] 0x46 225 * G73 0x4b 226 * C51_G7X 0x4c 227 * C51 0x4e 228 */ 229int 230nv40_graph_init(struct drm_device *dev) 231{ 232 struct drm_nouveau_private *dev_priv = 233 (struct drm_nouveau_private *)dev->dev_private; 234 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; 235 struct nouveau_grctx ctx = {}; 236 uint32_t vramsz, *cp; 237 int i, j; 238 239 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & 240 ~NV_PMC_ENABLE_PGRAPH); 241 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | 242 NV_PMC_ENABLE_PGRAPH); 243 244 cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL); 245 if (!cp) 246 return -ENOMEM; 247 248 ctx.dev = dev; 249 ctx.mode = NOUVEAU_GRCTX_PROG; 250 ctx.data = cp; 251 ctx.ctxprog_max = 256; 252 nv40_grctx_init(&ctx); 253 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4; 254 255 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0); 256 for (i = 0; i < ctx.ctxprog_len; i++) 257 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]); 258 259 kfree(cp); 260 261 /* No context present currently */ 262 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); 263 264 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF); 265 nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF); 266 267 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); 268 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000); 269 nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0); 270 nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055); 271 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000); 272 nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f); 273 274 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100); 275 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF); 276 277 j = nv_rd32(dev, 0x1540) & 0xff; 278 if (j) { 279 for (i = 0; !(j & 1); j >>= 1, i++) 280 ; 281 nv_wr32(dev, 0x405000, i); 282 } 283 284 if (dev_priv->chipset == 0x40) { 285 nv_wr32(dev, 0x4009b0, 0x83280fff); 286 nv_wr32(dev, 0x4009b4, 0x000000a0); 287 } else { 288 nv_wr32(dev, 0x400820, 0x83280eff); 289 nv_wr32(dev, 0x400824, 0x000000a0); 290 } 291 292 switch (dev_priv->chipset) { 293 case 0x40: 294 case 0x45: 295 nv_wr32(dev, 0x4009b8, 0x0078e366); 296 nv_wr32(dev, 0x4009bc, 0x0000014c); 297 break; 298 case 0x41: 299 case 0x42: /* pciid also 0x00Cx */ 300 nv_wr32(dev, 0x400828, 0x007596ff); 301 nv_wr32(dev, 0x40082c, 0x00000108); 302 break; 303 case 0x43: 304 nv_wr32(dev, 0x400828, 0x0072cb77); 305 nv_wr32(dev, 0x40082c, 0x00000108); 306 break; 307 case 0x44: 308 case 0x46: /* G72 */ 309 case 0x4a: 310 case 0x4c: /* G7x-based C51 */ 311 case 0x4e: 312 nv_wr32(dev, 0x400860, 0); 313 nv_wr32(dev, 0x400864, 0); 314 break; 315 case 0x47: /* G70 */ 316 case 0x49: /* G71 */ 317 case 0x4b: /* G73 */ 318 nv_wr32(dev, 0x400828, 0x07830610); 319 nv_wr32(dev, 0x40082c, 0x0000016A); 320 break; 321 default: 322 break; 323 } 324 325 nv_wr32(dev, 0x400b38, 0x2ffff800); 326 nv_wr32(dev, 0x400b3c, 0x00006000); 327 328 /* Tiling related stuff. */ 329 switch (dev_priv->chipset) { 330 case 0x44: 331 case 0x4a: 332 nv_wr32(dev, 0x400bc4, 0x1003d888); 333 nv_wr32(dev, 0x400bbc, 0xb7a7b500); 334 break; 335 case 0x46: 336 nv_wr32(dev, 0x400bc4, 0x0000e024); 337 nv_wr32(dev, 0x400bbc, 0xb7a7b520); 338 break; 339 case 0x4c: 340 case 0x4e: 341 case 0x67: 342 nv_wr32(dev, 0x400bc4, 0x1003d888); 343 nv_wr32(dev, 0x400bbc, 0xb7a7b540); 344 break; 345 default: 346 break; 347 } 348 349 /* Turn all the tiling regions off. */ 350 for (i = 0; i < pfb->num_tiles; i++) 351 nv40_graph_set_region_tiling(dev, i, 0, 0, 0); 352 353 /* begin RAM config */ 354 vramsz = pci_resource_len(dev->pdev, 0) - 1; 355 switch (dev_priv->chipset) { 356 case 0x40: 357 nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0)); 358 nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1)); 359 nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0)); 360 nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1)); 361 nv_wr32(dev, 0x400820, 0); 362 nv_wr32(dev, 0x400824, 0); 363 nv_wr32(dev, 0x400864, vramsz); 364 nv_wr32(dev, 0x400868, vramsz); 365 break; 366 default: 367 switch (dev_priv->chipset) { 368 case 0x46: 369 case 0x47: 370 case 0x49: 371 case 0x4b: 372 nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0)); 373 nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1)); 374 break; 375 default: 376 nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0)); 377 nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1)); 378 break; 379 } 380 nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0)); 381 nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1)); 382 nv_wr32(dev, 0x400840, 0); 383 nv_wr32(dev, 0x400844, 0); 384 nv_wr32(dev, 0x4008A0, vramsz); 385 nv_wr32(dev, 0x4008A4, vramsz); 386 break; 387 } 388 389 return 0; 390} 391 392void nv40_graph_takedown(struct drm_device *dev) 393{ 394} 395 396struct nouveau_pgraph_object_class nv40_graph_grclass[] = { 397 { 0x0030, false, NULL }, /* null */ 398 { 0x0039, false, NULL }, /* m2mf */ 399 { 0x004a, false, NULL }, /* gdirect */ 400 { 0x009f, false, NULL }, /* imageblit (nv12) */ 401 { 0x008a, false, NULL }, /* ifc */ 402 { 0x0089, false, NULL }, /* sifm */ 403 { 0x3089, false, NULL }, /* sifm (nv40) */ 404 { 0x0062, false, NULL }, /* surf2d */ 405 { 0x3062, false, NULL }, /* surf2d (nv40) */ 406 { 0x0043, false, NULL }, /* rop */ 407 { 0x0012, false, NULL }, /* beta1 */ 408 { 0x0072, false, NULL }, /* beta4 */ 409 { 0x0019, false, NULL }, /* cliprect */ 410 { 0x0044, false, NULL }, /* pattern */ 411 { 0x309e, false, NULL }, /* swzsurf */ 412 { 0x4097, false, NULL }, /* curie (nv40) */ 413 { 0x4497, false, NULL }, /* curie (nv44) */ 414 {} 415}; 416