1/* 2 * Copyright (C) 2009 Francisco Jerez. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27#include "drmP.h" 28#include "drm_crtc_helper.h" 29#include "nouveau_drv.h" 30#include "nouveau_encoder.h" 31#include "nouveau_connector.h" 32#include "nouveau_crtc.h" 33#include "nouveau_hw.h" 34#include "nv17_tv.h" 35 36static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder) 37{ 38 struct drm_device *dev = encoder->dev; 39 struct drm_nouveau_private *dev_priv = dev->dev_private; 40 struct nouveau_gpio_engine *gpio = &dev_priv->engine.gpio; 41 uint32_t testval, regoffset = nv04_dac_output_offset(encoder); 42 uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end, 43 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c; 44 uint32_t sample = 0; 45 int head; 46 47#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20) 48 testval = RGB_TEST_DATA(0x82, 0xeb, 0x82); 49 if (dev_priv->vbios.tvdactestval) 50 testval = dev_priv->vbios.tvdactestval; 51 52 dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset); 53 head = (dacclk & 0x100) >> 8; 54 55 /* Save the previous state. */ 56 gpio1 = gpio->get(dev, DCB_GPIO_TVDAC1); 57 gpio0 = gpio->get(dev, DCB_GPIO_TVDAC0); 58 fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL); 59 fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START); 60 fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END); 61 fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); 62 test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset); 63 ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c); 64 ctv_14 = NVReadRAMDAC(dev, head, 0x680c14); 65 ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c); 66 67 /* Prepare the DAC for load detection. */ 68 gpio->set(dev, DCB_GPIO_TVDAC1, true); 69 gpio->set(dev, DCB_GPIO_TVDAC0, true); 70 71 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343); 72 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047); 73 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183); 74 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, 75 NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | 76 NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 | 77 NV_PRAMDAC_FP_TG_CONTROL_READ_PROG | 78 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | 79 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS); 80 81 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0); 82 83 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, 84 (dacclk & ~0xff) | 0x22); 85 msleep(1); 86 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, 87 (dacclk & ~0xff) | 0x21); 88 89 NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20); 90 NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16); 91 92 /* Sample pin 0x4 (usually S-video luma). */ 93 NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff); 94 msleep(20); 95 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset) 96 & 0x4 << 28; 97 98 /* Sample the remaining pins. */ 99 NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff); 100 msleep(20); 101 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset) 102 & 0xa << 28; 103 104 /* Restore the previous state. */ 105 NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c); 106 NVWriteRAMDAC(dev, head, 0x680c14, ctv_14); 107 NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c); 108 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk); 109 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl); 110 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control); 111 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end); 112 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start); 113 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal); 114 gpio->set(dev, DCB_GPIO_TVDAC1, gpio1); 115 gpio->set(dev, DCB_GPIO_TVDAC0, gpio0); 116 117 return sample; 118} 119 120static bool 121get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask) 122{ 123 /* Zotac FX5200 */ 124 if (nv_match_device(dev, 0x0322, 0x19da, 0x1035) || 125 nv_match_device(dev, 0x0322, 0x19da, 0x2035)) { 126 *pin_mask = 0xc; 127 return false; 128 } 129 130 /* MSI nForce2 IGP */ 131 if (nv_match_device(dev, 0x01f0, 0x1462, 0x5710)) { 132 *pin_mask = 0xc; 133 return false; 134 } 135 136 return true; 137} 138 139static enum drm_connector_status 140nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector) 141{ 142 struct drm_device *dev = encoder->dev; 143 struct drm_nouveau_private *dev_priv = dev->dev_private; 144 struct drm_mode_config *conf = &dev->mode_config; 145 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 146 struct dcb_entry *dcb = tv_enc->base.dcb; 147 bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask); 148 149 if (nv04_dac_in_use(encoder)) 150 return connector_status_disconnected; 151 152 if (reliable) { 153 if (dev_priv->chipset == 0x42 || 154 dev_priv->chipset == 0x43) 155 tv_enc->pin_mask = 156 nv42_tv_sample_load(encoder) >> 28 & 0xe; 157 else 158 tv_enc->pin_mask = 159 nv17_dac_sample_load(encoder) >> 28 & 0xe; 160 } 161 162 switch (tv_enc->pin_mask) { 163 case 0x2: 164 case 0x4: 165 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Composite; 166 break; 167 case 0xc: 168 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO; 169 break; 170 case 0xe: 171 if (dcb->tvconf.has_component_output) 172 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component; 173 else 174 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART; 175 break; 176 default: 177 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 178 break; 179 } 180 181 drm_connector_property_set_value(connector, 182 conf->tv_subconnector_property, 183 tv_enc->subconnector); 184 185 if (!reliable) { 186 return connector_status_unknown; 187 } else if (tv_enc->subconnector) { 188 NV_INFO(dev, "Load detected on output %c\n", 189 '@' + ffs(dcb->or)); 190 return connector_status_connected; 191 } else { 192 return connector_status_disconnected; 193 } 194} 195 196static const struct { 197 int hdisplay; 198 int vdisplay; 199} modes[] = { 200 { 640, 400 }, 201 { 640, 480 }, 202 { 720, 480 }, 203 { 720, 576 }, 204 { 800, 600 }, 205 { 1024, 768 }, 206 { 1280, 720 }, 207 { 1280, 1024 }, 208 { 1920, 1080 } 209}; 210 211static int nv17_tv_get_modes(struct drm_encoder *encoder, 212 struct drm_connector *connector) 213{ 214 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 215 struct drm_display_mode *mode; 216 struct drm_display_mode *output_mode; 217 int n = 0; 218 int i; 219 220 if (tv_norm->kind != CTV_ENC_MODE) { 221 struct drm_display_mode *tv_mode; 222 223 for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) { 224 mode = drm_mode_duplicate(encoder->dev, tv_mode); 225 226 mode->clock = tv_norm->tv_enc_mode.vrefresh * 227 mode->htotal / 1000 * 228 mode->vtotal / 1000; 229 230 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 231 mode->clock *= 2; 232 233 if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay && 234 mode->vdisplay == tv_norm->tv_enc_mode.vdisplay) 235 mode->type |= DRM_MODE_TYPE_PREFERRED; 236 237 drm_mode_probed_add(connector, mode); 238 n++; 239 } 240 return n; 241 } 242 243 /* tv_norm->kind == CTV_ENC_MODE */ 244 output_mode = &tv_norm->ctv_enc_mode.mode; 245 for (i = 0; i < ARRAY_SIZE(modes); i++) { 246 if (modes[i].hdisplay > output_mode->hdisplay || 247 modes[i].vdisplay > output_mode->vdisplay) 248 continue; 249 250 if (modes[i].hdisplay == output_mode->hdisplay && 251 modes[i].vdisplay == output_mode->vdisplay) { 252 mode = drm_mode_duplicate(encoder->dev, output_mode); 253 mode->type |= DRM_MODE_TYPE_PREFERRED; 254 } else { 255 mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay, 256 modes[i].vdisplay, 60, false, 257 output_mode->flags & DRM_MODE_FLAG_INTERLACE, 258 false); 259 } 260 261 /* CVT modes are sometimes unsuitable... */ 262 if (output_mode->hdisplay <= 720 263 || output_mode->hdisplay >= 1920) { 264 mode->htotal = output_mode->htotal; 265 mode->hsync_start = (mode->hdisplay + (mode->htotal 266 - mode->hdisplay) * 9 / 10) & ~7; 267 mode->hsync_end = mode->hsync_start + 8; 268 } 269 if (output_mode->vdisplay >= 1024) { 270 mode->vtotal = output_mode->vtotal; 271 mode->vsync_start = output_mode->vsync_start; 272 mode->vsync_end = output_mode->vsync_end; 273 } 274 275 mode->type |= DRM_MODE_TYPE_DRIVER; 276 drm_mode_probed_add(connector, mode); 277 n++; 278 } 279 return n; 280} 281 282static int nv17_tv_mode_valid(struct drm_encoder *encoder, 283 struct drm_display_mode *mode) 284{ 285 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 286 287 if (tv_norm->kind == CTV_ENC_MODE) { 288 struct drm_display_mode *output_mode = 289 &tv_norm->ctv_enc_mode.mode; 290 291 if (mode->clock > 400000) 292 return MODE_CLOCK_HIGH; 293 294 if (mode->hdisplay > output_mode->hdisplay || 295 mode->vdisplay > output_mode->vdisplay) 296 return MODE_BAD; 297 298 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) != 299 (output_mode->flags & DRM_MODE_FLAG_INTERLACE)) 300 return MODE_NO_INTERLACE; 301 302 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 303 return MODE_NO_DBLESCAN; 304 305 } else { 306 const int vsync_tolerance = 600; 307 308 if (mode->clock > 70000) 309 return MODE_CLOCK_HIGH; 310 311 if (abs(drm_mode_vrefresh(mode) * 1000 - 312 tv_norm->tv_enc_mode.vrefresh) > vsync_tolerance) 313 return MODE_VSYNC; 314 315 /* The encoder takes care of the actual interlacing */ 316 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 317 return MODE_NO_INTERLACE; 318 } 319 320 return MODE_OK; 321} 322 323static bool nv17_tv_mode_fixup(struct drm_encoder *encoder, 324 struct drm_display_mode *mode, 325 struct drm_display_mode *adjusted_mode) 326{ 327 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 328 329 if (nv04_dac_in_use(encoder)) 330 return false; 331 332 if (tv_norm->kind == CTV_ENC_MODE) 333 adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock; 334 else 335 adjusted_mode->clock = 90000; 336 337 return true; 338} 339 340static void nv17_tv_dpms(struct drm_encoder *encoder, int mode) 341{ 342 struct drm_device *dev = encoder->dev; 343 struct drm_nouveau_private *dev_priv = dev->dev_private; 344 struct nouveau_gpio_engine *gpio = &dev_priv->engine.gpio; 345 struct nv17_tv_state *regs = &to_tv_enc(encoder)->state; 346 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 347 348 if (nouveau_encoder(encoder)->last_dpms == mode) 349 return; 350 nouveau_encoder(encoder)->last_dpms = mode; 351 352 NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n", 353 mode, nouveau_encoder(encoder)->dcb->index); 354 355 regs->ptv_200 &= ~1; 356 357 if (tv_norm->kind == CTV_ENC_MODE) { 358 nv04_dfp_update_fp_control(encoder, mode); 359 360 } else { 361 nv04_dfp_update_fp_control(encoder, DRM_MODE_DPMS_OFF); 362 363 if (mode == DRM_MODE_DPMS_ON) 364 regs->ptv_200 |= 1; 365 } 366 367 nv_load_ptv(dev, regs, 200); 368 369 gpio->set(dev, DCB_GPIO_TVDAC1, mode == DRM_MODE_DPMS_ON); 370 gpio->set(dev, DCB_GPIO_TVDAC0, mode == DRM_MODE_DPMS_ON); 371 372 nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON); 373} 374 375static void nv17_tv_prepare(struct drm_encoder *encoder) 376{ 377 struct drm_device *dev = encoder->dev; 378 struct drm_nouveau_private *dev_priv = dev->dev_private; 379 struct drm_encoder_helper_funcs *helper = encoder->helper_private; 380 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 381 int head = nouveau_crtc(encoder->crtc)->index; 382 uint8_t *cr_lcd = &dev_priv->mode_reg.crtc_reg[head].CRTC[ 383 NV_CIO_CRE_LCD__INDEX]; 384 uint32_t dacclk_off = NV_PRAMDAC_DACCLK + 385 nv04_dac_output_offset(encoder); 386 uint32_t dacclk; 387 388 helper->dpms(encoder, DRM_MODE_DPMS_OFF); 389 390 nv04_dfp_disable(dev, head); 391 392 /* Unbind any FP encoders from this head if we need the FP 393 * stuff enabled. */ 394 if (tv_norm->kind == CTV_ENC_MODE) { 395 struct drm_encoder *enc; 396 397 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { 398 struct dcb_entry *dcb = nouveau_encoder(enc)->dcb; 399 400 if ((dcb->type == OUTPUT_TMDS || 401 dcb->type == OUTPUT_LVDS) && 402 !enc->crtc && 403 nv04_dfp_get_bound_head(dev, dcb) == head) { 404 nv04_dfp_bind_head(dev, dcb, head ^ 1, 405 dev_priv->vbios.fp.dual_link); 406 } 407 } 408 409 } 410 411 /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f) 412 * at LCD__INDEX which we don't alter 413 */ 414 if (!(*cr_lcd & 0x44)) { 415 if (tv_norm->kind == CTV_ENC_MODE) 416 *cr_lcd = 0x1 | (head ? 0x0 : 0x8); 417 else 418 *cr_lcd = 0; 419 } 420 421 /* Set the DACCLK register */ 422 dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1; 423 424 if (dev_priv->card_type == NV_40) 425 dacclk |= 0x1a << 16; 426 427 if (tv_norm->kind == CTV_ENC_MODE) { 428 dacclk |= 0x20; 429 430 if (head) 431 dacclk |= 0x100; 432 else 433 dacclk &= ~0x100; 434 435 } else { 436 dacclk |= 0x10; 437 438 } 439 440 NVWriteRAMDAC(dev, 0, dacclk_off, dacclk); 441} 442 443static void nv17_tv_mode_set(struct drm_encoder *encoder, 444 struct drm_display_mode *drm_mode, 445 struct drm_display_mode *adjusted_mode) 446{ 447 struct drm_device *dev = encoder->dev; 448 struct drm_nouveau_private *dev_priv = dev->dev_private; 449 int head = nouveau_crtc(encoder->crtc)->index; 450 struct nv04_crtc_reg *regs = &dev_priv->mode_reg.crtc_reg[head]; 451 struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state; 452 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 453 int i; 454 455 regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */ 456 regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */ 457 regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */ 458 regs->tv_setup = 1; 459 regs->ramdac_8c0 = 0x0; 460 461 if (tv_norm->kind == TV_ENC_MODE) { 462 tv_regs->ptv_200 = 0x13111100; 463 if (head) 464 tv_regs->ptv_200 |= 0x10; 465 466 tv_regs->ptv_20c = 0x808010; 467 tv_regs->ptv_304 = 0x2d00000; 468 tv_regs->ptv_600 = 0x0; 469 tv_regs->ptv_60c = 0x0; 470 tv_regs->ptv_610 = 0x1e00000; 471 472 if (tv_norm->tv_enc_mode.vdisplay == 576) { 473 tv_regs->ptv_508 = 0x1200000; 474 tv_regs->ptv_614 = 0x33; 475 476 } else if (tv_norm->tv_enc_mode.vdisplay == 480) { 477 tv_regs->ptv_508 = 0xf00000; 478 tv_regs->ptv_614 = 0x13; 479 } 480 481 if (dev_priv->card_type >= NV_30) { 482 tv_regs->ptv_500 = 0xe8e0; 483 tv_regs->ptv_504 = 0x1710; 484 tv_regs->ptv_604 = 0x0; 485 tv_regs->ptv_608 = 0x0; 486 } else { 487 if (tv_norm->tv_enc_mode.vdisplay == 576) { 488 tv_regs->ptv_604 = 0x20; 489 tv_regs->ptv_608 = 0x10; 490 tv_regs->ptv_500 = 0x19710; 491 tv_regs->ptv_504 = 0x68f0; 492 493 } else if (tv_norm->tv_enc_mode.vdisplay == 480) { 494 tv_regs->ptv_604 = 0x10; 495 tv_regs->ptv_608 = 0x20; 496 tv_regs->ptv_500 = 0x4b90; 497 tv_regs->ptv_504 = 0x1b480; 498 } 499 } 500 501 for (i = 0; i < 0x40; i++) 502 tv_regs->tv_enc[i] = tv_norm->tv_enc_mode.tv_enc[i]; 503 504 } else { 505 struct drm_display_mode *output_mode = 506 &tv_norm->ctv_enc_mode.mode; 507 508 /* The registers in PRAMDAC+0xc00 control some timings and CSC 509 * parameters for the CTV encoder (It's only used for "HD" TV 510 * modes, I don't think I have enough working to guess what 511 * they exactly mean...), it's probably connected at the 512 * output of the FP encoder, but it also needs the analog 513 * encoder in its OR enabled and routed to the head it's 514 * using. It's enabled with the DACCLK register, bits [5:4]. 515 */ 516 for (i = 0; i < 38; i++) 517 regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i]; 518 519 regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1; 520 regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1; 521 regs->fp_horiz_regs[FP_SYNC_START] = 522 output_mode->hsync_start - 1; 523 regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1; 524 regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay + 525 max((output_mode->hdisplay-600)/40 - 1, 1); 526 527 regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1; 528 regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1; 529 regs->fp_vert_regs[FP_SYNC_START] = 530 output_mode->vsync_start - 1; 531 regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1; 532 regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1; 533 534 regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | 535 NV_PRAMDAC_FP_TG_CONTROL_READ_PROG | 536 NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12; 537 538 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC) 539 regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS; 540 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC) 541 regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS; 542 543 regs->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND | 544 NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND | 545 NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR | 546 NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR | 547 NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED | 548 NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE | 549 NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE; 550 551 regs->fp_debug_2 = 0; 552 553 regs->fp_margin_color = 0x801080; 554 555 } 556} 557 558static void nv17_tv_commit(struct drm_encoder *encoder) 559{ 560 struct drm_device *dev = encoder->dev; 561 struct drm_nouveau_private *dev_priv = dev->dev_private; 562 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 563 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 564 struct drm_encoder_helper_funcs *helper = encoder->helper_private; 565 566 if (get_tv_norm(encoder)->kind == TV_ENC_MODE) { 567 nv17_tv_update_rescaler(encoder); 568 nv17_tv_update_properties(encoder); 569 } else { 570 nv17_ctv_update_rescaler(encoder); 571 } 572 573 nv17_tv_state_load(dev, &to_tv_enc(encoder)->state); 574 575 /* This could use refinement for flatpanels, but it should work */ 576 if (dev_priv->chipset < 0x44) 577 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + 578 nv04_dac_output_offset(encoder), 579 0xf0000000); 580 else 581 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + 582 nv04_dac_output_offset(encoder), 583 0x00100000); 584 585 helper->dpms(encoder, DRM_MODE_DPMS_ON); 586 587 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n", 588 drm_get_connector_name( 589 &nouveau_encoder_connector_get(nv_encoder)->base), 590 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); 591} 592 593static void nv17_tv_save(struct drm_encoder *encoder) 594{ 595 struct drm_device *dev = encoder->dev; 596 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 597 598 nouveau_encoder(encoder)->restore.output = 599 NVReadRAMDAC(dev, 0, 600 NV_PRAMDAC_DACCLK + 601 nv04_dac_output_offset(encoder)); 602 603 nv17_tv_state_save(dev, &tv_enc->saved_state); 604 605 tv_enc->state.ptv_200 = tv_enc->saved_state.ptv_200; 606} 607 608static void nv17_tv_restore(struct drm_encoder *encoder) 609{ 610 struct drm_device *dev = encoder->dev; 611 612 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + 613 nv04_dac_output_offset(encoder), 614 nouveau_encoder(encoder)->restore.output); 615 616 nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state); 617 618 nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED; 619} 620 621static int nv17_tv_create_resources(struct drm_encoder *encoder, 622 struct drm_connector *connector) 623{ 624 struct drm_device *dev = encoder->dev; 625 struct drm_mode_config *conf = &dev->mode_config; 626 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 627 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; 628 int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS : 629 NUM_LD_TV_NORMS; 630 int i; 631 632 if (nouveau_tv_norm) { 633 for (i = 0; i < num_tv_norms; i++) { 634 if (!strcmp(nv17_tv_norm_names[i], nouveau_tv_norm)) { 635 tv_enc->tv_norm = i; 636 break; 637 } 638 } 639 640 if (i == num_tv_norms) 641 NV_WARN(dev, "Invalid TV norm setting \"%s\"\n", 642 nouveau_tv_norm); 643 } 644 645 drm_mode_create_tv_properties(dev, num_tv_norms, nv17_tv_norm_names); 646 647 drm_connector_attach_property(connector, 648 conf->tv_select_subconnector_property, 649 tv_enc->select_subconnector); 650 drm_connector_attach_property(connector, 651 conf->tv_subconnector_property, 652 tv_enc->subconnector); 653 drm_connector_attach_property(connector, 654 conf->tv_mode_property, 655 tv_enc->tv_norm); 656 drm_connector_attach_property(connector, 657 conf->tv_flicker_reduction_property, 658 tv_enc->flicker); 659 drm_connector_attach_property(connector, 660 conf->tv_saturation_property, 661 tv_enc->saturation); 662 drm_connector_attach_property(connector, 663 conf->tv_hue_property, 664 tv_enc->hue); 665 drm_connector_attach_property(connector, 666 conf->tv_overscan_property, 667 tv_enc->overscan); 668 669 return 0; 670} 671 672static int nv17_tv_set_property(struct drm_encoder *encoder, 673 struct drm_connector *connector, 674 struct drm_property *property, 675 uint64_t val) 676{ 677 struct drm_mode_config *conf = &encoder->dev->mode_config; 678 struct drm_crtc *crtc = encoder->crtc; 679 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 680 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 681 bool modes_changed = false; 682 683 if (property == conf->tv_overscan_property) { 684 tv_enc->overscan = val; 685 if (encoder->crtc) { 686 if (tv_norm->kind == CTV_ENC_MODE) 687 nv17_ctv_update_rescaler(encoder); 688 else 689 nv17_tv_update_rescaler(encoder); 690 } 691 692 } else if (property == conf->tv_saturation_property) { 693 if (tv_norm->kind != TV_ENC_MODE) 694 return -EINVAL; 695 696 tv_enc->saturation = val; 697 nv17_tv_update_properties(encoder); 698 699 } else if (property == conf->tv_hue_property) { 700 if (tv_norm->kind != TV_ENC_MODE) 701 return -EINVAL; 702 703 tv_enc->hue = val; 704 nv17_tv_update_properties(encoder); 705 706 } else if (property == conf->tv_flicker_reduction_property) { 707 if (tv_norm->kind != TV_ENC_MODE) 708 return -EINVAL; 709 710 tv_enc->flicker = val; 711 if (encoder->crtc) 712 nv17_tv_update_rescaler(encoder); 713 714 } else if (property == conf->tv_mode_property) { 715 if (connector->dpms != DRM_MODE_DPMS_OFF) 716 return -EINVAL; 717 718 tv_enc->tv_norm = val; 719 720 modes_changed = true; 721 722 } else if (property == conf->tv_select_subconnector_property) { 723 if (tv_norm->kind != TV_ENC_MODE) 724 return -EINVAL; 725 726 tv_enc->select_subconnector = val; 727 nv17_tv_update_properties(encoder); 728 729 } else { 730 return -EINVAL; 731 } 732 733 if (modes_changed) { 734 drm_helper_probe_single_connector_modes(connector, 0, 0); 735 736 /* Disable the crtc to ensure a full modeset is 737 * performed whenever it's turned on again. */ 738 if (crtc) { 739 struct drm_mode_set modeset = { 740 .crtc = crtc, 741 }; 742 743 crtc->funcs->set_config(&modeset); 744 } 745 } 746 747 return 0; 748} 749 750static void nv17_tv_destroy(struct drm_encoder *encoder) 751{ 752 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 753 754 NV_DEBUG_KMS(encoder->dev, "\n"); 755 756 drm_encoder_cleanup(encoder); 757 kfree(tv_enc); 758} 759 760static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = { 761 .dpms = nv17_tv_dpms, 762 .save = nv17_tv_save, 763 .restore = nv17_tv_restore, 764 .mode_fixup = nv17_tv_mode_fixup, 765 .prepare = nv17_tv_prepare, 766 .commit = nv17_tv_commit, 767 .mode_set = nv17_tv_mode_set, 768 .detect = nv17_tv_detect, 769}; 770 771static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = { 772 .get_modes = nv17_tv_get_modes, 773 .mode_valid = nv17_tv_mode_valid, 774 .create_resources = nv17_tv_create_resources, 775 .set_property = nv17_tv_set_property, 776}; 777 778static struct drm_encoder_funcs nv17_tv_funcs = { 779 .destroy = nv17_tv_destroy, 780}; 781 782int 783nv17_tv_create(struct drm_connector *connector, struct dcb_entry *entry) 784{ 785 struct drm_device *dev = connector->dev; 786 struct drm_encoder *encoder; 787 struct nv17_tv_encoder *tv_enc = NULL; 788 789 tv_enc = kzalloc(sizeof(*tv_enc), GFP_KERNEL); 790 if (!tv_enc) 791 return -ENOMEM; 792 793 tv_enc->overscan = 50; 794 tv_enc->flicker = 50; 795 tv_enc->saturation = 50; 796 tv_enc->hue = 0; 797 tv_enc->tv_norm = TV_NORM_PAL; 798 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 799 tv_enc->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic; 800 tv_enc->pin_mask = 0; 801 802 encoder = to_drm_encoder(&tv_enc->base); 803 804 tv_enc->base.dcb = entry; 805 tv_enc->base.or = ffs(entry->or) - 1; 806 807 drm_encoder_init(dev, encoder, &nv17_tv_funcs, DRM_MODE_ENCODER_TVDAC); 808 drm_encoder_helper_add(encoder, &nv17_tv_helper_funcs); 809 to_encoder_slave(encoder)->slave_funcs = &nv17_tv_slave_funcs; 810 811 encoder->possible_crtcs = entry->heads; 812 encoder->possible_clones = 0; 813 814 nv17_tv_create_resources(encoder, connector); 815 drm_mode_connector_attach_encoder(connector, encoder); 816 return 0; 817} 818