1/* 2 * AMD 76x Memory Controller kernel module 3 * (C) 2003 Linux Networx (http://lnxi.com) 4 * This file may be distributed under the terms of the 5 * GNU General Public License. 6 * 7 * Written by Thayne Harbaugh 8 * Based on work by Dan Hollis <goemon at anime dot net> and others. 9 * http://www.anime.net/~goemon/linux-ecc/ 10 * 11 * $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 Exp $ 12 * 13 */ 14 15#include <linux/module.h> 16#include <linux/init.h> 17#include <linux/pci.h> 18#include <linux/pci_ids.h> 19#include <linux/edac.h> 20#include "edac_core.h" 21 22#define AMD76X_REVISION " Ver: 2.0.2 " __DATE__ 23#define EDAC_MOD_STR "amd76x_edac" 24 25#define amd76x_printk(level, fmt, arg...) \ 26 edac_printk(level, "amd76x", fmt, ##arg) 27 28#define amd76x_mc_printk(mci, level, fmt, arg...) \ 29 edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg) 30 31#define AMD76X_NR_CSROWS 8 32#define AMD76X_NR_CHANS 1 33#define AMD76X_NR_DIMMS 4 34 35/* AMD 76x register addresses - device 0 function 0 - PCI bridge */ 36 37#define AMD76X_ECC_MODE_STATUS 0x48 /* Mode and status of ECC (32b) 38 * 39 * 31:16 reserved 40 * 15:14 SERR enabled: x1=ue 1x=ce 41 * 13 reserved 42 * 12 diag: disabled, enabled 43 * 11:10 mode: dis, EC, ECC, ECC+scrub 44 * 9:8 status: x1=ue 1x=ce 45 * 7:4 UE cs row 46 * 3:0 CE cs row 47 */ 48 49#define AMD76X_DRAM_MODE_STATUS 0x58 /* DRAM Mode and status (32b) 50 * 51 * 31:26 clock disable 5 - 0 52 * 25 SDRAM init 53 * 24 reserved 54 * 23 mode register service 55 * 22:21 suspend to RAM 56 * 20 burst refresh enable 57 * 19 refresh disable 58 * 18 reserved 59 * 17:16 cycles-per-refresh 60 * 15:8 reserved 61 * 7:0 x4 mode enable 7 - 0 62 */ 63 64#define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b) 65 * 66 * 31:23 chip-select base 67 * 22:16 reserved 68 * 15:7 chip-select mask 69 * 6:3 reserved 70 * 2:1 address mode 71 * 0 chip-select enable 72 */ 73 74struct amd76x_error_info { 75 u32 ecc_mode_status; 76}; 77 78enum amd76x_chips { 79 AMD761 = 0, 80 AMD762 81}; 82 83struct amd76x_dev_info { 84 const char *ctl_name; 85}; 86 87static const struct amd76x_dev_info amd76x_devs[] = { 88 [AMD761] = { 89 .ctl_name = "AMD761"}, 90 [AMD762] = { 91 .ctl_name = "AMD762"}, 92}; 93 94static struct edac_pci_ctl_info *amd76x_pci; 95 96/** 97 * amd76x_get_error_info - fetch error information 98 * @mci: Memory controller 99 * @info: Info to fill in 100 * 101 * Fetch and store the AMD76x ECC status. Clear pending status 102 * on the chip so that further errors will be reported 103 */ 104static void amd76x_get_error_info(struct mem_ctl_info *mci, 105 struct amd76x_error_info *info) 106{ 107 struct pci_dev *pdev; 108 109 pdev = to_pci_dev(mci->dev); 110 pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, 111 &info->ecc_mode_status); 112 113 if (info->ecc_mode_status & BIT(8)) 114 pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS, 115 (u32) BIT(8), (u32) BIT(8)); 116 117 if (info->ecc_mode_status & BIT(9)) 118 pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS, 119 (u32) BIT(9), (u32) BIT(9)); 120} 121 122/** 123 * amd76x_process_error_info - Error check 124 * @mci: Memory controller 125 * @info: Previously fetched information from chip 126 * @handle_errors: 1 if we should do recovery 127 * 128 * Process the chip state and decide if an error has occurred. 129 * A return of 1 indicates an error. Also if handle_errors is true 130 * then attempt to handle and clean up after the error 131 */ 132static int amd76x_process_error_info(struct mem_ctl_info *mci, 133 struct amd76x_error_info *info, 134 int handle_errors) 135{ 136 int error_found; 137 u32 row; 138 139 error_found = 0; 140 141 /* 142 * Check for an uncorrectable error 143 */ 144 if (info->ecc_mode_status & BIT(8)) { 145 error_found = 1; 146 147 if (handle_errors) { 148 row = (info->ecc_mode_status >> 4) & 0xf; 149 edac_mc_handle_ue(mci, mci->csrows[row].first_page, 0, 150 row, mci->ctl_name); 151 } 152 } 153 154 /* 155 * Check for a correctable error 156 */ 157 if (info->ecc_mode_status & BIT(9)) { 158 error_found = 1; 159 160 if (handle_errors) { 161 row = info->ecc_mode_status & 0xf; 162 edac_mc_handle_ce(mci, mci->csrows[row].first_page, 0, 163 0, row, 0, mci->ctl_name); 164 } 165 } 166 167 return error_found; 168} 169 170/** 171 * amd76x_check - Poll the controller 172 * @mci: Memory controller 173 * 174 * Called by the poll handlers this function reads the status 175 * from the controller and checks for errors. 176 */ 177static void amd76x_check(struct mem_ctl_info *mci) 178{ 179 struct amd76x_error_info info; 180 debugf3("%s()\n", __func__); 181 amd76x_get_error_info(mci, &info); 182 amd76x_process_error_info(mci, &info, 1); 183} 184 185static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, 186 enum edac_type edac_mode) 187{ 188 struct csrow_info *csrow; 189 u32 mba, mba_base, mba_mask, dms; 190 int index; 191 192 for (index = 0; index < mci->nr_csrows; index++) { 193 csrow = &mci->csrows[index]; 194 195 /* find the DRAM Chip Select Base address and mask */ 196 pci_read_config_dword(pdev, 197 AMD76X_MEM_BASE_ADDR + (index * 4), &mba); 198 199 if (!(mba & BIT(0))) 200 continue; 201 202 mba_base = mba & 0xff800000UL; 203 mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL; 204 pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms); 205 csrow->first_page = mba_base >> PAGE_SHIFT; 206 csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT; 207 csrow->last_page = csrow->first_page + csrow->nr_pages - 1; 208 csrow->page_mask = mba_mask >> PAGE_SHIFT; 209 csrow->grain = csrow->nr_pages << PAGE_SHIFT; 210 csrow->mtype = MEM_RDDR; 211 csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN; 212 csrow->edac_mode = edac_mode; 213 } 214} 215 216/** 217 * amd76x_probe1 - Perform set up for detected device 218 * @pdev; PCI device detected 219 * @dev_idx: Device type index 220 * 221 * We have found an AMD76x and now need to set up the memory 222 * controller status reporting. We configure and set up the 223 * memory controller reporting and claim the device. 224 */ 225static int amd76x_probe1(struct pci_dev *pdev, int dev_idx) 226{ 227 static const enum edac_type ems_modes[] = { 228 EDAC_NONE, 229 EDAC_EC, 230 EDAC_SECDED, 231 EDAC_SECDED 232 }; 233 struct mem_ctl_info *mci = NULL; 234 u32 ems; 235 u32 ems_mode; 236 struct amd76x_error_info discard; 237 238 debugf0("%s()\n", __func__); 239 pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems); 240 ems_mode = (ems >> 10) & 0x3; 241 mci = edac_mc_alloc(0, AMD76X_NR_CSROWS, AMD76X_NR_CHANS, 0); 242 243 if (mci == NULL) { 244 return -ENOMEM; 245 } 246 247 debugf0("%s(): mci = %p\n", __func__, mci); 248 mci->dev = &pdev->dev; 249 mci->mtype_cap = MEM_FLAG_RDDR; 250 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; 251 mci->edac_cap = ems_mode ? 252 (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE; 253 mci->mod_name = EDAC_MOD_STR; 254 mci->mod_ver = AMD76X_REVISION; 255 mci->ctl_name = amd76x_devs[dev_idx].ctl_name; 256 mci->dev_name = pci_name(pdev); 257 mci->edac_check = amd76x_check; 258 mci->ctl_page_to_phys = NULL; 259 260 amd76x_init_csrows(mci, pdev, ems_modes[ems_mode]); 261 amd76x_get_error_info(mci, &discard); /* clear counters */ 262 263 /* Here we assume that we will never see multiple instances of this 264 * type of memory controller. The ID is therefore hardcoded to 0. 265 */ 266 if (edac_mc_add_mc(mci)) { 267 debugf3("%s(): failed edac_mc_add_mc()\n", __func__); 268 goto fail; 269 } 270 271 /* allocating generic PCI control info */ 272 amd76x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); 273 if (!amd76x_pci) { 274 printk(KERN_WARNING 275 "%s(): Unable to create PCI control\n", 276 __func__); 277 printk(KERN_WARNING 278 "%s(): PCI error report via EDAC not setup\n", 279 __func__); 280 } 281 282 /* get this far and it's successful */ 283 debugf3("%s(): success\n", __func__); 284 return 0; 285 286fail: 287 edac_mc_free(mci); 288 return -ENODEV; 289} 290 291/* returns count (>= 0), or negative on error */ 292static int __devinit amd76x_init_one(struct pci_dev *pdev, 293 const struct pci_device_id *ent) 294{ 295 debugf0("%s()\n", __func__); 296 297 /* don't need to call pci_enable_device() */ 298 return amd76x_probe1(pdev, ent->driver_data); 299} 300 301/** 302 * amd76x_remove_one - driver shutdown 303 * @pdev: PCI device being handed back 304 * 305 * Called when the driver is unloaded. Find the matching mci 306 * structure for the device then delete the mci and free the 307 * resources. 308 */ 309static void __devexit amd76x_remove_one(struct pci_dev *pdev) 310{ 311 struct mem_ctl_info *mci; 312 313 debugf0("%s()\n", __func__); 314 315 if (amd76x_pci) 316 edac_pci_release_generic_ctl(amd76x_pci); 317 318 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) 319 return; 320 321 edac_mc_free(mci); 322} 323 324static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = { 325 { 326 PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 327 AMD762}, 328 { 329 PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 330 AMD761}, 331 { 332 0, 333 } /* 0 terminated list. */ 334}; 335 336MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl); 337 338static struct pci_driver amd76x_driver = { 339 .name = EDAC_MOD_STR, 340 .probe = amd76x_init_one, 341 .remove = __devexit_p(amd76x_remove_one), 342 .id_table = amd76x_pci_tbl, 343}; 344 345static int __init amd76x_init(void) 346{ 347 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 348 opstate_init(); 349 350 return pci_register_driver(&amd76x_driver); 351} 352 353static void __exit amd76x_exit(void) 354{ 355 pci_unregister_driver(&amd76x_driver); 356} 357 358module_init(amd76x_init); 359module_exit(amd76x_exit); 360 361MODULE_LICENSE("GPL"); 362MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh"); 363MODULE_DESCRIPTION("MC support for AMD 76x memory controllers"); 364 365module_param(edac_op_state, int, 0444); 366MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 367