1#ifndef CCISS_H 2#define CCISS_H 3 4#include <linux/genhd.h> 5#include <linux/mutex.h> 6 7#include "cciss_cmd.h" 8 9 10#define NWD_SHIFT 4 11#define MAX_PART (1 << NWD_SHIFT) 12 13#define IO_OK 0 14#define IO_ERROR 1 15#define IO_NEEDS_RETRY 3 16 17#define VENDOR_LEN 8 18#define MODEL_LEN 16 19#define REV_LEN 4 20 21struct ctlr_info; 22typedef struct ctlr_info ctlr_info_t; 23 24struct access_method { 25 void (*submit_command)(ctlr_info_t *h, CommandList_struct *c); 26 void (*set_intr_mask)(ctlr_info_t *h, unsigned long val); 27 unsigned long (*fifo_full)(ctlr_info_t *h); 28 bool (*intr_pending)(ctlr_info_t *h); 29 unsigned long (*command_completed)(ctlr_info_t *h); 30}; 31typedef struct _drive_info_struct 32{ 33 unsigned char LunID[8]; 34 int usage_count; 35 struct request_queue *queue; 36 sector_t nr_blocks; 37 int block_size; 38 int heads; 39 int sectors; 40 int cylinders; 41 int raid_level; /* set to -1 to indicate that 42 * the drive is not in use/configured 43 */ 44 int busy_configuring; /* This is set when a drive is being removed 45 * to prevent it from being opened or it's 46 * queue from being started. 47 */ 48 struct device dev; 49 __u8 serial_no[16]; /* from inquiry page 0x83, 50 * not necc. null terminated. 51 */ 52 char vendor[VENDOR_LEN + 1]; /* SCSI vendor string */ 53 char model[MODEL_LEN + 1]; /* SCSI model string */ 54 char rev[REV_LEN + 1]; /* SCSI revision string */ 55 char device_initialized; /* indicates whether dev is initialized */ 56} drive_info_struct; 57 58struct ctlr_info 59{ 60 int ctlr; 61 char devname[8]; 62 char *product_name; 63 char firm_ver[4]; /* Firmware version */ 64 struct pci_dev *pdev; 65 __u32 board_id; 66 void __iomem *vaddr; 67 unsigned long paddr; 68 int nr_cmds; /* Number of commands allowed on this controller */ 69 CfgTable_struct __iomem *cfgtable; 70 int interrupts_enabled; 71 int major; 72 int max_commands; 73 int commands_outstanding; 74 int max_outstanding; /* Debug */ 75 int num_luns; 76 int highest_lun; 77 int usage_count; /* number of opens all all minor devices */ 78 /* Need space for temp sg list 79 * number of scatter/gathers supported 80 * number of scatter/gathers in chained block 81 */ 82 struct scatterlist **scatter_list; 83 int maxsgentries; 84 int chainsize; 85 int max_cmd_sgentries; 86 SGDescriptor_struct **cmd_sg_list; 87 88# define PERF_MODE_INT 0 89# define DOORBELL_INT 1 90# define SIMPLE_MODE_INT 2 91# define MEMQ_MODE_INT 3 92 unsigned int intr[4]; 93 unsigned int msix_vector; 94 unsigned int msi_vector; 95 int cciss_max_sectors; 96 BYTE cciss_read; 97 BYTE cciss_write; 98 BYTE cciss_read_capacity; 99 100 /* information about each logical volume */ 101 drive_info_struct *drv[CISS_MAX_LUN]; 102 103 struct access_method access; 104 105 /* queue and queue Info */ 106 struct hlist_head reqQ; 107 struct hlist_head cmpQ; 108 unsigned int Qdepth; 109 unsigned int maxQsinceinit; 110 unsigned int maxSG; 111 spinlock_t lock; 112 113 /* pointers to command and error info pool */ 114 CommandList_struct *cmd_pool; 115 dma_addr_t cmd_pool_dhandle; 116 ErrorInfo_struct *errinfo_pool; 117 dma_addr_t errinfo_pool_dhandle; 118 unsigned long *cmd_pool_bits; 119 int nr_allocs; 120 int nr_frees; 121 int busy_configuring; 122 int busy_initializing; 123 int busy_scanning; 124 struct mutex busy_shutting_down; 125 126 /* This element holds the zero based queue number of the last 127 * queue to be started. It is used for fairness. 128 */ 129 int next_to_run; 130 131 /* Disk structures we need to pass back */ 132 struct gendisk *gendisk[CISS_MAX_LUN]; 133#ifdef CONFIG_CISS_SCSI_TAPE 134 struct cciss_scsi_adapter_data_t *scsi_ctlr; 135#endif 136 unsigned char alive; 137 struct list_head scan_list; 138 struct completion scan_wait; 139 struct device dev; 140 /* 141 * Performant mode tables. 142 */ 143 u32 trans_support; 144 u32 trans_offset; 145 struct TransTable_struct *transtable; 146 unsigned long transMethod; 147 148 /* 149 * Performant mode completion buffer 150 */ 151 u64 *reply_pool; 152 dma_addr_t reply_pool_dhandle; 153 u64 *reply_pool_head; 154 size_t reply_pool_size; 155 unsigned char reply_pool_wraparound; 156 u32 *blockFetchTable; 157}; 158 159/* Defining the diffent access_methods 160 * 161 * Memory mapped FIFO interface (SMART 53xx cards) 162 */ 163#define SA5_DOORBELL 0x20 164#define SA5_REQUEST_PORT_OFFSET 0x40 165#define SA5_REPLY_INTR_MASK_OFFSET 0x34 166#define SA5_REPLY_PORT_OFFSET 0x44 167#define SA5_INTR_STATUS 0x30 168#define SA5_SCRATCHPAD_OFFSET 0xB0 169 170#define SA5_CTCFG_OFFSET 0xB4 171#define SA5_CTMEM_OFFSET 0xB8 172 173#define SA5_INTR_OFF 0x08 174#define SA5B_INTR_OFF 0x04 175#define SA5_INTR_PENDING 0x08 176#define SA5B_INTR_PENDING 0x04 177#define FIFO_EMPTY 0xffffffff 178#define CCISS_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ 179/* Perf. mode flags */ 180#define SA5_PERF_INTR_PENDING 0x04 181#define SA5_PERF_INTR_OFF 0x05 182#define SA5_OUTDB_STATUS_PERF_BIT 0x01 183#define SA5_OUTDB_CLEAR_PERF_BIT 0x01 184#define SA5_OUTDB_CLEAR 0xA0 185#define SA5_OUTDB_CLEAR_PERF_BIT 0x01 186#define SA5_OUTDB_STATUS 0x9C 187 188 189#define CISS_ERROR_BIT 0x02 190 191#define CCISS_INTR_ON 1 192#define CCISS_INTR_OFF 0 193 194 195/* CCISS_BOARD_READY_WAIT_SECS is how long to wait for a board 196 * to become ready, in seconds, before giving up on it. 197 * CCISS_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait 198 * between polling the board to see if it is ready, in 199 * milliseconds. CCISS_BOARD_READY_ITERATIONS is derived 200 * the above. 201 */ 202#define CCISS_BOARD_READY_WAIT_SECS (120) 203#define CCISS_BOARD_READY_POLL_INTERVAL_MSECS (100) 204#define CCISS_BOARD_READY_ITERATIONS \ 205 ((CCISS_BOARD_READY_WAIT_SECS * 1000) / \ 206 CCISS_BOARD_READY_POLL_INTERVAL_MSECS) 207#define CCISS_POST_RESET_PAUSE_MSECS (3000) 208#define CCISS_POST_RESET_NOOP_INTERVAL_MSECS (1000) 209#define CCISS_POST_RESET_NOOP_RETRIES (12) 210 211/* 212 Send the command to the hardware 213*/ 214static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c) 215{ 216#ifdef CCISS_DEBUG 217 printk(KERN_WARNING "cciss%d: Sending %08x - down to controller\n", 218 h->ctlr, c->busaddr); 219#endif /* CCISS_DEBUG */ 220 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 221 h->commands_outstanding++; 222 if ( h->commands_outstanding > h->max_outstanding) 223 h->max_outstanding = h->commands_outstanding; 224} 225 226/* 227 * This card is the opposite of the other cards. 228 * 0 turns interrupts on... 229 * 0x08 turns them off... 230 */ 231static void SA5_intr_mask(ctlr_info_t *h, unsigned long val) 232{ 233 if (val) 234 { /* Turn interrupts on */ 235 h->interrupts_enabled = 1; 236 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 237 } else /* Turn them off */ 238 { 239 h->interrupts_enabled = 0; 240 writel( SA5_INTR_OFF, 241 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 242 } 243} 244/* 245 * This card is the opposite of the other cards. 246 * 0 turns interrupts on... 247 * 0x04 turns them off... 248 */ 249static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val) 250{ 251 if (val) 252 { /* Turn interrupts on */ 253 h->interrupts_enabled = 1; 254 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 255 } else /* Turn them off */ 256 { 257 h->interrupts_enabled = 0; 258 writel( SA5B_INTR_OFF, 259 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 260 } 261} 262 263/* Performant mode intr_mask */ 264static void SA5_performant_intr_mask(ctlr_info_t *h, unsigned long val) 265{ 266 if (val) { /* turn on interrupts */ 267 h->interrupts_enabled = 1; 268 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 269 } else { 270 h->interrupts_enabled = 0; 271 writel(SA5_PERF_INTR_OFF, 272 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 273 } 274} 275 276/* 277 * Returns true if fifo is full. 278 * 279 */ 280static unsigned long SA5_fifo_full(ctlr_info_t *h) 281{ 282 if( h->commands_outstanding >= h->max_commands) 283 return(1); 284 else 285 return(0); 286 287} 288/* 289 * returns value read from hardware. 290 * returns FIFO_EMPTY if there is nothing to read 291 */ 292static unsigned long SA5_completed(ctlr_info_t *h) 293{ 294 unsigned long register_value 295 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); 296 if(register_value != FIFO_EMPTY) 297 { 298 h->commands_outstanding--; 299#ifdef CCISS_DEBUG 300 printk("cciss: Read %lx back from board\n", register_value); 301#endif /* CCISS_DEBUG */ 302 } 303#ifdef CCISS_DEBUG 304 else 305 { 306 printk("cciss: FIFO Empty read\n"); 307 } 308#endif 309 return ( register_value); 310 311} 312 313/* Performant mode command completed */ 314static unsigned long SA5_performant_completed(ctlr_info_t *h) 315{ 316 unsigned long register_value = FIFO_EMPTY; 317 318 /* flush the controller write of the reply queue by reading 319 * outbound doorbell status register. 320 */ 321 register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 322 /* msi auto clears the interrupt pending bit. */ 323 if (!(h->msi_vector || h->msix_vector)) { 324 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); 325 /* Do a read in order to flush the write to the controller 326 * (as per spec.) 327 */ 328 register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 329 } 330 331 if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) { 332 register_value = *(h->reply_pool_head); 333 (h->reply_pool_head)++; 334 h->commands_outstanding--; 335 } else { 336 register_value = FIFO_EMPTY; 337 } 338 /* Check for wraparound */ 339 if (h->reply_pool_head == (h->reply_pool + h->max_commands)) { 340 h->reply_pool_head = h->reply_pool; 341 h->reply_pool_wraparound ^= 1; 342 } 343 344 return register_value; 345} 346/* 347 * Returns true if an interrupt is pending.. 348 */ 349static bool SA5_intr_pending(ctlr_info_t *h) 350{ 351 unsigned long register_value = 352 readl(h->vaddr + SA5_INTR_STATUS); 353#ifdef CCISS_DEBUG 354 printk("cciss: intr_pending %lx\n", register_value); 355#endif /* CCISS_DEBUG */ 356 if( register_value & SA5_INTR_PENDING) 357 return 1; 358 return 0 ; 359} 360 361/* 362 * Returns true if an interrupt is pending.. 363 */ 364static bool SA5B_intr_pending(ctlr_info_t *h) 365{ 366 unsigned long register_value = 367 readl(h->vaddr + SA5_INTR_STATUS); 368#ifdef CCISS_DEBUG 369 printk("cciss: intr_pending %lx\n", register_value); 370#endif /* CCISS_DEBUG */ 371 if( register_value & SA5B_INTR_PENDING) 372 return 1; 373 return 0 ; 374} 375 376static bool SA5_performant_intr_pending(ctlr_info_t *h) 377{ 378 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 379 380 if (!register_value) 381 return false; 382 383 if (h->msi_vector || h->msix_vector) 384 return true; 385 386 /* Read outbound doorbell to flush */ 387 register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 388 return register_value & SA5_OUTDB_STATUS_PERF_BIT; 389} 390 391static struct access_method SA5_access = { 392 SA5_submit_command, 393 SA5_intr_mask, 394 SA5_fifo_full, 395 SA5_intr_pending, 396 SA5_completed, 397}; 398 399static struct access_method SA5B_access = { 400 SA5_submit_command, 401 SA5B_intr_mask, 402 SA5_fifo_full, 403 SA5B_intr_pending, 404 SA5_completed, 405}; 406 407static struct access_method SA5_performant_access = { 408 SA5_submit_command, 409 SA5_performant_intr_mask, 410 SA5_fifo_full, 411 SA5_performant_intr_pending, 412 SA5_performant_completed, 413}; 414 415struct board_type { 416 __u32 board_id; 417 char *product_name; 418 struct access_method *access; 419 int nr_cmds; /* Max cmds this kind of ctlr can handle. */ 420}; 421 422#endif /* CCISS_H */ 423