1#include <linux/init.h> 2#include <linux/bitops.h> 3#include <linux/delay.h> 4#include <linux/pci.h> 5#include <asm/dma.h> 6#include <linux/io.h> 7#include <asm/processor-cyrix.h> 8#include <asm/processor-flags.h> 9#include <linux/timer.h> 10#include <asm/pci-direct.h> 11#include <asm/tsc.h> 12 13#include "cpu.h" 14 15/* 16 * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU 17 */ 18static void __cpuinit __do_cyrix_devid(unsigned char *dir0, unsigned char *dir1) 19{ 20 unsigned char ccr2, ccr3; 21 22 /* we test for DEVID by checking whether CCR3 is writable */ 23 ccr3 = getCx86(CX86_CCR3); 24 setCx86(CX86_CCR3, ccr3 ^ 0x80); 25 getCx86(0xc0); /* dummy to change bus */ 26 27 if (getCx86(CX86_CCR3) == ccr3) { /* no DEVID regs. */ 28 ccr2 = getCx86(CX86_CCR2); 29 setCx86(CX86_CCR2, ccr2 ^ 0x04); 30 getCx86(0xc0); /* dummy */ 31 32 if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */ 33 *dir0 = 0xfd; 34 else { /* Cx486S A step */ 35 setCx86(CX86_CCR2, ccr2); 36 *dir0 = 0xfe; 37 } 38 } else { 39 setCx86(CX86_CCR3, ccr3); /* restore CCR3 */ 40 41 /* read DIR0 and DIR1 CPU registers */ 42 *dir0 = getCx86(CX86_DIR0); 43 *dir1 = getCx86(CX86_DIR1); 44 } 45} 46 47static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1) 48{ 49 unsigned long flags; 50 51 local_irq_save(flags); 52 __do_cyrix_devid(dir0, dir1); 53 local_irq_restore(flags); 54} 55/* 56 * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in 57 * order to identify the Cyrix CPU model after we're out of setup.c 58 * 59 * Actually since bugs.h doesn't even reference this perhaps someone should 60 * fix the documentation ??? 61 */ 62static unsigned char Cx86_dir0_msb __cpuinitdata = 0; 63 64static const char __cpuinitconst Cx86_model[][9] = { 65 "Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ", 66 "M II ", "Unknown" 67}; 68static const char __cpuinitconst Cx486_name[][5] = { 69 "SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx", 70 "SRx2", "DRx2" 71}; 72static const char __cpuinitconst Cx486S_name[][4] = { 73 "S", "S2", "Se", "S2e" 74}; 75static const char __cpuinitconst Cx486D_name[][4] = { 76 "DX", "DX2", "?", "?", "?", "DX4" 77}; 78static char Cx86_cb[] __cpuinitdata = "?.5x Core/Bus Clock"; 79static const char __cpuinitconst cyrix_model_mult1[] = "12??43"; 80static const char __cpuinitconst cyrix_model_mult2[] = "12233445"; 81 82 83static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c) 84{ 85 unsigned long flags; 86 87 if (Cx86_dir0_msb == 3) { 88 unsigned char ccr3, ccr5; 89 90 local_irq_save(flags); 91 ccr3 = getCx86(CX86_CCR3); 92 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ 93 ccr5 = getCx86(CX86_CCR5); 94 if (ccr5 & 2) 95 setCx86(CX86_CCR5, ccr5 & 0xfd); /* reset SLOP */ 96 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ 97 local_irq_restore(flags); 98 99 if (ccr5 & 2) { /* possible wrong calibration done */ 100 printk(KERN_INFO "Recalibrating delay loop with SLOP bit reset\n"); 101 calibrate_delay(); 102 c->loops_per_jiffy = loops_per_jiffy; 103 } 104 } 105} 106 107 108static void __cpuinit set_cx86_reorder(void) 109{ 110 u8 ccr3; 111 112 printk(KERN_INFO "Enable Memory access reorder on Cyrix/NSC processor.\n"); 113 ccr3 = getCx86(CX86_CCR3); 114 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ 115 116 /* Load/Store Serialize to mem access disable (=reorder it) */ 117 setCx86_old(CX86_PCR0, getCx86_old(CX86_PCR0) & ~0x80); 118 /* set load/store serialize from 1GB to 4GB */ 119 ccr3 |= 0xe0; 120 setCx86(CX86_CCR3, ccr3); 121} 122 123static void __cpuinit set_cx86_memwb(void) 124{ 125 printk(KERN_INFO "Enable Memory-Write-back mode on Cyrix/NSC processor.\n"); 126 127 /* CCR2 bit 2: unlock NW bit */ 128 setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) & ~0x04); 129 /* set 'Not Write-through' */ 130 write_cr0(read_cr0() | X86_CR0_NW); 131 /* CCR2 bit 2: lock NW bit and set WT1 */ 132 setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x14); 133} 134 135/* 136 * Configure later MediaGX and/or Geode processor. 137 */ 138 139static void __cpuinit geode_configure(void) 140{ 141 unsigned long flags; 142 u8 ccr3; 143 local_irq_save(flags); 144 145 /* Suspend on halt power saving and enable #SUSP pin */ 146 setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x88); 147 148 ccr3 = getCx86(CX86_CCR3); 149 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ 150 151 152 /* FPU fast, DTE cache, Mem bypass */ 153 setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x38); 154 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ 155 156 set_cx86_memwb(); 157 set_cx86_reorder(); 158 159 local_irq_restore(flags); 160} 161 162static void __cpuinit early_init_cyrix(struct cpuinfo_x86 *c) 163{ 164 unsigned char dir0, dir0_msn, dir1 = 0; 165 166 __do_cyrix_devid(&dir0, &dir1); 167 dir0_msn = dir0 >> 4; /* identifies CPU "family" */ 168 169 switch (dir0_msn) { 170 case 3: /* 6x86/6x86L */ 171 /* Emulate MTRRs using Cyrix's ARRs. */ 172 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR); 173 break; 174 case 5: /* 6x86MX/M II */ 175 /* Emulate MTRRs using Cyrix's ARRs. */ 176 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR); 177 break; 178 } 179} 180 181static void __cpuinit init_cyrix(struct cpuinfo_x86 *c) 182{ 183 unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0; 184 char *buf = c->x86_model_id; 185 const char *p = NULL; 186 187 /* 188 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 189 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 190 */ 191 clear_cpu_cap(c, 0*32+31); 192 193 /* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */ 194 if (test_cpu_cap(c, 1*32+24)) { 195 clear_cpu_cap(c, 1*32+24); 196 set_cpu_cap(c, X86_FEATURE_CXMMX); 197 } 198 199 do_cyrix_devid(&dir0, &dir1); 200 201 check_cx686_slop(c); 202 203 Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family" */ 204 dir0_lsn = dir0 & 0xf; /* model or clock multiplier */ 205 206 /* common case step number/rev -- exceptions handled below */ 207 c->x86_model = (dir1 >> 4) + 1; 208 c->x86_mask = dir1 & 0xf; 209 210 /* Now cook; the original recipe is by Channing Corn, from Cyrix. 211 * We do the same thing for each generation: we work out 212 * the model, multiplier and stepping. Black magic included, 213 * to make the silicon step/rev numbers match the printed ones. 214 */ 215 216 switch (dir0_msn) { 217 unsigned char tmp; 218 219 case 0: /* Cx486SLC/DLC/SRx/DRx */ 220 p = Cx486_name[dir0_lsn & 7]; 221 break; 222 223 case 1: /* Cx486S/DX/DX2/DX4 */ 224 p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5] 225 : Cx486S_name[dir0_lsn & 3]; 226 break; 227 228 case 2: /* 5x86 */ 229 Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5]; 230 p = Cx86_cb+2; 231 break; 232 233 case 3: /* 6x86/6x86L */ 234 Cx86_cb[1] = ' '; 235 Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5]; 236 if (dir1 > 0x21) { /* 686L */ 237 Cx86_cb[0] = 'L'; 238 p = Cx86_cb; 239 (c->x86_model)++; 240 } else /* 686 */ 241 p = Cx86_cb+1; 242 /* Emulate MTRRs using Cyrix's ARRs. */ 243 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR); 244 /* 6x86's contain this bug */ 245 c->coma_bug = 1; 246 break; 247 248 case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */ 249#ifdef CONFIG_PCI 250 { 251 u32 vendor, device; 252 253 printk(KERN_INFO "Working around Cyrix MediaGX virtual DMA bugs.\n"); 254 isa_dma_bridge_buggy = 2; 255 256 /* We do this before the PCI layer is running. However we 257 are safe here as we know the bridge must be a Cyrix 258 companion and must be present */ 259 vendor = read_pci_config_16(0, 0, 0x12, PCI_VENDOR_ID); 260 device = read_pci_config_16(0, 0, 0x12, PCI_DEVICE_ID); 261 262 /* 263 * The 5510/5520 companion chips have a funky PIT. 264 */ 265 if (vendor == PCI_VENDOR_ID_CYRIX && 266 (device == PCI_DEVICE_ID_CYRIX_5510 || 267 device == PCI_DEVICE_ID_CYRIX_5520)) 268 mark_tsc_unstable("cyrix 5510/5520 detected"); 269 } 270#endif 271 c->x86_cache_size = 16; /* Yep 16K integrated cache thats it */ 272 273 /* GXm supports extended cpuid levels 'ala' AMD */ 274 if (c->cpuid_level == 2) { 275 /* Enable cxMMX extensions (GX1 Datasheet 54) */ 276 setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7) | 1); 277 278 /* 279 * GXm : 0x30 ... 0x5f GXm datasheet 51 280 * GXlv: 0x6x GXlv datasheet 54 281 * ? : 0x7x 282 * GX1 : 0x8x GX1 datasheet 56 283 */ 284 if ((0x30 <= dir1 && dir1 <= 0x6f) || 285 (0x80 <= dir1 && dir1 <= 0x8f)) 286 geode_configure(); 287 return; 288 } else { /* MediaGX */ 289 Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4'; 290 p = Cx86_cb+2; 291 c->x86_model = (dir1 & 0x20) ? 1 : 2; 292 } 293 break; 294 295 case 5: /* 6x86MX/M II */ 296 if (dir1 > 7) { 297 dir0_msn++; /* M II */ 298 /* Enable MMX extensions (App note 108) */ 299 setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7)|1); 300 } else { 301 c->coma_bug = 1; /* 6x86MX, it has the bug. */ 302 } 303 tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0; 304 Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7]; 305 p = Cx86_cb+tmp; 306 if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20)) 307 (c->x86_model)++; 308 /* Emulate MTRRs using Cyrix's ARRs. */ 309 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR); 310 break; 311 312 case 0xf: /* Cyrix 486 without DEVID registers */ 313 switch (dir0_lsn) { 314 case 0xd: /* either a 486SLC or DLC w/o DEVID */ 315 dir0_msn = 0; 316 p = Cx486_name[(c->hard_math) ? 1 : 0]; 317 break; 318 319 case 0xe: /* a 486S A step */ 320 dir0_msn = 0; 321 p = Cx486S_name[0]; 322 break; 323 } 324 break; 325 326 default: /* unknown (shouldn't happen, we know everyone ;-) */ 327 dir0_msn = 7; 328 break; 329 } 330 strcpy(buf, Cx86_model[dir0_msn & 7]); 331 if (p) 332 strcat(buf, p); 333 return; 334} 335 336/* 337 * Handle National Semiconductor branded processors 338 */ 339static void __cpuinit init_nsc(struct cpuinfo_x86 *c) 340{ 341 /* 342 * There may be GX1 processors in the wild that are branded 343 * NSC and not Cyrix. 344 * 345 * This function only handles the GX processor, and kicks every 346 * thing else to the Cyrix init function above - that should 347 * cover any processors that might have been branded differently 348 * after NSC acquired Cyrix. 349 * 350 * If this breaks your GX1 horribly, please e-mail 351 * info-linux@ldcmail.amd.com to tell us. 352 */ 353 354 /* Handle the GX (Formally known as the GX2) */ 355 356 if (c->x86 == 5 && c->x86_model == 5) 357 cpu_detect_cache_sizes(c); 358 else 359 init_cyrix(c); 360} 361 362/* 363 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected 364 * by the fact that they preserve the flags across the division of 5/2. 365 * PII and PPro exhibit this behavior too, but they have cpuid available. 366 */ 367 368/* 369 * Perform the Cyrix 5/2 test. A Cyrix won't change 370 * the flags, while other 486 chips will. 371 */ 372static inline int test_cyrix_52div(void) 373{ 374 unsigned int test; 375 376 __asm__ __volatile__( 377 "sahf\n\t" /* clear flags (%eax = 0x0005) */ 378 "div %b2\n\t" /* divide 5 by 2 */ 379 "lahf" /* store flags into %ah */ 380 : "=a" (test) 381 : "0" (5), "q" (2) 382 : "cc"); 383 384 /* AH is 0x02 on Cyrix after the divide.. */ 385 return (unsigned char) (test >> 8) == 0x02; 386} 387 388static void __cpuinit cyrix_identify(struct cpuinfo_x86 *c) 389{ 390 /* Detect Cyrix with disabled CPUID */ 391 if (c->x86 == 4 && test_cyrix_52div()) { 392 unsigned char dir0, dir1; 393 394 strcpy(c->x86_vendor_id, "CyrixInstead"); 395 c->x86_vendor = X86_VENDOR_CYRIX; 396 397 /* Actually enable cpuid on the older cyrix */ 398 399 /* Retrieve CPU revisions */ 400 401 do_cyrix_devid(&dir0, &dir1); 402 403 dir0 >>= 4; 404 405 /* Check it is an affected model */ 406 407 if (dir0 == 5 || dir0 == 3) { 408 unsigned char ccr3; 409 unsigned long flags; 410 printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n"); 411 local_irq_save(flags); 412 ccr3 = getCx86(CX86_CCR3); 413 /* enable MAPEN */ 414 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); 415 /* enable cpuid */ 416 setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x80); 417 /* disable MAPEN */ 418 setCx86(CX86_CCR3, ccr3); 419 local_irq_restore(flags); 420 } 421 } 422} 423 424static const struct cpu_dev __cpuinitconst cyrix_cpu_dev = { 425 .c_vendor = "Cyrix", 426 .c_ident = { "CyrixInstead" }, 427 .c_early_init = early_init_cyrix, 428 .c_init = init_cyrix, 429 .c_identify = cyrix_identify, 430 .c_x86_vendor = X86_VENDOR_CYRIX, 431}; 432 433cpu_dev_register(cyrix_cpu_dev); 434 435static const struct cpu_dev __cpuinitconst nsc_cpu_dev = { 436 .c_vendor = "NSC", 437 .c_ident = { "Geode by NSC" }, 438 .c_init = init_nsc, 439 .c_x86_vendor = X86_VENDOR_NSC, 440}; 441 442cpu_dev_register(nsc_cpu_dev); 443