1#ifndef _ASM_X86_MPSPEC_H 2#define _ASM_X86_MPSPEC_H 3 4#include <linux/init.h> 5 6#include <asm/mpspec_def.h> 7#include <asm/x86_init.h> 8 9extern int apic_version[MAX_APICS]; 10extern int pic_mode; 11 12#ifdef CONFIG_X86_32 13 14/* 15 * Summit or generic (i.e. installer) kernels need lots of bus entries. 16 * Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets. 17 */ 18#if CONFIG_BASE_SMALL == 0 19# define MAX_MP_BUSSES 260 20#else 21# define MAX_MP_BUSSES 32 22#endif 23 24#define MAX_IRQ_SOURCES 256 25 26extern unsigned int def_to_bigsmp; 27extern u8 apicid_2_node[]; 28 29#ifdef CONFIG_X86_NUMAQ 30extern int mp_bus_id_to_node[MAX_MP_BUSSES]; 31extern int mp_bus_id_to_local[MAX_MP_BUSSES]; 32extern int quad_local_to_mp_bus_id [NR_CPUS/4][4]; 33#endif 34 35#define MAX_APICID 256 36 37#else /* CONFIG_X86_64: */ 38 39#define MAX_MP_BUSSES 256 40/* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */ 41#define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4) 42 43#endif /* CONFIG_X86_64 */ 44 45#if defined(CONFIG_MCA) || defined(CONFIG_EISA) 46extern int mp_bus_id_to_type[MAX_MP_BUSSES]; 47#endif 48 49extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); 50 51extern unsigned int boot_cpu_physical_apicid; 52extern unsigned int max_physical_apicid; 53extern int mpc_default_type; 54extern unsigned long mp_lapic_addr; 55 56#ifdef CONFIG_X86_LOCAL_APIC 57extern int smp_found_config; 58#else 59# define smp_found_config 0 60#endif 61 62static inline void get_smp_config(void) 63{ 64 x86_init.mpparse.get_smp_config(0); 65} 66 67static inline void early_get_smp_config(void) 68{ 69 x86_init.mpparse.get_smp_config(1); 70} 71 72static inline void find_smp_config(void) 73{ 74 x86_init.mpparse.find_smp_config(); 75} 76 77#ifdef CONFIG_X86_MPPARSE 78extern void early_reserve_e820_mpc_new(void); 79extern int enable_update_mptable; 80extern int default_mpc_apic_id(struct mpc_cpu *m); 81extern void default_smp_read_mpc_oem(struct mpc_table *mpc); 82# ifdef CONFIG_X86_IO_APIC 83extern void default_mpc_oem_bus_info(struct mpc_bus *m, char *str); 84# else 85# define default_mpc_oem_bus_info NULL 86# endif 87extern void default_find_smp_config(void); 88extern void default_get_smp_config(unsigned int early); 89#else 90static inline void early_reserve_e820_mpc_new(void) { } 91#define enable_update_mptable 0 92#define default_mpc_apic_id NULL 93#define default_smp_read_mpc_oem NULL 94#define default_mpc_oem_bus_info NULL 95#define default_find_smp_config x86_init_noop 96#define default_get_smp_config x86_init_uint_noop 97#endif 98 99void __cpuinit generic_processor_info(int apicid, int version); 100#ifdef CONFIG_ACPI 101extern void mp_register_ioapic(int id, u32 address, u32 gsi_base); 102extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, 103 u32 gsi); 104extern void mp_config_acpi_legacy_irqs(void); 105struct device; 106extern int mp_register_gsi(struct device *dev, u32 gsi, int edge_level, 107 int active_high_low); 108#endif /* CONFIG_ACPI */ 109 110#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS) 111 112struct physid_mask { 113 unsigned long mask[PHYSID_ARRAY_SIZE]; 114}; 115 116typedef struct physid_mask physid_mask_t; 117 118#define physid_set(physid, map) set_bit(physid, (map).mask) 119#define physid_clear(physid, map) clear_bit(physid, (map).mask) 120#define physid_isset(physid, map) test_bit(physid, (map).mask) 121#define physid_test_and_set(physid, map) \ 122 test_and_set_bit(physid, (map).mask) 123 124#define physids_and(dst, src1, src2) \ 125 bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS) 126 127#define physids_or(dst, src1, src2) \ 128 bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS) 129 130#define physids_clear(map) \ 131 bitmap_zero((map).mask, MAX_APICS) 132 133#define physids_complement(dst, src) \ 134 bitmap_complement((dst).mask, (src).mask, MAX_APICS) 135 136#define physids_empty(map) \ 137 bitmap_empty((map).mask, MAX_APICS) 138 139#define physids_equal(map1, map2) \ 140 bitmap_equal((map1).mask, (map2).mask, MAX_APICS) 141 142#define physids_weight(map) \ 143 bitmap_weight((map).mask, MAX_APICS) 144 145#define physids_shift_right(d, s, n) \ 146 bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS) 147 148#define physids_shift_left(d, s, n) \ 149 bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS) 150 151static inline unsigned long physids_coerce(physid_mask_t *map) 152{ 153 return map->mask[0]; 154} 155 156static inline void physids_promote(unsigned long physids, physid_mask_t *map) 157{ 158 physids_clear(*map); 159 map->mask[0] = physids; 160} 161 162/* Note: will create very large stack frames if physid_mask_t is big */ 163#define physid_mask_of_physid(physid) \ 164 ({ \ 165 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ 166 physid_set(physid, __physid_mask); \ 167 __physid_mask; \ 168 }) 169 170static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map) 171{ 172 physids_clear(*map); 173 physid_set(physid, *map); 174} 175 176#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} } 177#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} } 178 179extern physid_mask_t phys_cpu_present_map; 180 181extern int generic_mps_oem_check(struct mpc_table *, char *, char *); 182 183extern int default_acpi_madt_oem_check(char *, char *); 184 185#endif /* _ASM_X86_MPSPEC_H */ 186