1#ifndef _ASM_X86_ACPI_H 2#define _ASM_X86_ACPI_H 3 4/* 5 * Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> 6 * Copyright (C) 2001 Patrick Mochel <mochel@osdl.org> 7 * 8 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 25 */ 26#include <acpi/pdc_intel.h> 27 28#include <asm/numa.h> 29#include <asm/processor.h> 30#include <asm/mmu.h> 31#include <asm/mpspec.h> 32 33#define COMPILER_DEPENDENT_INT64 long long 34#define COMPILER_DEPENDENT_UINT64 unsigned long long 35 36/* 37 * Calling conventions: 38 * 39 * ACPI_SYSTEM_XFACE - Interfaces to host OS (handlers, threads) 40 * ACPI_EXTERNAL_XFACE - External ACPI interfaces 41 * ACPI_INTERNAL_XFACE - Internal ACPI interfaces 42 * ACPI_INTERNAL_VAR_XFACE - Internal variable-parameter list interfaces 43 */ 44#define ACPI_SYSTEM_XFACE 45#define ACPI_EXTERNAL_XFACE 46#define ACPI_INTERNAL_XFACE 47#define ACPI_INTERNAL_VAR_XFACE 48 49/* Asm macros */ 50 51#define ACPI_ASM_MACROS 52#define BREAKPOINT3 53#define ACPI_DISABLE_IRQS() local_irq_disable() 54#define ACPI_ENABLE_IRQS() local_irq_enable() 55#define ACPI_FLUSH_CPU_CACHE() wbinvd() 56 57int __acpi_acquire_global_lock(unsigned int *lock); 58int __acpi_release_global_lock(unsigned int *lock); 59 60#define ACPI_ACQUIRE_GLOBAL_LOCK(facs, Acq) \ 61 ((Acq) = __acpi_acquire_global_lock(&facs->global_lock)) 62 63#define ACPI_RELEASE_GLOBAL_LOCK(facs, Acq) \ 64 ((Acq) = __acpi_release_global_lock(&facs->global_lock)) 65 66/* 67 * Math helper asm macros 68 */ 69#define ACPI_DIV_64_BY_32(n_hi, n_lo, d32, q32, r32) \ 70 asm("divl %2;" \ 71 : "=a"(q32), "=d"(r32) \ 72 : "r"(d32), \ 73 "0"(n_lo), "1"(n_hi)) 74 75 76#define ACPI_SHIFT_RIGHT_64(n_hi, n_lo) \ 77 asm("shrl $1,%2 ;" \ 78 "rcrl $1,%3;" \ 79 : "=r"(n_hi), "=r"(n_lo) \ 80 : "0"(n_hi), "1"(n_lo)) 81 82#ifdef CONFIG_ACPI 83extern int acpi_lapic; 84extern int acpi_ioapic; 85extern int acpi_noirq; 86extern int acpi_strict; 87extern int acpi_disabled; 88extern int acpi_pci_disabled; 89extern int acpi_skip_timer_override; 90extern int acpi_use_timer_override; 91 92extern u8 acpi_sci_flags; 93extern int acpi_sci_override_gsi; 94void acpi_pic_sci_set_trigger(unsigned int, u16); 95 96static inline void disable_acpi(void) 97{ 98 acpi_disabled = 1; 99 acpi_pci_disabled = 1; 100 acpi_noirq = 1; 101} 102 103extern int acpi_gsi_to_irq(u32 gsi, unsigned int *irq); 104 105static inline void acpi_noirq_set(void) { acpi_noirq = 1; } 106static inline void acpi_disable_pci(void) 107{ 108 acpi_pci_disabled = 1; 109 acpi_noirq_set(); 110} 111 112/* routines for saving/restoring kernel state */ 113extern int acpi_save_state_mem(void); 114extern void acpi_restore_state_mem(void); 115 116extern unsigned long acpi_wakeup_address; 117 118/* early initialization routine */ 119extern void acpi_reserve_wakeup_memory(void); 120 121/* 122 * Check if the CPU can handle C2 and deeper 123 */ 124static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate) 125{ 126 /* 127 * Early models (<=5) of AMD Opterons are not supposed to go into 128 * C2 state. 129 * 130 * Steppings 0x0A and later are good 131 */ 132 if (boot_cpu_data.x86 == 0x0F && 133 boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 134 boot_cpu_data.x86_model <= 0x05 && 135 boot_cpu_data.x86_mask < 0x0A) 136 return 1; 137 else if (c1e_detected) 138 return 1; 139 else 140 return max_cstate; 141} 142 143static inline bool arch_has_acpi_pdc(void) 144{ 145 struct cpuinfo_x86 *c = &cpu_data(0); 146 return (c->x86_vendor == X86_VENDOR_INTEL || 147 c->x86_vendor == X86_VENDOR_CENTAUR); 148} 149 150static inline void arch_acpi_set_pdc_bits(u32 *buf) 151{ 152 struct cpuinfo_x86 *c = &cpu_data(0); 153 154 buf[2] |= ACPI_PDC_C_CAPABILITY_SMP; 155 156 if (cpu_has(c, X86_FEATURE_EST)) 157 buf[2] |= ACPI_PDC_EST_CAPABILITY_SWSMP; 158 159 if (cpu_has(c, X86_FEATURE_ACPI)) 160 buf[2] |= ACPI_PDC_T_FFH; 161 162 /* 163 * If mwait/monitor is unsupported, C2/C3_FFH will be disabled 164 */ 165 if (!cpu_has(c, X86_FEATURE_MWAIT)) 166 buf[2] &= ~(ACPI_PDC_C_C2C3_FFH); 167} 168 169#else /* !CONFIG_ACPI */ 170 171#define acpi_lapic 0 172#define acpi_ioapic 0 173static inline void acpi_noirq_set(void) { } 174static inline void acpi_disable_pci(void) { } 175static inline void disable_acpi(void) { } 176 177#endif /* !CONFIG_ACPI */ 178 179#define ARCH_HAS_POWER_INIT 1 180 181struct bootnode; 182 183#ifdef CONFIG_ACPI_NUMA 184extern int acpi_numa; 185extern int acpi_get_nodes(struct bootnode *physnodes); 186extern int acpi_scan_nodes(unsigned long start, unsigned long end); 187#define NR_NODE_MEMBLKS (MAX_NUMNODES*2) 188extern void acpi_fake_nodes(const struct bootnode *fake_nodes, 189 int num_nodes); 190#else 191static inline void acpi_fake_nodes(const struct bootnode *fake_nodes, 192 int num_nodes) 193{ 194} 195#endif 196 197#define acpi_unlazy_tlb(x) leave_mm(x) 198 199#endif /* _ASM_X86_ACPI_H */ 200