1/* 2 * pcic.c: MicroSPARC-IIep PCI controller support 3 * 4 * Copyright (C) 1998 V. Roganov and G. Raiko 5 * 6 * Code is derived from Ultra/PCI PSYCHO controller support, see that 7 * for author info. 8 * 9 * Support for diverse IIep based platforms by Pete Zaitcev. 10 * CP-1200 by Eric Brower. 11 */ 12 13#include <linux/kernel.h> 14#include <linux/types.h> 15#include <linux/init.h> 16#include <linux/mm.h> 17#include <linux/slab.h> 18#include <linux/jiffies.h> 19 20#include <asm/swift.h> /* for cache flushing. */ 21#include <asm/io.h> 22 23#include <linux/ctype.h> 24#include <linux/pci.h> 25#include <linux/time.h> 26#include <linux/timex.h> 27#include <linux/interrupt.h> 28 29#include <asm/irq.h> 30#include <asm/oplib.h> 31#include <asm/prom.h> 32#include <asm/pcic.h> 33#include <asm/timex.h> 34#include <asm/timer.h> 35#include <asm/uaccess.h> 36#include <asm/irq_regs.h> 37 38#include "irq.h" 39 40/* 41 * I studied different documents and many live PROMs both from 2.30 42 * family and 3.xx versions. I came to the amazing conclusion: there is 43 * absolutely no way to route interrupts in IIep systems relying on 44 * information which PROM presents. We must hardcode interrupt routing 45 * schematics. And this actually sucks. -- zaitcev 1999/05/12 46 * 47 * To find irq for a device we determine which routing map 48 * is in effect or, in other words, on which machine we are running. 49 * We use PROM name for this although other techniques may be used 50 * in special cases (Gleb reports a PROMless IIep based system). 51 * Once we know the map we take device configuration address and 52 * find PCIC pin number where INT line goes. Then we may either program 53 * preferred irq into the PCIC or supply the preexisting irq to the device. 54 */ 55struct pcic_ca2irq { 56 unsigned char busno; /* PCI bus number */ 57 unsigned char devfn; /* Configuration address */ 58 unsigned char pin; /* PCIC external interrupt pin */ 59 unsigned char irq; /* Preferred IRQ (mappable in PCIC) */ 60 unsigned int force; /* Enforce preferred IRQ */ 61}; 62 63struct pcic_sn2list { 64 char *sysname; 65 struct pcic_ca2irq *intmap; 66 int mapdim; 67}; 68 69/* 70 * JavaEngine-1 apparently has different versions. 71 * 72 * According to communications with Sun folks, for P2 build 501-4628-03: 73 * pin 0 - parallel, audio; 74 * pin 1 - Ethernet; 75 * pin 2 - su; 76 * pin 3 - PS/2 kbd and mouse. 77 * 78 * OEM manual (805-1486): 79 * pin 0: Ethernet 80 * pin 1: All EBus 81 * pin 2: IGA (unused) 82 * pin 3: Not connected 83 * OEM manual says that 501-4628 & 501-4811 are the same thing, 84 * only the latter has NAND flash in place. 85 * 86 * So far unofficial Sun wins over the OEM manual. Poor OEMs... 87 */ 88static struct pcic_ca2irq pcic_i_je1a[] = { /* 501-4811-03 */ 89 { 0, 0x00, 2, 12, 0 }, /* EBus: hogs all */ 90 { 0, 0x01, 1, 6, 1 }, /* Happy Meal */ 91 { 0, 0x80, 0, 7, 0 }, /* IGA (unused) */ 92}; 93 94static struct pcic_ca2irq pcic_i_jse[] = { 95 { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */ 96 { 0, 0x01, 1, 6, 0 }, /* hme */ 97 { 0, 0x08, 2, 9, 0 }, /* VGA - we hope not used :) */ 98 { 0, 0x10, 6, 8, 0 }, /* PCI INTA# in Slot 1 */ 99 { 0, 0x18, 7, 12, 0 }, /* PCI INTA# in Slot 2, shared w. RTC */ 100 { 0, 0x38, 4, 9, 0 }, /* All ISA devices. Read 8259. */ 101 { 0, 0x80, 5, 11, 0 }, /* EIDE */ 102 /* {0,0x88, 0,0,0} - unknown device... PMU? Probably no interrupt. */ 103 { 0, 0xA0, 4, 9, 0 }, /* USB */ 104 /* 105 * Some pins belong to non-PCI devices, we hardcode them in drivers. 106 * sun4m timers - irq 10, 14 107 * PC style RTC - pin 7, irq 4 ? 108 * Smart card, Parallel - pin 4 shared with USB, ISA 109 * audio - pin 3, irq 5 ? 110 */ 111}; 112 113/* SPARCengine-6 was the original release name of CP1200. 114 * The documentation differs between the two versions 115 */ 116static struct pcic_ca2irq pcic_i_se6[] = { 117 { 0, 0x08, 0, 2, 0 }, /* SCSI */ 118 { 0, 0x01, 1, 6, 0 }, /* HME */ 119 { 0, 0x00, 3, 13, 0 }, /* EBus */ 120}; 121 122/* 123 * Krups (courtesy of Varol Kaptan) 124 * No documentation available, but it was easy to guess 125 * because it was very similar to Espresso. 126 * 127 * pin 0 - kbd, mouse, serial; 128 * pin 1 - Ethernet; 129 * pin 2 - igs (we do not use it); 130 * pin 3 - audio; 131 * pin 4,5,6 - unused; 132 * pin 7 - RTC (from P2 onwards as David B. says). 133 */ 134static struct pcic_ca2irq pcic_i_jk[] = { 135 { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */ 136 { 0, 0x01, 1, 6, 0 }, /* hme */ 137}; 138 139/* 140 * Several entries in this list may point to the same routing map 141 * as several PROMs may be installed on the same physical board. 142 */ 143#define SN2L_INIT(name, map) \ 144 { name, map, ARRAY_SIZE(map) } 145 146static struct pcic_sn2list pcic_known_sysnames[] = { 147 SN2L_INIT("SUNW,JavaEngine1", pcic_i_je1a), /* JE1, PROM 2.32 */ 148 SN2L_INIT("SUNW,JS-E", pcic_i_jse), /* PROLL JavaStation-E */ 149 SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6), /* SPARCengine-6/CP-1200 */ 150 SN2L_INIT("SUNW,JS-NC", pcic_i_jk), /* PROLL JavaStation-NC */ 151 SN2L_INIT("SUNW,JSIIep", pcic_i_jk), /* OBP JavaStation-NC */ 152 { NULL, NULL, 0 } 153}; 154 155/* 156 * Only one PCIC per IIep, 157 * and since we have no SMP IIep, only one per system. 158 */ 159static int pcic0_up; 160static struct linux_pcic pcic0; 161 162void __iomem *pcic_regs; 163volatile int pcic_speculative; 164volatile int pcic_trapped; 165 166 167#define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3)) 168 169static int pcic_read_config_dword(unsigned int busno, unsigned int devfn, 170 int where, u32 *value) 171{ 172 struct linux_pcic *pcic; 173 unsigned long flags; 174 175 pcic = &pcic0; 176 177 local_irq_save(flags); 178 writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr); 179 pcic_speculative = 2; 180 pcic_trapped = 0; 181 *value = readl(pcic->pcic_config_space_data + (where&4)); 182 nop(); 183 if (pcic_trapped) { 184 pcic_speculative = 0; 185 local_irq_restore(flags); 186 *value = ~0; 187 return 0; 188 } 189 pcic_speculative = 0; 190 local_irq_restore(flags); 191 return 0; 192} 193 194static int pcic_read_config(struct pci_bus *bus, unsigned int devfn, 195 int where, int size, u32 *val) 196{ 197 unsigned int v; 198 199 if (bus->number != 0) return -EINVAL; 200 switch (size) { 201 case 1: 202 pcic_read_config_dword(bus->number, devfn, where&~3, &v); 203 *val = 0xff & (v >> (8*(where & 3))); 204 return 0; 205 case 2: 206 if (where&1) return -EINVAL; 207 pcic_read_config_dword(bus->number, devfn, where&~3, &v); 208 *val = 0xffff & (v >> (8*(where & 3))); 209 return 0; 210 case 4: 211 if (where&3) return -EINVAL; 212 pcic_read_config_dword(bus->number, devfn, where&~3, val); 213 return 0; 214 } 215 return -EINVAL; 216} 217 218static int pcic_write_config_dword(unsigned int busno, unsigned int devfn, 219 int where, u32 value) 220{ 221 struct linux_pcic *pcic; 222 unsigned long flags; 223 224 pcic = &pcic0; 225 226 local_irq_save(flags); 227 writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr); 228 writel(value, pcic->pcic_config_space_data + (where&4)); 229 local_irq_restore(flags); 230 return 0; 231} 232 233static int pcic_write_config(struct pci_bus *bus, unsigned int devfn, 234 int where, int size, u32 val) 235{ 236 unsigned int v; 237 238 if (bus->number != 0) return -EINVAL; 239 switch (size) { 240 case 1: 241 pcic_read_config_dword(bus->number, devfn, where&~3, &v); 242 v = (v & ~(0xff << (8*(where&3)))) | 243 ((0xff&val) << (8*(where&3))); 244 return pcic_write_config_dword(bus->number, devfn, where&~3, v); 245 case 2: 246 if (where&1) return -EINVAL; 247 pcic_read_config_dword(bus->number, devfn, where&~3, &v); 248 v = (v & ~(0xffff << (8*(where&3)))) | 249 ((0xffff&val) << (8*(where&3))); 250 return pcic_write_config_dword(bus->number, devfn, where&~3, v); 251 case 4: 252 if (where&3) return -EINVAL; 253 return pcic_write_config_dword(bus->number, devfn, where, val); 254 } 255 return -EINVAL; 256} 257 258static struct pci_ops pcic_ops = { 259 .read = pcic_read_config, 260 .write = pcic_write_config, 261}; 262 263/* 264 * On sparc64 pcibios_init() calls pci_controller_probe(). 265 * We want PCIC probed little ahead so that interrupt controller 266 * would be operational. 267 */ 268int __init pcic_probe(void) 269{ 270 struct linux_pcic *pcic; 271 struct linux_prom_registers regs[PROMREG_MAX]; 272 struct linux_pbm_info* pbm; 273 char namebuf[64]; 274 int node; 275 int err; 276 277 if (pcic0_up) { 278 prom_printf("PCIC: called twice!\n"); 279 prom_halt(); 280 } 281 pcic = &pcic0; 282 283 node = prom_getchild (prom_root_node); 284 node = prom_searchsiblings (node, "pci"); 285 if (node == 0) 286 return -ENODEV; 287 /* 288 * Map in PCIC register set, config space, and IO base 289 */ 290 err = prom_getproperty(node, "reg", (char*)regs, sizeof(regs)); 291 if (err == 0 || err == -1) { 292 prom_printf("PCIC: Error, cannot get PCIC registers " 293 "from PROM.\n"); 294 prom_halt(); 295 } 296 297 pcic0_up = 1; 298 299 pcic->pcic_res_regs.name = "pcic_registers"; 300 pcic->pcic_regs = ioremap(regs[0].phys_addr, regs[0].reg_size); 301 if (!pcic->pcic_regs) { 302 prom_printf("PCIC: Error, cannot map PCIC registers.\n"); 303 prom_halt(); 304 } 305 306 pcic->pcic_res_io.name = "pcic_io"; 307 if ((pcic->pcic_io = (unsigned long) 308 ioremap(regs[1].phys_addr, 0x10000)) == 0) { 309 prom_printf("PCIC: Error, cannot map PCIC IO Base.\n"); 310 prom_halt(); 311 } 312 313 pcic->pcic_res_cfg_addr.name = "pcic_cfg_addr"; 314 if ((pcic->pcic_config_space_addr = 315 ioremap(regs[2].phys_addr, regs[2].reg_size * 2)) == 0) { 316 prom_printf("PCIC: Error, cannot map " 317 "PCI Configuration Space Address.\n"); 318 prom_halt(); 319 } 320 321 /* 322 * Docs say three least significant bits in address and data 323 * must be the same. Thus, we need adjust size of data. 324 */ 325 pcic->pcic_res_cfg_data.name = "pcic_cfg_data"; 326 if ((pcic->pcic_config_space_data = 327 ioremap(regs[3].phys_addr, regs[3].reg_size * 2)) == 0) { 328 prom_printf("PCIC: Error, cannot map " 329 "PCI Configuration Space Data.\n"); 330 prom_halt(); 331 } 332 333 pbm = &pcic->pbm; 334 pbm->prom_node = node; 335 prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0; 336 strcpy(pbm->prom_name, namebuf); 337 338 { 339 extern volatile int t_nmi[1]; 340 extern int pcic_nmi_trap_patch[1]; 341 342 t_nmi[0] = pcic_nmi_trap_patch[0]; 343 t_nmi[1] = pcic_nmi_trap_patch[1]; 344 t_nmi[2] = pcic_nmi_trap_patch[2]; 345 t_nmi[3] = pcic_nmi_trap_patch[3]; 346 swift_flush_dcache(); 347 pcic_regs = pcic->pcic_regs; 348 } 349 350 prom_getstring(prom_root_node, "name", namebuf, 63); namebuf[63] = 0; 351 { 352 struct pcic_sn2list *p; 353 354 for (p = pcic_known_sysnames; p->sysname != NULL; p++) { 355 if (strcmp(namebuf, p->sysname) == 0) 356 break; 357 } 358 pcic->pcic_imap = p->intmap; 359 pcic->pcic_imdim = p->mapdim; 360 } 361 if (pcic->pcic_imap == NULL) { 362 /* 363 * We do not panic here for the sake of embedded systems. 364 */ 365 printk("PCIC: System %s is unknown, cannot route interrupts\n", 366 namebuf); 367 } 368 369 return 0; 370} 371 372static void __init pcic_pbm_scan_bus(struct linux_pcic *pcic) 373{ 374 struct linux_pbm_info *pbm = &pcic->pbm; 375 376 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, &pcic_ops, pbm); 377} 378 379/* 380 * Main entry point from the PCI subsystem. 381 */ 382static int __init pcic_init(void) 383{ 384 struct linux_pcic *pcic; 385 386 /* 387 * PCIC should be initialized at start of the timer. 388 * So, here we report the presence of PCIC and do some magic passes. 389 */ 390 if(!pcic0_up) 391 return 0; 392 pcic = &pcic0; 393 394 /* 395 * Switch off IOTLB translation. 396 */ 397 writeb(PCI_DVMA_CONTROL_IOTLB_DISABLE, 398 pcic->pcic_regs+PCI_DVMA_CONTROL); 399 400 writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0); 401 writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY, 402 pcic->pcic_regs+PCI_BASE_ADDRESS_0); 403 404 pcic_pbm_scan_bus(pcic); 405 406 return 0; 407} 408 409int pcic_present(void) 410{ 411 return pcic0_up; 412} 413 414static int __devinit pdev_to_pnode(struct linux_pbm_info *pbm, 415 struct pci_dev *pdev) 416{ 417 struct linux_prom_pci_registers regs[PROMREG_MAX]; 418 int err; 419 int node = prom_getchild(pbm->prom_node); 420 421 while(node) { 422 err = prom_getproperty(node, "reg", 423 (char *)®s[0], sizeof(regs)); 424 if(err != 0 && err != -1) { 425 unsigned long devfn = (regs[0].which_io >> 8) & 0xff; 426 if(devfn == pdev->devfn) 427 return node; 428 } 429 node = prom_getsibling(node); 430 } 431 return 0; 432} 433 434static inline struct pcidev_cookie *pci_devcookie_alloc(void) 435{ 436 return kmalloc(sizeof(struct pcidev_cookie), GFP_ATOMIC); 437} 438 439static void pcic_map_pci_device(struct linux_pcic *pcic, 440 struct pci_dev *dev, int node) 441{ 442 char namebuf[64]; 443 unsigned long address; 444 unsigned long flags; 445 int j; 446 447 if (node == 0 || node == -1) { 448 strcpy(namebuf, "???"); 449 } else { 450 prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0; 451 } 452 453 for (j = 0; j < 6; j++) { 454 address = dev->resource[j].start; 455 if (address == 0) break; /* are sequential */ 456 flags = dev->resource[j].flags; 457 if ((flags & IORESOURCE_IO) != 0) { 458 if (address < 0x10000) { 459 dev->resource[j].start = 460 pcic->pcic_io + address; 461 dev->resource[j].end = 1; 462 dev->resource[j].flags = 463 (flags & ~IORESOURCE_IO) | IORESOURCE_MEM; 464 } else { 465 printk("PCIC: Skipping I/O space at 0x%lx, " 466 "this will Oops if a driver attaches " 467 "device '%s' at %02x:%02x)\n", address, 468 namebuf, dev->bus->number, dev->devfn); 469 } 470 } 471 } 472} 473 474static void 475pcic_fill_irq(struct linux_pcic *pcic, struct pci_dev *dev, int node) 476{ 477 struct pcic_ca2irq *p; 478 int i, ivec; 479 char namebuf[64]; 480 481 if (node == 0 || node == -1) { 482 strcpy(namebuf, "???"); 483 } else { 484 prom_getstring(node, "name", namebuf, sizeof(namebuf)); 485 } 486 487 if ((p = pcic->pcic_imap) == 0) { 488 dev->irq = 0; 489 return; 490 } 491 for (i = 0; i < pcic->pcic_imdim; i++) { 492 if (p->busno == dev->bus->number && p->devfn == dev->devfn) 493 break; 494 p++; 495 } 496 if (i >= pcic->pcic_imdim) { 497 printk("PCIC: device %s devfn %02x:%02x not found in %d\n", 498 namebuf, dev->bus->number, dev->devfn, pcic->pcic_imdim); 499 dev->irq = 0; 500 return; 501 } 502 503 i = p->pin; 504 if (i >= 0 && i < 4) { 505 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO); 506 dev->irq = ivec >> (i << 2) & 0xF; 507 } else if (i >= 4 && i < 8) { 508 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI); 509 dev->irq = ivec >> ((i-4) << 2) & 0xF; 510 } else { /* Corrupted map */ 511 printk("PCIC: BAD PIN %d\n", i); for (;;) {} 512 } 513/* P3 */ /* printk("PCIC: device %s pin %d ivec 0x%x irq %x\n", namebuf, i, ivec, dev->irq); */ 514 515 /* 516 * dev->irq=0 means PROM did not bother to program the upper 517 * half of PCIC. This happens on JS-E with PROM 3.11, for instance. 518 */ 519 if (dev->irq == 0 || p->force) { 520 if (p->irq == 0 || p->irq >= 15) { /* Corrupted map */ 521 printk("PCIC: BAD IRQ %d\n", p->irq); for (;;) {} 522 } 523 printk("PCIC: setting irq %d at pin %d for device %02x:%02x\n", 524 p->irq, p->pin, dev->bus->number, dev->devfn); 525 dev->irq = p->irq; 526 527 i = p->pin; 528 if (i >= 4) { 529 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI); 530 ivec &= ~(0xF << ((i - 4) << 2)); 531 ivec |= p->irq << ((i - 4) << 2); 532 writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI); 533 } else { 534 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO); 535 ivec &= ~(0xF << (i << 2)); 536 ivec |= p->irq << (i << 2); 537 writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO); 538 } 539 } 540} 541 542/* 543 * Normally called from {do_}pci_scan_bus... 544 */ 545void __devinit pcibios_fixup_bus(struct pci_bus *bus) 546{ 547 struct pci_dev *dev; 548 int i, has_io, has_mem; 549 unsigned int cmd; 550 struct linux_pcic *pcic; 551 /* struct linux_pbm_info* pbm = &pcic->pbm; */ 552 int node; 553 struct pcidev_cookie *pcp; 554 555 if (!pcic0_up) { 556 printk("pcibios_fixup_bus: no PCIC\n"); 557 return; 558 } 559 pcic = &pcic0; 560 561 /* 562 * Next crud is an equivalent of pbm = pcic_bus_to_pbm(bus); 563 */ 564 if (bus->number != 0) { 565 printk("pcibios_fixup_bus: nonzero bus 0x%x\n", bus->number); 566 return; 567 } 568 569 list_for_each_entry(dev, &bus->devices, bus_list) { 570 571 /* 572 * Comment from i386 branch: 573 * There are buggy BIOSes that forget to enable I/O and memory 574 * access to PCI devices. We try to fix this, but we need to 575 * be sure that the BIOS didn't forget to assign an address 576 * to the device. [mj] 577 * OBP is a case of such BIOS :-) 578 */ 579 has_io = has_mem = 0; 580 for(i=0; i<6; i++) { 581 unsigned long f = dev->resource[i].flags; 582 if (f & IORESOURCE_IO) { 583 has_io = 1; 584 } else if (f & IORESOURCE_MEM) 585 has_mem = 1; 586 } 587 pcic_read_config(dev->bus, dev->devfn, PCI_COMMAND, 2, &cmd); 588 if (has_io && !(cmd & PCI_COMMAND_IO)) { 589 printk("PCIC: Enabling I/O for device %02x:%02x\n", 590 dev->bus->number, dev->devfn); 591 cmd |= PCI_COMMAND_IO; 592 pcic_write_config(dev->bus, dev->devfn, 593 PCI_COMMAND, 2, cmd); 594 } 595 if (has_mem && !(cmd & PCI_COMMAND_MEMORY)) { 596 printk("PCIC: Enabling memory for device %02x:%02x\n", 597 dev->bus->number, dev->devfn); 598 cmd |= PCI_COMMAND_MEMORY; 599 pcic_write_config(dev->bus, dev->devfn, 600 PCI_COMMAND, 2, cmd); 601 } 602 603 node = pdev_to_pnode(&pcic->pbm, dev); 604 if(node == 0) 605 node = -1; 606 607 /* cookies */ 608 pcp = pci_devcookie_alloc(); 609 pcp->pbm = &pcic->pbm; 610 pcp->prom_node = of_find_node_by_phandle(node); 611 dev->sysdata = pcp; 612 613 /* fixing I/O to look like memory */ 614 if ((dev->class>>16) != PCI_BASE_CLASS_BRIDGE) 615 pcic_map_pci_device(pcic, dev, node); 616 617 pcic_fill_irq(pcic, dev, node); 618 } 619} 620 621/* 622 * pcic_pin_to_irq() is exported to bus probing code 623 */ 624unsigned int 625pcic_pin_to_irq(unsigned int pin, const char *name) 626{ 627 struct linux_pcic *pcic = &pcic0; 628 unsigned int irq; 629 unsigned int ivec; 630 631 if (pin < 4) { 632 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO); 633 irq = ivec >> (pin << 2) & 0xF; 634 } else if (pin < 8) { 635 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI); 636 irq = ivec >> ((pin-4) << 2) & 0xF; 637 } else { /* Corrupted map */ 638 printk("PCIC: BAD PIN %d FOR %s\n", pin, name); 639 for (;;) {} 640 } 641/* P3 */ /* printk("PCIC: dev %s pin %d ivec 0x%x irq %x\n", name, pin, ivec, irq); */ 642 return irq; 643} 644 645/* Makes compiler happy */ 646static volatile int pcic_timer_dummy; 647 648static void pcic_clear_clock_irq(void) 649{ 650 pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT); 651} 652 653static irqreturn_t pcic_timer_handler (int irq, void *h) 654{ 655 write_seqlock(&xtime_lock); /* Dummy, to show that we remember */ 656 pcic_clear_clock_irq(); 657 do_timer(1); 658 write_sequnlock(&xtime_lock); 659#ifndef CONFIG_SMP 660 update_process_times(user_mode(get_irq_regs())); 661#endif 662 return IRQ_HANDLED; 663} 664 665#define USECS_PER_JIFFY 10000 /* We have 100HZ "standard" timer for sparc */ 666#define TICK_TIMER_LIMIT ((100*1000000/4)/100) 667 668u32 pci_gettimeoffset(void) 669{ 670 /* 671 * We divide all by 100 672 * to have microsecond resolution and to avoid overflow 673 */ 674 unsigned long count = 675 readl(pcic0.pcic_regs+PCI_SYS_COUNTER) & ~PCI_SYS_COUNTER_OVERFLOW; 676 count = ((count/100)*USECS_PER_JIFFY) / (TICK_TIMER_LIMIT/100); 677 return count * 1000; 678} 679 680 681void __init pci_time_init(void) 682{ 683 struct linux_pcic *pcic = &pcic0; 684 unsigned long v; 685 int timer_irq, irq; 686 687 do_arch_gettimeoffset = pci_gettimeoffset; 688 689 btfixup(); 690 691 writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT); 692 /* PROM should set appropriate irq */ 693 v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ); 694 timer_irq = PCI_COUNTER_IRQ_SYS(v); 695 writel (PCI_COUNTER_IRQ_SET(timer_irq, 0), 696 pcic->pcic_regs+PCI_COUNTER_IRQ); 697 irq = request_irq(timer_irq, pcic_timer_handler, 698 (IRQF_DISABLED | SA_STATIC_ALLOC), "timer", NULL); 699 if (irq) { 700 prom_printf("time_init: unable to attach IRQ%d\n", timer_irq); 701 prom_halt(); 702 } 703 local_irq_enable(); 704} 705 706 707 708/* 709 * Other archs parse arguments here. 710 */ 711char * __devinit pcibios_setup(char *str) 712{ 713 return str; 714} 715 716resource_size_t pcibios_align_resource(void *data, const struct resource *res, 717 resource_size_t size, resource_size_t align) 718{ 719 return res->start; 720} 721 722int pcibios_enable_device(struct pci_dev *pdev, int mask) 723{ 724 return 0; 725} 726 727/* 728 * NMI 729 */ 730void pcic_nmi(unsigned int pend, struct pt_regs *regs) 731{ 732 733 pend = flip_dword(pend); 734 735 if (!pcic_speculative || (pend & PCI_SYS_INT_PENDING_PIO) == 0) { 736 printk("Aiee, NMI pend 0x%x pc 0x%x spec %d, hanging\n", 737 pend, (int)regs->pc, pcic_speculative); 738 for (;;) { } 739 } 740 pcic_speculative = 0; 741 pcic_trapped = 1; 742 regs->pc = regs->npc; 743 regs->npc += 4; 744} 745 746static inline unsigned long get_irqmask(int irq_nr) 747{ 748 return 1 << irq_nr; 749} 750 751static void pcic_disable_irq(unsigned int irq_nr) 752{ 753 unsigned long mask, flags; 754 755 mask = get_irqmask(irq_nr); 756 local_irq_save(flags); 757 writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET); 758 local_irq_restore(flags); 759} 760 761static void pcic_enable_irq(unsigned int irq_nr) 762{ 763 unsigned long mask, flags; 764 765 mask = get_irqmask(irq_nr); 766 local_irq_save(flags); 767 writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR); 768 local_irq_restore(flags); 769} 770 771static void pcic_load_profile_irq(int cpu, unsigned int limit) 772{ 773 printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__); 774} 775 776/* We assume the caller has disabled local interrupts when these are called, 777 * or else very bizarre behavior will result. 778 */ 779static void pcic_disable_pil_irq(unsigned int pil) 780{ 781 writel(get_irqmask(pil), pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET); 782} 783 784static void pcic_enable_pil_irq(unsigned int pil) 785{ 786 writel(get_irqmask(pil), pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR); 787} 788 789void __init sun4m_pci_init_IRQ(void) 790{ 791 BTFIXUPSET_CALL(enable_irq, pcic_enable_irq, BTFIXUPCALL_NORM); 792 BTFIXUPSET_CALL(disable_irq, pcic_disable_irq, BTFIXUPCALL_NORM); 793 BTFIXUPSET_CALL(enable_pil_irq, pcic_enable_pil_irq, BTFIXUPCALL_NORM); 794 BTFIXUPSET_CALL(disable_pil_irq, pcic_disable_pil_irq, BTFIXUPCALL_NORM); 795 BTFIXUPSET_CALL(clear_clock_irq, pcic_clear_clock_irq, BTFIXUPCALL_NORM); 796 BTFIXUPSET_CALL(load_profile_irq, pcic_load_profile_irq, BTFIXUPCALL_NORM); 797} 798 799int pcibios_assign_resource(struct pci_dev *pdev, int resource) 800{ 801 return -ENXIO; 802} 803 804struct device_node *pci_device_to_OF_node(struct pci_dev *pdev) 805{ 806 struct pcidev_cookie *pc = pdev->sysdata; 807 808 return pc->prom_node; 809} 810EXPORT_SYMBOL(pci_device_to_OF_node); 811 812/* 813 * This probably belongs here rather than ioport.c because 814 * we do not want this crud linked into SBus kernels. 815 * Also, think for a moment about likes of floppy.c that 816 * include architecture specific parts. They may want to redefine ins/outs. 817 * 818 * We do not use horrible macros here because we want to 819 * advance pointer by sizeof(size). 820 */ 821void outsb(unsigned long addr, const void *src, unsigned long count) 822{ 823 while (count) { 824 count -= 1; 825 outb(*(const char *)src, addr); 826 src += 1; 827 /* addr += 1; */ 828 } 829} 830EXPORT_SYMBOL(outsb); 831 832void outsw(unsigned long addr, const void *src, unsigned long count) 833{ 834 while (count) { 835 count -= 2; 836 outw(*(const short *)src, addr); 837 src += 2; 838 /* addr += 2; */ 839 } 840} 841EXPORT_SYMBOL(outsw); 842 843void outsl(unsigned long addr, const void *src, unsigned long count) 844{ 845 while (count) { 846 count -= 4; 847 outl(*(const long *)src, addr); 848 src += 4; 849 /* addr += 4; */ 850 } 851} 852EXPORT_SYMBOL(outsl); 853 854void insb(unsigned long addr, void *dst, unsigned long count) 855{ 856 while (count) { 857 count -= 1; 858 *(unsigned char *)dst = inb(addr); 859 dst += 1; 860 /* addr += 1; */ 861 } 862} 863EXPORT_SYMBOL(insb); 864 865void insw(unsigned long addr, void *dst, unsigned long count) 866{ 867 while (count) { 868 count -= 2; 869 *(unsigned short *)dst = inw(addr); 870 dst += 2; 871 /* addr += 2; */ 872 } 873} 874EXPORT_SYMBOL(insw); 875 876void insl(unsigned long addr, void *dst, unsigned long count) 877{ 878 while (count) { 879 count -= 4; 880 *(unsigned long *)dst = inl(addr); 881 dst += 4; 882 /* addr += 4; */ 883 } 884} 885EXPORT_SYMBOL(insl); 886 887subsys_initcall(pcic_init); 888