1#ifndef _SPARC64_HYPERVISOR_H 2#define _SPARC64_HYPERVISOR_H 3 4/* Sun4v hypervisor interfaces and defines. 5 * 6 * Hypervisor calls are made via traps to software traps number 0x80 7 * and above. Registers %o0 to %o5 serve as argument, status, and 8 * return value registers. 9 * 10 * There are two kinds of these traps. First there are the normal 11 * "fast traps" which use software trap 0x80 and encode the function 12 * to invoke by number in register %o5. Argument and return value 13 * handling is as follows: 14 * 15 * ----------------------------------------------- 16 * | %o5 | function number | undefined | 17 * | %o0 | argument 0 | return status | 18 * | %o1 | argument 1 | return value 1 | 19 * | %o2 | argument 2 | return value 2 | 20 * | %o3 | argument 3 | return value 3 | 21 * | %o4 | argument 4 | return value 4 | 22 * ----------------------------------------------- 23 * 24 * The second type are "hyper-fast traps" which encode the function 25 * number in the software trap number itself. So these use trap 26 * numbers > 0x80. The register usage for hyper-fast traps is as 27 * follows: 28 * 29 * ----------------------------------------------- 30 * | %o0 | argument 0 | return status | 31 * | %o1 | argument 1 | return value 1 | 32 * | %o2 | argument 2 | return value 2 | 33 * | %o3 | argument 3 | return value 3 | 34 * | %o4 | argument 4 | return value 4 | 35 * ----------------------------------------------- 36 * 37 * Registers providing explicit arguments to the hypervisor calls 38 * are volatile across the call. Upon return their values are 39 * undefined unless explicitly specified as containing a particular 40 * return value by the specific call. The return status is always 41 * returned in register %o0, zero indicates a successful execution of 42 * the hypervisor call and other values indicate an error status as 43 * defined below. So, for example, if a hyper-fast trap takes 44 * arguments 0, 1, and 2, then %o0, %o1, and %o2 are volatile across 45 * the call and %o3, %o4, and %o5 would be preserved. 46 * 47 * If the hypervisor trap is invalid, or the fast trap function number 48 * is invalid, HV_EBADTRAP will be returned in %o0. Also, all 64-bits 49 * of the argument and return values are significant. 50 */ 51 52/* Trap numbers. */ 53#define HV_FAST_TRAP 0x80 54#define HV_MMU_MAP_ADDR_TRAP 0x83 55#define HV_MMU_UNMAP_ADDR_TRAP 0x84 56#define HV_TTRACE_ADDENTRY_TRAP 0x85 57#define HV_CORE_TRAP 0xff 58 59/* Error codes. */ 60#define HV_EOK 0 /* Successful return */ 61#define HV_ENOCPU 1 /* Invalid CPU id */ 62#define HV_ENORADDR 2 /* Invalid real address */ 63#define HV_ENOINTR 3 /* Invalid interrupt id */ 64#define HV_EBADPGSZ 4 /* Invalid pagesize encoding */ 65#define HV_EBADTSB 5 /* Invalid TSB description */ 66#define HV_EINVAL 6 /* Invalid argument */ 67#define HV_EBADTRAP 7 /* Invalid function number */ 68#define HV_EBADALIGN 8 /* Invalid address alignment */ 69#define HV_EWOULDBLOCK 9 /* Cannot complete w/o blocking */ 70#define HV_ENOACCESS 10 /* No access to resource */ 71#define HV_EIO 11 /* I/O error */ 72#define HV_ECPUERROR 12 /* CPU in error state */ 73#define HV_ENOTSUPPORTED 13 /* Function not supported */ 74#define HV_ENOMAP 14 /* No mapping found */ 75#define HV_ETOOMANY 15 /* Too many items specified */ 76#define HV_ECHANNEL 16 /* Invalid LDC channel */ 77#define HV_EBUSY 17 /* Resource busy */ 78 79/* mach_exit() 80 * TRAP: HV_FAST_TRAP 81 * FUNCTION: HV_FAST_MACH_EXIT 82 * ARG0: exit code 83 * ERRORS: This service does not return. 84 * 85 * Stop all CPUs in the virtual domain and place them into the stopped 86 * state. The 64-bit exit code may be passed to a service entity as 87 * the domain's exit status. On systems without a service entity, the 88 * domain will undergo a reset, and the boot firmware will be 89 * reloaded. 90 * 91 * This function will never return to the guest that invokes it. 92 * 93 * Note: By convention an exit code of zero denotes a successful exit by 94 * the guest code. A non-zero exit code denotes a guest specific 95 * error indication. 96 * 97 */ 98#define HV_FAST_MACH_EXIT 0x00 99 100#ifndef __ASSEMBLY__ 101extern void sun4v_mach_exit(unsigned long exit_code); 102#endif 103 104/* Domain services. */ 105 106/* mach_desc() 107 * TRAP: HV_FAST_TRAP 108 * FUNCTION: HV_FAST_MACH_DESC 109 * ARG0: buffer 110 * ARG1: length 111 * RET0: status 112 * RET1: length 113 * ERRORS: HV_EBADALIGN Buffer is badly aligned 114 * HV_ENORADDR Buffer is to an illegal real address. 115 * HV_EINVAL Buffer length is too small for complete 116 * machine description. 117 * 118 * Copy the most current machine description into the buffer indicated 119 * by the real address in ARG0. The buffer provided must be 16 byte 120 * aligned. Upon success or HV_EINVAL, this service returns the 121 * actual size of the machine description in the RET1 return value. 122 * 123 * Note: A method of determining the appropriate buffer size for the 124 * machine description is to first call this service with a buffer 125 * length of 0 bytes. 126 */ 127#define HV_FAST_MACH_DESC 0x01 128 129#ifndef __ASSEMBLY__ 130extern unsigned long sun4v_mach_desc(unsigned long buffer_pa, 131 unsigned long buf_len, 132 unsigned long *real_buf_len); 133#endif 134 135/* mach_sir() 136 * TRAP: HV_FAST_TRAP 137 * FUNCTION: HV_FAST_MACH_SIR 138 * ERRORS: This service does not return. 139 * 140 * Perform a software initiated reset of the virtual machine domain. 141 * All CPUs are captured as soon as possible, all hardware devices are 142 * returned to the entry default state, and the domain is restarted at 143 * the SIR (trap type 0x04) real trap table (RTBA) entry point on one 144 * of the CPUs. The single CPU restarted is selected as determined by 145 * platform specific policy. Memory is preserved across this 146 * operation. 147 */ 148#define HV_FAST_MACH_SIR 0x02 149 150#ifndef __ASSEMBLY__ 151extern void sun4v_mach_sir(void); 152#endif 153 154/* mach_set_watchdog() 155 * TRAP: HV_FAST_TRAP 156 * FUNCTION: HV_FAST_MACH_SET_WATCHDOG 157 * ARG0: timeout in milliseconds 158 * RET0: status 159 * RET1: time remaining in milliseconds 160 * 161 * A guest uses this API to set a watchdog timer. Once the gues has set 162 * the timer, it must call the timer service again either to disable or 163 * postpone the expiration. If the timer expires before being reset or 164 * disabled, then the hypervisor take a platform specific action leading 165 * to guest termination within a bounded time period. The platform action 166 * may include recovery actions such as reporting the expiration to a 167 * Service Processor, and/or automatically restarting the gues. 168 * 169 * The 'timeout' parameter is specified in milliseconds, however the 170 * implementated granularity is given by the 'watchdog-resolution' 171 * property in the 'platform' node of the guest's machine description. 172 * The largest allowed timeout value is specified by the 173 * 'watchdog-max-timeout' property of the 'platform' node. 174 * 175 * If the 'timeout' argument is not zero, the watchdog timer is set to 176 * expire after a minimum of 'timeout' milliseconds. 177 * 178 * If the 'timeout' argument is zero, the watchdog timer is disabled. 179 * 180 * If the 'timeout' value exceeds the value of the 'max-watchdog-timeout' 181 * property, the hypervisor leaves the watchdog timer state unchanged, 182 * and returns a status of EINVAL. 183 * 184 * The 'time remaining' return value is valid regardless of whether the 185 * return status is EOK or EINVAL. A non-zero return value indicates the 186 * number of milliseconds that were remaining until the timer was to expire. 187 * If less than one millisecond remains, the return value is '1'. If the 188 * watchdog timer was disabled at the time of the call, the return value is 189 * zero. 190 * 191 * If the hypervisor cannot support the exact timeout value requested, but 192 * can support a larger timeout value, the hypervisor may round the actual 193 * timeout to a value larger than the requested timeout, consequently the 194 * 'time remaining' return value may be larger than the previously requested 195 * timeout value. 196 * 197 * Any guest OS debugger should be aware that the watchdog service may be in 198 * use. Consequently, it is recommended that the watchdog service is 199 * disabled upon debugger entry (e.g. reaching a breakpoint), and then 200 * re-enabled upon returning to normal execution. The API has been designed 201 * with this in mind, and the 'time remaining' result of the disable call may 202 * be used directly as the timeout argument of the re-enable call. 203 */ 204#define HV_FAST_MACH_SET_WATCHDOG 0x05 205 206#ifndef __ASSEMBLY__ 207extern unsigned long sun4v_mach_set_watchdog(unsigned long timeout, 208 unsigned long *orig_timeout); 209#endif 210 211/* CPU services. 212 * 213 * CPUs represent devices that can execute software threads. A single 214 * chip that contains multiple cores or strands is represented as 215 * multiple CPUs with unique CPU identifiers. CPUs are exported to 216 * OBP via the machine description (and to the OS via the OBP device 217 * tree). CPUs are always in one of three states: stopped, running, 218 * or error. 219 * 220 * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a 221 * CPU within a logical domain. Operations that are to be performed 222 * on multiple CPUs specify them via a CPU list. A CPU list is an 223 * array in real memory, of which each 16-bit word is a CPU ID. CPU 224 * lists are passed through the API as two arguments. The first is 225 * the number of entries (16-bit words) in the CPU list, and the 226 * second is the (real address) pointer to the CPU ID list. 227 */ 228 229/* cpu_start() 230 * TRAP: HV_FAST_TRAP 231 * FUNCTION: HV_FAST_CPU_START 232 * ARG0: CPU ID 233 * ARG1: PC 234 * ARG2: RTBA 235 * ARG3: target ARG0 236 * RET0: status 237 * ERRORS: ENOCPU Invalid CPU ID 238 * EINVAL Target CPU ID is not in the stopped state 239 * ENORADDR Invalid PC or RTBA real address 240 * EBADALIGN Unaligned PC or unaligned RTBA 241 * EWOULDBLOCK Starting resources are not available 242 * 243 * Start CPU with given CPU ID with PC in %pc and with a real trap 244 * base address value of RTBA. The indicated CPU must be in the 245 * stopped state. The supplied RTBA must be aligned on a 256 byte 246 * boundary. On successful completion, the specified CPU will be in 247 * the running state and will be supplied with "target ARG0" in %o0 248 * and RTBA in %tba. 249 */ 250#define HV_FAST_CPU_START 0x10 251 252#ifndef __ASSEMBLY__ 253extern unsigned long sun4v_cpu_start(unsigned long cpuid, 254 unsigned long pc, 255 unsigned long rtba, 256 unsigned long arg0); 257#endif 258 259/* cpu_stop() 260 * TRAP: HV_FAST_TRAP 261 * FUNCTION: HV_FAST_CPU_STOP 262 * ARG0: CPU ID 263 * RET0: status 264 * ERRORS: ENOCPU Invalid CPU ID 265 * EINVAL Target CPU ID is the current cpu 266 * EINVAL Target CPU ID is not in the running state 267 * EWOULDBLOCK Stopping resources are not available 268 * ENOTSUPPORTED Not supported on this platform 269 * 270 * The specified CPU is stopped. The indicated CPU must be in the 271 * running state. On completion, it will be in the stopped state. It 272 * is not legal to stop the current CPU. 273 * 274 * Note: As this service cannot be used to stop the current cpu, this service 275 * may not be used to stop the last running CPU in a domain. To stop 276 * and exit a running domain, a guest must use the mach_exit() service. 277 */ 278#define HV_FAST_CPU_STOP 0x11 279 280#ifndef __ASSEMBLY__ 281extern unsigned long sun4v_cpu_stop(unsigned long cpuid); 282#endif 283 284/* cpu_yield() 285 * TRAP: HV_FAST_TRAP 286 * FUNCTION: HV_FAST_CPU_YIELD 287 * RET0: status 288 * ERRORS: No possible error. 289 * 290 * Suspend execution on the current CPU. Execution will resume when 291 * an interrupt (device, %stick_compare, or cross-call) is targeted to 292 * the CPU. On some CPUs, this API may be used by the hypervisor to 293 * save power by disabling hardware strands. 294 */ 295#define HV_FAST_CPU_YIELD 0x12 296 297#ifndef __ASSEMBLY__ 298extern unsigned long sun4v_cpu_yield(void); 299#endif 300 301/* cpu_qconf() 302 * TRAP: HV_FAST_TRAP 303 * FUNCTION: HV_FAST_CPU_QCONF 304 * ARG0: queue 305 * ARG1: base real address 306 * ARG2: number of entries 307 * RET0: status 308 * ERRORS: ENORADDR Invalid base real address 309 * EINVAL Invalid queue or number of entries is less 310 * than 2 or too large. 311 * EBADALIGN Base real address is not correctly aligned 312 * for size. 313 * 314 * Configure the given queue to be placed at the given base real 315 * address, with the given number of entries. The number of entries 316 * must be a power of 2. The base real address must be aligned 317 * exactly to match the queue size. Each queue entry is 64 bytes 318 * long, so for example a 32 entry queue must be aligned on a 2048 319 * byte real address boundary. 320 * 321 * The specified queue is unconfigured if the number of entries is given 322 * as zero. 323 * 324 * For the current version of this API service, the argument queue is defined 325 * as follows: 326 * 327 * queue description 328 * ----- ------------------------- 329 * 0x3c cpu mondo queue 330 * 0x3d device mondo queue 331 * 0x3e resumable error queue 332 * 0x3f non-resumable error queue 333 * 334 * Note: The maximum number of entries for each queue for a specific cpu may 335 * be determined from the machine description. 336 */ 337#define HV_FAST_CPU_QCONF 0x14 338#define HV_CPU_QUEUE_CPU_MONDO 0x3c 339#define HV_CPU_QUEUE_DEVICE_MONDO 0x3d 340#define HV_CPU_QUEUE_RES_ERROR 0x3e 341#define HV_CPU_QUEUE_NONRES_ERROR 0x3f 342 343#ifndef __ASSEMBLY__ 344extern unsigned long sun4v_cpu_qconf(unsigned long type, 345 unsigned long queue_paddr, 346 unsigned long num_queue_entries); 347#endif 348 349/* cpu_qinfo() 350 * TRAP: HV_FAST_TRAP 351 * FUNCTION: HV_FAST_CPU_QINFO 352 * ARG0: queue 353 * RET0: status 354 * RET1: base real address 355 * RET1: number of entries 356 * ERRORS: EINVAL Invalid queue 357 * 358 * Return the configuration info for the given queue. The base real 359 * address and number of entries of the defined queue are returned. 360 * The queue argument values are the same as for cpu_qconf() above. 361 * 362 * If the specified queue is a valid queue number, but no queue has 363 * been defined, the number of entries will be set to zero and the 364 * base real address returned is undefined. 365 */ 366#define HV_FAST_CPU_QINFO 0x15 367 368/* cpu_mondo_send() 369 * TRAP: HV_FAST_TRAP 370 * FUNCTION: HV_FAST_CPU_MONDO_SEND 371 * ARG0-1: CPU list 372 * ARG2: data real address 373 * RET0: status 374 * ERRORS: EBADALIGN Mondo data is not 64-byte aligned or CPU list 375 * is not 2-byte aligned. 376 * ENORADDR Invalid data mondo address, or invalid cpu list 377 * address. 378 * ENOCPU Invalid cpu in CPU list 379 * EWOULDBLOCK Some or all of the listed CPUs did not receive 380 * the mondo 381 * ECPUERROR One or more of the listed CPUs are in error 382 * state, use HV_FAST_CPU_STATE to see which ones 383 * EINVAL CPU list includes caller's CPU ID 384 * 385 * Send a mondo interrupt to the CPUs in the given CPU list with the 386 * 64-bytes at the given data real address. The data must be 64-byte 387 * aligned. The mondo data will be delivered to the cpu_mondo queues 388 * of the recipient CPUs. 389 * 390 * In all cases, error or not, the CPUs in the CPU list to which the 391 * mondo has been successfully delivered will be indicated by having 392 * their entry in CPU list updated with the value 0xffff. 393 */ 394#define HV_FAST_CPU_MONDO_SEND 0x42 395 396#ifndef __ASSEMBLY__ 397extern unsigned long sun4v_cpu_mondo_send(unsigned long cpu_count, unsigned long cpu_list_pa, unsigned long mondo_block_pa); 398#endif 399 400/* cpu_myid() 401 * TRAP: HV_FAST_TRAP 402 * FUNCTION: HV_FAST_CPU_MYID 403 * RET0: status 404 * RET1: CPU ID 405 * ERRORS: No errors defined. 406 * 407 * Return the hypervisor ID handle for the current CPU. Use by a 408 * virtual CPU to discover it's own identity. 409 */ 410#define HV_FAST_CPU_MYID 0x16 411 412/* cpu_state() 413 * TRAP: HV_FAST_TRAP 414 * FUNCTION: HV_FAST_CPU_STATE 415 * ARG0: CPU ID 416 * RET0: status 417 * RET1: state 418 * ERRORS: ENOCPU Invalid CPU ID 419 * 420 * Retrieve the current state of the CPU with the given CPU ID. 421 */ 422#define HV_FAST_CPU_STATE 0x17 423#define HV_CPU_STATE_STOPPED 0x01 424#define HV_CPU_STATE_RUNNING 0x02 425#define HV_CPU_STATE_ERROR 0x03 426 427#ifndef __ASSEMBLY__ 428extern long sun4v_cpu_state(unsigned long cpuid); 429#endif 430 431/* cpu_set_rtba() 432 * TRAP: HV_FAST_TRAP 433 * FUNCTION: HV_FAST_CPU_SET_RTBA 434 * ARG0: RTBA 435 * RET0: status 436 * RET1: previous RTBA 437 * ERRORS: ENORADDR Invalid RTBA real address 438 * EBADALIGN RTBA is incorrectly aligned for a trap table 439 * 440 * Set the real trap base address of the local cpu to the given RTBA. 441 * The supplied RTBA must be aligned on a 256 byte boundary. Upon 442 * success the previous value of the RTBA is returned in RET1. 443 * 444 * Note: This service does not affect %tba 445 */ 446#define HV_FAST_CPU_SET_RTBA 0x18 447 448/* cpu_set_rtba() 449 * TRAP: HV_FAST_TRAP 450 * FUNCTION: HV_FAST_CPU_GET_RTBA 451 * RET0: status 452 * RET1: previous RTBA 453 * ERRORS: No possible error. 454 * 455 * Returns the current value of RTBA in RET1. 456 */ 457#define HV_FAST_CPU_GET_RTBA 0x19 458 459/* MMU services. 460 * 461 * Layout of a TSB description for mmu_tsb_ctx{,non}0() calls. 462 */ 463#ifndef __ASSEMBLY__ 464struct hv_tsb_descr { 465 unsigned short pgsz_idx; 466 unsigned short assoc; 467 unsigned int num_ttes; /* in TTEs */ 468 unsigned int ctx_idx; 469 unsigned int pgsz_mask; 470 unsigned long tsb_base; 471 unsigned long resv; 472}; 473#endif 474#define HV_TSB_DESCR_PGSZ_IDX_OFFSET 0x00 475#define HV_TSB_DESCR_ASSOC_OFFSET 0x02 476#define HV_TSB_DESCR_NUM_TTES_OFFSET 0x04 477#define HV_TSB_DESCR_CTX_IDX_OFFSET 0x08 478#define HV_TSB_DESCR_PGSZ_MASK_OFFSET 0x0c 479#define HV_TSB_DESCR_TSB_BASE_OFFSET 0x10 480#define HV_TSB_DESCR_RESV_OFFSET 0x18 481 482/* Page size bitmask. */ 483#define HV_PGSZ_MASK_8K (1 << 0) 484#define HV_PGSZ_MASK_64K (1 << 1) 485#define HV_PGSZ_MASK_512K (1 << 2) 486#define HV_PGSZ_MASK_4MB (1 << 3) 487#define HV_PGSZ_MASK_32MB (1 << 4) 488#define HV_PGSZ_MASK_256MB (1 << 5) 489#define HV_PGSZ_MASK_2GB (1 << 6) 490#define HV_PGSZ_MASK_16GB (1 << 7) 491 492/* Page size index. The value given in the TSB descriptor must correspond 493 * to the smallest page size specified in the pgsz_mask page size bitmask. 494 */ 495#define HV_PGSZ_IDX_8K 0 496#define HV_PGSZ_IDX_64K 1 497#define HV_PGSZ_IDX_512K 2 498#define HV_PGSZ_IDX_4MB 3 499#define HV_PGSZ_IDX_32MB 4 500#define HV_PGSZ_IDX_256MB 5 501#define HV_PGSZ_IDX_2GB 6 502#define HV_PGSZ_IDX_16GB 7 503 504/* MMU fault status area. 505 * 506 * MMU related faults have their status and fault address information 507 * placed into a memory region made available by privileged code. Each 508 * virtual processor must make a mmu_fault_area_conf() call to tell the 509 * hypervisor where that processor's fault status should be stored. 510 * 511 * The fault status block is a multiple of 64-bytes and must be aligned 512 * on a 64-byte boundary. 513 */ 514#ifndef __ASSEMBLY__ 515struct hv_fault_status { 516 unsigned long i_fault_type; 517 unsigned long i_fault_addr; 518 unsigned long i_fault_ctx; 519 unsigned long i_reserved[5]; 520 unsigned long d_fault_type; 521 unsigned long d_fault_addr; 522 unsigned long d_fault_ctx; 523 unsigned long d_reserved[5]; 524}; 525#endif 526#define HV_FAULT_I_TYPE_OFFSET 0x00 527#define HV_FAULT_I_ADDR_OFFSET 0x08 528#define HV_FAULT_I_CTX_OFFSET 0x10 529#define HV_FAULT_D_TYPE_OFFSET 0x40 530#define HV_FAULT_D_ADDR_OFFSET 0x48 531#define HV_FAULT_D_CTX_OFFSET 0x50 532 533#define HV_FAULT_TYPE_FAST_MISS 1 534#define HV_FAULT_TYPE_FAST_PROT 2 535#define HV_FAULT_TYPE_MMU_MISS 3 536#define HV_FAULT_TYPE_INV_RA 4 537#define HV_FAULT_TYPE_PRIV_VIOL 5 538#define HV_FAULT_TYPE_PROT_VIOL 6 539#define HV_FAULT_TYPE_NFO 7 540#define HV_FAULT_TYPE_NFO_SEFF 8 541#define HV_FAULT_TYPE_INV_VA 9 542#define HV_FAULT_TYPE_INV_ASI 10 543#define HV_FAULT_TYPE_NC_ATOMIC 11 544#define HV_FAULT_TYPE_PRIV_ACT 12 545#define HV_FAULT_TYPE_RESV1 13 546#define HV_FAULT_TYPE_UNALIGNED 14 547#define HV_FAULT_TYPE_INV_PGSZ 15 548/* Values 16 --> -2 are reserved. */ 549#define HV_FAULT_TYPE_MULTIPLE -1 550 551/* Flags argument for mmu_{map,unmap}_addr(), mmu_demap_{page,context,all}(), 552 * and mmu_{map,unmap}_perm_addr(). 553 */ 554#define HV_MMU_DMMU 0x01 555#define HV_MMU_IMMU 0x02 556#define HV_MMU_ALL (HV_MMU_DMMU | HV_MMU_IMMU) 557 558/* mmu_map_addr() 559 * TRAP: HV_MMU_MAP_ADDR_TRAP 560 * ARG0: virtual address 561 * ARG1: mmu context 562 * ARG2: TTE 563 * ARG3: flags (HV_MMU_{IMMU,DMMU}) 564 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags 565 * EBADPGSZ Invalid page size value 566 * ENORADDR Invalid real address in TTE 567 * 568 * Create a non-permanent mapping using the given TTE, virtual 569 * address, and mmu context. The flags argument determines which 570 * (data, or instruction, or both) TLB the mapping gets loaded into. 571 * 572 * The behavior is undefined if the valid bit is clear in the TTE. 573 * 574 * Note: This API call is for privileged code to specify temporary translation 575 * mappings without the need to create and manage a TSB. 576 */ 577 578/* mmu_unmap_addr() 579 * TRAP: HV_MMU_UNMAP_ADDR_TRAP 580 * ARG0: virtual address 581 * ARG1: mmu context 582 * ARG2: flags (HV_MMU_{IMMU,DMMU}) 583 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags 584 * 585 * Demaps the given virtual address in the given mmu context on this 586 * CPU. This function is intended to be used to demap pages mapped 587 * with mmu_map_addr. This service is equivalent to invoking 588 * mmu_demap_page() with only the current CPU in the CPU list. The 589 * flags argument determines which (data, or instruction, or both) TLB 590 * the mapping gets unmapped from. 591 * 592 * Attempting to perform an unmap operation for a previously defined 593 * permanent mapping will have undefined results. 594 */ 595 596/* mmu_tsb_ctx0() 597 * TRAP: HV_FAST_TRAP 598 * FUNCTION: HV_FAST_MMU_TSB_CTX0 599 * ARG0: number of TSB descriptions 600 * ARG1: TSB descriptions pointer 601 * RET0: status 602 * ERRORS: ENORADDR Invalid TSB descriptions pointer or 603 * TSB base within a descriptor 604 * EBADALIGN TSB descriptions pointer is not aligned 605 * to an 8-byte boundary, or TSB base 606 * within a descriptor is not aligned for 607 * the given TSB size 608 * EBADPGSZ Invalid page size in a TSB descriptor 609 * EBADTSB Invalid associativity or size in a TSB 610 * descriptor 611 * EINVAL Invalid number of TSB descriptions, or 612 * invalid context index in a TSB 613 * descriptor, or index page size not 614 * equal to smallest page size in page 615 * size bitmask field. 616 * 617 * Configures the TSBs for the current CPU for virtual addresses with 618 * context zero. The TSB descriptions pointer is a pointer to an 619 * array of the given number of TSB descriptions. 620 * 621 * Note: The maximum number of TSBs available to a virtual CPU is given by the 622 * mmu-max-#tsbs property of the cpu's corresponding "cpu" node in the 623 * machine description. 624 */ 625#define HV_FAST_MMU_TSB_CTX0 0x20 626 627#ifndef __ASSEMBLY__ 628extern unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions, 629 unsigned long tsb_desc_ra); 630#endif 631 632/* mmu_tsb_ctxnon0() 633 * TRAP: HV_FAST_TRAP 634 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0 635 * ARG0: number of TSB descriptions 636 * ARG1: TSB descriptions pointer 637 * RET0: status 638 * ERRORS: Same as for mmu_tsb_ctx0() above. 639 * 640 * Configures the TSBs for the current CPU for virtual addresses with 641 * non-zero contexts. The TSB descriptions pointer is a pointer to an 642 * array of the given number of TSB descriptions. 643 * 644 * Note: A maximum of 16 TSBs may be specified in the TSB description list. 645 */ 646#define HV_FAST_MMU_TSB_CTXNON0 0x21 647 648/* mmu_demap_page() 649 * TRAP: HV_FAST_TRAP 650 * FUNCTION: HV_FAST_MMU_DEMAP_PAGE 651 * ARG0: reserved, must be zero 652 * ARG1: reserved, must be zero 653 * ARG2: virtual address 654 * ARG3: mmu context 655 * ARG4: flags (HV_MMU_{IMMU,DMMU}) 656 * RET0: status 657 * ERRORS: EINVAL Invalid virutal address, context, or 658 * flags value 659 * ENOTSUPPORTED ARG0 or ARG1 is non-zero 660 * 661 * Demaps any page mapping of the given virtual address in the given 662 * mmu context for the current virtual CPU. Any virtually tagged 663 * caches are guaranteed to be kept consistent. The flags argument 664 * determines which TLB (instruction, or data, or both) participate in 665 * the operation. 666 * 667 * ARG0 and ARG1 are both reserved and must be set to zero. 668 */ 669#define HV_FAST_MMU_DEMAP_PAGE 0x22 670 671/* mmu_demap_ctx() 672 * TRAP: HV_FAST_TRAP 673 * FUNCTION: HV_FAST_MMU_DEMAP_CTX 674 * ARG0: reserved, must be zero 675 * ARG1: reserved, must be zero 676 * ARG2: mmu context 677 * ARG3: flags (HV_MMU_{IMMU,DMMU}) 678 * RET0: status 679 * ERRORS: EINVAL Invalid context or flags value 680 * ENOTSUPPORTED ARG0 or ARG1 is non-zero 681 * 682 * Demaps all non-permanent virtual page mappings previously specified 683 * for the given context for the current virtual CPU. Any virtual 684 * tagged caches are guaranteed to be kept consistent. The flags 685 * argument determines which TLB (instruction, or data, or both) 686 * participate in the operation. 687 * 688 * ARG0 and ARG1 are both reserved and must be set to zero. 689 */ 690#define HV_FAST_MMU_DEMAP_CTX 0x23 691 692/* mmu_demap_all() 693 * TRAP: HV_FAST_TRAP 694 * FUNCTION: HV_FAST_MMU_DEMAP_ALL 695 * ARG0: reserved, must be zero 696 * ARG1: reserved, must be zero 697 * ARG2: flags (HV_MMU_{IMMU,DMMU}) 698 * RET0: status 699 * ERRORS: EINVAL Invalid flags value 700 * ENOTSUPPORTED ARG0 or ARG1 is non-zero 701 * 702 * Demaps all non-permanent virtual page mappings previously specified 703 * for the current virtual CPU. Any virtual tagged caches are 704 * guaranteed to be kept consistent. The flags argument determines 705 * which TLB (instruction, or data, or both) participate in the 706 * operation. 707 * 708 * ARG0 and ARG1 are both reserved and must be set to zero. 709 */ 710#define HV_FAST_MMU_DEMAP_ALL 0x24 711 712#ifndef __ASSEMBLY__ 713extern void sun4v_mmu_demap_all(void); 714#endif 715 716/* mmu_map_perm_addr() 717 * TRAP: HV_FAST_TRAP 718 * FUNCTION: HV_FAST_MMU_MAP_PERM_ADDR 719 * ARG0: virtual address 720 * ARG1: reserved, must be zero 721 * ARG2: TTE 722 * ARG3: flags (HV_MMU_{IMMU,DMMU}) 723 * RET0: status 724 * ERRORS: EINVAL Invalid virutal address or flags value 725 * EBADPGSZ Invalid page size value 726 * ENORADDR Invalid real address in TTE 727 * ETOOMANY Too many mappings (max of 8 reached) 728 * 729 * Create a permanent mapping using the given TTE and virtual address 730 * for context 0 on the calling virtual CPU. A maximum of 8 such 731 * permanent mappings may be specified by privileged code. Mappings 732 * may be removed with mmu_unmap_perm_addr(). 733 * 734 * The behavior is undefined if a TTE with the valid bit clear is given. 735 * 736 * Note: This call is used to specify address space mappings for which 737 * privileged code does not expect to receive misses. For example, 738 * this mechanism can be used to map kernel nucleus code and data. 739 */ 740#define HV_FAST_MMU_MAP_PERM_ADDR 0x25 741 742#ifndef __ASSEMBLY__ 743extern unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr, 744 unsigned long set_to_zero, 745 unsigned long tte, 746 unsigned long flags); 747#endif 748 749/* mmu_fault_area_conf() 750 * TRAP: HV_FAST_TRAP 751 * FUNCTION: HV_FAST_MMU_FAULT_AREA_CONF 752 * ARG0: real address 753 * RET0: status 754 * RET1: previous mmu fault area real address 755 * ERRORS: ENORADDR Invalid real address 756 * EBADALIGN Invalid alignment for fault area 757 * 758 * Configure the MMU fault status area for the calling CPU. A 64-byte 759 * aligned real address specifies where MMU fault status information 760 * is placed. The return value is the previously specified area, or 0 761 * for the first invocation. Specifying a fault area at real address 762 * 0 is not allowed. 763 */ 764#define HV_FAST_MMU_FAULT_AREA_CONF 0x26 765 766/* mmu_enable() 767 * TRAP: HV_FAST_TRAP 768 * FUNCTION: HV_FAST_MMU_ENABLE 769 * ARG0: enable flag 770 * ARG1: return target address 771 * RET0: status 772 * ERRORS: ENORADDR Invalid real address when disabling 773 * translation. 774 * EBADALIGN The return target address is not 775 * aligned to an instruction. 776 * EINVAL The enable flag request the current 777 * operating mode (e.g. disable if already 778 * disabled) 779 * 780 * Enable or disable virtual address translation for the calling CPU 781 * within the virtual machine domain. If the enable flag is zero, 782 * translation is disabled, any non-zero value will enable 783 * translation. 784 * 785 * When this function returns, the newly selected translation mode 786 * will be active. If the mmu is being enabled, then the return 787 * target address is a virtual address else it is a real address. 788 * 789 * Upon successful completion, control will be returned to the given 790 * return target address (ie. the cpu will jump to that address). On 791 * failure, the previous mmu mode remains and the trap simply returns 792 * as normal with the appropriate error code in RET0. 793 */ 794#define HV_FAST_MMU_ENABLE 0x27 795 796/* mmu_unmap_perm_addr() 797 * TRAP: HV_FAST_TRAP 798 * FUNCTION: HV_FAST_MMU_UNMAP_PERM_ADDR 799 * ARG0: virtual address 800 * ARG1: reserved, must be zero 801 * ARG2: flags (HV_MMU_{IMMU,DMMU}) 802 * RET0: status 803 * ERRORS: EINVAL Invalid virutal address or flags value 804 * ENOMAP Specified mapping was not found 805 * 806 * Demaps any permanent page mapping (established via 807 * mmu_map_perm_addr()) at the given virtual address for context 0 on 808 * the current virtual CPU. Any virtual tagged caches are guaranteed 809 * to be kept consistent. 810 */ 811#define HV_FAST_MMU_UNMAP_PERM_ADDR 0x28 812 813/* mmu_tsb_ctx0_info() 814 * TRAP: HV_FAST_TRAP 815 * FUNCTION: HV_FAST_MMU_TSB_CTX0_INFO 816 * ARG0: max TSBs 817 * ARG1: buffer pointer 818 * RET0: status 819 * RET1: number of TSBs 820 * ERRORS: EINVAL Supplied buffer is too small 821 * EBADALIGN The buffer pointer is badly aligned 822 * ENORADDR Invalid real address for buffer pointer 823 * 824 * Return the TSB configuration as previous defined by mmu_tsb_ctx0() 825 * into the provided buffer. The size of the buffer is given in ARG1 826 * in terms of the number of TSB description entries. 827 * 828 * Upon return, RET1 always contains the number of TSB descriptions 829 * previously configured. If zero TSBs were configured, EOK is 830 * returned with RET1 containing 0. 831 */ 832#define HV_FAST_MMU_TSB_CTX0_INFO 0x29 833 834/* mmu_tsb_ctxnon0_info() 835 * TRAP: HV_FAST_TRAP 836 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0_INFO 837 * ARG0: max TSBs 838 * ARG1: buffer pointer 839 * RET0: status 840 * RET1: number of TSBs 841 * ERRORS: EINVAL Supplied buffer is too small 842 * EBADALIGN The buffer pointer is badly aligned 843 * ENORADDR Invalid real address for buffer pointer 844 * 845 * Return the TSB configuration as previous defined by 846 * mmu_tsb_ctxnon0() into the provided buffer. The size of the buffer 847 * is given in ARG1 in terms of the number of TSB description entries. 848 * 849 * Upon return, RET1 always contains the number of TSB descriptions 850 * previously configured. If zero TSBs were configured, EOK is 851 * returned with RET1 containing 0. 852 */ 853#define HV_FAST_MMU_TSB_CTXNON0_INFO 0x2a 854 855/* mmu_fault_area_info() 856 * TRAP: HV_FAST_TRAP 857 * FUNCTION: HV_FAST_MMU_FAULT_AREA_INFO 858 * RET0: status 859 * RET1: fault area real address 860 * ERRORS: No errors defined. 861 * 862 * Return the currently defined MMU fault status area for the current 863 * CPU. The real address of the fault status area is returned in 864 * RET1, or 0 is returned in RET1 if no fault status area is defined. 865 * 866 * Note: mmu_fault_area_conf() may be called with the return value (RET1) 867 * from this service if there is a need to save and restore the fault 868 * area for a cpu. 869 */ 870#define HV_FAST_MMU_FAULT_AREA_INFO 0x2b 871 872/* Cache and Memory services. */ 873 874/* mem_scrub() 875 * TRAP: HV_FAST_TRAP 876 * FUNCTION: HV_FAST_MEM_SCRUB 877 * ARG0: real address 878 * ARG1: length 879 * RET0: status 880 * RET1: length scrubbed 881 * ERRORS: ENORADDR Invalid real address 882 * EBADALIGN Start address or length are not correctly 883 * aligned 884 * EINVAL Length is zero 885 * 886 * Zero the memory contents in the range real address to real address 887 * plus length minus 1. Also, valid ECC will be generated for that 888 * memory address range. Scrubbing is started at the given real 889 * address, but may not scrub the entire given length. The actual 890 * length scrubbed will be returned in RET1. 891 * 892 * The real address and length must be aligned on an 8K boundary, or 893 * contain the start address and length from a sun4v error report. 894 * 895 * Note: There are two uses for this function. The first use is to block clear 896 * and initialize memory and the second is to scrub an u ncorrectable 897 * error reported via a resumable or non-resumable trap. The second 898 * use requires the arguments to be equal to the real address and length 899 * provided in a sun4v memory error report. 900 */ 901#define HV_FAST_MEM_SCRUB 0x31 902 903/* mem_sync() 904 * TRAP: HV_FAST_TRAP 905 * FUNCTION: HV_FAST_MEM_SYNC 906 * ARG0: real address 907 * ARG1: length 908 * RET0: status 909 * RET1: length synced 910 * ERRORS: ENORADDR Invalid real address 911 * EBADALIGN Start address or length are not correctly 912 * aligned 913 * EINVAL Length is zero 914 * 915 * Force the next access within the real address to real address plus 916 * length minus 1 to be fetches from main system memory. Less than 917 * the given length may be synced, the actual amount synced is 918 * returned in RET1. The real address and length must be aligned on 919 * an 8K boundary. 920 */ 921#define HV_FAST_MEM_SYNC 0x32 922 923/* Time of day services. 924 * 925 * The hypervisor maintains the time of day on a per-domain basis. 926 * Changing the time of day in one domain does not affect the time of 927 * day on any other domain. 928 * 929 * Time is described by a single unsigned 64-bit word which is the 930 * number of seconds since the UNIX Epoch (00:00:00 UTC, January 1, 931 * 1970). 932 */ 933 934/* tod_get() 935 * TRAP: HV_FAST_TRAP 936 * FUNCTION: HV_FAST_TOD_GET 937 * RET0: status 938 * RET1: TOD 939 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable 940 * ENOTSUPPORTED If TOD not supported on this platform 941 * 942 * Return the current time of day. May block if TOD access is 943 * temporarily not possible. 944 */ 945#define HV_FAST_TOD_GET 0x50 946 947#ifndef __ASSEMBLY__ 948extern unsigned long sun4v_tod_get(unsigned long *time); 949#endif 950 951/* tod_set() 952 * TRAP: HV_FAST_TRAP 953 * FUNCTION: HV_FAST_TOD_SET 954 * ARG0: TOD 955 * RET0: status 956 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable 957 * ENOTSUPPORTED If TOD not supported on this platform 958 * 959 * The current time of day is set to the value specified in ARG0. May 960 * block if TOD access is temporarily not possible. 961 */ 962#define HV_FAST_TOD_SET 0x51 963 964#ifndef __ASSEMBLY__ 965extern unsigned long sun4v_tod_set(unsigned long time); 966#endif 967 968/* Console services */ 969 970/* con_getchar() 971 * TRAP: HV_FAST_TRAP 972 * FUNCTION: HV_FAST_CONS_GETCHAR 973 * RET0: status 974 * RET1: character 975 * ERRORS: EWOULDBLOCK No character available. 976 * 977 * Returns a character from the console device. If no character is 978 * available then an EWOULDBLOCK error is returned. If a character is 979 * available, then the returned status is EOK and the character value 980 * is in RET1. 981 * 982 * A virtual BREAK is represented by the 64-bit value -1. 983 * 984 * A virtual HUP signal is represented by the 64-bit value -2. 985 */ 986#define HV_FAST_CONS_GETCHAR 0x60 987 988/* con_putchar() 989 * TRAP: HV_FAST_TRAP 990 * FUNCTION: HV_FAST_CONS_PUTCHAR 991 * ARG0: character 992 * RET0: status 993 * ERRORS: EINVAL Illegal character 994 * EWOULDBLOCK Output buffer currently full, would block 995 * 996 * Send a character to the console device. Only character values 997 * between 0 and 255 may be used. Values outside this range are 998 * invalid except for the 64-bit value -1 which is used to send a 999 * virtual BREAK. 1000 */ 1001#define HV_FAST_CONS_PUTCHAR 0x61 1002 1003/* con_read() 1004 * TRAP: HV_FAST_TRAP 1005 * FUNCTION: HV_FAST_CONS_READ 1006 * ARG0: buffer real address 1007 * ARG1: buffer size in bytes 1008 * RET0: status 1009 * RET1: bytes read or BREAK or HUP 1010 * ERRORS: EWOULDBLOCK No character available. 1011 * 1012 * Reads characters into a buffer from the console device. If no 1013 * character is available then an EWOULDBLOCK error is returned. 1014 * If a character is available, then the returned status is EOK 1015 * and the number of bytes read into the given buffer is provided 1016 * in RET1. 1017 * 1018 * A virtual BREAK is represented by the 64-bit RET1 value -1. 1019 * 1020 * A virtual HUP signal is represented by the 64-bit RET1 value -2. 1021 * 1022 * If BREAK or HUP are indicated, no bytes were read into buffer. 1023 */ 1024#define HV_FAST_CONS_READ 0x62 1025 1026/* con_write() 1027 * TRAP: HV_FAST_TRAP 1028 * FUNCTION: HV_FAST_CONS_WRITE 1029 * ARG0: buffer real address 1030 * ARG1: buffer size in bytes 1031 * RET0: status 1032 * RET1: bytes written 1033 * ERRORS: EWOULDBLOCK Output buffer currently full, would block 1034 * 1035 * Send a characters in buffer to the console device. Breaks must be 1036 * sent using con_putchar(). 1037 */ 1038#define HV_FAST_CONS_WRITE 0x63 1039 1040#ifndef __ASSEMBLY__ 1041extern long sun4v_con_getchar(long *status); 1042extern long sun4v_con_putchar(long c); 1043extern long sun4v_con_read(unsigned long buffer, 1044 unsigned long size, 1045 unsigned long *bytes_read); 1046extern unsigned long sun4v_con_write(unsigned long buffer, 1047 unsigned long size, 1048 unsigned long *bytes_written); 1049#endif 1050 1051/* mach_set_soft_state() 1052 * TRAP: HV_FAST_TRAP 1053 * FUNCTION: HV_FAST_MACH_SET_SOFT_STATE 1054 * ARG0: software state 1055 * ARG1: software state description pointer 1056 * RET0: status 1057 * ERRORS: EINVAL software state not valid or software state 1058 * description is not NULL terminated 1059 * ENORADDR software state description pointer is not a 1060 * valid real address 1061 * EBADALIGNED software state description is not correctly 1062 * aligned 1063 * 1064 * This allows the guest to report it's soft state to the hypervisor. There 1065 * are two primary components to this state. The first part states whether 1066 * the guest software is running or not. The second containts optional 1067 * details specific to the software. 1068 * 1069 * The software state argument is defined below in HV_SOFT_STATE_*, and 1070 * indicates whether the guest is operating normally or in a transitional 1071 * state. 1072 * 1073 * The software state description argument is a real address of a data buffer 1074 * of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL 1075 * terminated 7-bit ASCII string of up to 31 characters not including the 1076 * NULL termination. 1077 */ 1078#define HV_FAST_MACH_SET_SOFT_STATE 0x70 1079#define HV_SOFT_STATE_NORMAL 0x01 1080#define HV_SOFT_STATE_TRANSITION 0x02 1081 1082#ifndef __ASSEMBLY__ 1083extern unsigned long sun4v_mach_set_soft_state(unsigned long soft_state, 1084 unsigned long msg_string_ra); 1085#endif 1086 1087/* mach_get_soft_state() 1088 * TRAP: HV_FAST_TRAP 1089 * FUNCTION: HV_FAST_MACH_GET_SOFT_STATE 1090 * ARG0: software state description pointer 1091 * RET0: status 1092 * RET1: software state 1093 * ERRORS: ENORADDR software state description pointer is not a 1094 * valid real address 1095 * EBADALIGNED software state description is not correctly 1096 * aligned 1097 * 1098 * Retrieve the current value of the guest's software state. The rules 1099 * for the software state pointer are the same as for mach_set_soft_state() 1100 * above. 1101 */ 1102#define HV_FAST_MACH_GET_SOFT_STATE 0x71 1103 1104/* svc_send() 1105 * TRAP: HV_FAST_TRAP 1106 * FUNCTION: HV_FAST_SVC_SEND 1107 * ARG0: service ID 1108 * ARG1: buffer real address 1109 * ARG2: buffer size 1110 * RET0: STATUS 1111 * RET1: sent_bytes 1112 * 1113 * Be careful, all output registers are clobbered by this operation, 1114 * so for example it is not possible to save away a value in %o4 1115 * across the trap. 1116 */ 1117#define HV_FAST_SVC_SEND 0x80 1118 1119/* svc_recv() 1120 * TRAP: HV_FAST_TRAP 1121 * FUNCTION: HV_FAST_SVC_RECV 1122 * ARG0: service ID 1123 * ARG1: buffer real address 1124 * ARG2: buffer size 1125 * RET0: STATUS 1126 * RET1: recv_bytes 1127 * 1128 * Be careful, all output registers are clobbered by this operation, 1129 * so for example it is not possible to save away a value in %o4 1130 * across the trap. 1131 */ 1132#define HV_FAST_SVC_RECV 0x81 1133 1134/* svc_getstatus() 1135 * TRAP: HV_FAST_TRAP 1136 * FUNCTION: HV_FAST_SVC_GETSTATUS 1137 * ARG0: service ID 1138 * RET0: STATUS 1139 * RET1: status bits 1140 */ 1141#define HV_FAST_SVC_GETSTATUS 0x82 1142 1143/* svc_setstatus() 1144 * TRAP: HV_FAST_TRAP 1145 * FUNCTION: HV_FAST_SVC_SETSTATUS 1146 * ARG0: service ID 1147 * ARG1: bits to set 1148 * RET0: STATUS 1149 */ 1150#define HV_FAST_SVC_SETSTATUS 0x83 1151 1152/* svc_clrstatus() 1153 * TRAP: HV_FAST_TRAP 1154 * FUNCTION: HV_FAST_SVC_CLRSTATUS 1155 * ARG0: service ID 1156 * ARG1: bits to clear 1157 * RET0: STATUS 1158 */ 1159#define HV_FAST_SVC_CLRSTATUS 0x84 1160 1161#ifndef __ASSEMBLY__ 1162extern unsigned long sun4v_svc_send(unsigned long svc_id, 1163 unsigned long buffer, 1164 unsigned long buffer_size, 1165 unsigned long *sent_bytes); 1166extern unsigned long sun4v_svc_recv(unsigned long svc_id, 1167 unsigned long buffer, 1168 unsigned long buffer_size, 1169 unsigned long *recv_bytes); 1170extern unsigned long sun4v_svc_getstatus(unsigned long svc_id, 1171 unsigned long *status_bits); 1172extern unsigned long sun4v_svc_setstatus(unsigned long svc_id, 1173 unsigned long status_bits); 1174extern unsigned long sun4v_svc_clrstatus(unsigned long svc_id, 1175 unsigned long status_bits); 1176#endif 1177 1178/* Trap trace services. 1179 * 1180 * The hypervisor provides a trap tracing capability for privileged 1181 * code running on each virtual CPU. Privileged code provides a 1182 * round-robin trap trace queue within which the hypervisor writes 1183 * 64-byte entries detailing hyperprivileged traps taken n behalf of 1184 * privileged code. This is provided as a debugging capability for 1185 * privileged code. 1186 * 1187 * The trap trace control structure is 64-bytes long and placed at the 1188 * start (offset 0) of the trap trace buffer, and is described as 1189 * follows: 1190 */ 1191#ifndef __ASSEMBLY__ 1192struct hv_trap_trace_control { 1193 unsigned long head_offset; 1194 unsigned long tail_offset; 1195 unsigned long __reserved[0x30 / sizeof(unsigned long)]; 1196}; 1197#endif 1198#define HV_TRAP_TRACE_CTRL_HEAD_OFFSET 0x00 1199#define HV_TRAP_TRACE_CTRL_TAIL_OFFSET 0x08 1200 1201/* The head offset is the offset of the most recently completed entry 1202 * in the trap-trace buffer. The tail offset is the offset of the 1203 * next entry to be written. The control structure is owned and 1204 * modified by the hypervisor. A guest may not modify the control 1205 * structure contents. Attempts to do so will result in undefined 1206 * behavior for the guest. 1207 * 1208 * Each trap trace buffer entry is layed out as follows: 1209 */ 1210#ifndef __ASSEMBLY__ 1211struct hv_trap_trace_entry { 1212 unsigned char type; /* Hypervisor or guest entry? */ 1213 unsigned char hpstate; /* Hyper-privileged state */ 1214 unsigned char tl; /* Trap level */ 1215 unsigned char gl; /* Global register level */ 1216 unsigned short tt; /* Trap type */ 1217 unsigned short tag; /* Extended trap identifier */ 1218 unsigned long tstate; /* Trap state */ 1219 unsigned long tick; /* Tick */ 1220 unsigned long tpc; /* Trap PC */ 1221 unsigned long f1; /* Entry specific */ 1222 unsigned long f2; /* Entry specific */ 1223 unsigned long f3; /* Entry specific */ 1224 unsigned long f4; /* Entry specific */ 1225}; 1226#endif 1227#define HV_TRAP_TRACE_ENTRY_TYPE 0x00 1228#define HV_TRAP_TRACE_ENTRY_HPSTATE 0x01 1229#define HV_TRAP_TRACE_ENTRY_TL 0x02 1230#define HV_TRAP_TRACE_ENTRY_GL 0x03 1231#define HV_TRAP_TRACE_ENTRY_TT 0x04 1232#define HV_TRAP_TRACE_ENTRY_TAG 0x06 1233#define HV_TRAP_TRACE_ENTRY_TSTATE 0x08 1234#define HV_TRAP_TRACE_ENTRY_TICK 0x10 1235#define HV_TRAP_TRACE_ENTRY_TPC 0x18 1236#define HV_TRAP_TRACE_ENTRY_F1 0x20 1237#define HV_TRAP_TRACE_ENTRY_F2 0x28 1238#define HV_TRAP_TRACE_ENTRY_F3 0x30 1239#define HV_TRAP_TRACE_ENTRY_F4 0x38 1240 1241/* The type field is encoded as follows. */ 1242#define HV_TRAP_TYPE_UNDEF 0x00 /* Entry content undefined */ 1243#define HV_TRAP_TYPE_HV 0x01 /* Hypervisor trap entry */ 1244#define HV_TRAP_TYPE_GUEST 0xff /* Added via ttrace_addentry() */ 1245 1246/* ttrace_buf_conf() 1247 * TRAP: HV_FAST_TRAP 1248 * FUNCTION: HV_FAST_TTRACE_BUF_CONF 1249 * ARG0: real address 1250 * ARG1: number of entries 1251 * RET0: status 1252 * RET1: number of entries 1253 * ERRORS: ENORADDR Invalid real address 1254 * EINVAL Size is too small 1255 * EBADALIGN Real address not aligned on 64-byte boundary 1256 * 1257 * Requests hypervisor trap tracing and declares a virtual CPU's trap 1258 * trace buffer to the hypervisor. The real address supplies the real 1259 * base address of the trap trace queue and must be 64-byte aligned. 1260 * Specifying a value of 0 for the number of entries disables trap 1261 * tracing for the calling virtual CPU. The buffer allocated must be 1262 * sized for a power of two number of 64-byte trap trace entries plus 1263 * an initial 64-byte control structure. 1264 * 1265 * This may be invoked any number of times so that a virtual CPU may 1266 * relocate a trap trace buffer or create "snapshots" of information. 1267 * 1268 * If the real address is illegal or badly aligned, then trap tracing 1269 * is disabled and an error is returned. 1270 * 1271 * Upon failure with EINVAL, this service call returns in RET1 the 1272 * minimum number of buffer entries required. Upon other failures 1273 * RET1 is undefined. 1274 */ 1275#define HV_FAST_TTRACE_BUF_CONF 0x90 1276 1277/* ttrace_buf_info() 1278 * TRAP: HV_FAST_TRAP 1279 * FUNCTION: HV_FAST_TTRACE_BUF_INFO 1280 * RET0: status 1281 * RET1: real address 1282 * RET2: size 1283 * ERRORS: None defined. 1284 * 1285 * Returns the size and location of the previously declared trap-trace 1286 * buffer. In the event that no buffer was previously defined, or the 1287 * buffer is disabled, this call will return a size of zero bytes. 1288 */ 1289#define HV_FAST_TTRACE_BUF_INFO 0x91 1290 1291/* ttrace_enable() 1292 * TRAP: HV_FAST_TRAP 1293 * FUNCTION: HV_FAST_TTRACE_ENABLE 1294 * ARG0: enable 1295 * RET0: status 1296 * RET1: previous enable state 1297 * ERRORS: EINVAL No trap trace buffer currently defined 1298 * 1299 * Enable or disable trap tracing, and return the previous enabled 1300 * state in RET1. Future systems may define various flags for the 1301 * enable argument (ARG0), for the moment a guest should pass 1302 * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all 1303 * tracing - which will ensure future compatability. 1304 */ 1305#define HV_FAST_TTRACE_ENABLE 0x92 1306 1307/* ttrace_freeze() 1308 * TRAP: HV_FAST_TRAP 1309 * FUNCTION: HV_FAST_TTRACE_FREEZE 1310 * ARG0: freeze 1311 * RET0: status 1312 * RET1: previous freeze state 1313 * ERRORS: EINVAL No trap trace buffer currently defined 1314 * 1315 * Freeze or unfreeze trap tracing, returning the previous freeze 1316 * state in RET1. A guest should pass a non-zero value to freeze and 1317 * a zero value to unfreeze all tracing. The returned previous state 1318 * is 0 for not frozen and 1 for frozen. 1319 */ 1320#define HV_FAST_TTRACE_FREEZE 0x93 1321 1322/* ttrace_addentry() 1323 * TRAP: HV_TTRACE_ADDENTRY_TRAP 1324 * ARG0: tag (16-bits) 1325 * ARG1: data word 0 1326 * ARG2: data word 1 1327 * ARG3: data word 2 1328 * ARG4: data word 3 1329 * RET0: status 1330 * ERRORS: EINVAL No trap trace buffer currently defined 1331 * 1332 * Add an entry to the trap trace buffer. Upon return only ARG0/RET0 1333 * is modified - none of the other registers holding arguments are 1334 * volatile across this hypervisor service. 1335 */ 1336 1337/* Core dump services. 1338 * 1339 * Since the hypervisor viraulizes and thus obscures a lot of the 1340 * physical machine layout and state, traditional OS crash dumps can 1341 * be difficult to diagnose especially when the problem is a 1342 * configuration error of some sort. 1343 * 1344 * The dump services provide an opaque buffer into which the 1345 * hypervisor can place it's internal state in order to assist in 1346 * debugging such situations. The contents are opaque and extremely 1347 * platform and hypervisor implementation specific. The guest, during 1348 * a core dump, requests that the hypervisor update any information in 1349 * the dump buffer in preparation to being dumped as part of the 1350 * domain's memory image. 1351 */ 1352 1353/* dump_buf_update() 1354 * TRAP: HV_FAST_TRAP 1355 * FUNCTION: HV_FAST_DUMP_BUF_UPDATE 1356 * ARG0: real address 1357 * ARG1: size 1358 * RET0: status 1359 * RET1: required size of dump buffer 1360 * ERRORS: ENORADDR Invalid real address 1361 * EBADALIGN Real address is not aligned on a 64-byte 1362 * boundary 1363 * EINVAL Size is non-zero but less than minimum size 1364 * required 1365 * ENOTSUPPORTED Operation not supported on current logical 1366 * domain 1367 * 1368 * Declare a domain dump buffer to the hypervisor. The real address 1369 * provided for the domain dump buffer must be 64-byte aligned. The 1370 * size specifies the size of the dump buffer and may be larger than 1371 * the minimum size specified in the machine description. The 1372 * hypervisor will fill the dump buffer with opaque data. 1373 * 1374 * Note: A guest may elect to include dump buffer contents as part of a crash 1375 * dump to assist with debugging. This function may be called any number 1376 * of times so that a guest may relocate a dump buffer, or create 1377 * "snapshots" of any dump-buffer information. Each call to 1378 * dump_buf_update() atomically declares the new dump buffer to the 1379 * hypervisor. 1380 * 1381 * A specified size of 0 unconfigures the dump buffer. If the real 1382 * address is illegal or badly aligned, then any currently active dump 1383 * buffer is disabled and an error is returned. 1384 * 1385 * In the event that the call fails with EINVAL, RET1 contains the 1386 * minimum size requires by the hypervisor for a valid dump buffer. 1387 */ 1388#define HV_FAST_DUMP_BUF_UPDATE 0x94 1389 1390/* dump_buf_info() 1391 * TRAP: HV_FAST_TRAP 1392 * FUNCTION: HV_FAST_DUMP_BUF_INFO 1393 * RET0: status 1394 * RET1: real address of current dump buffer 1395 * RET2: size of current dump buffer 1396 * ERRORS: No errors defined. 1397 * 1398 * Return the currently configures dump buffer description. A 1399 * returned size of 0 bytes indicates an undefined dump buffer. In 1400 * this case the return address in RET1 is undefined. 1401 */ 1402#define HV_FAST_DUMP_BUF_INFO 0x95 1403 1404/* Device interrupt services. 1405 * 1406 * Device interrupts are allocated to system bus bridges by the hypervisor, 1407 * and described to OBP in the machine description. OBP then describes 1408 * these interrupts to the OS via properties in the device tree. 1409 * 1410 * Terminology: 1411 * 1412 * cpuid Unique opaque value which represents a target cpu. 1413 * 1414 * devhandle Device handle. It uniquely identifies a device, and 1415 * consistes of the lower 28-bits of the hi-cell of the 1416 * first entry of the device's "reg" property in the 1417 * OBP device tree. 1418 * 1419 * devino Device interrupt number. Specifies the relative 1420 * interrupt number within the device. The unique 1421 * combination of devhandle and devino are used to 1422 * identify a specific device interrupt. 1423 * 1424 * Note: The devino value is the same as the values in the 1425 * "interrupts" property or "interrupt-map" property 1426 * in the OBP device tree for that device. 1427 * 1428 * sysino System interrupt number. A 64-bit unsigned interger 1429 * representing a unique interrupt within a virtual 1430 * machine. 1431 * 1432 * intr_state A flag representing the interrupt state for a given 1433 * sysino. The state values are defined below. 1434 * 1435 * intr_enabled A flag representing the 'enabled' state for a given 1436 * sysino. The enable values are defined below. 1437 */ 1438 1439#define HV_INTR_STATE_IDLE 0 /* Nothing pending */ 1440#define HV_INTR_STATE_RECEIVED 1 /* Interrupt received by hardware */ 1441#define HV_INTR_STATE_DELIVERED 2 /* Interrupt delivered to queue */ 1442 1443#define HV_INTR_DISABLED 0 /* sysino not enabled */ 1444#define HV_INTR_ENABLED 1 /* sysino enabled */ 1445 1446/* intr_devino_to_sysino() 1447 * TRAP: HV_FAST_TRAP 1448 * FUNCTION: HV_FAST_INTR_DEVINO2SYSINO 1449 * ARG0: devhandle 1450 * ARG1: devino 1451 * RET0: status 1452 * RET1: sysino 1453 * ERRORS: EINVAL Invalid devhandle/devino 1454 * 1455 * Converts a device specific interrupt number of the given 1456 * devhandle/devino into a system specific ino (sysino). 1457 */ 1458#define HV_FAST_INTR_DEVINO2SYSINO 0xa0 1459 1460#ifndef __ASSEMBLY__ 1461extern unsigned long sun4v_devino_to_sysino(unsigned long devhandle, 1462 unsigned long devino); 1463#endif 1464 1465/* intr_getenabled() 1466 * TRAP: HV_FAST_TRAP 1467 * FUNCTION: HV_FAST_INTR_GETENABLED 1468 * ARG0: sysino 1469 * RET0: status 1470 * RET1: intr_enabled (HV_INTR_{DISABLED,ENABLED}) 1471 * ERRORS: EINVAL Invalid sysino 1472 * 1473 * Returns interrupt enabled state in RET1 for the interrupt defined 1474 * by the given sysino. 1475 */ 1476#define HV_FAST_INTR_GETENABLED 0xa1 1477 1478#ifndef __ASSEMBLY__ 1479extern unsigned long sun4v_intr_getenabled(unsigned long sysino); 1480#endif 1481 1482/* intr_setenabled() 1483 * TRAP: HV_FAST_TRAP 1484 * FUNCTION: HV_FAST_INTR_SETENABLED 1485 * ARG0: sysino 1486 * ARG1: intr_enabled (HV_INTR_{DISABLED,ENABLED}) 1487 * RET0: status 1488 * ERRORS: EINVAL Invalid sysino or intr_enabled value 1489 * 1490 * Set the 'enabled' state of the interrupt sysino. 1491 */ 1492#define HV_FAST_INTR_SETENABLED 0xa2 1493 1494#ifndef __ASSEMBLY__ 1495extern unsigned long sun4v_intr_setenabled(unsigned long sysino, unsigned long intr_enabled); 1496#endif 1497 1498/* intr_getstate() 1499 * TRAP: HV_FAST_TRAP 1500 * FUNCTION: HV_FAST_INTR_GETSTATE 1501 * ARG0: sysino 1502 * RET0: status 1503 * RET1: intr_state (HV_INTR_STATE_*) 1504 * ERRORS: EINVAL Invalid sysino 1505 * 1506 * Returns current state of the interrupt defined by the given sysino. 1507 */ 1508#define HV_FAST_INTR_GETSTATE 0xa3 1509 1510#ifndef __ASSEMBLY__ 1511extern unsigned long sun4v_intr_getstate(unsigned long sysino); 1512#endif 1513 1514/* intr_setstate() 1515 * TRAP: HV_FAST_TRAP 1516 * FUNCTION: HV_FAST_INTR_SETSTATE 1517 * ARG0: sysino 1518 * ARG1: intr_state (HV_INTR_STATE_*) 1519 * RET0: status 1520 * ERRORS: EINVAL Invalid sysino or intr_state value 1521 * 1522 * Sets the current state of the interrupt described by the given sysino 1523 * value. 1524 * 1525 * Note: Setting the state to HV_INTR_STATE_IDLE clears any pending 1526 * interrupt for sysino. 1527 */ 1528#define HV_FAST_INTR_SETSTATE 0xa4 1529 1530#ifndef __ASSEMBLY__ 1531extern unsigned long sun4v_intr_setstate(unsigned long sysino, unsigned long intr_state); 1532#endif 1533 1534/* intr_gettarget() 1535 * TRAP: HV_FAST_TRAP 1536 * FUNCTION: HV_FAST_INTR_GETTARGET 1537 * ARG0: sysino 1538 * RET0: status 1539 * RET1: cpuid 1540 * ERRORS: EINVAL Invalid sysino 1541 * 1542 * Returns CPU that is the current target of the interrupt defined by 1543 * the given sysino. The CPU value returned is undefined if the target 1544 * has not been set via intr_settarget(). 1545 */ 1546#define HV_FAST_INTR_GETTARGET 0xa5 1547 1548#ifndef __ASSEMBLY__ 1549extern unsigned long sun4v_intr_gettarget(unsigned long sysino); 1550#endif 1551 1552/* intr_settarget() 1553 * TRAP: HV_FAST_TRAP 1554 * FUNCTION: HV_FAST_INTR_SETTARGET 1555 * ARG0: sysino 1556 * ARG1: cpuid 1557 * RET0: status 1558 * ERRORS: EINVAL Invalid sysino 1559 * ENOCPU Invalid cpuid 1560 * 1561 * Set the target CPU for the interrupt defined by the given sysino. 1562 */ 1563#define HV_FAST_INTR_SETTARGET 0xa6 1564 1565#ifndef __ASSEMBLY__ 1566extern unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid); 1567#endif 1568 1569/* vintr_get_cookie() 1570 * TRAP: HV_FAST_TRAP 1571 * FUNCTION: HV_FAST_VINTR_GET_COOKIE 1572 * ARG0: device handle 1573 * ARG1: device ino 1574 * RET0: status 1575 * RET1: cookie 1576 */ 1577#define HV_FAST_VINTR_GET_COOKIE 0xa7 1578 1579/* vintr_set_cookie() 1580 * TRAP: HV_FAST_TRAP 1581 * FUNCTION: HV_FAST_VINTR_SET_COOKIE 1582 * ARG0: device handle 1583 * ARG1: device ino 1584 * ARG2: cookie 1585 * RET0: status 1586 */ 1587#define HV_FAST_VINTR_SET_COOKIE 0xa8 1588 1589/* vintr_get_valid() 1590 * TRAP: HV_FAST_TRAP 1591 * FUNCTION: HV_FAST_VINTR_GET_VALID 1592 * ARG0: device handle 1593 * ARG1: device ino 1594 * RET0: status 1595 * RET1: valid state 1596 */ 1597#define HV_FAST_VINTR_GET_VALID 0xa9 1598 1599/* vintr_set_valid() 1600 * TRAP: HV_FAST_TRAP 1601 * FUNCTION: HV_FAST_VINTR_SET_VALID 1602 * ARG0: device handle 1603 * ARG1: device ino 1604 * ARG2: valid state 1605 * RET0: status 1606 */ 1607#define HV_FAST_VINTR_SET_VALID 0xaa 1608 1609/* vintr_get_state() 1610 * TRAP: HV_FAST_TRAP 1611 * FUNCTION: HV_FAST_VINTR_GET_STATE 1612 * ARG0: device handle 1613 * ARG1: device ino 1614 * RET0: status 1615 * RET1: state 1616 */ 1617#define HV_FAST_VINTR_GET_STATE 0xab 1618 1619/* vintr_set_state() 1620 * TRAP: HV_FAST_TRAP 1621 * FUNCTION: HV_FAST_VINTR_SET_STATE 1622 * ARG0: device handle 1623 * ARG1: device ino 1624 * ARG2: state 1625 * RET0: status 1626 */ 1627#define HV_FAST_VINTR_SET_STATE 0xac 1628 1629/* vintr_get_target() 1630 * TRAP: HV_FAST_TRAP 1631 * FUNCTION: HV_FAST_VINTR_GET_TARGET 1632 * ARG0: device handle 1633 * ARG1: device ino 1634 * RET0: status 1635 * RET1: cpuid 1636 */ 1637#define HV_FAST_VINTR_GET_TARGET 0xad 1638 1639/* vintr_set_target() 1640 * TRAP: HV_FAST_TRAP 1641 * FUNCTION: HV_FAST_VINTR_SET_TARGET 1642 * ARG0: device handle 1643 * ARG1: device ino 1644 * ARG2: cpuid 1645 * RET0: status 1646 */ 1647#define HV_FAST_VINTR_SET_TARGET 0xae 1648 1649#ifndef __ASSEMBLY__ 1650extern unsigned long sun4v_vintr_get_cookie(unsigned long dev_handle, 1651 unsigned long dev_ino, 1652 unsigned long *cookie); 1653extern unsigned long sun4v_vintr_set_cookie(unsigned long dev_handle, 1654 unsigned long dev_ino, 1655 unsigned long cookie); 1656extern unsigned long sun4v_vintr_get_valid(unsigned long dev_handle, 1657 unsigned long dev_ino, 1658 unsigned long *valid); 1659extern unsigned long sun4v_vintr_set_valid(unsigned long dev_handle, 1660 unsigned long dev_ino, 1661 unsigned long valid); 1662extern unsigned long sun4v_vintr_get_state(unsigned long dev_handle, 1663 unsigned long dev_ino, 1664 unsigned long *state); 1665extern unsigned long sun4v_vintr_set_state(unsigned long dev_handle, 1666 unsigned long dev_ino, 1667 unsigned long state); 1668extern unsigned long sun4v_vintr_get_target(unsigned long dev_handle, 1669 unsigned long dev_ino, 1670 unsigned long *cpuid); 1671extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle, 1672 unsigned long dev_ino, 1673 unsigned long cpuid); 1674#endif 1675 1676/* PCI IO services. 1677 * 1678 * See the terminology descriptions in the device interrupt services 1679 * section above as those apply here too. Here are terminology 1680 * definitions specific to these PCI IO services: 1681 * 1682 * tsbnum TSB number. Indentifies which io-tsb is used. 1683 * For this version of the specification, tsbnum 1684 * must be zero. 1685 * 1686 * tsbindex TSB index. Identifies which entry in the TSB 1687 * is used. The first entry is zero. 1688 * 1689 * tsbid A 64-bit aligned data structure which contains 1690 * a tsbnum and a tsbindex. Bits 63:32 contain the 1691 * tsbnum and bits 31:00 contain the tsbindex. 1692 * 1693 * Use the HV_PCI_TSBID() macro to construct such 1694 * values. 1695 * 1696 * io_attributes IO attributes for IOMMU mappings. One of more 1697 * of the attritbute bits are stores in a 64-bit 1698 * value. The values are defined below. 1699 * 1700 * r_addr 64-bit real address 1701 * 1702 * pci_device PCI device address. A PCI device address identifies 1703 * a specific device on a specific PCI bus segment. 1704 * A PCI device address ia a 32-bit unsigned integer 1705 * with the following format: 1706 * 1707 * 00000000.bbbbbbbb.dddddfff.00000000 1708 * 1709 * Use the HV_PCI_DEVICE_BUILD() macro to construct 1710 * such values. 1711 * 1712 * pci_config_offset 1713 * PCI configureation space offset. For conventional 1714 * PCI a value between 0 and 255. For extended 1715 * configuration space, a value between 0 and 4095. 1716 * 1717 * Note: For PCI configuration space accesses, the offset 1718 * must be aligned to the access size. 1719 * 1720 * error_flag A return value which specifies if the action succeeded 1721 * or failed. 0 means no error, non-0 means some error 1722 * occurred while performing the service. 1723 * 1724 * io_sync_direction 1725 * Direction definition for pci_dma_sync(), defined 1726 * below in HV_PCI_SYNC_*. 1727 * 1728 * io_page_list A list of io_page_addresses, an io_page_address is 1729 * a real address. 1730 * 1731 * io_page_list_p A pointer to an io_page_list. 1732 * 1733 * "size based byte swap" - Some functions do size based byte swapping 1734 * which allows sw to access pointers and 1735 * counters in native form when the processor 1736 * operates in a different endianness than the 1737 * IO bus. Size-based byte swapping converts a 1738 * multi-byte field between big-endian and 1739 * little-endian format. 1740 */ 1741 1742#define HV_PCI_MAP_ATTR_READ 0x01 1743#define HV_PCI_MAP_ATTR_WRITE 0x02 1744 1745#define HV_PCI_DEVICE_BUILD(b,d,f) \ 1746 ((((b) & 0xff) << 16) | \ 1747 (((d) & 0x1f) << 11) | \ 1748 (((f) & 0x07) << 8)) 1749 1750#define HV_PCI_TSBID(__tsb_num, __tsb_index) \ 1751 ((((u64)(__tsb_num)) << 32UL) | ((u64)(__tsb_index))) 1752 1753#define HV_PCI_SYNC_FOR_DEVICE 0x01 1754#define HV_PCI_SYNC_FOR_CPU 0x02 1755 1756/* pci_iommu_map() 1757 * TRAP: HV_FAST_TRAP 1758 * FUNCTION: HV_FAST_PCI_IOMMU_MAP 1759 * ARG0: devhandle 1760 * ARG1: tsbid 1761 * ARG2: #ttes 1762 * ARG3: io_attributes 1763 * ARG4: io_page_list_p 1764 * RET0: status 1765 * RET1: #ttes mapped 1766 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex/io_attributes 1767 * EBADALIGN Improperly aligned real address 1768 * ENORADDR Invalid real address 1769 * 1770 * Create IOMMU mappings in the sun4v device defined by the given 1771 * devhandle. The mappings are created in the TSB defined by the 1772 * tsbnum component of the given tsbid. The first mapping is created 1773 * in the TSB i ndex defined by the tsbindex component of the given tsbid. 1774 * The call creates up to #ttes mappings, the first one at tsbnum, tsbindex, 1775 * the second at tsbnum, tsbindex + 1, etc. 1776 * 1777 * All mappings are created with the attributes defined by the io_attributes 1778 * argument. The page mapping addresses are described in the io_page_list 1779 * defined by the given io_page_list_p, which is a pointer to the io_page_list. 1780 * The first entry in the io_page_list is the address for the first iotte, the 1781 * 2nd for the 2nd iotte, and so on. 1782 * 1783 * Each io_page_address in the io_page_list must be appropriately aligned. 1784 * #ttes must be greater than zero. For this version of the spec, the tsbnum 1785 * component of the given tsbid must be zero. 1786 * 1787 * Returns the actual number of mappings creates, which may be less than 1788 * or equal to the argument #ttes. If the function returns a value which 1789 * is less than the #ttes, the caller may continus to call the function with 1790 * an updated tsbid, #ttes, io_page_list_p arguments until all pages are 1791 * mapped. 1792 * 1793 * Note: This function does not imply an iotte cache flush. The guest must 1794 * demap an entry before re-mapping it. 1795 */ 1796#define HV_FAST_PCI_IOMMU_MAP 0xb0 1797 1798/* pci_iommu_demap() 1799 * TRAP: HV_FAST_TRAP 1800 * FUNCTION: HV_FAST_PCI_IOMMU_DEMAP 1801 * ARG0: devhandle 1802 * ARG1: tsbid 1803 * ARG2: #ttes 1804 * RET0: status 1805 * RET1: #ttes demapped 1806 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex 1807 * 1808 * Demap and flush IOMMU mappings in the device defined by the given 1809 * devhandle. Demaps up to #ttes entries in the TSB defined by the tsbnum 1810 * component of the given tsbid, starting at the TSB index defined by the 1811 * tsbindex component of the given tsbid. 1812 * 1813 * For this version of the spec, the tsbnum of the given tsbid must be zero. 1814 * #ttes must be greater than zero. 1815 * 1816 * Returns the actual number of ttes demapped, which may be less than or equal 1817 * to the argument #ttes. If #ttes demapped is less than #ttes, the caller 1818 * may continue to call this function with updated tsbid and #ttes arguments 1819 * until all pages are demapped. 1820 * 1821 * Note: Entries do not have to be mapped to be demapped. A demap of an 1822 * unmapped page will flush the entry from the tte cache. 1823 */ 1824#define HV_FAST_PCI_IOMMU_DEMAP 0xb1 1825 1826/* pci_iommu_getmap() 1827 * TRAP: HV_FAST_TRAP 1828 * FUNCTION: HV_FAST_PCI_IOMMU_GETMAP 1829 * ARG0: devhandle 1830 * ARG1: tsbid 1831 * RET0: status 1832 * RET1: io_attributes 1833 * RET2: real address 1834 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex 1835 * ENOMAP Mapping is not valid, no translation exists 1836 * 1837 * Read and return the mapping in the device described by the given devhandle 1838 * and tsbid. If successful, the io_attributes shall be returned in RET1 1839 * and the page address of the mapping shall be returned in RET2. 1840 * 1841 * For this version of the spec, the tsbnum component of the given tsbid 1842 * must be zero. 1843 */ 1844#define HV_FAST_PCI_IOMMU_GETMAP 0xb2 1845 1846/* pci_iommu_getbypass() 1847 * TRAP: HV_FAST_TRAP 1848 * FUNCTION: HV_FAST_PCI_IOMMU_GETBYPASS 1849 * ARG0: devhandle 1850 * ARG1: real address 1851 * ARG2: io_attributes 1852 * RET0: status 1853 * RET1: io_addr 1854 * ERRORS: EINVAL Invalid devhandle/io_attributes 1855 * ENORADDR Invalid real address 1856 * ENOTSUPPORTED Function not supported in this implementation. 1857 * 1858 * Create a "special" mapping in the device described by the given devhandle, 1859 * for the given real address and attributes. Return the IO address in RET1 1860 * if successful. 1861 */ 1862#define HV_FAST_PCI_IOMMU_GETBYPASS 0xb3 1863 1864/* pci_config_get() 1865 * TRAP: HV_FAST_TRAP 1866 * FUNCTION: HV_FAST_PCI_CONFIG_GET 1867 * ARG0: devhandle 1868 * ARG1: pci_device 1869 * ARG2: pci_config_offset 1870 * ARG3: size 1871 * RET0: status 1872 * RET1: error_flag 1873 * RET2: data 1874 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size 1875 * EBADALIGN pci_config_offset not size aligned 1876 * ENOACCESS Access to this offset is not permitted 1877 * 1878 * Read PCI configuration space for the adapter described by the given 1879 * devhandle. Read size (1, 2, or 4) bytes of data from the given 1880 * pci_device, at pci_config_offset from the beginning of the device's 1881 * configuration space. If there was no error, RET1 is set to zero and 1882 * RET2 is set to the data read. Insignificant bits in RET2 are not 1883 * guarenteed to have any specific value and therefore must be ignored. 1884 * 1885 * The data returned in RET2 is size based byte swapped. 1886 * 1887 * If an error occurs during the read, set RET1 to a non-zero value. The 1888 * given pci_config_offset must be 'size' aligned. 1889 */ 1890#define HV_FAST_PCI_CONFIG_GET 0xb4 1891 1892/* pci_config_put() 1893 * TRAP: HV_FAST_TRAP 1894 * FUNCTION: HV_FAST_PCI_CONFIG_PUT 1895 * ARG0: devhandle 1896 * ARG1: pci_device 1897 * ARG2: pci_config_offset 1898 * ARG3: size 1899 * ARG4: data 1900 * RET0: status 1901 * RET1: error_flag 1902 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size 1903 * EBADALIGN pci_config_offset not size aligned 1904 * ENOACCESS Access to this offset is not permitted 1905 * 1906 * Write PCI configuration space for the adapter described by the given 1907 * devhandle. Write size (1, 2, or 4) bytes of data in a single operation, 1908 * at pci_config_offset from the beginning of the device's configuration 1909 * space. The data argument contains the data to be written to configuration 1910 * space. Prior to writing, the data is size based byte swapped. 1911 * 1912 * If an error occurs during the write access, do not generate an error 1913 * report, do set RET1 to a non-zero value. Otherwise RET1 is zero. 1914 * The given pci_config_offset must be 'size' aligned. 1915 * 1916 * This function is permitted to read from offset zero in the configuration 1917 * space described by the given pci_device if necessary to ensure that the 1918 * write access to config space completes. 1919 */ 1920#define HV_FAST_PCI_CONFIG_PUT 0xb5 1921 1922/* pci_peek() 1923 * TRAP: HV_FAST_TRAP 1924 * FUNCTION: HV_FAST_PCI_PEEK 1925 * ARG0: devhandle 1926 * ARG1: real address 1927 * ARG2: size 1928 * RET0: status 1929 * RET1: error_flag 1930 * RET2: data 1931 * ERRORS: EINVAL Invalid devhandle or size 1932 * EBADALIGN Improperly aligned real address 1933 * ENORADDR Bad real address 1934 * ENOACCESS Guest access prohibited 1935 * 1936 * Attempt to read the IO address given by the given devhandle, real address, 1937 * and size. Size must be 1, 2, 4, or 8. The read is performed as a single 1938 * access operation using the given size. If an error occurs when reading 1939 * from the given location, do not generate an error report, but return a 1940 * non-zero value in RET1. If the read was successful, return zero in RET1 1941 * and return the actual data read in RET2. The data returned is size based 1942 * byte swapped. 1943 * 1944 * Non-significant bits in RET2 are not guarenteed to have any specific value 1945 * and therefore must be ignored. If RET1 is returned as non-zero, the data 1946 * value is not guarenteed to have any specific value and should be ignored. 1947 * 1948 * The caller must have permission to read from the given devhandle, real 1949 * address, which must be an IO address. The argument real address must be a 1950 * size aligned address. 1951 * 1952 * The hypervisor implementation of this function must block access to any 1953 * IO address that the guest does not have explicit permission to access. 1954 */ 1955#define HV_FAST_PCI_PEEK 0xb6 1956 1957/* pci_poke() 1958 * TRAP: HV_FAST_TRAP 1959 * FUNCTION: HV_FAST_PCI_POKE 1960 * ARG0: devhandle 1961 * ARG1: real address 1962 * ARG2: size 1963 * ARG3: data 1964 * ARG4: pci_device 1965 * RET0: status 1966 * RET1: error_flag 1967 * ERRORS: EINVAL Invalid devhandle, size, or pci_device 1968 * EBADALIGN Improperly aligned real address 1969 * ENORADDR Bad real address 1970 * ENOACCESS Guest access prohibited 1971 * ENOTSUPPORTED Function is not supported by implementation 1972 * 1973 * Attempt to write data to the IO address given by the given devhandle, 1974 * real address, and size. Size must be 1, 2, 4, or 8. The write is 1975 * performed as a single access operation using the given size. Prior to 1976 * writing the data is size based swapped. 1977 * 1978 * If an error occurs when writing to the given location, do not generate an 1979 * error report, but return a non-zero value in RET1. If the write was 1980 * successful, return zero in RET1. 1981 * 1982 * pci_device describes the configuration address of the device being 1983 * written to. The implementation may safely read from offset 0 with 1984 * the configuration space of the device described by devhandle and 1985 * pci_device in order to guarantee that the write portion of the operation 1986 * completes 1987 * 1988 * Any error that occurs due to the read shall be reported using the normal 1989 * error reporting mechanisms .. the read error is not suppressed. 1990 * 1991 * The caller must have permission to write to the given devhandle, real 1992 * address, which must be an IO address. The argument real address must be a 1993 * size aligned address. The caller must have permission to read from 1994 * the given devhandle, pci_device cofiguration space offset 0. 1995 * 1996 * The hypervisor implementation of this function must block access to any 1997 * IO address that the guest does not have explicit permission to access. 1998 */ 1999#define HV_FAST_PCI_POKE 0xb7 2000 2001/* pci_dma_sync() 2002 * TRAP: HV_FAST_TRAP 2003 * FUNCTION: HV_FAST_PCI_DMA_SYNC 2004 * ARG0: devhandle 2005 * ARG1: real address 2006 * ARG2: size 2007 * ARG3: io_sync_direction 2008 * RET0: status 2009 * RET1: #synced 2010 * ERRORS: EINVAL Invalid devhandle or io_sync_direction 2011 * ENORADDR Bad real address 2012 * 2013 * Synchronize a memory region described by the given real address and size, 2014 * for the device defined by the given devhandle using the direction(s) 2015 * defined by the given io_sync_direction. The argument size is the size of 2016 * the memory region in bytes. 2017 * 2018 * Return the actual number of bytes synchronized in the return value #synced, 2019 * which may be less than or equal to the argument size. If the return 2020 * value #synced is less than size, the caller must continue to call this 2021 * function with updated real address and size arguments until the entire 2022 * memory region is synchronized. 2023 */ 2024#define HV_FAST_PCI_DMA_SYNC 0xb8 2025 2026/* PCI MSI services. */ 2027 2028#define HV_MSITYPE_MSI32 0x00 2029#define HV_MSITYPE_MSI64 0x01 2030 2031#define HV_MSIQSTATE_IDLE 0x00 2032#define HV_MSIQSTATE_ERROR 0x01 2033 2034#define HV_MSIQ_INVALID 0x00 2035#define HV_MSIQ_VALID 0x01 2036 2037#define HV_MSISTATE_IDLE 0x00 2038#define HV_MSISTATE_DELIVERED 0x01 2039 2040#define HV_MSIVALID_INVALID 0x00 2041#define HV_MSIVALID_VALID 0x01 2042 2043#define HV_PCIE_MSGTYPE_PME_MSG 0x18 2044#define HV_PCIE_MSGTYPE_PME_ACK_MSG 0x1b 2045#define HV_PCIE_MSGTYPE_CORR_MSG 0x30 2046#define HV_PCIE_MSGTYPE_NONFATAL_MSG 0x31 2047#define HV_PCIE_MSGTYPE_FATAL_MSG 0x33 2048 2049#define HV_MSG_INVALID 0x00 2050#define HV_MSG_VALID 0x01 2051 2052/* pci_msiq_conf() 2053 * TRAP: HV_FAST_TRAP 2054 * FUNCTION: HV_FAST_PCI_MSIQ_CONF 2055 * ARG0: devhandle 2056 * ARG1: msiqid 2057 * ARG2: real address 2058 * ARG3: number of entries 2059 * RET0: status 2060 * ERRORS: EINVAL Invalid devhandle, msiqid or nentries 2061 * EBADALIGN Improperly aligned real address 2062 * ENORADDR Bad real address 2063 * 2064 * Configure the MSI queue given by the devhandle and msiqid arguments, 2065 * and to be placed at the given real address and be of the given 2066 * number of entries. The real address must be aligned exactly to match 2067 * the queue size. Each queue entry is 64-bytes long, so f.e. a 32 entry 2068 * queue must be aligned on a 2048 byte real address boundary. The MSI-EQ 2069 * Head and Tail are initialized so that the MSI-EQ is 'empty'. 2070 * 2071 * Implementation Note: Certain implementations have fixed sized queues. In 2072 * that case, number of entries must contain the correct 2073 * value. 2074 */ 2075#define HV_FAST_PCI_MSIQ_CONF 0xc0 2076 2077/* pci_msiq_info() 2078 * TRAP: HV_FAST_TRAP 2079 * FUNCTION: HV_FAST_PCI_MSIQ_INFO 2080 * ARG0: devhandle 2081 * ARG1: msiqid 2082 * RET0: status 2083 * RET1: real address 2084 * RET2: number of entries 2085 * ERRORS: EINVAL Invalid devhandle or msiqid 2086 * 2087 * Return the configuration information for the MSI queue described 2088 * by the given devhandle and msiqid. The base address of the queue 2089 * is returned in ARG1 and the number of entries is returned in ARG2. 2090 * If the queue is unconfigured, the real address is undefined and the 2091 * number of entries will be returned as zero. 2092 */ 2093#define HV_FAST_PCI_MSIQ_INFO 0xc1 2094 2095/* pci_msiq_getvalid() 2096 * TRAP: HV_FAST_TRAP 2097 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID 2098 * ARG0: devhandle 2099 * ARG1: msiqid 2100 * RET0: status 2101 * RET1: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID) 2102 * ERRORS: EINVAL Invalid devhandle or msiqid 2103 * 2104 * Get the valid state of the MSI-EQ described by the given devhandle and 2105 * msiqid. 2106 */ 2107#define HV_FAST_PCI_MSIQ_GETVALID 0xc2 2108 2109/* pci_msiq_setvalid() 2110 * TRAP: HV_FAST_TRAP 2111 * FUNCTION: HV_FAST_PCI_MSIQ_SETVALID 2112 * ARG0: devhandle 2113 * ARG1: msiqid 2114 * ARG2: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID) 2115 * RET0: status 2116 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqvalid 2117 * value or MSI EQ is uninitialized 2118 * 2119 * Set the valid state of the MSI-EQ described by the given devhandle and 2120 * msiqid to the given msiqvalid. 2121 */ 2122#define HV_FAST_PCI_MSIQ_SETVALID 0xc3 2123 2124/* pci_msiq_getstate() 2125 * TRAP: HV_FAST_TRAP 2126 * FUNCTION: HV_FAST_PCI_MSIQ_GETSTATE 2127 * ARG0: devhandle 2128 * ARG1: msiqid 2129 * RET0: status 2130 * RET1: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR) 2131 * ERRORS: EINVAL Invalid devhandle or msiqid 2132 * 2133 * Get the state of the MSI-EQ described by the given devhandle and 2134 * msiqid. 2135 */ 2136#define HV_FAST_PCI_MSIQ_GETSTATE 0xc4 2137 2138/* pci_msiq_getvalid() 2139 * TRAP: HV_FAST_TRAP 2140 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID 2141 * ARG0: devhandle 2142 * ARG1: msiqid 2143 * ARG2: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR) 2144 * RET0: status 2145 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqstate 2146 * value or MSI EQ is uninitialized 2147 * 2148 * Set the state of the MSI-EQ described by the given devhandle and 2149 * msiqid to the given msiqvalid. 2150 */ 2151#define HV_FAST_PCI_MSIQ_SETSTATE 0xc5 2152 2153/* pci_msiq_gethead() 2154 * TRAP: HV_FAST_TRAP 2155 * FUNCTION: HV_FAST_PCI_MSIQ_GETHEAD 2156 * ARG0: devhandle 2157 * ARG1: msiqid 2158 * RET0: status 2159 * RET1: msiqhead 2160 * ERRORS: EINVAL Invalid devhandle or msiqid 2161 * 2162 * Get the current MSI EQ queue head for the MSI-EQ described by the 2163 * given devhandle and msiqid. 2164 */ 2165#define HV_FAST_PCI_MSIQ_GETHEAD 0xc6 2166 2167/* pci_msiq_sethead() 2168 * TRAP: HV_FAST_TRAP 2169 * FUNCTION: HV_FAST_PCI_MSIQ_SETHEAD 2170 * ARG0: devhandle 2171 * ARG1: msiqid 2172 * ARG2: msiqhead 2173 * RET0: status 2174 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqhead, 2175 * or MSI EQ is uninitialized 2176 * 2177 * Set the current MSI EQ queue head for the MSI-EQ described by the 2178 * given devhandle and msiqid. 2179 */ 2180#define HV_FAST_PCI_MSIQ_SETHEAD 0xc7 2181 2182/* pci_msiq_gettail() 2183 * TRAP: HV_FAST_TRAP 2184 * FUNCTION: HV_FAST_PCI_MSIQ_GETTAIL 2185 * ARG0: devhandle 2186 * ARG1: msiqid 2187 * RET0: status 2188 * RET1: msiqtail 2189 * ERRORS: EINVAL Invalid devhandle or msiqid 2190 * 2191 * Get the current MSI EQ queue tail for the MSI-EQ described by the 2192 * given devhandle and msiqid. 2193 */ 2194#define HV_FAST_PCI_MSIQ_GETTAIL 0xc8 2195 2196/* pci_msi_getvalid() 2197 * TRAP: HV_FAST_TRAP 2198 * FUNCTION: HV_FAST_PCI_MSI_GETVALID 2199 * ARG0: devhandle 2200 * ARG1: msinum 2201 * RET0: status 2202 * RET1: msivalidstate 2203 * ERRORS: EINVAL Invalid devhandle or msinum 2204 * 2205 * Get the current valid/enabled state for the MSI defined by the 2206 * given devhandle and msinum. 2207 */ 2208#define HV_FAST_PCI_MSI_GETVALID 0xc9 2209 2210/* pci_msi_setvalid() 2211 * TRAP: HV_FAST_TRAP 2212 * FUNCTION: HV_FAST_PCI_MSI_SETVALID 2213 * ARG0: devhandle 2214 * ARG1: msinum 2215 * ARG2: msivalidstate 2216 * RET0: status 2217 * ERRORS: EINVAL Invalid devhandle or msinum or msivalidstate 2218 * 2219 * Set the current valid/enabled state for the MSI defined by the 2220 * given devhandle and msinum. 2221 */ 2222#define HV_FAST_PCI_MSI_SETVALID 0xca 2223 2224/* pci_msi_getmsiq() 2225 * TRAP: HV_FAST_TRAP 2226 * FUNCTION: HV_FAST_PCI_MSI_GETMSIQ 2227 * ARG0: devhandle 2228 * ARG1: msinum 2229 * RET0: status 2230 * RET1: msiqid 2231 * ERRORS: EINVAL Invalid devhandle or msinum or MSI is unbound 2232 * 2233 * Get the MSI EQ that the MSI defined by the given devhandle and 2234 * msinum is bound to. 2235 */ 2236#define HV_FAST_PCI_MSI_GETMSIQ 0xcb 2237 2238/* pci_msi_setmsiq() 2239 * TRAP: HV_FAST_TRAP 2240 * FUNCTION: HV_FAST_PCI_MSI_SETMSIQ 2241 * ARG0: devhandle 2242 * ARG1: msinum 2243 * ARG2: msitype 2244 * ARG3: msiqid 2245 * RET0: status 2246 * ERRORS: EINVAL Invalid devhandle or msinum or msiqid 2247 * 2248 * Set the MSI EQ that the MSI defined by the given devhandle and 2249 * msinum is bound to. 2250 */ 2251#define HV_FAST_PCI_MSI_SETMSIQ 0xcc 2252 2253/* pci_msi_getstate() 2254 * TRAP: HV_FAST_TRAP 2255 * FUNCTION: HV_FAST_PCI_MSI_GETSTATE 2256 * ARG0: devhandle 2257 * ARG1: msinum 2258 * RET0: status 2259 * RET1: msistate 2260 * ERRORS: EINVAL Invalid devhandle or msinum 2261 * 2262 * Get the state of the MSI defined by the given devhandle and msinum. 2263 * If not initialized, return HV_MSISTATE_IDLE. 2264 */ 2265#define HV_FAST_PCI_MSI_GETSTATE 0xcd 2266 2267/* pci_msi_setstate() 2268 * TRAP: HV_FAST_TRAP 2269 * FUNCTION: HV_FAST_PCI_MSI_SETSTATE 2270 * ARG0: devhandle 2271 * ARG1: msinum 2272 * ARG2: msistate 2273 * RET0: status 2274 * ERRORS: EINVAL Invalid devhandle or msinum or msistate 2275 * 2276 * Set the state of the MSI defined by the given devhandle and msinum. 2277 */ 2278#define HV_FAST_PCI_MSI_SETSTATE 0xce 2279 2280/* pci_msg_getmsiq() 2281 * TRAP: HV_FAST_TRAP 2282 * FUNCTION: HV_FAST_PCI_MSG_GETMSIQ 2283 * ARG0: devhandle 2284 * ARG1: msgtype 2285 * RET0: status 2286 * RET1: msiqid 2287 * ERRORS: EINVAL Invalid devhandle or msgtype 2288 * 2289 * Get the MSI EQ of the MSG defined by the given devhandle and msgtype. 2290 */ 2291#define HV_FAST_PCI_MSG_GETMSIQ 0xd0 2292 2293/* pci_msg_setmsiq() 2294 * TRAP: HV_FAST_TRAP 2295 * FUNCTION: HV_FAST_PCI_MSG_SETMSIQ 2296 * ARG0: devhandle 2297 * ARG1: msgtype 2298 * ARG2: msiqid 2299 * RET0: status 2300 * ERRORS: EINVAL Invalid devhandle, msgtype, or msiqid 2301 * 2302 * Set the MSI EQ of the MSG defined by the given devhandle and msgtype. 2303 */ 2304#define HV_FAST_PCI_MSG_SETMSIQ 0xd1 2305 2306/* pci_msg_getvalid() 2307 * TRAP: HV_FAST_TRAP 2308 * FUNCTION: HV_FAST_PCI_MSG_GETVALID 2309 * ARG0: devhandle 2310 * ARG1: msgtype 2311 * RET0: status 2312 * RET1: msgvalidstate 2313 * ERRORS: EINVAL Invalid devhandle or msgtype 2314 * 2315 * Get the valid/enabled state of the MSG defined by the given 2316 * devhandle and msgtype. 2317 */ 2318#define HV_FAST_PCI_MSG_GETVALID 0xd2 2319 2320/* pci_msg_setvalid() 2321 * TRAP: HV_FAST_TRAP 2322 * FUNCTION: HV_FAST_PCI_MSG_SETVALID 2323 * ARG0: devhandle 2324 * ARG1: msgtype 2325 * ARG2: msgvalidstate 2326 * RET0: status 2327 * ERRORS: EINVAL Invalid devhandle or msgtype or msgvalidstate 2328 * 2329 * Set the valid/enabled state of the MSG defined by the given 2330 * devhandle and msgtype. 2331 */ 2332#define HV_FAST_PCI_MSG_SETVALID 0xd3 2333 2334/* Logical Domain Channel services. */ 2335 2336#define LDC_CHANNEL_DOWN 0 2337#define LDC_CHANNEL_UP 1 2338#define LDC_CHANNEL_RESETTING 2 2339 2340/* ldc_tx_qconf() 2341 * TRAP: HV_FAST_TRAP 2342 * FUNCTION: HV_FAST_LDC_TX_QCONF 2343 * ARG0: channel ID 2344 * ARG1: real address base of queue 2345 * ARG2: num entries in queue 2346 * RET0: status 2347 * 2348 * Configure transmit queue for the LDC endpoint specified by the 2349 * given channel ID, to be placed at the given real address, and 2350 * be of the given num entries. Num entries must be a power of two. 2351 * The real address base of the queue must be aligned on the queue 2352 * size. Each queue entry is 64-bytes, so for example, a 32 entry 2353 * queue must be aligned on a 2048 byte real address boundary. 2354 * 2355 * Upon configuration of a valid transmit queue the head and tail 2356 * pointers are set to a hypervisor specific identical value indicating 2357 * that the queue initially is empty. 2358 * 2359 * The endpoint's transmit queue is un-configured if num entries is zero. 2360 * 2361 * The maximum number of entries for each queue for a specific cpu may be 2362 * determined from the machine description. A transmit queue may be 2363 * specified even in the event that the LDC is down (peer endpoint has no 2364 * receive queue specified). Transmission will begin as soon as the peer 2365 * endpoint defines a receive queue. 2366 * 2367 * It is recommended that a guest wait for a transmit queue to empty prior 2368 * to reconfiguring it, or un-configuring it. Re or un-configuring of a 2369 * non-empty transmit queue behaves exactly as defined above, however it 2370 * is undefined as to how many of the pending entries in the original queue 2371 * will be delivered prior to the re-configuration taking effect. 2372 * Furthermore, as the queue configuration causes a reset of the head and 2373 * tail pointers there is no way for a guest to determine how many entries 2374 * have been sent after the configuration operation. 2375 */ 2376#define HV_FAST_LDC_TX_QCONF 0xe0 2377 2378/* ldc_tx_qinfo() 2379 * TRAP: HV_FAST_TRAP 2380 * FUNCTION: HV_FAST_LDC_TX_QINFO 2381 * ARG0: channel ID 2382 * RET0: status 2383 * RET1: real address base of queue 2384 * RET2: num entries in queue 2385 * 2386 * Return the configuration info for the transmit queue of LDC endpoint 2387 * defined by the given channel ID. The real address is the currently 2388 * defined real address base of the defined queue, and num entries is the 2389 * size of the queue in terms of number of entries. 2390 * 2391 * If the specified channel ID is a valid endpoint number, but no transmit 2392 * queue has been defined this service will return success, but with num 2393 * entries set to zero and the real address will have an undefined value. 2394 */ 2395#define HV_FAST_LDC_TX_QINFO 0xe1 2396 2397/* ldc_tx_get_state() 2398 * TRAP: HV_FAST_TRAP 2399 * FUNCTION: HV_FAST_LDC_TX_GET_STATE 2400 * ARG0: channel ID 2401 * RET0: status 2402 * RET1: head offset 2403 * RET2: tail offset 2404 * RET3: channel state 2405 * 2406 * Return the transmit state, and the head and tail queue pointers, for 2407 * the transmit queue of the LDC endpoint defined by the given channel ID. 2408 * The head and tail values are the byte offset of the head and tail 2409 * positions of the transmit queue for the specified endpoint. 2410 */ 2411#define HV_FAST_LDC_TX_GET_STATE 0xe2 2412 2413/* ldc_tx_set_qtail() 2414 * TRAP: HV_FAST_TRAP 2415 * FUNCTION: HV_FAST_LDC_TX_SET_QTAIL 2416 * ARG0: channel ID 2417 * ARG1: tail offset 2418 * RET0: status 2419 * 2420 * Update the tail pointer for the transmit queue associated with the LDC 2421 * endpoint defined by the given channel ID. The tail offset specified 2422 * must be aligned on a 64 byte boundary, and calculated so as to increase 2423 * the number of pending entries on the transmit queue. Any attempt to 2424 * decrease the number of pending transmit queue entires is considered 2425 * an invalid tail offset and will result in an EINVAL error. 2426 * 2427 * Since the tail of the transmit queue may not be moved backwards, the 2428 * transmit queue may be flushed by configuring a new transmit queue, 2429 * whereupon the hypervisor will configure the initial transmit head and 2430 * tail pointers to be equal. 2431 */ 2432#define HV_FAST_LDC_TX_SET_QTAIL 0xe3 2433 2434/* ldc_rx_qconf() 2435 * TRAP: HV_FAST_TRAP 2436 * FUNCTION: HV_FAST_LDC_RX_QCONF 2437 * ARG0: channel ID 2438 * ARG1: real address base of queue 2439 * ARG2: num entries in queue 2440 * RET0: status 2441 * 2442 * Configure receive queue for the LDC endpoint specified by the 2443 * given channel ID, to be placed at the given real address, and 2444 * be of the given num entries. Num entries must be a power of two. 2445 * The real address base of the queue must be aligned on the queue 2446 * size. Each queue entry is 64-bytes, so for example, a 32 entry 2447 * queue must be aligned on a 2048 byte real address boundary. 2448 * 2449 * The endpoint's transmit queue is un-configured if num entries is zero. 2450 * 2451 * If a valid receive queue is specified for a local endpoint the LDC is 2452 * in the up state for the purpose of transmission to this endpoint. 2453 * 2454 * The maximum number of entries for each queue for a specific cpu may be 2455 * determined from the machine description. 2456 * 2457 * As receive queue configuration causes a reset of the queue's head and 2458 * tail pointers there is no way for a gues to determine how many entries 2459 * have been received between a preceeding ldc_get_rx_state() API call 2460 * and the completion of the configuration operation. It should be noted 2461 * that datagram delivery is not guarenteed via domain channels anyway, 2462 * and therefore any higher protocol should be resilient to datagram 2463 * loss if necessary. However, to overcome this specific race potential 2464 * it is recommended, for example, that a higher level protocol be employed 2465 * to ensure either retransmission, or ensure that no datagrams are pending 2466 * on the peer endpoint's transmit queue prior to the configuration process. 2467 */ 2468#define HV_FAST_LDC_RX_QCONF 0xe4 2469 2470/* ldc_rx_qinfo() 2471 * TRAP: HV_FAST_TRAP 2472 * FUNCTION: HV_FAST_LDC_RX_QINFO 2473 * ARG0: channel ID 2474 * RET0: status 2475 * RET1: real address base of queue 2476 * RET2: num entries in queue 2477 * 2478 * Return the configuration info for the receive queue of LDC endpoint 2479 * defined by the given channel ID. The real address is the currently 2480 * defined real address base of the defined queue, and num entries is the 2481 * size of the queue in terms of number of entries. 2482 * 2483 * If the specified channel ID is a valid endpoint number, but no receive 2484 * queue has been defined this service will return success, but with num 2485 * entries set to zero and the real address will have an undefined value. 2486 */ 2487#define HV_FAST_LDC_RX_QINFO 0xe5 2488 2489/* ldc_rx_get_state() 2490 * TRAP: HV_FAST_TRAP 2491 * FUNCTION: HV_FAST_LDC_RX_GET_STATE 2492 * ARG0: channel ID 2493 * RET0: status 2494 * RET1: head offset 2495 * RET2: tail offset 2496 * RET3: channel state 2497 * 2498 * Return the receive state, and the head and tail queue pointers, for 2499 * the receive queue of the LDC endpoint defined by the given channel ID. 2500 * The head and tail values are the byte offset of the head and tail 2501 * positions of the receive queue for the specified endpoint. 2502 */ 2503#define HV_FAST_LDC_RX_GET_STATE 0xe6 2504 2505/* ldc_rx_set_qhead() 2506 * TRAP: HV_FAST_TRAP 2507 * FUNCTION: HV_FAST_LDC_RX_SET_QHEAD 2508 * ARG0: channel ID 2509 * ARG1: head offset 2510 * RET0: status 2511 * 2512 * Update the head pointer for the receive queue associated with the LDC 2513 * endpoint defined by the given channel ID. The head offset specified 2514 * must be aligned on a 64 byte boundary, and calculated so as to decrease 2515 * the number of pending entries on the receive queue. Any attempt to 2516 * increase the number of pending receive queue entires is considered 2517 * an invalid head offset and will result in an EINVAL error. 2518 * 2519 * The receive queue may be flushed by setting the head offset equal 2520 * to the current tail offset. 2521 */ 2522#define HV_FAST_LDC_RX_SET_QHEAD 0xe7 2523 2524/* LDC Map Table Entry. Each slot is defined by a translation table 2525 * entry, as specified by the LDC_MTE_* bits below, and a 64-bit 2526 * hypervisor invalidation cookie. 2527 */ 2528#define LDC_MTE_PADDR 0x0fffffffffffe000 /* pa[55:13] */ 2529#define LDC_MTE_COPY_W 0x0000000000000400 /* copy write access */ 2530#define LDC_MTE_COPY_R 0x0000000000000200 /* copy read access */ 2531#define LDC_MTE_IOMMU_W 0x0000000000000100 /* IOMMU write access */ 2532#define LDC_MTE_IOMMU_R 0x0000000000000080 /* IOMMU read access */ 2533#define LDC_MTE_EXEC 0x0000000000000040 /* execute */ 2534#define LDC_MTE_WRITE 0x0000000000000020 /* read */ 2535#define LDC_MTE_READ 0x0000000000000010 /* write */ 2536#define LDC_MTE_SZALL 0x000000000000000f /* page size bits */ 2537#define LDC_MTE_SZ16GB 0x0000000000000007 /* 16GB page */ 2538#define LDC_MTE_SZ2GB 0x0000000000000006 /* 2GB page */ 2539#define LDC_MTE_SZ256MB 0x0000000000000005 /* 256MB page */ 2540#define LDC_MTE_SZ32MB 0x0000000000000004 /* 32MB page */ 2541#define LDC_MTE_SZ4MB 0x0000000000000003 /* 4MB page */ 2542#define LDC_MTE_SZ512K 0x0000000000000002 /* 512K page */ 2543#define LDC_MTE_SZ64K 0x0000000000000001 /* 64K page */ 2544#define LDC_MTE_SZ8K 0x0000000000000000 /* 8K page */ 2545 2546#ifndef __ASSEMBLY__ 2547struct ldc_mtable_entry { 2548 unsigned long mte; 2549 unsigned long cookie; 2550}; 2551#endif 2552 2553/* ldc_set_map_table() 2554 * TRAP: HV_FAST_TRAP 2555 * FUNCTION: HV_FAST_LDC_SET_MAP_TABLE 2556 * ARG0: channel ID 2557 * ARG1: table real address 2558 * ARG2: num entries 2559 * RET0: status 2560 * 2561 * Register the MTE table at the given table real address, with the 2562 * specified num entries, for the LDC indicated by the given channel 2563 * ID. 2564 */ 2565#define HV_FAST_LDC_SET_MAP_TABLE 0xea 2566 2567/* ldc_get_map_table() 2568 * TRAP: HV_FAST_TRAP 2569 * FUNCTION: HV_FAST_LDC_GET_MAP_TABLE 2570 * ARG0: channel ID 2571 * RET0: status 2572 * RET1: table real address 2573 * RET2: num entries 2574 * 2575 * Return the configuration of the current mapping table registered 2576 * for the given channel ID. 2577 */ 2578#define HV_FAST_LDC_GET_MAP_TABLE 0xeb 2579 2580#define LDC_COPY_IN 0 2581#define LDC_COPY_OUT 1 2582 2583/* ldc_copy() 2584 * TRAP: HV_FAST_TRAP 2585 * FUNCTION: HV_FAST_LDC_COPY 2586 * ARG0: channel ID 2587 * ARG1: LDC_COPY_* direction code 2588 * ARG2: target real address 2589 * ARG3: local real address 2590 * ARG4: length in bytes 2591 * RET0: status 2592 * RET1: actual length in bytes 2593 */ 2594#define HV_FAST_LDC_COPY 0xec 2595 2596#define LDC_MEM_READ 1 2597#define LDC_MEM_WRITE 2 2598#define LDC_MEM_EXEC 4 2599 2600/* ldc_mapin() 2601 * TRAP: HV_FAST_TRAP 2602 * FUNCTION: HV_FAST_LDC_MAPIN 2603 * ARG0: channel ID 2604 * ARG1: cookie 2605 * RET0: status 2606 * RET1: real address 2607 * RET2: LDC_MEM_* permissions 2608 */ 2609#define HV_FAST_LDC_MAPIN 0xed 2610 2611/* ldc_unmap() 2612 * TRAP: HV_FAST_TRAP 2613 * FUNCTION: HV_FAST_LDC_UNMAP 2614 * ARG0: real address 2615 * RET0: status 2616 */ 2617#define HV_FAST_LDC_UNMAP 0xee 2618 2619/* ldc_revoke() 2620 * TRAP: HV_FAST_TRAP 2621 * FUNCTION: HV_FAST_LDC_REVOKE 2622 * ARG0: channel ID 2623 * ARG1: cookie 2624 * ARG2: ldc_mtable_entry cookie 2625 * RET0: status 2626 */ 2627#define HV_FAST_LDC_REVOKE 0xef 2628 2629#ifndef __ASSEMBLY__ 2630extern unsigned long sun4v_ldc_tx_qconf(unsigned long channel, 2631 unsigned long ra, 2632 unsigned long num_entries); 2633extern unsigned long sun4v_ldc_tx_qinfo(unsigned long channel, 2634 unsigned long *ra, 2635 unsigned long *num_entries); 2636extern unsigned long sun4v_ldc_tx_get_state(unsigned long channel, 2637 unsigned long *head_off, 2638 unsigned long *tail_off, 2639 unsigned long *chan_state); 2640extern unsigned long sun4v_ldc_tx_set_qtail(unsigned long channel, 2641 unsigned long tail_off); 2642extern unsigned long sun4v_ldc_rx_qconf(unsigned long channel, 2643 unsigned long ra, 2644 unsigned long num_entries); 2645extern unsigned long sun4v_ldc_rx_qinfo(unsigned long channel, 2646 unsigned long *ra, 2647 unsigned long *num_entries); 2648extern unsigned long sun4v_ldc_rx_get_state(unsigned long channel, 2649 unsigned long *head_off, 2650 unsigned long *tail_off, 2651 unsigned long *chan_state); 2652extern unsigned long sun4v_ldc_rx_set_qhead(unsigned long channel, 2653 unsigned long head_off); 2654extern unsigned long sun4v_ldc_set_map_table(unsigned long channel, 2655 unsigned long ra, 2656 unsigned long num_entries); 2657extern unsigned long sun4v_ldc_get_map_table(unsigned long channel, 2658 unsigned long *ra, 2659 unsigned long *num_entries); 2660extern unsigned long sun4v_ldc_copy(unsigned long channel, 2661 unsigned long dir_code, 2662 unsigned long tgt_raddr, 2663 unsigned long lcl_raddr, 2664 unsigned long len, 2665 unsigned long *actual_len); 2666extern unsigned long sun4v_ldc_mapin(unsigned long channel, 2667 unsigned long cookie, 2668 unsigned long *ra, 2669 unsigned long *perm); 2670extern unsigned long sun4v_ldc_unmap(unsigned long ra); 2671extern unsigned long sun4v_ldc_revoke(unsigned long channel, 2672 unsigned long cookie, 2673 unsigned long mte_cookie); 2674#endif 2675 2676/* Performance counter services. */ 2677 2678#define HV_PERF_JBUS_PERF_CTRL_REG 0x00 2679#define HV_PERF_JBUS_PERF_CNT_REG 0x01 2680#define HV_PERF_DRAM_PERF_CTRL_REG_0 0x02 2681#define HV_PERF_DRAM_PERF_CNT_REG_0 0x03 2682#define HV_PERF_DRAM_PERF_CTRL_REG_1 0x04 2683#define HV_PERF_DRAM_PERF_CNT_REG_1 0x05 2684#define HV_PERF_DRAM_PERF_CTRL_REG_2 0x06 2685#define HV_PERF_DRAM_PERF_CNT_REG_2 0x07 2686#define HV_PERF_DRAM_PERF_CTRL_REG_3 0x08 2687#define HV_PERF_DRAM_PERF_CNT_REG_3 0x09 2688 2689/* get_perfreg() 2690 * TRAP: HV_FAST_TRAP 2691 * FUNCTION: HV_FAST_GET_PERFREG 2692 * ARG0: performance reg number 2693 * RET0: status 2694 * RET1: performance reg value 2695 * ERRORS: EINVAL Invalid performance register number 2696 * ENOACCESS No access allowed to performance counters 2697 * 2698 * Read the value of the given DRAM/JBUS performance counter/control register. 2699 */ 2700#define HV_FAST_GET_PERFREG 0x100 2701 2702/* set_perfreg() 2703 * TRAP: HV_FAST_TRAP 2704 * FUNCTION: HV_FAST_SET_PERFREG 2705 * ARG0: performance reg number 2706 * ARG1: performance reg value 2707 * RET0: status 2708 * ERRORS: EINVAL Invalid performance register number 2709 * ENOACCESS No access allowed to performance counters 2710 * 2711 * Write the given performance reg value to the given DRAM/JBUS 2712 * performance counter/control register. 2713 */ 2714#define HV_FAST_SET_PERFREG 0x101 2715 2716#define HV_N2_PERF_SPARC_CTL 0x0 2717#define HV_N2_PERF_DRAM_CTL0 0x1 2718#define HV_N2_PERF_DRAM_CNT0 0x2 2719#define HV_N2_PERF_DRAM_CTL1 0x3 2720#define HV_N2_PERF_DRAM_CNT1 0x4 2721#define HV_N2_PERF_DRAM_CTL2 0x5 2722#define HV_N2_PERF_DRAM_CNT2 0x6 2723#define HV_N2_PERF_DRAM_CTL3 0x7 2724#define HV_N2_PERF_DRAM_CNT3 0x8 2725 2726#define HV_FAST_N2_GET_PERFREG 0x104 2727#define HV_FAST_N2_SET_PERFREG 0x105 2728 2729#ifndef __ASSEMBLY__ 2730extern unsigned long sun4v_niagara_getperf(unsigned long reg, 2731 unsigned long *val); 2732extern unsigned long sun4v_niagara_setperf(unsigned long reg, 2733 unsigned long val); 2734extern unsigned long sun4v_niagara2_getperf(unsigned long reg, 2735 unsigned long *val); 2736extern unsigned long sun4v_niagara2_setperf(unsigned long reg, 2737 unsigned long val); 2738#endif 2739 2740/* MMU statistics services. 2741 * 2742 * The hypervisor maintains MMU statistics and privileged code provides 2743 * a buffer where these statistics can be collected. It is continually 2744 * updated once configured. The layout is as follows: 2745 */ 2746#ifndef __ASSEMBLY__ 2747struct hv_mmu_statistics { 2748 unsigned long immu_tsb_hits_ctx0_8k_tte; 2749 unsigned long immu_tsb_ticks_ctx0_8k_tte; 2750 unsigned long immu_tsb_hits_ctx0_64k_tte; 2751 unsigned long immu_tsb_ticks_ctx0_64k_tte; 2752 unsigned long __reserved1[2]; 2753 unsigned long immu_tsb_hits_ctx0_4mb_tte; 2754 unsigned long immu_tsb_ticks_ctx0_4mb_tte; 2755 unsigned long __reserved2[2]; 2756 unsigned long immu_tsb_hits_ctx0_256mb_tte; 2757 unsigned long immu_tsb_ticks_ctx0_256mb_tte; 2758 unsigned long __reserved3[4]; 2759 unsigned long immu_tsb_hits_ctxnon0_8k_tte; 2760 unsigned long immu_tsb_ticks_ctxnon0_8k_tte; 2761 unsigned long immu_tsb_hits_ctxnon0_64k_tte; 2762 unsigned long immu_tsb_ticks_ctxnon0_64k_tte; 2763 unsigned long __reserved4[2]; 2764 unsigned long immu_tsb_hits_ctxnon0_4mb_tte; 2765 unsigned long immu_tsb_ticks_ctxnon0_4mb_tte; 2766 unsigned long __reserved5[2]; 2767 unsigned long immu_tsb_hits_ctxnon0_256mb_tte; 2768 unsigned long immu_tsb_ticks_ctxnon0_256mb_tte; 2769 unsigned long __reserved6[4]; 2770 unsigned long dmmu_tsb_hits_ctx0_8k_tte; 2771 unsigned long dmmu_tsb_ticks_ctx0_8k_tte; 2772 unsigned long dmmu_tsb_hits_ctx0_64k_tte; 2773 unsigned long dmmu_tsb_ticks_ctx0_64k_tte; 2774 unsigned long __reserved7[2]; 2775 unsigned long dmmu_tsb_hits_ctx0_4mb_tte; 2776 unsigned long dmmu_tsb_ticks_ctx0_4mb_tte; 2777 unsigned long __reserved8[2]; 2778 unsigned long dmmu_tsb_hits_ctx0_256mb_tte; 2779 unsigned long dmmu_tsb_ticks_ctx0_256mb_tte; 2780 unsigned long __reserved9[4]; 2781 unsigned long dmmu_tsb_hits_ctxnon0_8k_tte; 2782 unsigned long dmmu_tsb_ticks_ctxnon0_8k_tte; 2783 unsigned long dmmu_tsb_hits_ctxnon0_64k_tte; 2784 unsigned long dmmu_tsb_ticks_ctxnon0_64k_tte; 2785 unsigned long __reserved10[2]; 2786 unsigned long dmmu_tsb_hits_ctxnon0_4mb_tte; 2787 unsigned long dmmu_tsb_ticks_ctxnon0_4mb_tte; 2788 unsigned long __reserved11[2]; 2789 unsigned long dmmu_tsb_hits_ctxnon0_256mb_tte; 2790 unsigned long dmmu_tsb_ticks_ctxnon0_256mb_tte; 2791 unsigned long __reserved12[4]; 2792}; 2793#endif 2794 2795/* mmustat_conf() 2796 * TRAP: HV_FAST_TRAP 2797 * FUNCTION: HV_FAST_MMUSTAT_CONF 2798 * ARG0: real address 2799 * RET0: status 2800 * RET1: real address 2801 * ERRORS: ENORADDR Invalid real address 2802 * EBADALIGN Real address not aligned on 64-byte boundary 2803 * EBADTRAP API not supported on this processor 2804 * 2805 * Enable MMU statistic gathering using the buffer at the given real 2806 * address on the current virtual CPU. The new buffer real address 2807 * is given in ARG1, and the previously specified buffer real address 2808 * is returned in RET1, or is returned as zero for the first invocation. 2809 * 2810 * If the passed in real address argument is zero, this will disable 2811 * MMU statistic collection on the current virtual CPU. If an error is 2812 * returned then no statistics are collected. 2813 * 2814 * The buffer contents should be initialized to all zeros before being 2815 * given to the hypervisor or else the statistics will be meaningless. 2816 */ 2817#define HV_FAST_MMUSTAT_CONF 0x102 2818 2819/* mmustat_info() 2820 * TRAP: HV_FAST_TRAP 2821 * FUNCTION: HV_FAST_MMUSTAT_INFO 2822 * RET0: status 2823 * RET1: real address 2824 * ERRORS: EBADTRAP API not supported on this processor 2825 * 2826 * Return the current state and real address of the currently configured 2827 * MMU statistics buffer on the current virtual CPU. 2828 */ 2829#define HV_FAST_MMUSTAT_INFO 0x103 2830 2831#ifndef __ASSEMBLY__ 2832extern unsigned long sun4v_mmustat_conf(unsigned long ra, unsigned long *orig_ra); 2833extern unsigned long sun4v_mmustat_info(unsigned long *ra); 2834#endif 2835 2836/* NCS crypto services */ 2837 2838/* ncs_request() sub-function numbers */ 2839#define HV_NCS_QCONF 0x01 2840#define HV_NCS_QTAIL_UPDATE 0x02 2841 2842#ifndef __ASSEMBLY__ 2843struct hv_ncs_queue_entry { 2844 /* MAU Control Register */ 2845 unsigned long mau_control; 2846#define MAU_CONTROL_INV_PARITY 0x0000000000002000 2847#define MAU_CONTROL_STRAND 0x0000000000001800 2848#define MAU_CONTROL_BUSY 0x0000000000000400 2849#define MAU_CONTROL_INT 0x0000000000000200 2850#define MAU_CONTROL_OP 0x00000000000001c0 2851#define MAU_CONTROL_OP_SHIFT 6 2852#define MAU_OP_LOAD_MA_MEMORY 0x0 2853#define MAU_OP_STORE_MA_MEMORY 0x1 2854#define MAU_OP_MODULAR_MULT 0x2 2855#define MAU_OP_MODULAR_REDUCE 0x3 2856#define MAU_OP_MODULAR_EXP_LOOP 0x4 2857#define MAU_CONTROL_LEN 0x000000000000003f 2858#define MAU_CONTROL_LEN_SHIFT 0 2859 2860 /* Real address of bytes to load or store bytes 2861 * into/out-of the MAU. 2862 */ 2863 unsigned long mau_mpa; 2864 2865 /* Modular Arithmetic MA Offset Register. */ 2866 unsigned long mau_ma; 2867 2868 /* Modular Arithmetic N Prime Register. */ 2869 unsigned long mau_np; 2870}; 2871 2872struct hv_ncs_qconf_arg { 2873 unsigned long mid; /* MAU ID, 1 per core on Niagara */ 2874 unsigned long base; /* Real address base of queue */ 2875 unsigned long end; /* Real address end of queue */ 2876 unsigned long num_ents; /* Number of entries in queue */ 2877}; 2878 2879struct hv_ncs_qtail_update_arg { 2880 unsigned long mid; /* MAU ID, 1 per core on Niagara */ 2881 unsigned long tail; /* New tail index to use */ 2882 unsigned long syncflag; /* only SYNCFLAG_SYNC is implemented */ 2883#define HV_NCS_SYNCFLAG_SYNC 0x00 2884#define HV_NCS_SYNCFLAG_ASYNC 0x01 2885}; 2886#endif 2887 2888/* ncs_request() 2889 * TRAP: HV_FAST_TRAP 2890 * FUNCTION: HV_FAST_NCS_REQUEST 2891 * ARG0: NCS sub-function 2892 * ARG1: sub-function argument real address 2893 * ARG2: size in bytes of sub-function argument 2894 * RET0: status 2895 * 2896 * The MAU chip of the Niagara processor is not directly accessible 2897 * to privileged code, instead it is programmed indirectly via this 2898 * hypervisor API. 2899 * 2900 * The interfaces defines a queue of MAU operations to perform. 2901 * Privileged code registers a queue with the hypervisor by invoking 2902 * this HVAPI with the HV_NCS_QCONF sub-function, which defines the 2903 * base, end, and number of entries of the queue. Each queue entry 2904 * contains a MAU register struct block. 2905 * 2906 * The privileged code then proceeds to add entries to the queue and 2907 * then invoke the HV_NCS_QTAIL_UPDATE sub-function. Since only 2908 * synchronous operations are supported by the current hypervisor, 2909 * HV_NCS_QTAIL_UPDATE will run all the pending queue entries to 2910 * completion and return HV_EOK, or return an error code. 2911 * 2912 * The real address of the sub-function argument must be aligned on at 2913 * least an 8-byte boundary. 2914 * 2915 * The tail argument of HV_NCS_QTAIL_UPDATE is an index, not a byte 2916 * offset, into the queue and must be less than or equal the 'num_ents' 2917 * argument given in the HV_NCS_QCONF call. 2918 */ 2919#define HV_FAST_NCS_REQUEST 0x110 2920 2921#ifndef __ASSEMBLY__ 2922extern unsigned long sun4v_ncs_request(unsigned long request, 2923 unsigned long arg_ra, 2924 unsigned long arg_size); 2925#endif 2926 2927#define HV_FAST_FIRE_GET_PERFREG 0x120 2928#define HV_FAST_FIRE_SET_PERFREG 0x121 2929 2930/* Function numbers for HV_CORE_TRAP. */ 2931#define HV_CORE_SET_VER 0x00 2932#define HV_CORE_PUTCHAR 0x01 2933#define HV_CORE_EXIT 0x02 2934#define HV_CORE_GET_VER 0x03 2935 2936/* Hypervisor API groups for use with HV_CORE_SET_VER and 2937 * HV_CORE_GET_VER. 2938 */ 2939#define HV_GRP_SUN4V 0x0000 2940#define HV_GRP_CORE 0x0001 2941#define HV_GRP_INTR 0x0002 2942#define HV_GRP_SOFT_STATE 0x0003 2943#define HV_GRP_PCI 0x0100 2944#define HV_GRP_LDOM 0x0101 2945#define HV_GRP_SVC_CHAN 0x0102 2946#define HV_GRP_NCS 0x0103 2947#define HV_GRP_RNG 0x0104 2948#define HV_GRP_NIAG_PERF 0x0200 2949#define HV_GRP_FIRE_PERF 0x0201 2950#define HV_GRP_N2_CPU 0x0202 2951#define HV_GRP_NIU 0x0204 2952#define HV_GRP_VF_CPU 0x0205 2953#define HV_GRP_DIAG 0x0300 2954 2955#ifndef __ASSEMBLY__ 2956extern unsigned long sun4v_get_version(unsigned long group, 2957 unsigned long *major, 2958 unsigned long *minor); 2959extern unsigned long sun4v_set_version(unsigned long group, 2960 unsigned long major, 2961 unsigned long minor, 2962 unsigned long *actual_minor); 2963 2964extern int sun4v_hvapi_register(unsigned long group, unsigned long major, 2965 unsigned long *minor); 2966extern void sun4v_hvapi_unregister(unsigned long group); 2967extern int sun4v_hvapi_get(unsigned long group, 2968 unsigned long *major, 2969 unsigned long *minor); 2970extern void sun4v_hvapi_init(void); 2971#endif 2972 2973#endif /* !(_SPARC64_HYPERVISOR_H) */ 2974