1/* 2 * SH7203 and SH7263 Setup 3 * 4 * Copyright (C) 2007 - 2009 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10#include <linux/platform_device.h> 11#include <linux/init.h> 12#include <linux/serial.h> 13#include <linux/serial_sci.h> 14#include <linux/sh_timer.h> 15#include <linux/io.h> 16 17enum { 18 UNUSED = 0, 19 20 /* interrupt sources */ 21 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 22 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 23 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, 24 USB, LCDC, CMT0, CMT1, BSC, WDT, 25 26 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU, 27 MTU3_ABCD, MTU4_ABCD, MTU2_TCI3V, MTU2_TCI4V, 28 29 ADC_ADI, 30 31 IIC30, IIC31, IIC32, IIC33, 32 SCIF0, SCIF1, SCIF2, SCIF3, 33 34 SSU0, SSU1, 35 36 SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII, 37 38 /* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */ 39 ROMDEC, FLCTL, SDHI, RTC, RCAN0, RCAN1, 40 SRC, IEBI, 41 42 /* interrupt groups */ 43 PINT, 44}; 45 46static struct intc_vect vectors[] __initdata = { 47 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), 48 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), 49 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), 50 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), 51 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), 52 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), 53 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), 54 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), 55 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109), 56 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113), 57 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117), 58 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121), 59 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125), 60 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129), 61 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133), 62 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137), 63 INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141), 64 INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143), 65 INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145), 66 INTC_IRQ(MTU0_ABCD, 146), INTC_IRQ(MTU0_ABCD, 147), 67 INTC_IRQ(MTU0_ABCD, 148), INTC_IRQ(MTU0_ABCD, 149), 68 INTC_IRQ(MTU0_VEF, 150), 69 INTC_IRQ(MTU0_VEF, 151), INTC_IRQ(MTU0_VEF, 152), 70 INTC_IRQ(MTU1_AB, 153), INTC_IRQ(MTU1_AB, 154), 71 INTC_IRQ(MTU1_VU, 155), INTC_IRQ(MTU1_VU, 156), 72 INTC_IRQ(MTU2_AB, 157), INTC_IRQ(MTU2_AB, 158), 73 INTC_IRQ(MTU2_VU, 159), INTC_IRQ(MTU2_VU, 160), 74 INTC_IRQ(MTU3_ABCD, 161), INTC_IRQ(MTU3_ABCD, 162), 75 INTC_IRQ(MTU3_ABCD, 163), INTC_IRQ(MTU3_ABCD, 164), 76 INTC_IRQ(MTU2_TCI3V, 165), 77 INTC_IRQ(MTU4_ABCD, 166), INTC_IRQ(MTU4_ABCD, 167), 78 INTC_IRQ(MTU4_ABCD, 168), INTC_IRQ(MTU4_ABCD, 169), 79 INTC_IRQ(MTU2_TCI4V, 170), 80 INTC_IRQ(ADC_ADI, 171), 81 INTC_IRQ(IIC30, 172), INTC_IRQ(IIC30, 173), 82 INTC_IRQ(IIC30, 174), INTC_IRQ(IIC30, 175), 83 INTC_IRQ(IIC30, 176), 84 INTC_IRQ(IIC31, 177), INTC_IRQ(IIC31, 178), 85 INTC_IRQ(IIC31, 179), INTC_IRQ(IIC31, 180), 86 INTC_IRQ(IIC31, 181), 87 INTC_IRQ(IIC32, 182), INTC_IRQ(IIC32, 183), 88 INTC_IRQ(IIC32, 184), INTC_IRQ(IIC32, 185), 89 INTC_IRQ(IIC32, 186), 90 INTC_IRQ(IIC33, 187), INTC_IRQ(IIC33, 188), 91 INTC_IRQ(IIC33, 189), INTC_IRQ(IIC33, 190), 92 INTC_IRQ(IIC33, 191), 93 INTC_IRQ(SCIF0, 192), INTC_IRQ(SCIF0, 193), 94 INTC_IRQ(SCIF0, 194), INTC_IRQ(SCIF0, 195), 95 INTC_IRQ(SCIF1, 196), INTC_IRQ(SCIF1, 197), 96 INTC_IRQ(SCIF1, 198), INTC_IRQ(SCIF1, 199), 97 INTC_IRQ(SCIF2, 200), INTC_IRQ(SCIF2, 201), 98 INTC_IRQ(SCIF2, 202), INTC_IRQ(SCIF2, 203), 99 INTC_IRQ(SCIF3, 204), INTC_IRQ(SCIF3, 205), 100 INTC_IRQ(SCIF3, 206), INTC_IRQ(SCIF3, 207), 101 INTC_IRQ(SSU0, 208), INTC_IRQ(SSU0, 209), 102 INTC_IRQ(SSU0, 210), 103 INTC_IRQ(SSU1, 211), INTC_IRQ(SSU1, 212), 104 INTC_IRQ(SSU1, 213), 105 INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215), 106 INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217), 107 INTC_IRQ(FLCTL, 224), INTC_IRQ(FLCTL, 225), 108 INTC_IRQ(FLCTL, 226), INTC_IRQ(FLCTL, 227), 109 INTC_IRQ(RTC, 231), INTC_IRQ(RTC, 232), 110 INTC_IRQ(RTC, 233), 111 INTC_IRQ(RCAN0, 234), INTC_IRQ(RCAN0, 235), 112 INTC_IRQ(RCAN0, 236), INTC_IRQ(RCAN0, 237), 113 INTC_IRQ(RCAN0, 238), 114 INTC_IRQ(RCAN1, 239), INTC_IRQ(RCAN1, 240), 115 INTC_IRQ(RCAN1, 241), INTC_IRQ(RCAN1, 242), 116 INTC_IRQ(RCAN1, 243), 117 118 /* SH7263-specific trash */ 119#ifdef CONFIG_CPU_SUBTYPE_SH7263 120 INTC_IRQ(ROMDEC, 218), INTC_IRQ(ROMDEC, 219), 121 INTC_IRQ(ROMDEC, 220), INTC_IRQ(ROMDEC, 221), 122 INTC_IRQ(ROMDEC, 222), INTC_IRQ(ROMDEC, 223), 123 124 INTC_IRQ(SDHI, 228), INTC_IRQ(SDHI, 229), 125 INTC_IRQ(SDHI, 230), 126 127 INTC_IRQ(SRC, 244), INTC_IRQ(SRC, 245), 128 INTC_IRQ(SRC, 246), 129 130 INTC_IRQ(IEBI, 247), 131#endif 132}; 133 134static struct intc_group groups[] __initdata = { 135 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 136 PINT4, PINT5, PINT6, PINT7), 137}; 138 139static struct intc_prio_reg prio_registers[] __initdata = { 140 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, 141 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, 142 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } }, 143 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } }, 144 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } }, 145 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } }, 146 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } }, 147 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU1_AB, MTU1_VU, MTU2_AB, 148 MTU2_VU } }, 149 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU3_ABCD, MTU2_TCI3V, MTU4_ABCD, 150 MTU2_TCI4V } }, 151 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } }, 152 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } }, 153 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } }, 154#ifdef CONFIG_CPU_SUBTYPE_SH7203 155 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII, 156 SSI3_SSII, 0 } }, 157 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } }, 158 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } }, 159#else 160 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII, 161 SSI3_SSII, ROMDEC } }, 162 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, SDHI, RTC, RCAN0 } }, 163 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, SRC, IEBI, 0 } }, 164#endif 165}; 166 167static struct intc_mask_reg mask_registers[] __initdata = { 168 { 0xfffe0808, 0, 16, /* PINTER */ 169 { 0, 0, 0, 0, 0, 0, 0, 0, 170 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, 171}; 172 173static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups, 174 mask_registers, prio_registers, NULL); 175 176static struct plat_sci_port scif0_platform_data = { 177 .mapbase = 0xfffe8000, 178 .flags = UPF_BOOT_AUTOCONF, 179 .type = PORT_SCIF, 180 .irqs = { 192, 192, 192, 192 }, 181}; 182 183static struct platform_device scif0_device = { 184 .name = "sh-sci", 185 .id = 0, 186 .dev = { 187 .platform_data = &scif0_platform_data, 188 }, 189}; 190 191static struct plat_sci_port scif1_platform_data = { 192 .mapbase = 0xfffe8800, 193 .flags = UPF_BOOT_AUTOCONF, 194 .type = PORT_SCIF, 195 .irqs = { 196, 196, 196, 196 }, 196}; 197 198static struct platform_device scif1_device = { 199 .name = "sh-sci", 200 .id = 1, 201 .dev = { 202 .platform_data = &scif1_platform_data, 203 }, 204}; 205 206static struct plat_sci_port scif2_platform_data = { 207 .mapbase = 0xfffe9000, 208 .flags = UPF_BOOT_AUTOCONF, 209 .type = PORT_SCIF, 210 .irqs = { 200, 200, 200, 200 }, 211}; 212 213static struct platform_device scif2_device = { 214 .name = "sh-sci", 215 .id = 2, 216 .dev = { 217 .platform_data = &scif2_platform_data, 218 }, 219}; 220 221static struct plat_sci_port scif3_platform_data = { 222 .mapbase = 0xfffe9800, 223 .flags = UPF_BOOT_AUTOCONF, 224 .type = PORT_SCIF, 225 .irqs = { 204, 204, 204, 204 }, 226}; 227 228static struct platform_device scif3_device = { 229 .name = "sh-sci", 230 .id = 3, 231 .dev = { 232 .platform_data = &scif3_platform_data, 233 }, 234}; 235 236static struct sh_timer_config cmt0_platform_data = { 237 .channel_offset = 0x02, 238 .timer_bit = 0, 239 .clockevent_rating = 125, 240 .clocksource_rating = 0, /* disabled due to code generation issues */ 241}; 242 243static struct resource cmt0_resources[] = { 244 [0] = { 245 .start = 0xfffec002, 246 .end = 0xfffec007, 247 .flags = IORESOURCE_MEM, 248 }, 249 [1] = { 250 .start = 142, 251 .flags = IORESOURCE_IRQ, 252 }, 253}; 254 255static struct platform_device cmt0_device = { 256 .name = "sh_cmt", 257 .id = 0, 258 .dev = { 259 .platform_data = &cmt0_platform_data, 260 }, 261 .resource = cmt0_resources, 262 .num_resources = ARRAY_SIZE(cmt0_resources), 263}; 264 265static struct sh_timer_config cmt1_platform_data = { 266 .channel_offset = 0x08, 267 .timer_bit = 1, 268 .clockevent_rating = 125, 269 .clocksource_rating = 0, /* disabled due to code generation issues */ 270}; 271 272static struct resource cmt1_resources[] = { 273 [0] = { 274 .start = 0xfffec008, 275 .end = 0xfffec00d, 276 .flags = IORESOURCE_MEM, 277 }, 278 [1] = { 279 .start = 143, 280 .flags = IORESOURCE_IRQ, 281 }, 282}; 283 284static struct platform_device cmt1_device = { 285 .name = "sh_cmt", 286 .id = 1, 287 .dev = { 288 .platform_data = &cmt1_platform_data, 289 }, 290 .resource = cmt1_resources, 291 .num_resources = ARRAY_SIZE(cmt1_resources), 292}; 293 294static struct sh_timer_config mtu2_0_platform_data = { 295 .channel_offset = -0x80, 296 .timer_bit = 0, 297 .clockevent_rating = 200, 298}; 299 300static struct resource mtu2_0_resources[] = { 301 [0] = { 302 .start = 0xfffe4300, 303 .end = 0xfffe4326, 304 .flags = IORESOURCE_MEM, 305 }, 306 [1] = { 307 .start = 146, 308 .flags = IORESOURCE_IRQ, 309 }, 310}; 311 312static struct platform_device mtu2_0_device = { 313 .name = "sh_mtu2", 314 .id = 0, 315 .dev = { 316 .platform_data = &mtu2_0_platform_data, 317 }, 318 .resource = mtu2_0_resources, 319 .num_resources = ARRAY_SIZE(mtu2_0_resources), 320}; 321 322static struct sh_timer_config mtu2_1_platform_data = { 323 .channel_offset = -0x100, 324 .timer_bit = 1, 325 .clockevent_rating = 200, 326}; 327 328static struct resource mtu2_1_resources[] = { 329 [0] = { 330 .start = 0xfffe4380, 331 .end = 0xfffe4390, 332 .flags = IORESOURCE_MEM, 333 }, 334 [1] = { 335 .start = 153, 336 .flags = IORESOURCE_IRQ, 337 }, 338}; 339 340static struct platform_device mtu2_1_device = { 341 .name = "sh_mtu2", 342 .id = 1, 343 .dev = { 344 .platform_data = &mtu2_1_platform_data, 345 }, 346 .resource = mtu2_1_resources, 347 .num_resources = ARRAY_SIZE(mtu2_1_resources), 348}; 349 350static struct resource rtc_resources[] = { 351 [0] = { 352 .start = 0xffff2000, 353 .end = 0xffff2000 + 0x58 - 1, 354 .flags = IORESOURCE_IO, 355 }, 356 [1] = { 357 /* Shared Period/Carry/Alarm IRQ */ 358 .start = 231, 359 .flags = IORESOURCE_IRQ, 360 }, 361}; 362 363static struct platform_device rtc_device = { 364 .name = "sh-rtc", 365 .id = -1, 366 .num_resources = ARRAY_SIZE(rtc_resources), 367 .resource = rtc_resources, 368}; 369 370static struct platform_device *sh7203_devices[] __initdata = { 371 &scif0_device, 372 &scif1_device, 373 &scif2_device, 374 &scif3_device, 375 &cmt0_device, 376 &cmt1_device, 377 &mtu2_0_device, 378 &mtu2_1_device, 379 &rtc_device, 380}; 381 382static int __init sh7203_devices_setup(void) 383{ 384 return platform_add_devices(sh7203_devices, 385 ARRAY_SIZE(sh7203_devices)); 386} 387arch_initcall(sh7203_devices_setup); 388 389void __init plat_irq_setup(void) 390{ 391 register_intc_controller(&intc_desc); 392} 393 394static struct platform_device *sh7203_early_devices[] __initdata = { 395 &scif0_device, 396 &scif1_device, 397 &scif2_device, 398 &scif3_device, 399 &cmt0_device, 400 &cmt1_device, 401 &mtu2_0_device, 402 &mtu2_1_device, 403}; 404 405#define STBCR3 0xfffe0408 406#define STBCR4 0xfffe040c 407 408void __init plat_early_device_setup(void) 409{ 410 /* enable CMT clock */ 411 __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4); 412 413 /* enable MTU2 clock */ 414 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3); 415 416 early_platform_add_devices(sh7203_early_devices, 417 ARRAY_SIZE(sh7203_early_devices)); 418} 419