1/* 2 * SH4 CPU-specific DMA definitions, used by both DMA drivers 3 * 4 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10#ifndef CPU_DMA_REGISTER_H 11#define CPU_DMA_REGISTER_H 12 13/* SH7751/7760/7780 DMA IRQ sources */ 14 15#ifdef CONFIG_CPU_SH4A 16 17#define DMAOR_INIT DMAOR_DME 18 19#if defined(CONFIG_CPU_SUBTYPE_SH7343) || defined(CONFIG_CPU_SUBTYPE_SH7730) 20#define CHCR_TS_LOW_MASK 0x00000018 21#define CHCR_TS_LOW_SHIFT 3 22#define CHCR_TS_HIGH_MASK 0 23#define CHCR_TS_HIGH_SHIFT 0 24#elif defined(CONFIG_CPU_SUBTYPE_SH7722) || \ 25 defined(CONFIG_CPU_SUBTYPE_SH7724) || \ 26 defined(CONFIG_CPU_SUBTYPE_SH7786) 27#define CHCR_TS_LOW_MASK 0x00000018 28#define CHCR_TS_LOW_SHIFT 3 29#define CHCR_TS_HIGH_MASK 0x00300000 30#define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */ 31#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 32 defined(CONFIG_CPU_SUBTYPE_SH7764) 33#define CHCR_TS_LOW_MASK 0x00000018 34#define CHCR_TS_LOW_SHIFT 3 35#define CHCR_TS_HIGH_MASK 0 36#define CHCR_TS_HIGH_SHIFT 0 37#elif defined(CONFIG_CPU_SUBTYPE_SH7723) 38#define CHCR_TS_LOW_MASK 0x00000018 39#define CHCR_TS_LOW_SHIFT 3 40#define CHCR_TS_HIGH_MASK 0 41#define CHCR_TS_HIGH_SHIFT 0 42#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 43#define CHCR_TS_LOW_MASK 0x00000018 44#define CHCR_TS_LOW_SHIFT 3 45#define CHCR_TS_HIGH_MASK 0 46#define CHCR_TS_HIGH_SHIFT 0 47#else /* SH7785 */ 48#define CHCR_TS_LOW_MASK 0x00000018 49#define CHCR_TS_LOW_SHIFT 3 50#define CHCR_TS_HIGH_MASK 0 51#define CHCR_TS_HIGH_SHIFT 0 52#endif 53 54/* Transmit sizes and respective CHCR register values */ 55enum { 56 XMIT_SZ_8BIT = 0, 57 XMIT_SZ_16BIT = 1, 58 XMIT_SZ_32BIT = 2, 59 XMIT_SZ_64BIT = 7, 60 XMIT_SZ_128BIT = 3, 61 XMIT_SZ_256BIT = 4, 62 XMIT_SZ_128BIT_BLK = 0xb, 63 XMIT_SZ_256BIT_BLK = 0xc, 64}; 65 66/* log2(size / 8) - used to calculate number of transfers */ 67#define TS_SHIFT { \ 68 [XMIT_SZ_8BIT] = 0, \ 69 [XMIT_SZ_16BIT] = 1, \ 70 [XMIT_SZ_32BIT] = 2, \ 71 [XMIT_SZ_64BIT] = 3, \ 72 [XMIT_SZ_128BIT] = 4, \ 73 [XMIT_SZ_256BIT] = 5, \ 74 [XMIT_SZ_128BIT_BLK] = 4, \ 75 [XMIT_SZ_256BIT_BLK] = 5, \ 76} 77 78#define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \ 79 (((i) & 0xc) << CHCR_TS_HIGH_SHIFT)) 80 81#else /* CONFIG_CPU_SH4A */ 82 83#define DMAOR_INIT (0x8000 | DMAOR_DME) 84 85#define CHCR_TS_LOW_MASK 0x70 86#define CHCR_TS_LOW_SHIFT 4 87#define CHCR_TS_HIGH_MASK 0 88#define CHCR_TS_HIGH_SHIFT 0 89 90/* Transmit sizes and respective CHCR register values */ 91enum { 92 XMIT_SZ_8BIT = 1, 93 XMIT_SZ_16BIT = 2, 94 XMIT_SZ_32BIT = 3, 95 XMIT_SZ_64BIT = 0, 96 XMIT_SZ_256BIT = 4, 97}; 98 99/* log2(size / 8) - used to calculate number of transfers */ 100#define TS_SHIFT { \ 101 [XMIT_SZ_8BIT] = 0, \ 102 [XMIT_SZ_16BIT] = 1, \ 103 [XMIT_SZ_32BIT] = 2, \ 104 [XMIT_SZ_64BIT] = 3, \ 105 [XMIT_SZ_256BIT] = 5, \ 106} 107 108#define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT) 109 110#endif /* CONFIG_CPU_SH4A */ 111 112#endif 113