1/* 2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. 3 * 4 * Authors: Shlomi Gridish <gridish@freescale.com> 5 * Li Yang <leoli@freescale.com> 6 * 7 * Description: 8 * QE UCC Fast API Set - UCC Fast specific routines implementations. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15#include <linux/kernel.h> 16#include <linux/init.h> 17#include <linux/errno.h> 18#include <linux/slab.h> 19#include <linux/stddef.h> 20#include <linux/interrupt.h> 21#include <linux/err.h> 22#include <linux/module.h> 23 24#include <asm/io.h> 25#include <asm/immap_qe.h> 26#include <asm/qe.h> 27 28#include <asm/ucc.h> 29#include <asm/ucc_fast.h> 30 31void ucc_fast_dump_regs(struct ucc_fast_private * uccf) 32{ 33 printk(KERN_INFO "UCC%u Fast registers:\n", uccf->uf_info->ucc_num); 34 printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs); 35 36 printk(KERN_INFO "gumr : addr=0x%p, val=0x%08x\n", 37 &uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr)); 38 printk(KERN_INFO "upsmr : addr=0x%p, val=0x%08x\n", 39 &uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr)); 40 printk(KERN_INFO "utodr : addr=0x%p, val=0x%04x\n", 41 &uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr)); 42 printk(KERN_INFO "udsr : addr=0x%p, val=0x%04x\n", 43 &uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr)); 44 printk(KERN_INFO "ucce : addr=0x%p, val=0x%08x\n", 45 &uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce)); 46 printk(KERN_INFO "uccm : addr=0x%p, val=0x%08x\n", 47 &uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm)); 48 printk(KERN_INFO "uccs : addr=0x%p, val=0x%02x\n", 49 &uccf->uf_regs->uccs, in_8(&uccf->uf_regs->uccs)); 50 printk(KERN_INFO "urfb : addr=0x%p, val=0x%08x\n", 51 &uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb)); 52 printk(KERN_INFO "urfs : addr=0x%p, val=0x%04x\n", 53 &uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs)); 54 printk(KERN_INFO "urfet : addr=0x%p, val=0x%04x\n", 55 &uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet)); 56 printk(KERN_INFO "urfset: addr=0x%p, val=0x%04x\n", 57 &uccf->uf_regs->urfset, in_be16(&uccf->uf_regs->urfset)); 58 printk(KERN_INFO "utfb : addr=0x%p, val=0x%08x\n", 59 &uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb)); 60 printk(KERN_INFO "utfs : addr=0x%p, val=0x%04x\n", 61 &uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs)); 62 printk(KERN_INFO "utfet : addr=0x%p, val=0x%04x\n", 63 &uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet)); 64 printk(KERN_INFO "utftt : addr=0x%p, val=0x%04x\n", 65 &uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt)); 66 printk(KERN_INFO "utpt : addr=0x%p, val=0x%04x\n", 67 &uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt)); 68 printk(KERN_INFO "urtry : addr=0x%p, val=0x%08x\n", 69 &uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry)); 70 printk(KERN_INFO "guemr : addr=0x%p, val=0x%02x\n", 71 &uccf->uf_regs->guemr, in_8(&uccf->uf_regs->guemr)); 72} 73EXPORT_SYMBOL(ucc_fast_dump_regs); 74 75u32 ucc_fast_get_qe_cr_subblock(int uccf_num) 76{ 77 switch (uccf_num) { 78 case 0: return QE_CR_SUBBLOCK_UCCFAST1; 79 case 1: return QE_CR_SUBBLOCK_UCCFAST2; 80 case 2: return QE_CR_SUBBLOCK_UCCFAST3; 81 case 3: return QE_CR_SUBBLOCK_UCCFAST4; 82 case 4: return QE_CR_SUBBLOCK_UCCFAST5; 83 case 5: return QE_CR_SUBBLOCK_UCCFAST6; 84 case 6: return QE_CR_SUBBLOCK_UCCFAST7; 85 case 7: return QE_CR_SUBBLOCK_UCCFAST8; 86 default: return QE_CR_SUBBLOCK_INVALID; 87 } 88} 89EXPORT_SYMBOL(ucc_fast_get_qe_cr_subblock); 90 91void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf) 92{ 93 out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD); 94} 95EXPORT_SYMBOL(ucc_fast_transmit_on_demand); 96 97void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode) 98{ 99 struct ucc_fast __iomem *uf_regs; 100 u32 gumr; 101 102 uf_regs = uccf->uf_regs; 103 104 /* Enable reception and/or transmission on this UCC. */ 105 gumr = in_be32(&uf_regs->gumr); 106 if (mode & COMM_DIR_TX) { 107 gumr |= UCC_FAST_GUMR_ENT; 108 uccf->enabled_tx = 1; 109 } 110 if (mode & COMM_DIR_RX) { 111 gumr |= UCC_FAST_GUMR_ENR; 112 uccf->enabled_rx = 1; 113 } 114 out_be32(&uf_regs->gumr, gumr); 115} 116EXPORT_SYMBOL(ucc_fast_enable); 117 118void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode) 119{ 120 struct ucc_fast __iomem *uf_regs; 121 u32 gumr; 122 123 uf_regs = uccf->uf_regs; 124 125 /* Disable reception and/or transmission on this UCC. */ 126 gumr = in_be32(&uf_regs->gumr); 127 if (mode & COMM_DIR_TX) { 128 gumr &= ~UCC_FAST_GUMR_ENT; 129 uccf->enabled_tx = 0; 130 } 131 if (mode & COMM_DIR_RX) { 132 gumr &= ~UCC_FAST_GUMR_ENR; 133 uccf->enabled_rx = 0; 134 } 135 out_be32(&uf_regs->gumr, gumr); 136} 137EXPORT_SYMBOL(ucc_fast_disable); 138 139int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret) 140{ 141 struct ucc_fast_private *uccf; 142 struct ucc_fast __iomem *uf_regs; 143 u32 gumr; 144 int ret; 145 146 if (!uf_info) 147 return -EINVAL; 148 149 /* check if the UCC port number is in range. */ 150 if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) { 151 printk(KERN_ERR "%s: illegal UCC number\n", __func__); 152 return -EINVAL; 153 } 154 155 /* Check that 'max_rx_buf_length' is properly aligned (4). */ 156 if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) { 157 printk(KERN_ERR "%s: max_rx_buf_length not aligned\n", 158 __func__); 159 return -EINVAL; 160 } 161 162 /* Validate Virtual Fifo register values */ 163 if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) { 164 printk(KERN_ERR "%s: urfs is too small\n", __func__); 165 return -EINVAL; 166 } 167 168 if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 169 printk(KERN_ERR "%s: urfs is not aligned\n", __func__); 170 return -EINVAL; 171 } 172 173 if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 174 printk(KERN_ERR "%s: urfet is not aligned.\n", __func__); 175 return -EINVAL; 176 } 177 178 if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 179 printk(KERN_ERR "%s: urfset is not aligned\n", __func__); 180 return -EINVAL; 181 } 182 183 if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 184 printk(KERN_ERR "%s: utfs is not aligned\n", __func__); 185 return -EINVAL; 186 } 187 188 if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 189 printk(KERN_ERR "%s: utfet is not aligned\n", __func__); 190 return -EINVAL; 191 } 192 193 if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 194 printk(KERN_ERR "%s: utftt is not aligned\n", __func__); 195 return -EINVAL; 196 } 197 198 uccf = kzalloc(sizeof(struct ucc_fast_private), GFP_KERNEL); 199 if (!uccf) { 200 printk(KERN_ERR "%s: Cannot allocate private data\n", 201 __func__); 202 return -ENOMEM; 203 } 204 205 /* Fill fast UCC structure */ 206 uccf->uf_info = uf_info; 207 /* Set the PHY base address */ 208 uccf->uf_regs = ioremap(uf_info->regs, sizeof(struct ucc_fast)); 209 if (uccf->uf_regs == NULL) { 210 printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__); 211 kfree(uccf); 212 return -ENOMEM; 213 } 214 215 uccf->enabled_tx = 0; 216 uccf->enabled_rx = 0; 217 uccf->stopped_tx = 0; 218 uccf->stopped_rx = 0; 219 uf_regs = uccf->uf_regs; 220 uccf->p_ucce = &uf_regs->ucce; 221 uccf->p_uccm = &uf_regs->uccm; 222#ifdef CONFIG_UGETH_TX_ON_DEMAND 223 uccf->p_utodr = &uf_regs->utodr; 224#endif 225#ifdef STATISTICS 226 uccf->tx_frames = 0; 227 uccf->rx_frames = 0; 228 uccf->rx_discarded = 0; 229#endif /* STATISTICS */ 230 231 /* Set UCC to fast type */ 232 ret = ucc_set_type(uf_info->ucc_num, UCC_SPEED_TYPE_FAST); 233 if (ret) { 234 printk(KERN_ERR "%s: cannot set UCC type\n", __func__); 235 ucc_fast_free(uccf); 236 return ret; 237 } 238 239 uccf->mrblr = uf_info->max_rx_buf_length; 240 241 /* Set GUMR */ 242 /* For more details see the hardware spec. */ 243 gumr = uf_info->ttx_trx; 244 if (uf_info->tci) 245 gumr |= UCC_FAST_GUMR_TCI; 246 if (uf_info->cdp) 247 gumr |= UCC_FAST_GUMR_CDP; 248 if (uf_info->ctsp) 249 gumr |= UCC_FAST_GUMR_CTSP; 250 if (uf_info->cds) 251 gumr |= UCC_FAST_GUMR_CDS; 252 if (uf_info->ctss) 253 gumr |= UCC_FAST_GUMR_CTSS; 254 if (uf_info->txsy) 255 gumr |= UCC_FAST_GUMR_TXSY; 256 if (uf_info->rsyn) 257 gumr |= UCC_FAST_GUMR_RSYN; 258 gumr |= uf_info->synl; 259 if (uf_info->rtsm) 260 gumr |= UCC_FAST_GUMR_RTSM; 261 gumr |= uf_info->renc; 262 if (uf_info->revd) 263 gumr |= UCC_FAST_GUMR_REVD; 264 gumr |= uf_info->tenc; 265 gumr |= uf_info->tcrc; 266 gumr |= uf_info->mode; 267 out_be32(&uf_regs->gumr, gumr); 268 269 /* Allocate memory for Tx Virtual Fifo */ 270 uccf->ucc_fast_tx_virtual_fifo_base_offset = 271 qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); 272 if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) { 273 printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n", 274 __func__); 275 uccf->ucc_fast_tx_virtual_fifo_base_offset = 0; 276 ucc_fast_free(uccf); 277 return -ENOMEM; 278 } 279 280 /* Allocate memory for Rx Virtual Fifo */ 281 uccf->ucc_fast_rx_virtual_fifo_base_offset = 282 qe_muram_alloc(uf_info->urfs + 283 UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR, 284 UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); 285 if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) { 286 printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n", 287 __func__); 288 uccf->ucc_fast_rx_virtual_fifo_base_offset = 0; 289 ucc_fast_free(uccf); 290 return -ENOMEM; 291 } 292 293 /* Set Virtual Fifo registers */ 294 out_be16(&uf_regs->urfs, uf_info->urfs); 295 out_be16(&uf_regs->urfet, uf_info->urfet); 296 out_be16(&uf_regs->urfset, uf_info->urfset); 297 out_be16(&uf_regs->utfs, uf_info->utfs); 298 out_be16(&uf_regs->utfet, uf_info->utfet); 299 out_be16(&uf_regs->utftt, uf_info->utftt); 300 /* utfb, urfb are offsets from MURAM base */ 301 out_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset); 302 out_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset); 303 304 /* Mux clocking */ 305 /* Grant Support */ 306 ucc_set_qe_mux_grant(uf_info->ucc_num, uf_info->grant_support); 307 /* Breakpoint Support */ 308 ucc_set_qe_mux_bkpt(uf_info->ucc_num, uf_info->brkpt_support); 309 /* Set Tsa or NMSI mode. */ 310 ucc_set_qe_mux_tsa(uf_info->ucc_num, uf_info->tsa); 311 /* If NMSI (not Tsa), set Tx and Rx clock. */ 312 if (!uf_info->tsa) { 313 /* Rx clock routing */ 314 if ((uf_info->rx_clock != QE_CLK_NONE) && 315 ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->rx_clock, 316 COMM_DIR_RX)) { 317 printk(KERN_ERR "%s: illegal value for RX clock\n", 318 __func__); 319 ucc_fast_free(uccf); 320 return -EINVAL; 321 } 322 /* Tx clock routing */ 323 if ((uf_info->tx_clock != QE_CLK_NONE) && 324 ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->tx_clock, 325 COMM_DIR_TX)) { 326 printk(KERN_ERR "%s: illegal value for TX clock\n", 327 __func__); 328 ucc_fast_free(uccf); 329 return -EINVAL; 330 } 331 } 332 333 /* Set interrupt mask register at UCC level. */ 334 out_be32(&uf_regs->uccm, uf_info->uccm_mask); 335 336 /* First, clear anything pending at UCC level, 337 * otherwise, old garbage may come through 338 * as soon as the dam is opened. */ 339 340 /* Writing '1' clears */ 341 out_be32(&uf_regs->ucce, 0xffffffff); 342 343 *uccf_ret = uccf; 344 return 0; 345} 346EXPORT_SYMBOL(ucc_fast_init); 347 348void ucc_fast_free(struct ucc_fast_private * uccf) 349{ 350 if (!uccf) 351 return; 352 353 if (uccf->ucc_fast_tx_virtual_fifo_base_offset) 354 qe_muram_free(uccf->ucc_fast_tx_virtual_fifo_base_offset); 355 356 if (uccf->ucc_fast_rx_virtual_fifo_base_offset) 357 qe_muram_free(uccf->ucc_fast_rx_virtual_fifo_base_offset); 358 359 if (uccf->uf_regs) 360 iounmap(uccf->uf_regs); 361 362 kfree(uccf); 363} 364EXPORT_SYMBOL(ucc_fast_free); 365