1/* 2 * PCI / PCI-X / PCI-Express support for 4xx parts 3 * 4 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp. 5 * 6 * Most PCI Express code is coming from Stefan Roese implementation for 7 * arch/ppc in the Denx tree, slightly reworked by me. 8 * 9 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de> 10 * 11 * Some of that comes itself from a previous implementation for 440SPE only 12 * by Roland Dreier: 13 * 14 * Copyright (c) 2005 Cisco Systems. All rights reserved. 15 * Roland Dreier <rolandd@cisco.com> 16 * 17 */ 18 19#undef DEBUG 20 21#include <linux/kernel.h> 22#include <linux/pci.h> 23#include <linux/init.h> 24#include <linux/of.h> 25#include <linux/bootmem.h> 26#include <linux/delay.h> 27#include <linux/slab.h> 28 29#include <asm/io.h> 30#include <asm/pci-bridge.h> 31#include <asm/machdep.h> 32#include <asm/dcr.h> 33#include <asm/dcr-regs.h> 34#include <mm/mmu_decl.h> 35 36#include "ppc4xx_pci.h" 37 38static int dma_offset_set; 39 40#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL)) 41#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32)) 42 43#define RES_TO_U32_LOW(val) \ 44 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val)) 45#define RES_TO_U32_HIGH(val) \ 46 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0)) 47 48static inline int ppc440spe_revA(void) 49{ 50 /* Catch both 440SPe variants, with and without RAID6 support */ 51 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890) 52 return 1; 53 else 54 return 0; 55} 56 57static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev) 58{ 59 struct pci_controller *hose; 60 int i; 61 62 if (dev->devfn != 0 || dev->bus->self != NULL) 63 return; 64 65 hose = pci_bus_to_host(dev->bus); 66 if (hose == NULL) 67 return; 68 69 if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") && 70 !of_device_is_compatible(hose->dn, "ibm,plb-pcix") && 71 !of_device_is_compatible(hose->dn, "ibm,plb-pci")) 72 return; 73 74 if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") || 75 of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) { 76 hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM; 77 } 78 79 /* Hide the PCI host BARs from the kernel as their content doesn't 80 * fit well in the resource management 81 */ 82 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 83 dev->resource[i].start = dev->resource[i].end = 0; 84 dev->resource[i].flags = 0; 85 } 86 87 printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n", 88 pci_name(dev)); 89} 90DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge); 91 92static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose, 93 void __iomem *reg, 94 struct resource *res) 95{ 96 u64 size; 97 const u32 *ranges; 98 int rlen; 99 int pna = of_n_addr_cells(hose->dn); 100 int np = pna + 5; 101 102 /* Default */ 103 res->start = 0; 104 size = 0x80000000; 105 res->end = size - 1; 106 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; 107 108 /* Get dma-ranges property */ 109 ranges = of_get_property(hose->dn, "dma-ranges", &rlen); 110 if (ranges == NULL) 111 goto out; 112 113 /* Walk it */ 114 while ((rlen -= np * 4) >= 0) { 115 u32 pci_space = ranges[0]; 116 u64 pci_addr = of_read_number(ranges + 1, 2); 117 u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3); 118 size = of_read_number(ranges + pna + 3, 2); 119 ranges += np; 120 if (cpu_addr == OF_BAD_ADDR || size == 0) 121 continue; 122 123 /* We only care about memory */ 124 if ((pci_space & 0x03000000) != 0x02000000) 125 continue; 126 127 /* We currently only support memory at 0, and pci_addr 128 * within 32 bits space 129 */ 130 if (cpu_addr != 0 || pci_addr > 0xffffffff) { 131 printk(KERN_WARNING "%s: Ignored unsupported dma range" 132 " 0x%016llx...0x%016llx -> 0x%016llx\n", 133 hose->dn->full_name, 134 pci_addr, pci_addr + size - 1, cpu_addr); 135 continue; 136 } 137 138 /* Check if not prefetchable */ 139 if (!(pci_space & 0x40000000)) 140 res->flags &= ~IORESOURCE_PREFETCH; 141 142 143 /* Use that */ 144 res->start = pci_addr; 145 /* Beware of 32 bits resources */ 146 if (sizeof(resource_size_t) == sizeof(u32) && 147 (pci_addr + size) > 0x100000000ull) 148 res->end = 0xffffffff; 149 else 150 res->end = res->start + size - 1; 151 break; 152 } 153 154 /* We only support one global DMA offset */ 155 if (dma_offset_set && pci_dram_offset != res->start) { 156 printk(KERN_ERR "%s: dma-ranges(s) mismatch\n", 157 hose->dn->full_name); 158 return -ENXIO; 159 } 160 161 /* Check that we can fit all of memory as we don't support 162 * DMA bounce buffers 163 */ 164 if (size < total_memory) { 165 printk(KERN_ERR "%s: dma-ranges too small " 166 "(size=%llx total_memory=%llx)\n", 167 hose->dn->full_name, size, (u64)total_memory); 168 return -ENXIO; 169 } 170 171 /* Check we are a power of 2 size and that base is a multiple of size*/ 172 if ((size & (size - 1)) != 0 || 173 (res->start & (size - 1)) != 0) { 174 printk(KERN_ERR "%s: dma-ranges unaligned\n", 175 hose->dn->full_name); 176 return -ENXIO; 177 } 178 179 /* Check that we are fully contained within 32 bits space */ 180 if (res->end > 0xffffffff) { 181 printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n", 182 hose->dn->full_name); 183 return -ENXIO; 184 } 185 out: 186 dma_offset_set = 1; 187 pci_dram_offset = res->start; 188 189 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n", 190 pci_dram_offset); 191 return 0; 192} 193 194/* 195 * 4xx PCI 2.x part 196 */ 197 198static int __init ppc4xx_setup_one_pci_PMM(struct pci_controller *hose, 199 void __iomem *reg, 200 u64 plb_addr, 201 u64 pci_addr, 202 u64 size, 203 unsigned int flags, 204 int index) 205{ 206 u32 ma, pcila, pciha; 207 208 /* Hack warning ! The "old" PCI 2.x cell only let us configure the low 209 * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit 210 * address are actually hard wired to a value that appears to depend 211 * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx. 212 * 213 * The trick here is we just crop those top bits and ignore them when 214 * programming the chip. That means the device-tree has to be right 215 * for the specific part used (we don't print a warning if it's wrong 216 * but on the other hand, you'll crash quickly enough), but at least 217 * this code should work whatever the hard coded value is 218 */ 219 plb_addr &= 0xffffffffull; 220 221 /* Note: Due to the above hack, the test below doesn't actually test 222 * if you address is above 4G, but it tests that address and 223 * (address + size) are both contained in the same 4G 224 */ 225 if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) || 226 size < 0x1000 || (plb_addr & (size - 1)) != 0) { 227 printk(KERN_WARNING "%s: Resource out of range\n", 228 hose->dn->full_name); 229 return -1; 230 } 231 ma = (0xffffffffu << ilog2(size)) | 1; 232 if (flags & IORESOURCE_PREFETCH) 233 ma |= 2; 234 235 pciha = RES_TO_U32_HIGH(pci_addr); 236 pcila = RES_TO_U32_LOW(pci_addr); 237 238 writel(plb_addr, reg + PCIL0_PMM0LA + (0x10 * index)); 239 writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * index)); 240 writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * index)); 241 writel(ma, reg + PCIL0_PMM0MA + (0x10 * index)); 242 243 return 0; 244} 245 246static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose, 247 void __iomem *reg) 248{ 249 int i, j, found_isa_hole = 0; 250 251 /* Setup outbound memory windows */ 252 for (i = j = 0; i < 3; i++) { 253 struct resource *res = &hose->mem_resources[i]; 254 255 /* we only care about memory windows */ 256 if (!(res->flags & IORESOURCE_MEM)) 257 continue; 258 if (j > 2) { 259 printk(KERN_WARNING "%s: Too many ranges\n", 260 hose->dn->full_name); 261 break; 262 } 263 264 /* Configure the resource */ 265 if (ppc4xx_setup_one_pci_PMM(hose, reg, 266 res->start, 267 res->start - hose->pci_mem_offset, 268 res->end + 1 - res->start, 269 res->flags, 270 j) == 0) { 271 j++; 272 273 /* If the resource PCI address is 0 then we have our 274 * ISA memory hole 275 */ 276 if (res->start == hose->pci_mem_offset) 277 found_isa_hole = 1; 278 } 279 } 280 281 /* Handle ISA memory hole if not already covered */ 282 if (j <= 2 && !found_isa_hole && hose->isa_mem_size) 283 if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0, 284 hose->isa_mem_size, 0, j) == 0) 285 printk(KERN_INFO "%s: Legacy ISA memory support enabled\n", 286 hose->dn->full_name); 287} 288 289static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose, 290 void __iomem *reg, 291 const struct resource *res) 292{ 293 resource_size_t size = res->end - res->start + 1; 294 u32 sa; 295 296 /* Calculate window size */ 297 sa = (0xffffffffu << ilog2(size)) | 1; 298 sa |= 0x1; 299 300 /* RAM is always at 0 local for now */ 301 writel(0, reg + PCIL0_PTM1LA); 302 writel(sa, reg + PCIL0_PTM1MS); 303 304 /* Map on PCI side */ 305 early_write_config_dword(hose, hose->first_busno, 0, 306 PCI_BASE_ADDRESS_1, res->start); 307 early_write_config_dword(hose, hose->first_busno, 0, 308 PCI_BASE_ADDRESS_2, 0x00000000); 309 early_write_config_word(hose, hose->first_busno, 0, 310 PCI_COMMAND, 0x0006); 311} 312 313static void __init ppc4xx_probe_pci_bridge(struct device_node *np) 314{ 315 /* NYI */ 316 struct resource rsrc_cfg; 317 struct resource rsrc_reg; 318 struct resource dma_window; 319 struct pci_controller *hose = NULL; 320 void __iomem *reg = NULL; 321 const int *bus_range; 322 int primary = 0; 323 324 /* Check if device is enabled */ 325 if (!of_device_is_available(np)) { 326 printk(KERN_INFO "%s: Port disabled via device-tree\n", 327 np->full_name); 328 return; 329 } 330 331 /* Fetch config space registers address */ 332 if (of_address_to_resource(np, 0, &rsrc_cfg)) { 333 printk(KERN_ERR "%s: Can't get PCI config register base !", 334 np->full_name); 335 return; 336 } 337 /* Fetch host bridge internal registers address */ 338 if (of_address_to_resource(np, 3, &rsrc_reg)) { 339 printk(KERN_ERR "%s: Can't get PCI internal register base !", 340 np->full_name); 341 return; 342 } 343 344 /* Check if primary bridge */ 345 if (of_get_property(np, "primary", NULL)) 346 primary = 1; 347 348 /* Get bus range if any */ 349 bus_range = of_get_property(np, "bus-range", NULL); 350 351 /* Map registers */ 352 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start); 353 if (reg == NULL) { 354 printk(KERN_ERR "%s: Can't map registers !", np->full_name); 355 goto fail; 356 } 357 358 /* Allocate the host controller data structure */ 359 hose = pcibios_alloc_controller(np); 360 if (!hose) 361 goto fail; 362 363 hose->first_busno = bus_range ? bus_range[0] : 0x0; 364 hose->last_busno = bus_range ? bus_range[1] : 0xff; 365 366 /* Setup config space */ 367 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0); 368 369 /* Disable all windows */ 370 writel(0, reg + PCIL0_PMM0MA); 371 writel(0, reg + PCIL0_PMM1MA); 372 writel(0, reg + PCIL0_PMM2MA); 373 writel(0, reg + PCIL0_PTM1MS); 374 writel(0, reg + PCIL0_PTM2MS); 375 376 /* Parse outbound mapping resources */ 377 pci_process_bridge_OF_ranges(hose, np, primary); 378 379 /* Parse inbound mapping resources */ 380 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0) 381 goto fail; 382 383 /* Configure outbound ranges POMs */ 384 ppc4xx_configure_pci_PMMs(hose, reg); 385 386 /* Configure inbound ranges PIMs */ 387 ppc4xx_configure_pci_PTMs(hose, reg, &dma_window); 388 389 /* We don't need the registers anymore */ 390 iounmap(reg); 391 return; 392 393 fail: 394 if (hose) 395 pcibios_free_controller(hose); 396 if (reg) 397 iounmap(reg); 398} 399 400/* 401 * 4xx PCI-X part 402 */ 403 404static int __init ppc4xx_setup_one_pcix_POM(struct pci_controller *hose, 405 void __iomem *reg, 406 u64 plb_addr, 407 u64 pci_addr, 408 u64 size, 409 unsigned int flags, 410 int index) 411{ 412 u32 lah, lal, pciah, pcial, sa; 413 414 if (!is_power_of_2(size) || size < 0x1000 || 415 (plb_addr & (size - 1)) != 0) { 416 printk(KERN_WARNING "%s: Resource out of range\n", 417 hose->dn->full_name); 418 return -1; 419 } 420 421 /* Calculate register values */ 422 lah = RES_TO_U32_HIGH(plb_addr); 423 lal = RES_TO_U32_LOW(plb_addr); 424 pciah = RES_TO_U32_HIGH(pci_addr); 425 pcial = RES_TO_U32_LOW(pci_addr); 426 sa = (0xffffffffu << ilog2(size)) | 0x1; 427 428 /* Program register values */ 429 if (index == 0) { 430 writel(lah, reg + PCIX0_POM0LAH); 431 writel(lal, reg + PCIX0_POM0LAL); 432 writel(pciah, reg + PCIX0_POM0PCIAH); 433 writel(pcial, reg + PCIX0_POM0PCIAL); 434 writel(sa, reg + PCIX0_POM0SA); 435 } else { 436 writel(lah, reg + PCIX0_POM1LAH); 437 writel(lal, reg + PCIX0_POM1LAL); 438 writel(pciah, reg + PCIX0_POM1PCIAH); 439 writel(pcial, reg + PCIX0_POM1PCIAL); 440 writel(sa, reg + PCIX0_POM1SA); 441 } 442 443 return 0; 444} 445 446static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose, 447 void __iomem *reg) 448{ 449 int i, j, found_isa_hole = 0; 450 451 /* Setup outbound memory windows */ 452 for (i = j = 0; i < 3; i++) { 453 struct resource *res = &hose->mem_resources[i]; 454 455 /* we only care about memory windows */ 456 if (!(res->flags & IORESOURCE_MEM)) 457 continue; 458 if (j > 1) { 459 printk(KERN_WARNING "%s: Too many ranges\n", 460 hose->dn->full_name); 461 break; 462 } 463 464 /* Configure the resource */ 465 if (ppc4xx_setup_one_pcix_POM(hose, reg, 466 res->start, 467 res->start - hose->pci_mem_offset, 468 res->end + 1 - res->start, 469 res->flags, 470 j) == 0) { 471 j++; 472 473 /* If the resource PCI address is 0 then we have our 474 * ISA memory hole 475 */ 476 if (res->start == hose->pci_mem_offset) 477 found_isa_hole = 1; 478 } 479 } 480 481 /* Handle ISA memory hole if not already covered */ 482 if (j <= 1 && !found_isa_hole && hose->isa_mem_size) 483 if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0, 484 hose->isa_mem_size, 0, j) == 0) 485 printk(KERN_INFO "%s: Legacy ISA memory support enabled\n", 486 hose->dn->full_name); 487} 488 489static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose, 490 void __iomem *reg, 491 const struct resource *res, 492 int big_pim, 493 int enable_msi_hole) 494{ 495 resource_size_t size = res->end - res->start + 1; 496 u32 sa; 497 498 /* RAM is always at 0 */ 499 writel(0x00000000, reg + PCIX0_PIM0LAH); 500 writel(0x00000000, reg + PCIX0_PIM0LAL); 501 502 /* Calculate window size */ 503 sa = (0xffffffffu << ilog2(size)) | 1; 504 sa |= 0x1; 505 if (res->flags & IORESOURCE_PREFETCH) 506 sa |= 0x2; 507 if (enable_msi_hole) 508 sa |= 0x4; 509 writel(sa, reg + PCIX0_PIM0SA); 510 if (big_pim) 511 writel(0xffffffff, reg + PCIX0_PIM0SAH); 512 513 /* Map on PCI side */ 514 writel(0x00000000, reg + PCIX0_BAR0H); 515 writel(res->start, reg + PCIX0_BAR0L); 516 writew(0x0006, reg + PCIX0_COMMAND); 517} 518 519static void __init ppc4xx_probe_pcix_bridge(struct device_node *np) 520{ 521 struct resource rsrc_cfg; 522 struct resource rsrc_reg; 523 struct resource dma_window; 524 struct pci_controller *hose = NULL; 525 void __iomem *reg = NULL; 526 const int *bus_range; 527 int big_pim = 0, msi = 0, primary = 0; 528 529 /* Fetch config space registers address */ 530 if (of_address_to_resource(np, 0, &rsrc_cfg)) { 531 printk(KERN_ERR "%s:Can't get PCI-X config register base !", 532 np->full_name); 533 return; 534 } 535 /* Fetch host bridge internal registers address */ 536 if (of_address_to_resource(np, 3, &rsrc_reg)) { 537 printk(KERN_ERR "%s: Can't get PCI-X internal register base !", 538 np->full_name); 539 return; 540 } 541 542 /* Check if it supports large PIMs (440GX) */ 543 if (of_get_property(np, "large-inbound-windows", NULL)) 544 big_pim = 1; 545 546 /* Check if we should enable MSIs inbound hole */ 547 if (of_get_property(np, "enable-msi-hole", NULL)) 548 msi = 1; 549 550 /* Check if primary bridge */ 551 if (of_get_property(np, "primary", NULL)) 552 primary = 1; 553 554 /* Get bus range if any */ 555 bus_range = of_get_property(np, "bus-range", NULL); 556 557 /* Map registers */ 558 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start); 559 if (reg == NULL) { 560 printk(KERN_ERR "%s: Can't map registers !", np->full_name); 561 goto fail; 562 } 563 564 /* Allocate the host controller data structure */ 565 hose = pcibios_alloc_controller(np); 566 if (!hose) 567 goto fail; 568 569 hose->first_busno = bus_range ? bus_range[0] : 0x0; 570 hose->last_busno = bus_range ? bus_range[1] : 0xff; 571 572 /* Setup config space */ 573 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 574 PPC_INDIRECT_TYPE_SET_CFG_TYPE); 575 576 /* Disable all windows */ 577 writel(0, reg + PCIX0_POM0SA); 578 writel(0, reg + PCIX0_POM1SA); 579 writel(0, reg + PCIX0_POM2SA); 580 writel(0, reg + PCIX0_PIM0SA); 581 writel(0, reg + PCIX0_PIM1SA); 582 writel(0, reg + PCIX0_PIM2SA); 583 if (big_pim) { 584 writel(0, reg + PCIX0_PIM0SAH); 585 writel(0, reg + PCIX0_PIM2SAH); 586 } 587 588 /* Parse outbound mapping resources */ 589 pci_process_bridge_OF_ranges(hose, np, primary); 590 591 /* Parse inbound mapping resources */ 592 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0) 593 goto fail; 594 595 /* Configure outbound ranges POMs */ 596 ppc4xx_configure_pcix_POMs(hose, reg); 597 598 /* Configure inbound ranges PIMs */ 599 ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi); 600 601 /* We don't need the registers anymore */ 602 iounmap(reg); 603 return; 604 605 fail: 606 if (hose) 607 pcibios_free_controller(hose); 608 if (reg) 609 iounmap(reg); 610} 611 612#ifdef CONFIG_PPC4xx_PCI_EXPRESS 613 614/* 615 * 4xx PCI-Express part 616 * 617 * We support 3 parts currently based on the compatible property: 618 * 619 * ibm,plb-pciex-440spe 620 * ibm,plb-pciex-405ex 621 * ibm,plb-pciex-460ex 622 * 623 * Anything else will be rejected for now as they are all subtly 624 * different unfortunately. 625 * 626 */ 627 628#define MAX_PCIE_BUS_MAPPED 0x40 629 630struct ppc4xx_pciex_port 631{ 632 struct pci_controller *hose; 633 struct device_node *node; 634 unsigned int index; 635 int endpoint; 636 int link; 637 int has_ibpre; 638 unsigned int sdr_base; 639 dcr_host_t dcrs; 640 struct resource cfg_space; 641 struct resource utl_regs; 642 void __iomem *utl_base; 643}; 644 645static struct ppc4xx_pciex_port *ppc4xx_pciex_ports; 646static unsigned int ppc4xx_pciex_port_count; 647 648struct ppc4xx_pciex_hwops 649{ 650 int (*core_init)(struct device_node *np); 651 int (*port_init_hw)(struct ppc4xx_pciex_port *port); 652 int (*setup_utl)(struct ppc4xx_pciex_port *port); 653}; 654 655static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops; 656 657#ifdef CONFIG_44x 658 659/* Check various reset bits of the 440SPe PCIe core */ 660static int __init ppc440spe_pciex_check_reset(struct device_node *np) 661{ 662 u32 valPE0, valPE1, valPE2; 663 int err = 0; 664 665 /* SDR0_PEGPLLLCT1 reset */ 666 if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) { 667 /* 668 * the PCIe core was probably already initialised 669 * by firmware - let's re-reset RCSSET regs 670 * 671 * -- Shouldn't we also re-reset the whole thing ? -- BenH 672 */ 673 pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n"); 674 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000); 675 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000); 676 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000); 677 } 678 679 valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET); 680 valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET); 681 valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET); 682 683 /* SDR0_PExRCSSET rstgu */ 684 if (!(valPE0 & 0x01000000) || 685 !(valPE1 & 0x01000000) || 686 !(valPE2 & 0x01000000)) { 687 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n"); 688 err = -1; 689 } 690 691 /* SDR0_PExRCSSET rstdl */ 692 if (!(valPE0 & 0x00010000) || 693 !(valPE1 & 0x00010000) || 694 !(valPE2 & 0x00010000)) { 695 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n"); 696 err = -1; 697 } 698 699 /* SDR0_PExRCSSET rstpyn */ 700 if ((valPE0 & 0x00001000) || 701 (valPE1 & 0x00001000) || 702 (valPE2 & 0x00001000)) { 703 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n"); 704 err = -1; 705 } 706 707 /* SDR0_PExRCSSET hldplb */ 708 if ((valPE0 & 0x10000000) || 709 (valPE1 & 0x10000000) || 710 (valPE2 & 0x10000000)) { 711 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n"); 712 err = -1; 713 } 714 715 /* SDR0_PExRCSSET rdy */ 716 if ((valPE0 & 0x00100000) || 717 (valPE1 & 0x00100000) || 718 (valPE2 & 0x00100000)) { 719 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n"); 720 err = -1; 721 } 722 723 /* SDR0_PExRCSSET shutdown */ 724 if ((valPE0 & 0x00000100) || 725 (valPE1 & 0x00000100) || 726 (valPE2 & 0x00000100)) { 727 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n"); 728 err = -1; 729 } 730 731 return err; 732} 733 734/* Global PCIe core initializations for 440SPe core */ 735static int __init ppc440spe_pciex_core_init(struct device_node *np) 736{ 737 int time_out = 20; 738 739 /* Set PLL clock receiver to LVPECL */ 740 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28); 741 742 /* Shouldn't we do all the calibration stuff etc... here ? */ 743 if (ppc440spe_pciex_check_reset(np)) 744 return -ENXIO; 745 746 if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) { 747 printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration " 748 "failed (0x%08x)\n", 749 mfdcri(SDR0, PESDR0_PLLLCT2)); 750 return -1; 751 } 752 753 /* De-assert reset of PCIe PLL, wait for lock */ 754 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0); 755 udelay(3); 756 757 while (time_out) { 758 if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) { 759 time_out--; 760 udelay(1); 761 } else 762 break; 763 } 764 if (!time_out) { 765 printk(KERN_INFO "PCIE: VCO output not locked\n"); 766 return -1; 767 } 768 769 pr_debug("PCIE initialization OK\n"); 770 771 return 3; 772} 773 774static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port) 775{ 776 u32 val = 1 << 24; 777 778 if (port->endpoint) 779 val = PTYPE_LEGACY_ENDPOINT << 20; 780 else 781 val = PTYPE_ROOT_PORT << 20; 782 783 if (port->index == 0) 784 val |= LNKW_X8 << 12; 785 else 786 val |= LNKW_X4 << 12; 787 788 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); 789 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222); 790 if (ppc440spe_revA()) 791 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000); 792 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000); 793 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000); 794 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000); 795 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000); 796 if (port->index == 0) { 797 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1, 798 0x35000000); 799 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1, 800 0x35000000); 801 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1, 802 0x35000000); 803 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1, 804 0x35000000); 805 } 806 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 807 (1 << 24) | (1 << 16), 1 << 12); 808 809 return 0; 810} 811 812static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port) 813{ 814 return ppc440spe_pciex_init_port_hw(port); 815} 816 817static int ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port) 818{ 819 int rc = ppc440spe_pciex_init_port_hw(port); 820 821 port->has_ibpre = 1; 822 823 return rc; 824} 825 826static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port) 827{ 828 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800); 829 830 /* 831 * Set buffer allocations and then assert VRB and TXE. 832 */ 833 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); 834 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); 835 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000); 836 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000); 837 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000); 838 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000); 839 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); 840 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); 841 842 return 0; 843} 844 845static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port) 846{ 847 /* Report CRS to the operating system */ 848 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); 849 850 return 0; 851} 852 853static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata = 854{ 855 .core_init = ppc440spe_pciex_core_init, 856 .port_init_hw = ppc440speA_pciex_init_port_hw, 857 .setup_utl = ppc440speA_pciex_init_utl, 858}; 859 860static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata = 861{ 862 .core_init = ppc440spe_pciex_core_init, 863 .port_init_hw = ppc440speB_pciex_init_port_hw, 864 .setup_utl = ppc440speB_pciex_init_utl, 865}; 866 867static int __init ppc460ex_pciex_core_init(struct device_node *np) 868{ 869 /* Nothing to do, return 2 ports */ 870 return 2; 871} 872 873static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port) 874{ 875 u32 val; 876 u32 utlset1; 877 878 if (port->endpoint) 879 val = PTYPE_LEGACY_ENDPOINT << 20; 880 else 881 val = PTYPE_ROOT_PORT << 20; 882 883 if (port->index == 0) { 884 val |= LNKW_X1 << 12; 885 utlset1 = 0x20000000; 886 } else { 887 val |= LNKW_X4 << 12; 888 utlset1 = 0x20101101; 889 } 890 891 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); 892 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1); 893 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000); 894 895 switch (port->index) { 896 case 0: 897 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230); 898 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130); 899 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); 900 901 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000); 902 break; 903 904 case 1: 905 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230); 906 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230); 907 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230); 908 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230); 909 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130); 910 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130); 911 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130); 912 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130); 913 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006); 914 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006); 915 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006); 916 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006); 917 918 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000); 919 break; 920 } 921 922 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 923 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | 924 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN)); 925 926 /* Poll for PHY reset */ 927 switch (port->index) { 928 case 0: 929 while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1)) 930 udelay(10); 931 break; 932 case 1: 933 while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1)) 934 udelay(10); 935 break; 936 } 937 938 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 939 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) & 940 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) | 941 PESDRx_RCSSET_RSTPYN); 942 943 port->has_ibpre = 1; 944 945 return 0; 946} 947 948static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port) 949{ 950 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); 951 952 /* 953 * Set buffer allocations and then assert VRB and TXE. 954 */ 955 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c); 956 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); 957 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); 958 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); 959 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000); 960 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); 961 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); 962 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000); 963 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); 964 965 return 0; 966} 967 968static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata = 969{ 970 .core_init = ppc460ex_pciex_core_init, 971 .port_init_hw = ppc460ex_pciex_init_port_hw, 972 .setup_utl = ppc460ex_pciex_init_utl, 973}; 974 975static int __init ppc460sx_pciex_core_init(struct device_node *np) 976{ 977 /* HSS drive amplitude */ 978 mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211); 979 mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211); 980 mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211); 981 mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211); 982 mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211); 983 mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211); 984 mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211); 985 mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211); 986 987 mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211); 988 mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211); 989 mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211); 990 mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211); 991 992 mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211); 993 mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211); 994 mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211); 995 mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211); 996 997 /* HSS TX pre-emphasis */ 998 mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987); 999 mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987); 1000 mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987); 1001 mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987); 1002 mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987); 1003 mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987); 1004 mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987); 1005 mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987); 1006 1007 mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987); 1008 mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987); 1009 mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987); 1010 mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987); 1011 1012 mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987); 1013 mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987); 1014 mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987); 1015 mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987); 1016 1017 /* HSS TX calibration control */ 1018 mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222); 1019 mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000); 1020 mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000); 1021 1022 /* HSS TX slew control */ 1023 mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF); 1024 mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000); 1025 mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000); 1026 1027 udelay(100); 1028 1029 /* De-assert PLLRESET */ 1030 dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0); 1031 1032 /* Reset DL, UTL, GPL before configuration */ 1033 mtdcri(SDR0, PESDR0_460SX_RCSSET, 1034 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU); 1035 mtdcri(SDR0, PESDR1_460SX_RCSSET, 1036 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU); 1037 mtdcri(SDR0, PESDR2_460SX_RCSSET, 1038 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU); 1039 1040 udelay(100); 1041 1042 /* 1043 * If bifurcation is not enabled, u-boot would have disabled the 1044 * third PCIe port 1045 */ 1046 if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) == 1047 0x00000001)) { 1048 printk(KERN_INFO "PCI: PCIE bifurcation setup successfully.\n"); 1049 printk(KERN_INFO "PCI: Total 3 PCIE ports are present\n"); 1050 return 3; 1051 } 1052 1053 printk(KERN_INFO "PCI: Total 2 PCIE ports are present\n"); 1054 return 2; 1055} 1056 1057static int ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port) 1058{ 1059 1060 if (port->endpoint) 1061 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, 1062 0x01000000, 0); 1063 else 1064 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, 1065 0, 0x01000000); 1066 1067 /*Gen-1*/ 1068 mtdcri(SDR0, port->sdr_base + PESDRn_460SX_RCEI, 0x08000000); 1069 1070 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 1071 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL), 1072 PESDRx_RCSSET_RSTPYN); 1073 1074 port->has_ibpre = 1; 1075 1076 return 0; 1077} 1078 1079static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port) 1080{ 1081 /* Max 128 Bytes */ 1082 out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000); 1083 return 0; 1084} 1085 1086static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = { 1087 .core_init = ppc460sx_pciex_core_init, 1088 .port_init_hw = ppc460sx_pciex_init_port_hw, 1089 .setup_utl = ppc460sx_pciex_init_utl, 1090}; 1091 1092#endif /* CONFIG_44x */ 1093 1094#ifdef CONFIG_40x 1095 1096static int __init ppc405ex_pciex_core_init(struct device_node *np) 1097{ 1098 /* Nothing to do, return 2 ports */ 1099 return 2; 1100} 1101 1102static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port) 1103{ 1104 /* Assert the PE0_PHY reset */ 1105 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000); 1106 msleep(1); 1107 1108 /* deassert the PE0_hotreset */ 1109 if (port->endpoint) 1110 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000); 1111 else 1112 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000); 1113 1114 /* poll for phy !reset */ 1115 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000)) 1116 ; 1117 1118 /* deassert the PE0_gpl_utl_reset */ 1119 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000); 1120} 1121 1122static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port) 1123{ 1124 u32 val; 1125 1126 if (port->endpoint) 1127 val = PTYPE_LEGACY_ENDPOINT; 1128 else 1129 val = PTYPE_ROOT_PORT; 1130 1131 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, 1132 1 << 24 | val << 20 | LNKW_X1 << 12); 1133 1134 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); 1135 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); 1136 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000); 1137 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003); 1138 1139 /* 1140 * Only reset the PHY when no link is currently established. 1141 * This is for the Atheros PCIe board which has problems to establish 1142 * the link (again) after this PHY reset. All other currently tested 1143 * PCIe boards don't show this problem. 1144 * This has to be re-tested and fixed in a later release! 1145 */ 1146 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); 1147 if (!(val & 0x00001000)) 1148 ppc405ex_pcie_phy_reset(port); 1149 1150 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */ 1151 1152 port->has_ibpre = 1; 1153 1154 return 0; 1155} 1156 1157static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port) 1158{ 1159 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); 1160 1161 /* 1162 * Set buffer allocations and then assert VRB and TXE. 1163 */ 1164 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000); 1165 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); 1166 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); 1167 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000); 1168 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); 1169 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); 1170 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); 1171 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); 1172 1173 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); 1174 1175 return 0; 1176} 1177 1178static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata = 1179{ 1180 .core_init = ppc405ex_pciex_core_init, 1181 .port_init_hw = ppc405ex_pciex_init_port_hw, 1182 .setup_utl = ppc405ex_pciex_init_utl, 1183}; 1184 1185#endif /* CONFIG_40x */ 1186 1187 1188/* Check that the core has been initied and if not, do it */ 1189static int __init ppc4xx_pciex_check_core_init(struct device_node *np) 1190{ 1191 static int core_init; 1192 int count = -ENODEV; 1193 1194 if (core_init++) 1195 return 0; 1196 1197#ifdef CONFIG_44x 1198 if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) { 1199 if (ppc440spe_revA()) 1200 ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops; 1201 else 1202 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops; 1203 } 1204 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex")) 1205 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops; 1206 if (of_device_is_compatible(np, "ibm,plb-pciex-460sx")) 1207 ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops; 1208#endif /* CONFIG_44x */ 1209#ifdef CONFIG_40x 1210 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex")) 1211 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops; 1212#endif 1213 if (ppc4xx_pciex_hwops == NULL) { 1214 printk(KERN_WARNING "PCIE: unknown host type %s\n", 1215 np->full_name); 1216 return -ENODEV; 1217 } 1218 1219 count = ppc4xx_pciex_hwops->core_init(np); 1220 if (count > 0) { 1221 ppc4xx_pciex_ports = 1222 kzalloc(count * sizeof(struct ppc4xx_pciex_port), 1223 GFP_KERNEL); 1224 if (ppc4xx_pciex_ports) { 1225 ppc4xx_pciex_port_count = count; 1226 return 0; 1227 } 1228 printk(KERN_WARNING "PCIE: failed to allocate ports array\n"); 1229 return -ENOMEM; 1230 } 1231 return -ENODEV; 1232} 1233 1234static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port) 1235{ 1236 /* We map PCI Express configuration based on the reg property */ 1237 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH, 1238 RES_TO_U32_HIGH(port->cfg_space.start)); 1239 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL, 1240 RES_TO_U32_LOW(port->cfg_space.start)); 1241 1242 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001); 1243 1244 /* We map UTL registers based on the reg property */ 1245 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH, 1246 RES_TO_U32_HIGH(port->utl_regs.start)); 1247 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL, 1248 RES_TO_U32_LOW(port->utl_regs.start)); 1249 1250 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001); 1251 1252 /* Disable all other outbound windows */ 1253 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0); 1254 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0); 1255 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0); 1256 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0); 1257} 1258 1259static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port, 1260 unsigned int sdr_offset, 1261 unsigned int mask, 1262 unsigned int value, 1263 int timeout_ms) 1264{ 1265 u32 val; 1266 1267 while(timeout_ms--) { 1268 val = mfdcri(SDR0, port->sdr_base + sdr_offset); 1269 if ((val & mask) == value) { 1270 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n", 1271 port->index, sdr_offset, timeout_ms, val); 1272 return 0; 1273 } 1274 msleep(1); 1275 } 1276 return -1; 1277} 1278 1279static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port) 1280{ 1281 int rc = 0; 1282 1283 /* Init HW */ 1284 if (ppc4xx_pciex_hwops->port_init_hw) 1285 rc = ppc4xx_pciex_hwops->port_init_hw(port); 1286 if (rc != 0) 1287 return rc; 1288 1289 printk(KERN_INFO "PCIE%d: Checking link...\n", 1290 port->index); 1291 1292 /* Wait for reset to complete */ 1293 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) { 1294 printk(KERN_WARNING "PCIE%d: PGRST failed\n", 1295 port->index); 1296 return -1; 1297 } 1298 1299 /* Check for card presence detect if supported, if not, just wait for 1300 * link unconditionally. 1301 * 1302 * note that we don't fail if there is no link, we just filter out 1303 * config space accesses. That way, it will be easier to implement 1304 * hotplug later on. 1305 */ 1306 if (!port->has_ibpre || 1307 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP, 1308 1 << 28, 1 << 28, 100)) { 1309 printk(KERN_INFO 1310 "PCIE%d: Device detected, waiting for link...\n", 1311 port->index); 1312 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP, 1313 0x1000, 0x1000, 2000)) 1314 printk(KERN_WARNING 1315 "PCIE%d: Link up failed\n", port->index); 1316 else { 1317 printk(KERN_INFO 1318 "PCIE%d: link is up !\n", port->index); 1319 port->link = 1; 1320 } 1321 } else 1322 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index); 1323 1324 /* 1325 * Initialize mapping: disable all regions and configure 1326 * CFG and REG regions based on resources in the device tree 1327 */ 1328 ppc4xx_pciex_port_init_mapping(port); 1329 1330 /* 1331 * Map UTL 1332 */ 1333 port->utl_base = ioremap(port->utl_regs.start, 0x100); 1334 BUG_ON(port->utl_base == NULL); 1335 1336 /* 1337 * Setup UTL registers --BenH. 1338 */ 1339 if (ppc4xx_pciex_hwops->setup_utl) 1340 ppc4xx_pciex_hwops->setup_utl(port); 1341 1342 /* 1343 * Check for VC0 active and assert RDY. 1344 */ 1345 if (port->link && 1346 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1347 1 << 16, 1 << 16, 5000)) { 1348 printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index); 1349 port->link = 0; 1350 } 1351 1352 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20); 1353 msleep(100); 1354 1355 return 0; 1356} 1357 1358static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port, 1359 struct pci_bus *bus, 1360 unsigned int devfn) 1361{ 1362 static int message; 1363 1364 /* Endpoint can not generate upstream(remote) config cycles */ 1365 if (port->endpoint && bus->number != port->hose->first_busno) 1366 return PCIBIOS_DEVICE_NOT_FOUND; 1367 1368 /* Check we are within the mapped range */ 1369 if (bus->number > port->hose->last_busno) { 1370 if (!message) { 1371 printk(KERN_WARNING "Warning! Probing bus %u" 1372 " out of range !\n", bus->number); 1373 message++; 1374 } 1375 return PCIBIOS_DEVICE_NOT_FOUND; 1376 } 1377 1378 /* The root complex has only one device / function */ 1379 if (bus->number == port->hose->first_busno && devfn != 0) 1380 return PCIBIOS_DEVICE_NOT_FOUND; 1381 1382 /* The other side of the RC has only one device as well */ 1383 if (bus->number == (port->hose->first_busno + 1) && 1384 PCI_SLOT(devfn) != 0) 1385 return PCIBIOS_DEVICE_NOT_FOUND; 1386 1387 /* Check if we have a link */ 1388 if ((bus->number != port->hose->first_busno) && !port->link) 1389 return PCIBIOS_DEVICE_NOT_FOUND; 1390 1391 return 0; 1392} 1393 1394static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port, 1395 struct pci_bus *bus, 1396 unsigned int devfn) 1397{ 1398 int relbus; 1399 1400 /* Remove the casts when we finally remove the stupid volatile 1401 * in struct pci_controller 1402 */ 1403 if (bus->number == port->hose->first_busno) 1404 return (void __iomem *)port->hose->cfg_addr; 1405 1406 relbus = bus->number - (port->hose->first_busno + 1); 1407 return (void __iomem *)port->hose->cfg_data + 1408 ((relbus << 20) | (devfn << 12)); 1409} 1410 1411static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn, 1412 int offset, int len, u32 *val) 1413{ 1414 struct pci_controller *hose = pci_bus_to_host(bus); 1415 struct ppc4xx_pciex_port *port = 1416 &ppc4xx_pciex_ports[hose->indirect_type]; 1417 void __iomem *addr; 1418 u32 gpl_cfg; 1419 1420 BUG_ON(hose != port->hose); 1421 1422 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0) 1423 return PCIBIOS_DEVICE_NOT_FOUND; 1424 1425 addr = ppc4xx_pciex_get_config_base(port, bus, devfn); 1426 1427 /* 1428 * Reading from configuration space of non-existing device can 1429 * generate transaction errors. For the read duration we suppress 1430 * assertion of machine check exceptions to avoid those. 1431 */ 1432 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); 1433 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); 1434 1435 /* Make sure no CRS is recorded */ 1436 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000); 1437 1438 switch (len) { 1439 case 1: 1440 *val = in_8((u8 *)(addr + offset)); 1441 break; 1442 case 2: 1443 *val = in_le16((u16 *)(addr + offset)); 1444 break; 1445 default: 1446 *val = in_le32((u32 *)(addr + offset)); 1447 break; 1448 } 1449 1450 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x" 1451 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n", 1452 bus->number, hose->first_busno, hose->last_busno, 1453 devfn, offset, len, addr + offset, *val); 1454 1455 /* Check for CRS (440SPe rev B does that for us but heh ..) */ 1456 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) { 1457 pr_debug("Got CRS !\n"); 1458 if (len != 4 || offset != 0) 1459 return PCIBIOS_DEVICE_NOT_FOUND; 1460 *val = 0xffff0001; 1461 } 1462 1463 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); 1464 1465 return PCIBIOS_SUCCESSFUL; 1466} 1467 1468static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn, 1469 int offset, int len, u32 val) 1470{ 1471 struct pci_controller *hose = pci_bus_to_host(bus); 1472 struct ppc4xx_pciex_port *port = 1473 &ppc4xx_pciex_ports[hose->indirect_type]; 1474 void __iomem *addr; 1475 u32 gpl_cfg; 1476 1477 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0) 1478 return PCIBIOS_DEVICE_NOT_FOUND; 1479 1480 addr = ppc4xx_pciex_get_config_base(port, bus, devfn); 1481 1482 /* 1483 * Reading from configuration space of non-existing device can 1484 * generate transaction errors. For the read duration we suppress 1485 * assertion of machine check exceptions to avoid those. 1486 */ 1487 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); 1488 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); 1489 1490 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x" 1491 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n", 1492 bus->number, hose->first_busno, hose->last_busno, 1493 devfn, offset, len, addr + offset, val); 1494 1495 switch (len) { 1496 case 1: 1497 out_8((u8 *)(addr + offset), val); 1498 break; 1499 case 2: 1500 out_le16((u16 *)(addr + offset), val); 1501 break; 1502 default: 1503 out_le32((u32 *)(addr + offset), val); 1504 break; 1505 } 1506 1507 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); 1508 1509 return PCIBIOS_SUCCESSFUL; 1510} 1511 1512static struct pci_ops ppc4xx_pciex_pci_ops = 1513{ 1514 .read = ppc4xx_pciex_read_config, 1515 .write = ppc4xx_pciex_write_config, 1516}; 1517 1518static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port *port, 1519 struct pci_controller *hose, 1520 void __iomem *mbase, 1521 u64 plb_addr, 1522 u64 pci_addr, 1523 u64 size, 1524 unsigned int flags, 1525 int index) 1526{ 1527 u32 lah, lal, pciah, pcial, sa; 1528 1529 if (!is_power_of_2(size) || 1530 (index < 2 && size < 0x100000) || 1531 (index == 2 && size < 0x100) || 1532 (plb_addr & (size - 1)) != 0) { 1533 printk(KERN_WARNING "%s: Resource out of range\n", 1534 hose->dn->full_name); 1535 return -1; 1536 } 1537 1538 /* Calculate register values */ 1539 lah = RES_TO_U32_HIGH(plb_addr); 1540 lal = RES_TO_U32_LOW(plb_addr); 1541 pciah = RES_TO_U32_HIGH(pci_addr); 1542 pcial = RES_TO_U32_LOW(pci_addr); 1543 sa = (0xffffffffu << ilog2(size)) | 0x1; 1544 1545 /* Program register values */ 1546 switch (index) { 1547 case 0: 1548 out_le32(mbase + PECFG_POM0LAH, pciah); 1549 out_le32(mbase + PECFG_POM0LAL, pcial); 1550 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah); 1551 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal); 1552 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff); 1553 /* Note that 3 here means enabled | single region */ 1554 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, sa | 3); 1555 break; 1556 case 1: 1557 out_le32(mbase + PECFG_POM1LAH, pciah); 1558 out_le32(mbase + PECFG_POM1LAL, pcial); 1559 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah); 1560 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal); 1561 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff); 1562 /* Note that 3 here means enabled | single region */ 1563 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, sa | 3); 1564 break; 1565 case 2: 1566 out_le32(mbase + PECFG_POM2LAH, pciah); 1567 out_le32(mbase + PECFG_POM2LAL, pcial); 1568 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah); 1569 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal); 1570 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff); 1571 /* Note that 3 here means enabled | IO space !!! */ 1572 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, sa | 3); 1573 break; 1574 } 1575 1576 return 0; 1577} 1578 1579static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port, 1580 struct pci_controller *hose, 1581 void __iomem *mbase) 1582{ 1583 int i, j, found_isa_hole = 0; 1584 1585 /* Setup outbound memory windows */ 1586 for (i = j = 0; i < 3; i++) { 1587 struct resource *res = &hose->mem_resources[i]; 1588 1589 /* we only care about memory windows */ 1590 if (!(res->flags & IORESOURCE_MEM)) 1591 continue; 1592 if (j > 1) { 1593 printk(KERN_WARNING "%s: Too many ranges\n", 1594 port->node->full_name); 1595 break; 1596 } 1597 1598 /* Configure the resource */ 1599 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase, 1600 res->start, 1601 res->start - hose->pci_mem_offset, 1602 res->end + 1 - res->start, 1603 res->flags, 1604 j) == 0) { 1605 j++; 1606 1607 /* If the resource PCI address is 0 then we have our 1608 * ISA memory hole 1609 */ 1610 if (res->start == hose->pci_mem_offset) 1611 found_isa_hole = 1; 1612 } 1613 } 1614 1615 /* Handle ISA memory hole if not already covered */ 1616 if (j <= 1 && !found_isa_hole && hose->isa_mem_size) 1617 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase, 1618 hose->isa_mem_phys, 0, 1619 hose->isa_mem_size, 0, j) == 0) 1620 printk(KERN_INFO "%s: Legacy ISA memory support enabled\n", 1621 hose->dn->full_name); 1622 1623 /* Configure IO, always 64K starting at 0. We hard wire it to 64K ! 1624 * Note also that it -has- to be region index 2 on this HW 1625 */ 1626 if (hose->io_resource.flags & IORESOURCE_IO) 1627 ppc4xx_setup_one_pciex_POM(port, hose, mbase, 1628 hose->io_base_phys, 0, 1629 0x10000, IORESOURCE_IO, 2); 1630} 1631 1632static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port, 1633 struct pci_controller *hose, 1634 void __iomem *mbase, 1635 struct resource *res) 1636{ 1637 resource_size_t size = res->end - res->start + 1; 1638 u64 sa; 1639 1640 if (port->endpoint) { 1641 resource_size_t ep_addr = 0; 1642 resource_size_t ep_size = 32 << 20; 1643 1644 /* Currently we map a fixed 64MByte window to PLB address 1645 * 0 (SDRAM). This should probably be configurable via a dts 1646 * property. 1647 */ 1648 1649 /* Calculate window size */ 1650 sa = (0xffffffffffffffffull << ilog2(ep_size)); 1651 1652 /* Setup BAR0 */ 1653 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa)); 1654 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) | 1655 PCI_BASE_ADDRESS_MEM_TYPE_64); 1656 1657 /* Disable BAR1 & BAR2 */ 1658 out_le32(mbase + PECFG_BAR1MPA, 0); 1659 out_le32(mbase + PECFG_BAR2HMPA, 0); 1660 out_le32(mbase + PECFG_BAR2LMPA, 0); 1661 1662 out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa)); 1663 out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa)); 1664 1665 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr)); 1666 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr)); 1667 } else { 1668 /* Calculate window size */ 1669 sa = (0xffffffffffffffffull << ilog2(size)); 1670 if (res->flags & IORESOURCE_PREFETCH) 1671 sa |= 0x8; 1672 1673 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa)); 1674 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa)); 1675 1676 /* The setup of the split looks weird to me ... let's see 1677 * if it works 1678 */ 1679 out_le32(mbase + PECFG_PIM0LAL, 0x00000000); 1680 out_le32(mbase + PECFG_PIM0LAH, 0x00000000); 1681 out_le32(mbase + PECFG_PIM1LAL, 0x00000000); 1682 out_le32(mbase + PECFG_PIM1LAH, 0x00000000); 1683 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); 1684 out_le32(mbase + PECFG_PIM01SAL, 0x00000000); 1685 1686 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start)); 1687 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start)); 1688 } 1689 1690 /* Enable inbound mapping */ 1691 out_le32(mbase + PECFG_PIMEN, 0x1); 1692 1693 /* Enable I/O, Mem, and Busmaster cycles */ 1694 out_le16(mbase + PCI_COMMAND, 1695 in_le16(mbase + PCI_COMMAND) | 1696 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 1697} 1698 1699static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port) 1700{ 1701 struct resource dma_window; 1702 struct pci_controller *hose = NULL; 1703 const int *bus_range; 1704 int primary = 0, busses; 1705 void __iomem *mbase = NULL, *cfg_data = NULL; 1706 const u32 *pval; 1707 u32 val; 1708 1709 /* Check if primary bridge */ 1710 if (of_get_property(port->node, "primary", NULL)) 1711 primary = 1; 1712 1713 /* Get bus range if any */ 1714 bus_range = of_get_property(port->node, "bus-range", NULL); 1715 1716 /* Allocate the host controller data structure */ 1717 hose = pcibios_alloc_controller(port->node); 1718 if (!hose) 1719 goto fail; 1720 1721 /* We stick the port number in "indirect_type" so the config space 1722 * ops can retrieve the port data structure easily 1723 */ 1724 hose->indirect_type = port->index; 1725 1726 /* Get bus range */ 1727 hose->first_busno = bus_range ? bus_range[0] : 0x0; 1728 hose->last_busno = bus_range ? bus_range[1] : 0xff; 1729 1730 /* Because of how big mapping the config space is (1M per bus), we 1731 * limit how many busses we support. In the long run, we could replace 1732 * that with something akin to kmap_atomic instead. We set aside 1 bus 1733 * for the host itself too. 1734 */ 1735 busses = hose->last_busno - hose->first_busno; /* This is off by 1 */ 1736 if (busses > MAX_PCIE_BUS_MAPPED) { 1737 busses = MAX_PCIE_BUS_MAPPED; 1738 hose->last_busno = hose->first_busno + busses; 1739 } 1740 1741 if (!port->endpoint) { 1742 /* Only map the external config space in cfg_data for 1743 * PCIe root-complexes. External space is 1M per bus 1744 */ 1745 cfg_data = ioremap(port->cfg_space.start + 1746 (hose->first_busno + 1) * 0x100000, 1747 busses * 0x100000); 1748 if (cfg_data == NULL) { 1749 printk(KERN_ERR "%s: Can't map external config space !", 1750 port->node->full_name); 1751 goto fail; 1752 } 1753 hose->cfg_data = cfg_data; 1754 } 1755 1756 /* Always map the host config space in cfg_addr. 1757 * Internal space is 4K 1758 */ 1759 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); 1760 if (mbase == NULL) { 1761 printk(KERN_ERR "%s: Can't map internal config space !", 1762 port->node->full_name); 1763 goto fail; 1764 } 1765 hose->cfg_addr = mbase; 1766 1767 pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name, 1768 hose->first_busno, hose->last_busno); 1769 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n", 1770 hose->cfg_addr, hose->cfg_data); 1771 1772 /* Setup config space */ 1773 hose->ops = &ppc4xx_pciex_pci_ops; 1774 port->hose = hose; 1775 mbase = (void __iomem *)hose->cfg_addr; 1776 1777 if (!port->endpoint) { 1778 /* 1779 * Set bus numbers on our root port 1780 */ 1781 out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno); 1782 out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1); 1783 out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno); 1784 } 1785 1786 /* 1787 * OMRs are already reset, also disable PIMs 1788 */ 1789 out_le32(mbase + PECFG_PIMEN, 0); 1790 1791 /* Parse outbound mapping resources */ 1792 pci_process_bridge_OF_ranges(hose, port->node, primary); 1793 1794 /* Parse inbound mapping resources */ 1795 if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0) 1796 goto fail; 1797 1798 /* Configure outbound ranges POMs */ 1799 ppc4xx_configure_pciex_POMs(port, hose, mbase); 1800 1801 /* Configure inbound ranges PIMs */ 1802 ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window); 1803 1804 /* The root complex doesn't show up if we don't set some vendor 1805 * and device IDs into it. The defaults below are the same bogus 1806 * one that the initial code in arch/ppc had. This can be 1807 * overwritten by setting the "vendor-id/device-id" properties 1808 * in the pciex node. 1809 */ 1810 1811 /* Get the (optional) vendor-/device-id from the device-tree */ 1812 pval = of_get_property(port->node, "vendor-id", NULL); 1813 if (pval) { 1814 val = *pval; 1815 } else { 1816 if (!port->endpoint) 1817 val = 0xaaa0 + port->index; 1818 else 1819 val = 0xeee0 + port->index; 1820 } 1821 out_le16(mbase + 0x200, val); 1822 1823 pval = of_get_property(port->node, "device-id", NULL); 1824 if (pval) { 1825 val = *pval; 1826 } else { 1827 if (!port->endpoint) 1828 val = 0xbed0 + port->index; 1829 else 1830 val = 0xfed0 + port->index; 1831 } 1832 out_le16(mbase + 0x202, val); 1833 1834 if (!port->endpoint) { 1835 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ 1836 out_le32(mbase + 0x208, 0x06040001); 1837 1838 printk(KERN_INFO "PCIE%d: successfully set as root-complex\n", 1839 port->index); 1840 } else { 1841 /* Set Class Code to Processor/PPC */ 1842 out_le32(mbase + 0x208, 0x0b200001); 1843 1844 printk(KERN_INFO "PCIE%d: successfully set as endpoint\n", 1845 port->index); 1846 } 1847 1848 return; 1849 fail: 1850 if (hose) 1851 pcibios_free_controller(hose); 1852 if (cfg_data) 1853 iounmap(cfg_data); 1854 if (mbase) 1855 iounmap(mbase); 1856} 1857 1858static void __init ppc4xx_probe_pciex_bridge(struct device_node *np) 1859{ 1860 struct ppc4xx_pciex_port *port; 1861 const u32 *pval; 1862 int portno; 1863 unsigned int dcrs; 1864 const char *val; 1865 1866 /* First, proceed to core initialization as we assume there's 1867 * only one PCIe core in the system 1868 */ 1869 if (ppc4xx_pciex_check_core_init(np)) 1870 return; 1871 1872 /* Get the port number from the device-tree */ 1873 pval = of_get_property(np, "port", NULL); 1874 if (pval == NULL) { 1875 printk(KERN_ERR "PCIE: Can't find port number for %s\n", 1876 np->full_name); 1877 return; 1878 } 1879 portno = *pval; 1880 if (portno >= ppc4xx_pciex_port_count) { 1881 printk(KERN_ERR "PCIE: port number out of range for %s\n", 1882 np->full_name); 1883 return; 1884 } 1885 port = &ppc4xx_pciex_ports[portno]; 1886 port->index = portno; 1887 1888 /* 1889 * Check if device is enabled 1890 */ 1891 if (!of_device_is_available(np)) { 1892 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index); 1893 return; 1894 } 1895 1896 port->node = of_node_get(np); 1897 pval = of_get_property(np, "sdr-base", NULL); 1898 if (pval == NULL) { 1899 printk(KERN_ERR "PCIE: missing sdr-base for %s\n", 1900 np->full_name); 1901 return; 1902 } 1903 port->sdr_base = *pval; 1904 1905 /* Check if device_type property is set to "pci" or "pci-endpoint". 1906 * Resulting from this setup this PCIe port will be configured 1907 * as root-complex or as endpoint. 1908 */ 1909 val = of_get_property(port->node, "device_type", NULL); 1910 if (!strcmp(val, "pci-endpoint")) { 1911 port->endpoint = 1; 1912 } else if (!strcmp(val, "pci")) { 1913 port->endpoint = 0; 1914 } else { 1915 printk(KERN_ERR "PCIE: missing or incorrect device_type for %s\n", 1916 np->full_name); 1917 return; 1918 } 1919 1920 /* Fetch config space registers address */ 1921 if (of_address_to_resource(np, 0, &port->cfg_space)) { 1922 printk(KERN_ERR "%s: Can't get PCI-E config space !", 1923 np->full_name); 1924 return; 1925 } 1926 /* Fetch host bridge internal registers address */ 1927 if (of_address_to_resource(np, 1, &port->utl_regs)) { 1928 printk(KERN_ERR "%s: Can't get UTL register base !", 1929 np->full_name); 1930 return; 1931 } 1932 1933 /* Map DCRs */ 1934 dcrs = dcr_resource_start(np, 0); 1935 if (dcrs == 0) { 1936 printk(KERN_ERR "%s: Can't get DCR register base !", 1937 np->full_name); 1938 return; 1939 } 1940 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0)); 1941 1942 /* Initialize the port specific registers */ 1943 if (ppc4xx_pciex_port_init(port)) { 1944 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index); 1945 return; 1946 } 1947 1948 /* Setup the linux hose data structure */ 1949 ppc4xx_pciex_port_setup_hose(port); 1950} 1951 1952#endif /* CONFIG_PPC4xx_PCI_EXPRESS */ 1953 1954static int __init ppc4xx_pci_find_bridges(void) 1955{ 1956 struct device_node *np; 1957 1958 ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0; 1959 1960#ifdef CONFIG_PPC4xx_PCI_EXPRESS 1961 for_each_compatible_node(np, NULL, "ibm,plb-pciex") 1962 ppc4xx_probe_pciex_bridge(np); 1963#endif 1964 for_each_compatible_node(np, NULL, "ibm,plb-pcix") 1965 ppc4xx_probe_pcix_bridge(np); 1966 for_each_compatible_node(np, NULL, "ibm,plb-pci") 1967 ppc4xx_probe_pci_bridge(np); 1968 1969 return 0; 1970} 1971arch_initcall(ppc4xx_pci_find_bridges); 1972