1/* 2 * PS3 Platform spu routines. 3 * 4 * Copyright (C) 2006 Sony Computer Entertainment Inc. 5 * Copyright 2006 Sony Corp. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 */ 20 21#include <linux/kernel.h> 22#include <linux/init.h> 23#include <linux/slab.h> 24#include <linux/mmzone.h> 25#include <linux/io.h> 26#include <linux/mm.h> 27 28#include <asm/spu.h> 29#include <asm/spu_priv1.h> 30#include <asm/lv1call.h> 31#include <asm/ps3.h> 32 33#include "../cell/spufs/spufs.h" 34#include "platform.h" 35 36/* spu_management_ops */ 37 38/** 39 * enum spe_type - Type of spe to create. 40 * @spe_type_logical: Standard logical spe. 41 * 42 * For use with lv1_construct_logical_spe(). The current HV does not support 43 * any types other than those listed. 44 */ 45 46enum spe_type { 47 SPE_TYPE_LOGICAL = 0, 48}; 49 50/** 51 * struct spe_shadow - logical spe shadow register area. 52 * 53 * Read-only shadow of spe registers. 54 */ 55 56struct spe_shadow { 57 u8 padding_0140[0x0140]; 58 u64 int_status_class0_RW; /* 0x0140 */ 59 u64 int_status_class1_RW; /* 0x0148 */ 60 u64 int_status_class2_RW; /* 0x0150 */ 61 u8 padding_0158[0x0610-0x0158]; 62 u64 mfc_dsisr_RW; /* 0x0610 */ 63 u8 padding_0618[0x0620-0x0618]; 64 u64 mfc_dar_RW; /* 0x0620 */ 65 u8 padding_0628[0x0800-0x0628]; 66 u64 mfc_dsipr_R; /* 0x0800 */ 67 u8 padding_0808[0x0810-0x0808]; 68 u64 mfc_lscrr_R; /* 0x0810 */ 69 u8 padding_0818[0x0c00-0x0818]; 70 u64 mfc_cer_R; /* 0x0c00 */ 71 u8 padding_0c08[0x0f00-0x0c08]; 72 u64 spe_execution_status; /* 0x0f00 */ 73 u8 padding_0f08[0x1000-0x0f08]; 74}; 75 76/** 77 * enum spe_ex_state - Logical spe execution state. 78 * @spe_ex_state_unexecutable: Uninitialized. 79 * @spe_ex_state_executable: Enabled, not ready. 80 * @spe_ex_state_executed: Ready for use. 81 * 82 * The execution state (status) of the logical spe as reported in 83 * struct spe_shadow:spe_execution_status. 84 */ 85 86enum spe_ex_state { 87 SPE_EX_STATE_UNEXECUTABLE = 0, 88 SPE_EX_STATE_EXECUTABLE = 2, 89 SPE_EX_STATE_EXECUTED = 3, 90}; 91 92/** 93 * struct priv1_cache - Cached values of priv1 registers. 94 * @masks[]: Array of cached spe interrupt masks, indexed by class. 95 * @sr1: Cached mfc_sr1 register. 96 * @tclass_id: Cached mfc_tclass_id register. 97 */ 98 99struct priv1_cache { 100 u64 masks[3]; 101 u64 sr1; 102 u64 tclass_id; 103}; 104 105/** 106 * struct spu_pdata - Platform state variables. 107 * @spe_id: HV spe id returned by lv1_construct_logical_spe(). 108 * @resource_id: HV spe resource id returned by 109 * ps3_repository_read_spe_resource_id(). 110 * @priv2_addr: lpar address of spe priv2 area returned by 111 * lv1_construct_logical_spe(). 112 * @shadow_addr: lpar address of spe register shadow area returned by 113 * lv1_construct_logical_spe(). 114 * @shadow: Virtual (ioremap) address of spe register shadow area. 115 * @cache: Cached values of priv1 registers. 116 */ 117 118struct spu_pdata { 119 u64 spe_id; 120 u64 resource_id; 121 u64 priv2_addr; 122 u64 shadow_addr; 123 struct spe_shadow __iomem *shadow; 124 struct priv1_cache cache; 125}; 126 127static struct spu_pdata *spu_pdata(struct spu *spu) 128{ 129 return spu->pdata; 130} 131 132#define dump_areas(_a, _b, _c, _d, _e) \ 133 _dump_areas(_a, _b, _c, _d, _e, __func__, __LINE__) 134static void _dump_areas(unsigned int spe_id, unsigned long priv2, 135 unsigned long problem, unsigned long ls, unsigned long shadow, 136 const char* func, int line) 137{ 138 pr_debug("%s:%d: spe_id: %xh (%u)\n", func, line, spe_id, spe_id); 139 pr_debug("%s:%d: priv2: %lxh\n", func, line, priv2); 140 pr_debug("%s:%d: problem: %lxh\n", func, line, problem); 141 pr_debug("%s:%d: ls: %lxh\n", func, line, ls); 142 pr_debug("%s:%d: shadow: %lxh\n", func, line, shadow); 143} 144 145inline u64 ps3_get_spe_id(void *arg) 146{ 147 return spu_pdata(arg)->spe_id; 148} 149EXPORT_SYMBOL_GPL(ps3_get_spe_id); 150 151static unsigned long get_vas_id(void) 152{ 153 u64 id; 154 155 lv1_get_logical_ppe_id(&id); 156 lv1_get_virtual_address_space_id_of_ppe(id, &id); 157 158 return id; 159} 160 161static int __init construct_spu(struct spu *spu) 162{ 163 int result; 164 u64 unused; 165 u64 problem_phys; 166 u64 local_store_phys; 167 168 result = lv1_construct_logical_spe(PAGE_SHIFT, PAGE_SHIFT, PAGE_SHIFT, 169 PAGE_SHIFT, PAGE_SHIFT, get_vas_id(), SPE_TYPE_LOGICAL, 170 &spu_pdata(spu)->priv2_addr, &problem_phys, 171 &local_store_phys, &unused, 172 &spu_pdata(spu)->shadow_addr, 173 &spu_pdata(spu)->spe_id); 174 spu->problem_phys = problem_phys; 175 spu->local_store_phys = local_store_phys; 176 177 if (result) { 178 pr_debug("%s:%d: lv1_construct_logical_spe failed: %s\n", 179 __func__, __LINE__, ps3_result(result)); 180 return result; 181 } 182 183 return result; 184} 185 186static void spu_unmap(struct spu *spu) 187{ 188 iounmap(spu->priv2); 189 iounmap(spu->problem); 190 iounmap((__force u8 __iomem *)spu->local_store); 191 iounmap(spu_pdata(spu)->shadow); 192} 193 194/** 195 * setup_areas - Map the spu regions into the address space. 196 * 197 * The current HV requires the spu shadow regs to be mapped with the 198 * PTE page protection bits set as read-only (PP=3). This implementation 199 * uses the low level __ioremap() to bypass the page protection settings 200 * inforced by ioremap_flags() to get the needed PTE bits set for the 201 * shadow regs. 202 */ 203 204static int __init setup_areas(struct spu *spu) 205{ 206 struct table {char* name; unsigned long addr; unsigned long size;}; 207 static const unsigned long shadow_flags = _PAGE_NO_CACHE | 3; 208 209 spu_pdata(spu)->shadow = __ioremap(spu_pdata(spu)->shadow_addr, 210 sizeof(struct spe_shadow), 211 shadow_flags); 212 if (!spu_pdata(spu)->shadow) { 213 pr_debug("%s:%d: ioremap shadow failed\n", __func__, __LINE__); 214 goto fail_ioremap; 215 } 216 217 spu->local_store = (__force void *)ioremap_flags(spu->local_store_phys, 218 LS_SIZE, _PAGE_NO_CACHE); 219 220 if (!spu->local_store) { 221 pr_debug("%s:%d: ioremap local_store failed\n", 222 __func__, __LINE__); 223 goto fail_ioremap; 224 } 225 226 spu->problem = ioremap(spu->problem_phys, 227 sizeof(struct spu_problem)); 228 229 if (!spu->problem) { 230 pr_debug("%s:%d: ioremap problem failed\n", __func__, __LINE__); 231 goto fail_ioremap; 232 } 233 234 spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr, 235 sizeof(struct spu_priv2)); 236 237 if (!spu->priv2) { 238 pr_debug("%s:%d: ioremap priv2 failed\n", __func__, __LINE__); 239 goto fail_ioremap; 240 } 241 242 dump_areas(spu_pdata(spu)->spe_id, spu_pdata(spu)->priv2_addr, 243 spu->problem_phys, spu->local_store_phys, 244 spu_pdata(spu)->shadow_addr); 245 dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2, 246 (unsigned long)spu->problem, (unsigned long)spu->local_store, 247 (unsigned long)spu_pdata(spu)->shadow); 248 249 return 0; 250 251fail_ioremap: 252 spu_unmap(spu); 253 254 return -ENOMEM; 255} 256 257static int __init setup_interrupts(struct spu *spu) 258{ 259 int result; 260 261 result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id, 262 0, &spu->irqs[0]); 263 264 if (result) 265 goto fail_alloc_0; 266 267 result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id, 268 1, &spu->irqs[1]); 269 270 if (result) 271 goto fail_alloc_1; 272 273 result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id, 274 2, &spu->irqs[2]); 275 276 if (result) 277 goto fail_alloc_2; 278 279 return result; 280 281fail_alloc_2: 282 ps3_spe_irq_destroy(spu->irqs[1]); 283fail_alloc_1: 284 ps3_spe_irq_destroy(spu->irqs[0]); 285fail_alloc_0: 286 spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ; 287 return result; 288} 289 290static int __init enable_spu(struct spu *spu) 291{ 292 int result; 293 294 result = lv1_enable_logical_spe(spu_pdata(spu)->spe_id, 295 spu_pdata(spu)->resource_id); 296 297 if (result) { 298 pr_debug("%s:%d: lv1_enable_logical_spe failed: %s\n", 299 __func__, __LINE__, ps3_result(result)); 300 goto fail_enable; 301 } 302 303 result = setup_areas(spu); 304 305 if (result) 306 goto fail_areas; 307 308 result = setup_interrupts(spu); 309 310 if (result) 311 goto fail_interrupts; 312 313 return 0; 314 315fail_interrupts: 316 spu_unmap(spu); 317fail_areas: 318 lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0); 319fail_enable: 320 return result; 321} 322 323static int ps3_destroy_spu(struct spu *spu) 324{ 325 int result; 326 327 pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number); 328 329 result = lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0); 330 BUG_ON(result); 331 332 ps3_spe_irq_destroy(spu->irqs[2]); 333 ps3_spe_irq_destroy(spu->irqs[1]); 334 ps3_spe_irq_destroy(spu->irqs[0]); 335 336 spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ; 337 338 spu_unmap(spu); 339 340 result = lv1_destruct_logical_spe(spu_pdata(spu)->spe_id); 341 BUG_ON(result); 342 343 kfree(spu->pdata); 344 spu->pdata = NULL; 345 346 return 0; 347} 348 349static int __init ps3_create_spu(struct spu *spu, void *data) 350{ 351 int result; 352 353 pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number); 354 355 spu->pdata = kzalloc(sizeof(struct spu_pdata), 356 GFP_KERNEL); 357 358 if (!spu->pdata) { 359 result = -ENOMEM; 360 goto fail_malloc; 361 } 362 363 spu_pdata(spu)->resource_id = (unsigned long)data; 364 365 /* Init cached reg values to HV defaults. */ 366 367 spu_pdata(spu)->cache.sr1 = 0x33; 368 369 result = construct_spu(spu); 370 371 if (result) 372 goto fail_construct; 373 374 /* For now, just go ahead and enable it. */ 375 376 result = enable_spu(spu); 377 378 if (result) 379 goto fail_enable; 380 381 /* Make sure the spu is in SPE_EX_STATE_EXECUTED. */ 382 383 /* need something better here!!! */ 384 while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status) 385 != SPE_EX_STATE_EXECUTED) 386 (void)0; 387 388 return result; 389 390fail_enable: 391fail_construct: 392 ps3_destroy_spu(spu); 393fail_malloc: 394 return result; 395} 396 397static int __init ps3_enumerate_spus(int (*fn)(void *data)) 398{ 399 int result; 400 unsigned int num_resource_id; 401 unsigned int i; 402 403 result = ps3_repository_read_num_spu_resource_id(&num_resource_id); 404 405 pr_debug("%s:%d: num_resource_id %u\n", __func__, __LINE__, 406 num_resource_id); 407 408 /* 409 * For now, just create logical spus equal to the number 410 * of physical spus reserved for the partition. 411 */ 412 413 for (i = 0; i < num_resource_id; i++) { 414 enum ps3_spu_resource_type resource_type; 415 unsigned int resource_id; 416 417 result = ps3_repository_read_spu_resource_id(i, 418 &resource_type, &resource_id); 419 420 if (result) 421 break; 422 423 if (resource_type == PS3_SPU_RESOURCE_TYPE_EXCLUSIVE) { 424 result = fn((void*)(unsigned long)resource_id); 425 426 if (result) 427 break; 428 } 429 } 430 431 if (result) { 432 printk(KERN_WARNING "%s:%d: Error initializing spus\n", 433 __func__, __LINE__); 434 return result; 435 } 436 437 return num_resource_id; 438} 439 440static int ps3_init_affinity(void) 441{ 442 return 0; 443} 444 445/** 446 * ps3_enable_spu - Enable SPU run control. 447 * 448 * An outstanding enhancement for the PS3 would be to add a guard to check 449 * for incorrect access to the spu problem state when the spu context is 450 * disabled. This check could be implemented with a flag added to the spu 451 * context that would inhibit mapping problem state pages, and a routine 452 * to unmap spu problem state pages. When the spu is enabled with 453 * ps3_enable_spu() the flag would be set allowing pages to be mapped, 454 * and when the spu is disabled with ps3_disable_spu() the flag would be 455 * cleared and the mapped problem state pages would be unmapped. 456 */ 457 458static void ps3_enable_spu(struct spu_context *ctx) 459{ 460} 461 462static void ps3_disable_spu(struct spu_context *ctx) 463{ 464 ctx->ops->runcntl_stop(ctx); 465} 466 467const struct spu_management_ops spu_management_ps3_ops = { 468 .enumerate_spus = ps3_enumerate_spus, 469 .create_spu = ps3_create_spu, 470 .destroy_spu = ps3_destroy_spu, 471 .enable_spu = ps3_enable_spu, 472 .disable_spu = ps3_disable_spu, 473 .init_affinity = ps3_init_affinity, 474}; 475 476/* spu_priv1_ops */ 477 478static void int_mask_and(struct spu *spu, int class, u64 mask) 479{ 480 u64 old_mask; 481 482 /* are these serialized by caller??? */ 483 old_mask = spu_int_mask_get(spu, class); 484 spu_int_mask_set(spu, class, old_mask & mask); 485} 486 487static void int_mask_or(struct spu *spu, int class, u64 mask) 488{ 489 u64 old_mask; 490 491 old_mask = spu_int_mask_get(spu, class); 492 spu_int_mask_set(spu, class, old_mask | mask); 493} 494 495static void int_mask_set(struct spu *spu, int class, u64 mask) 496{ 497 spu_pdata(spu)->cache.masks[class] = mask; 498 lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class, 499 spu_pdata(spu)->cache.masks[class]); 500} 501 502static u64 int_mask_get(struct spu *spu, int class) 503{ 504 return spu_pdata(spu)->cache.masks[class]; 505} 506 507static void int_stat_clear(struct spu *spu, int class, u64 stat) 508{ 509 /* Note that MFC_DSISR will be cleared when class1[MF] is set. */ 510 511 lv1_clear_spe_interrupt_status(spu_pdata(spu)->spe_id, class, 512 stat, 0); 513} 514 515static u64 int_stat_get(struct spu *spu, int class) 516{ 517 u64 stat; 518 519 lv1_get_spe_interrupt_status(spu_pdata(spu)->spe_id, class, &stat); 520 return stat; 521} 522 523static void cpu_affinity_set(struct spu *spu, int cpu) 524{ 525 /* No support. */ 526} 527 528static u64 mfc_dar_get(struct spu *spu) 529{ 530 return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW); 531} 532 533static void mfc_dsisr_set(struct spu *spu, u64 dsisr) 534{ 535 /* Nothing to do, cleared in int_stat_clear(). */ 536} 537 538static u64 mfc_dsisr_get(struct spu *spu) 539{ 540 return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW); 541} 542 543static void mfc_sdr_setup(struct spu *spu) 544{ 545 /* Nothing to do. */ 546} 547 548static void mfc_sr1_set(struct spu *spu, u64 sr1) 549{ 550 /* Check bits allowed by HV. */ 551 552 static const u64 allowed = ~(MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 553 | MFC_STATE1_PROBLEM_STATE_MASK); 554 555 BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed)); 556 557 spu_pdata(spu)->cache.sr1 = sr1; 558 lv1_set_spe_privilege_state_area_1_register( 559 spu_pdata(spu)->spe_id, 560 offsetof(struct spu_priv1, mfc_sr1_RW), 561 spu_pdata(spu)->cache.sr1); 562} 563 564static u64 mfc_sr1_get(struct spu *spu) 565{ 566 return spu_pdata(spu)->cache.sr1; 567} 568 569static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id) 570{ 571 spu_pdata(spu)->cache.tclass_id = tclass_id; 572 lv1_set_spe_privilege_state_area_1_register( 573 spu_pdata(spu)->spe_id, 574 offsetof(struct spu_priv1, mfc_tclass_id_RW), 575 spu_pdata(spu)->cache.tclass_id); 576} 577 578static u64 mfc_tclass_id_get(struct spu *spu) 579{ 580 return spu_pdata(spu)->cache.tclass_id; 581} 582 583static void tlb_invalidate(struct spu *spu) 584{ 585 /* Nothing to do. */ 586} 587 588static void resource_allocation_groupID_set(struct spu *spu, u64 id) 589{ 590 /* No support. */ 591} 592 593static u64 resource_allocation_groupID_get(struct spu *spu) 594{ 595 return 0; /* No support. */ 596} 597 598static void resource_allocation_enable_set(struct spu *spu, u64 enable) 599{ 600 /* No support. */ 601} 602 603static u64 resource_allocation_enable_get(struct spu *spu) 604{ 605 return 0; /* No support. */ 606} 607 608const struct spu_priv1_ops spu_priv1_ps3_ops = { 609 .int_mask_and = int_mask_and, 610 .int_mask_or = int_mask_or, 611 .int_mask_set = int_mask_set, 612 .int_mask_get = int_mask_get, 613 .int_stat_clear = int_stat_clear, 614 .int_stat_get = int_stat_get, 615 .cpu_affinity_set = cpu_affinity_set, 616 .mfc_dar_get = mfc_dar_get, 617 .mfc_dsisr_set = mfc_dsisr_set, 618 .mfc_dsisr_get = mfc_dsisr_get, 619 .mfc_sdr_setup = mfc_sdr_setup, 620 .mfc_sr1_set = mfc_sr1_set, 621 .mfc_sr1_get = mfc_sr1_get, 622 .mfc_tclass_id_set = mfc_tclass_id_set, 623 .mfc_tclass_id_get = mfc_tclass_id_get, 624 .tlb_invalidate = tlb_invalidate, 625 .resource_allocation_groupID_set = resource_allocation_groupID_set, 626 .resource_allocation_groupID_get = resource_allocation_groupID_get, 627 .resource_allocation_enable_set = resource_allocation_enable_set, 628 .resource_allocation_enable_get = resource_allocation_enable_get, 629}; 630 631void ps3_spu_set_platform(void) 632{ 633 spu_priv1_ops = &spu_priv1_ps3_ops; 634 spu_management_ops = &spu_management_ps3_ops; 635} 636