1/* 2 * External Interrupt Controller on Spider South Bridge 3 * 4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005 5 * 6 * Author: Arnd Bergmann <arndb@de.ibm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23#include <linux/interrupt.h> 24#include <linux/irq.h> 25#include <linux/ioport.h> 26 27#include <asm/pgtable.h> 28#include <asm/prom.h> 29#include <asm/io.h> 30 31#include "interrupt.h" 32 33/* register layout taken from Spider spec, table 7.4-4 */ 34enum { 35 TIR_DEN = 0x004, /* Detection Enable Register */ 36 TIR_MSK = 0x084, /* Mask Level Register */ 37 TIR_EDC = 0x0c0, /* Edge Detection Clear Register */ 38 TIR_PNDA = 0x100, /* Pending Register A */ 39 TIR_PNDB = 0x104, /* Pending Register B */ 40 TIR_CS = 0x144, /* Current Status Register */ 41 TIR_LCSA = 0x150, /* Level Current Status Register A */ 42 TIR_LCSB = 0x154, /* Level Current Status Register B */ 43 TIR_LCSC = 0x158, /* Level Current Status Register C */ 44 TIR_LCSD = 0x15c, /* Level Current Status Register D */ 45 TIR_CFGA = 0x200, /* Setting Register A0 */ 46 TIR_CFGB = 0x204, /* Setting Register B0 */ 47 /* 0x208 ... 0x3ff Setting Register An/Bn */ 48 TIR_PPNDA = 0x400, /* Packet Pending Register A */ 49 TIR_PPNDB = 0x404, /* Packet Pending Register B */ 50 TIR_PIERA = 0x408, /* Packet Output Error Register A */ 51 TIR_PIERB = 0x40c, /* Packet Output Error Register B */ 52 TIR_PIEN = 0x444, /* Packet Output Enable Register */ 53 TIR_PIPND = 0x454, /* Packet Output Pending Register */ 54 TIRDID = 0x484, /* Spider Device ID Register */ 55 REISTIM = 0x500, /* Reissue Command Timeout Time Setting */ 56 REISTIMEN = 0x504, /* Reissue Command Timeout Setting */ 57 REISWAITEN = 0x508, /* Reissue Wait Control*/ 58}; 59 60#define SPIDER_CHIP_COUNT 4 61#define SPIDER_SRC_COUNT 64 62#define SPIDER_IRQ_INVALID 63 63 64struct spider_pic { 65 struct irq_host *host; 66 void __iomem *regs; 67 unsigned int node_id; 68}; 69static struct spider_pic spider_pics[SPIDER_CHIP_COUNT]; 70 71static struct spider_pic *spider_virq_to_pic(unsigned int virq) 72{ 73 return irq_map[virq].host->host_data; 74} 75 76static void __iomem *spider_get_irq_config(struct spider_pic *pic, 77 unsigned int src) 78{ 79 return pic->regs + TIR_CFGA + 8 * src; 80} 81 82static void spider_unmask_irq(unsigned int virq) 83{ 84 struct spider_pic *pic = spider_virq_to_pic(virq); 85 void __iomem *cfg = spider_get_irq_config(pic, irq_map[virq].hwirq); 86 87 out_be32(cfg, in_be32(cfg) | 0x30000000u); 88} 89 90static void spider_mask_irq(unsigned int virq) 91{ 92 struct spider_pic *pic = spider_virq_to_pic(virq); 93 void __iomem *cfg = spider_get_irq_config(pic, irq_map[virq].hwirq); 94 95 out_be32(cfg, in_be32(cfg) & ~0x30000000u); 96} 97 98static void spider_ack_irq(unsigned int virq) 99{ 100 struct spider_pic *pic = spider_virq_to_pic(virq); 101 unsigned int src = irq_map[virq].hwirq; 102 103 /* Reset edge detection logic if necessary 104 */ 105 if (irq_to_desc(virq)->status & IRQ_LEVEL) 106 return; 107 108 /* Only interrupts 47 to 50 can be set to edge */ 109 if (src < 47 || src > 50) 110 return; 111 112 /* Perform the clear of the edge logic */ 113 out_be32(pic->regs + TIR_EDC, 0x100 | (src & 0xf)); 114} 115 116static int spider_set_irq_type(unsigned int virq, unsigned int type) 117{ 118 unsigned int sense = type & IRQ_TYPE_SENSE_MASK; 119 struct spider_pic *pic = spider_virq_to_pic(virq); 120 unsigned int hw = irq_map[virq].hwirq; 121 void __iomem *cfg = spider_get_irq_config(pic, hw); 122 struct irq_desc *desc = irq_to_desc(virq); 123 u32 old_mask; 124 u32 ic; 125 126 /* Note that only level high is supported for most interrupts */ 127 if (sense != IRQ_TYPE_NONE && sense != IRQ_TYPE_LEVEL_HIGH && 128 (hw < 47 || hw > 50)) 129 return -EINVAL; 130 131 /* Decode sense type */ 132 switch(sense) { 133 case IRQ_TYPE_EDGE_RISING: 134 ic = 0x3; 135 break; 136 case IRQ_TYPE_EDGE_FALLING: 137 ic = 0x2; 138 break; 139 case IRQ_TYPE_LEVEL_LOW: 140 ic = 0x0; 141 break; 142 case IRQ_TYPE_LEVEL_HIGH: 143 case IRQ_TYPE_NONE: 144 ic = 0x1; 145 break; 146 default: 147 return -EINVAL; 148 } 149 150 /* Update irq_desc */ 151 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 152 desc->status |= type & IRQ_TYPE_SENSE_MASK; 153 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 154 desc->status |= IRQ_LEVEL; 155 156 /* Configure the source. One gross hack that was there before and 157 * that I've kept around is the priority to the BE which I set to 158 * be the same as the interrupt source number. I don't know wether 159 * that's supposed to make any kind of sense however, we'll have to 160 * decide that, but for now, I'm not changing the behaviour. 161 */ 162 old_mask = in_be32(cfg) & 0x30000000u; 163 out_be32(cfg, old_mask | (ic << 24) | (0x7 << 16) | 164 (pic->node_id << 4) | 0xe); 165 out_be32(cfg + 4, (0x2 << 16) | (hw & 0xff)); 166 167 return 0; 168} 169 170static struct irq_chip spider_pic = { 171 .name = "SPIDER", 172 .unmask = spider_unmask_irq, 173 .mask = spider_mask_irq, 174 .ack = spider_ack_irq, 175 .set_type = spider_set_irq_type, 176}; 177 178static int spider_host_map(struct irq_host *h, unsigned int virq, 179 irq_hw_number_t hw) 180{ 181 set_irq_chip_and_handler(virq, &spider_pic, handle_level_irq); 182 183 /* Set default irq type */ 184 set_irq_type(virq, IRQ_TYPE_NONE); 185 186 return 0; 187} 188 189static int spider_host_xlate(struct irq_host *h, struct device_node *ct, 190 const u32 *intspec, unsigned int intsize, 191 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 192 193{ 194 /* Spider interrupts have 2 cells, first is the interrupt source, 195 * second, well, I don't know for sure yet ... We mask the top bits 196 * because old device-trees encode a node number in there 197 */ 198 *out_hwirq = intspec[0] & 0x3f; 199 *out_flags = IRQ_TYPE_LEVEL_HIGH; 200 return 0; 201} 202 203static struct irq_host_ops spider_host_ops = { 204 .map = spider_host_map, 205 .xlate = spider_host_xlate, 206}; 207 208static void spider_irq_cascade(unsigned int irq, struct irq_desc *desc) 209{ 210 struct spider_pic *pic = desc->handler_data; 211 unsigned int cs, virq; 212 213 cs = in_be32(pic->regs + TIR_CS) >> 24; 214 if (cs == SPIDER_IRQ_INVALID) 215 virq = NO_IRQ; 216 else 217 virq = irq_linear_revmap(pic->host, cs); 218 if (virq != NO_IRQ) 219 generic_handle_irq(virq); 220 desc->chip->eoi(irq); 221} 222 223/* For hooking up the cascace we have a problem. Our device-tree is 224 * crap and we don't know on which BE iic interrupt we are hooked on at 225 * least not the "standard" way. We can reconstitute it based on two 226 * informations though: which BE node we are connected to and wether 227 * we are connected to IOIF0 or IOIF1. Right now, we really only care 228 * about the IBM cell blade and we know that its firmware gives us an 229 * interrupt-map property which is pretty strange. 230 */ 231static unsigned int __init spider_find_cascade_and_node(struct spider_pic *pic) 232{ 233 unsigned int virq; 234 const u32 *imap, *tmp; 235 int imaplen, intsize, unit; 236 struct device_node *iic; 237 238 /* First, we check wether we have a real "interrupts" in the device 239 * tree in case the device-tree is ever fixed 240 */ 241 struct of_irq oirq; 242 if (of_irq_map_one(pic->host->of_node, 0, &oirq) == 0) { 243 virq = irq_create_of_mapping(oirq.controller, oirq.specifier, 244 oirq.size); 245 return virq; 246 } 247 248 /* Now do the horrible hacks */ 249 tmp = of_get_property(pic->host->of_node, "#interrupt-cells", NULL); 250 if (tmp == NULL) 251 return NO_IRQ; 252 intsize = *tmp; 253 imap = of_get_property(pic->host->of_node, "interrupt-map", &imaplen); 254 if (imap == NULL || imaplen < (intsize + 1)) 255 return NO_IRQ; 256 iic = of_find_node_by_phandle(imap[intsize]); 257 if (iic == NULL) 258 return NO_IRQ; 259 imap += intsize + 1; 260 tmp = of_get_property(iic, "#interrupt-cells", NULL); 261 if (tmp == NULL) 262 return NO_IRQ; 263 intsize = *tmp; 264 /* Assume unit is last entry of interrupt specifier */ 265 unit = imap[intsize - 1]; 266 /* Ok, we have a unit, now let's try to get the node */ 267 tmp = of_get_property(iic, "ibm,interrupt-server-ranges", NULL); 268 if (tmp == NULL) { 269 of_node_put(iic); 270 return NO_IRQ; 271 } 272 /* ugly as hell but works for now */ 273 pic->node_id = (*tmp) >> 1; 274 of_node_put(iic); 275 276 /* Ok, now let's get cracking. You may ask me why I just didn't match 277 * the iic host from the iic OF node, but that way I'm still compatible 278 * with really really old old firmwares for which we don't have a node 279 */ 280 /* Manufacture an IIC interrupt number of class 2 */ 281 virq = irq_create_mapping(NULL, 282 (pic->node_id << IIC_IRQ_NODE_SHIFT) | 283 (2 << IIC_IRQ_CLASS_SHIFT) | 284 unit); 285 if (virq == NO_IRQ) 286 printk(KERN_ERR "spider_pic: failed to map cascade !"); 287 return virq; 288} 289 290 291static void __init spider_init_one(struct device_node *of_node, int chip, 292 unsigned long addr) 293{ 294 struct spider_pic *pic = &spider_pics[chip]; 295 int i, virq; 296 297 /* Map registers */ 298 pic->regs = ioremap(addr, 0x1000); 299 if (pic->regs == NULL) 300 panic("spider_pic: can't map registers !"); 301 302 /* Allocate a host */ 303 pic->host = irq_alloc_host(of_node, IRQ_HOST_MAP_LINEAR, 304 SPIDER_SRC_COUNT, &spider_host_ops, 305 SPIDER_IRQ_INVALID); 306 if (pic->host == NULL) 307 panic("spider_pic: can't allocate irq host !"); 308 pic->host->host_data = pic; 309 310 /* Go through all sources and disable them */ 311 for (i = 0; i < SPIDER_SRC_COUNT; i++) { 312 void __iomem *cfg = pic->regs + TIR_CFGA + 8 * i; 313 out_be32(cfg, in_be32(cfg) & ~0x30000000u); 314 } 315 316 /* do not mask any interrupts because of level */ 317 out_be32(pic->regs + TIR_MSK, 0x0); 318 319 /* enable interrupt packets to be output */ 320 out_be32(pic->regs + TIR_PIEN, in_be32(pic->regs + TIR_PIEN) | 0x1); 321 322 /* Hook up the cascade interrupt to the iic and nodeid */ 323 virq = spider_find_cascade_and_node(pic); 324 if (virq == NO_IRQ) 325 return; 326 set_irq_data(virq, pic); 327 set_irq_chained_handler(virq, spider_irq_cascade); 328 329 printk(KERN_INFO "spider_pic: node %d, addr: 0x%lx %s\n", 330 pic->node_id, addr, of_node->full_name); 331 332 /* Enable the interrupt detection enable bit. Do this last! */ 333 out_be32(pic->regs + TIR_DEN, in_be32(pic->regs + TIR_DEN) | 0x1); 334} 335 336void __init spider_init_IRQ(void) 337{ 338 struct resource r; 339 struct device_node *dn; 340 int chip = 0; 341 342 for (dn = NULL; 343 (dn = of_find_node_by_name(dn, "interrupt-controller"));) { 344 if (of_device_is_compatible(dn, "CBEA,platform-spider-pic")) { 345 if (of_address_to_resource(dn, 0, &r)) { 346 printk(KERN_WARNING "spider-pic: Failed\n"); 347 continue; 348 } 349 } else if (of_device_is_compatible(dn, "sti,platform-spider-pic") 350 && (chip < 2)) { 351 static long hard_coded_pics[] = 352 { 0x24000008000ul, 0x34000008000ul}; 353 r.start = hard_coded_pics[chip]; 354 } else 355 continue; 356 spider_init_one(dn, chip++, r.start); 357 } 358} 359