1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 6 * Adapted for Power Macintosh by Paul Mackerras. 7 * Low-level exception handlers and MMU support 8 * rewritten by Paul Mackerras. 9 * Copyright (C) 1996 Paul Mackerras. 10 * 11 * This file contains low-level assembler routines for managing 12 * the PowerPC MMU hash table. (PPC 8xx processors don't use a 13 * hash table, so this file is not used on them.) 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 */ 21 22#include <asm/reg.h> 23#include <asm/page.h> 24#include <asm/pgtable.h> 25#include <asm/cputable.h> 26#include <asm/ppc_asm.h> 27#include <asm/thread_info.h> 28#include <asm/asm-offsets.h> 29 30#ifdef CONFIG_SMP 31 .section .bss 32 .align 2 33 .globl mmu_hash_lock 34mmu_hash_lock: 35 .space 4 36#endif /* CONFIG_SMP */ 37 38/* 39 * Load a PTE into the hash table, if possible. 40 * The address is in r4, and r3 contains an access flag: 41 * _PAGE_RW (0x400) if a write. 42 * r9 contains the SRR1 value, from which we use the MSR_PR bit. 43 * SPRG_THREAD contains the physical address of the current task's thread. 44 * 45 * Returns to the caller if the access is illegal or there is no 46 * mapping for the address. Otherwise it places an appropriate PTE 47 * in the hash table and returns from the exception. 48 * Uses r0, r3 - r8, r10, ctr, lr. 49 */ 50 .text 51_GLOBAL(hash_page) 52 tophys(r7,0) /* gets -KERNELBASE into r7 */ 53#ifdef CONFIG_SMP 54 addis r8,r7,mmu_hash_lock@h 55 ori r8,r8,mmu_hash_lock@l 56 lis r0,0x0fff 57 b 10f 5811: lwz r6,0(r8) 59 cmpwi 0,r6,0 60 bne 11b 6110: lwarx r6,0,r8 62 cmpwi 0,r6,0 63 bne- 11b 64 stwcx. r0,0,r8 65 bne- 10b 66 isync 67#endif 68 /* Get PTE (linux-style) and check access */ 69 lis r0,KERNELBASE@h /* check if kernel address */ 70 cmplw 0,r4,r0 71 mfspr r8,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 72 ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */ 73 lwz r5,PGDIR(r8) /* virt page-table root */ 74 blt+ 112f /* assume user more likely */ 75 lis r5,swapper_pg_dir@ha /* if kernel address, use */ 76 addi r5,r5,swapper_pg_dir@l /* kernel page table */ 77 rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */ 78112: add r5,r5,r7 /* convert to phys addr */ 79#ifndef CONFIG_PTE_64BIT 80 rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */ 81 lwz r8,0(r5) /* get pmd entry */ 82 rlwinm. r8,r8,0,0,19 /* extract address of pte page */ 83#else 84 rlwinm r8,r4,13,19,29 /* Compute pgdir/pmd offset */ 85 lwzx r8,r8,r5 /* Get L1 entry */ 86 rlwinm. r8,r8,0,0,20 /* extract pt base address */ 87#endif 88#ifdef CONFIG_SMP 89 beq- hash_page_out /* return if no mapping */ 90#else 91 beqlr- 92#endif 93#ifndef CONFIG_PTE_64BIT 94 rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */ 95#else 96 rlwimi r8,r4,23,20,28 /* compute pte address */ 97#endif 98 rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */ 99 ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE 100 101 /* 102 * Update the linux PTE atomically. We do the lwarx up-front 103 * because almost always, there won't be a permission violation 104 * and there won't already be an HPTE, and thus we will have 105 * to update the PTE to set _PAGE_HASHPTE. -- paulus. 106 * 107 * If PTE_64BIT is set, the low word is the flags word; use that 108 * word for locking since it contains all the interesting bits. 109 */ 110#if (PTE_FLAGS_OFFSET != 0) 111 addi r8,r8,PTE_FLAGS_OFFSET 112#endif 113retry: 114 lwarx r6,0,r8 /* get linux-style pte, flag word */ 115 andc. r5,r3,r6 /* check access & ~permission */ 116#ifdef CONFIG_SMP 117 bne- hash_page_out /* return if access not permitted */ 118#else 119 bnelr- 120#endif 121 or r5,r0,r6 /* set accessed/dirty bits */ 122#ifdef CONFIG_PTE_64BIT 123#ifdef CONFIG_SMP 124 subf r10,r6,r8 /* create false data dependency */ 125 subi r10,r10,PTE_FLAGS_OFFSET 126 lwzx r10,r6,r10 /* Get upper PTE word */ 127#else 128 lwz r10,-PTE_FLAGS_OFFSET(r8) 129#endif /* CONFIG_SMP */ 130#endif /* CONFIG_PTE_64BIT */ 131 stwcx. r5,0,r8 /* attempt to update PTE */ 132 bne- retry /* retry if someone got there first */ 133 134 mfsrin r3,r4 /* get segment reg for segment */ 135 mfctr r0 136 stw r0,_CTR(r11) 137 bl create_hpte /* add the hash table entry */ 138 139#ifdef CONFIG_SMP 140 eieio 141 addis r8,r7,mmu_hash_lock@ha 142 li r0,0 143 stw r0,mmu_hash_lock@l(r8) 144#endif 145 146 /* Return from the exception */ 147 lwz r5,_CTR(r11) 148 mtctr r5 149 lwz r0,GPR0(r11) 150 lwz r7,GPR7(r11) 151 lwz r8,GPR8(r11) 152 b fast_exception_return 153 154#ifdef CONFIG_SMP 155hash_page_out: 156 eieio 157 addis r8,r7,mmu_hash_lock@ha 158 li r0,0 159 stw r0,mmu_hash_lock@l(r8) 160 blr 161#endif /* CONFIG_SMP */ 162 163/* 164 * Add an entry for a particular page to the hash table. 165 * 166 * add_hash_page(unsigned context, unsigned long va, unsigned long pmdval) 167 * 168 * We assume any necessary modifications to the pte (e.g. setting 169 * the accessed bit) have already been done and that there is actually 170 * a hash table in use (i.e. we're not on a 603). 171 */ 172_GLOBAL(add_hash_page) 173 mflr r0 174 stw r0,4(r1) 175 176 /* Convert context and va to VSID */ 177 mulli r3,r3,897*16 /* multiply context by context skew */ 178 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ 179 mulli r0,r0,0x111 /* multiply by ESID skew */ 180 add r3,r3,r0 /* note create_hpte trims to 24 bits */ 181 182#ifdef CONFIG_SMP 183 rlwinm r8,r1,0,0,(31-THREAD_SHIFT) /* use cpu number to make tag */ 184 lwz r8,TI_CPU(r8) /* to go in mmu_hash_lock */ 185 oris r8,r8,12 186#endif /* CONFIG_SMP */ 187 188 /* 189 * We disable interrupts here, even on UP, because we don't 190 * want to race with hash_page, and because we want the 191 * _PAGE_HASHPTE bit to be a reliable indication of whether 192 * the HPTE exists (or at least whether one did once). 193 * We also turn off the MMU for data accesses so that we 194 * we can't take a hash table miss (assuming the code is 195 * covered by a BAT). -- paulus 196 */ 197 mfmsr r9 198 SYNC 199 rlwinm r0,r9,0,17,15 /* clear bit 16 (MSR_EE) */ 200 rlwinm r0,r0,0,28,26 /* clear MSR_DR */ 201 mtmsr r0 202 SYNC_601 203 isync 204 205 tophys(r7,0) 206 207#ifdef CONFIG_SMP 208 addis r6,r7,mmu_hash_lock@ha 209 addi r6,r6,mmu_hash_lock@l 21010: lwarx r0,0,r6 /* take the mmu_hash_lock */ 211 cmpi 0,r0,0 212 bne- 11f 213 stwcx. r8,0,r6 214 beq+ 12f 21511: lwz r0,0(r6) 216 cmpi 0,r0,0 217 beq 10b 218 b 11b 21912: isync 220#endif 221 222 /* 223 * Fetch the linux pte and test and set _PAGE_HASHPTE atomically. 224 * If _PAGE_HASHPTE was already set, we don't replace the existing 225 * HPTE, so we just unlock and return. 226 */ 227 mr r8,r5 228#ifndef CONFIG_PTE_64BIT 229 rlwimi r8,r4,22,20,29 230#else 231 rlwimi r8,r4,23,20,28 232 addi r8,r8,PTE_FLAGS_OFFSET 233#endif 2341: lwarx r6,0,r8 235 andi. r0,r6,_PAGE_HASHPTE 236 bne 9f /* if HASHPTE already set, done */ 237#ifdef CONFIG_PTE_64BIT 238#ifdef CONFIG_SMP 239 subf r10,r6,r8 /* create false data dependency */ 240 subi r10,r10,PTE_FLAGS_OFFSET 241 lwzx r10,r6,r10 /* Get upper PTE word */ 242#else 243 lwz r10,-PTE_FLAGS_OFFSET(r8) 244#endif /* CONFIG_SMP */ 245#endif /* CONFIG_PTE_64BIT */ 246 ori r5,r6,_PAGE_HASHPTE 247 stwcx. r5,0,r8 248 bne- 1b 249 250 bl create_hpte 251 2529: 253#ifdef CONFIG_SMP 254 addis r6,r7,mmu_hash_lock@ha 255 addi r6,r6,mmu_hash_lock@l 256 eieio 257 li r0,0 258 stw r0,0(r6) /* clear mmu_hash_lock */ 259#endif 260 261 /* reenable interrupts and DR */ 262 mtmsr r9 263 SYNC_601 264 isync 265 266 lwz r0,4(r1) 267 mtlr r0 268 blr 269 270/* 271 * This routine adds a hardware PTE to the hash table. 272 * It is designed to be called with the MMU either on or off. 273 * r3 contains the VSID, r4 contains the virtual address, 274 * r5 contains the linux PTE, r6 contains the old value of the 275 * linux PTE (before setting _PAGE_HASHPTE) and r7 contains the 276 * offset to be added to addresses (0 if the MMU is on, 277 * -KERNELBASE if it is off). r10 contains the upper half of 278 * the PTE if CONFIG_PTE_64BIT. 279 * On SMP, the caller should have the mmu_hash_lock held. 280 * We assume that the caller has (or will) set the _PAGE_HASHPTE 281 * bit in the linux PTE in memory. The value passed in r6 should 282 * be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set 283 * this routine will skip the search for an existing HPTE. 284 * This procedure modifies r0, r3 - r6, r8, cr0. 285 * -- paulus. 286 * 287 * For speed, 4 of the instructions get patched once the size and 288 * physical address of the hash table are known. These definitions 289 * of Hash_base and Hash_bits below are just an example. 290 */ 291Hash_base = 0xc0180000 292Hash_bits = 12 /* e.g. 256kB hash table */ 293Hash_msk = (((1 << Hash_bits) - 1) * 64) 294 295/* defines for the PTE format for 32-bit PPCs */ 296#define HPTE_SIZE 8 297#define PTEG_SIZE 64 298#define LG_PTEG_SIZE 6 299#define LDPTEu lwzu 300#define LDPTE lwz 301#define STPTE stw 302#define CMPPTE cmpw 303#define PTE_H 0x40 304#define PTE_V 0x80000000 305#define TST_V(r) rlwinm. r,r,0,0,0 306#define SET_V(r) oris r,r,PTE_V@h 307#define CLR_V(r,t) rlwinm r,r,0,1,31 308 309#define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1) 310#define HASH_RIGHT 31-LG_PTEG_SIZE 311 312_GLOBAL(create_hpte) 313 /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */ 314 rlwinm r8,r5,32-10,31,31 /* _PAGE_RW -> PP lsb */ 315 rlwinm r0,r5,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */ 316 and r8,r8,r0 /* writable if _RW & _DIRTY */ 317 rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */ 318 rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */ 319 ori r8,r8,0xe04 /* clear out reserved bits */ 320 andc r8,r5,r8 /* PP = user? (rw&dirty? 2: 3): 0 */ 321BEGIN_FTR_SECTION 322 rlwinm r8,r8,0,~_PAGE_COHERENT /* clear M (coherence not required) */ 323END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) 324#ifdef CONFIG_PTE_64BIT 325 /* Put the XPN bits into the PTE */ 326 rlwimi r8,r10,8,20,22 327 rlwimi r8,r10,2,29,29 328#endif 329 330 /* Construct the high word of the PPC-style PTE (r5) */ 331 rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ 332 rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */ 333 SET_V(r5) /* set V (valid) bit */ 334 335 /* Get the address of the primary PTE group in the hash table (r3) */ 336_GLOBAL(hash_page_patch_A) 337 addis r0,r7,Hash_base@h /* base address of hash table */ 338 rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ 339 rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ 340 xor r3,r3,r0 /* make primary hash */ 341 li r0,8 /* PTEs/group */ 342 343 /* 344 * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search 345 * if it is clear, meaning that the HPTE isn't there already... 346 */ 347 andi. r6,r6,_PAGE_HASHPTE 348 beq+ 10f /* no PTE: go look for an empty slot */ 349 tlbie r4 350 351 addis r4,r7,htab_hash_searches@ha 352 lwz r6,htab_hash_searches@l(r4) 353 addi r6,r6,1 /* count how many searches we do */ 354 stw r6,htab_hash_searches@l(r4) 355 356 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ 357 mtctr r0 358 addi r4,r3,-HPTE_SIZE 3591: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */ 360 CMPPTE 0,r6,r5 361 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ 362 beq+ found_slot 363 364 /* Search the secondary PTEG for a matching PTE */ 365 ori r5,r5,PTE_H /* set H (secondary hash) bit */ 366_GLOBAL(hash_page_patch_B) 367 xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ 368 xori r4,r4,(-PTEG_SIZE & 0xffff) 369 addi r4,r4,-HPTE_SIZE 370 mtctr r0 3712: LDPTEu r6,HPTE_SIZE(r4) 372 CMPPTE 0,r6,r5 373 bdnzf 2,2b 374 beq+ found_slot 375 xori r5,r5,PTE_H /* clear H bit again */ 376 377 /* Search the primary PTEG for an empty slot */ 37810: mtctr r0 379 addi r4,r3,-HPTE_SIZE /* search primary PTEG */ 3801: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */ 381 TST_V(r6) /* test valid bit */ 382 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ 383 beq+ found_empty 384 385 /* update counter of times that the primary PTEG is full */ 386 addis r4,r7,primary_pteg_full@ha 387 lwz r6,primary_pteg_full@l(r4) 388 addi r6,r6,1 389 stw r6,primary_pteg_full@l(r4) 390 391 /* Search the secondary PTEG for an empty slot */ 392 ori r5,r5,PTE_H /* set H (secondary hash) bit */ 393_GLOBAL(hash_page_patch_C) 394 xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ 395 xori r4,r4,(-PTEG_SIZE & 0xffff) 396 addi r4,r4,-HPTE_SIZE 397 mtctr r0 3982: LDPTEu r6,HPTE_SIZE(r4) 399 TST_V(r6) 400 bdnzf 2,2b 401 beq+ found_empty 402 xori r5,r5,PTE_H /* clear H bit again */ 403 404 /* 405 * Choose an arbitrary slot in the primary PTEG to overwrite. 406 * Since both the primary and secondary PTEGs are full, and we 407 * have no information that the PTEs in the primary PTEG are 408 * more important or useful than those in the secondary PTEG, 409 * and we know there is a definite (although small) speed 410 * advantage to putting the PTE in the primary PTEG, we always 411 * put the PTE in the primary PTEG. 412 * 413 * In addition, we skip any slot that is mapping kernel text in 414 * order to avoid a deadlock when not using BAT mappings if 415 * trying to hash in the kernel hash code itself after it has 416 * already taken the hash table lock. This works in conjunction 417 * with pre-faulting of the kernel text. 418 * 419 * If the hash table bucket is full of kernel text entries, we'll 420 * lockup here but that shouldn't happen 421 */ 422 4231: addis r4,r7,next_slot@ha /* get next evict slot */ 424 lwz r6,next_slot@l(r4) 425 addi r6,r6,HPTE_SIZE /* search for candidate */ 426 andi. r6,r6,7*HPTE_SIZE 427 stw r6,next_slot@l(r4) 428 add r4,r3,r6 429 LDPTE r0,HPTE_SIZE/2(r4) /* get PTE second word */ 430 clrrwi r0,r0,12 431 lis r6,etext@h 432 ori r6,r6,etext@l /* get etext */ 433 tophys(r6,r6) 434 cmpl cr0,r0,r6 /* compare and try again */ 435 blt 1b 436 437#ifndef CONFIG_SMP 438 /* Store PTE in PTEG */ 439found_empty: 440 STPTE r5,0(r4) 441found_slot: 442 STPTE r8,HPTE_SIZE/2(r4) 443 444#else /* CONFIG_SMP */ 445/* 446 * Between the tlbie above and updating the hash table entry below, 447 * another CPU could read the hash table entry and put it in its TLB. 448 * There are 3 cases: 449 * 1. using an empty slot 450 * 2. updating an earlier entry to change permissions (i.e. enable write) 451 * 3. taking over the PTE for an unrelated address 452 * 453 * In each case it doesn't really matter if the other CPUs have the old 454 * PTE in their TLB. So we don't need to bother with another tlbie here, 455 * which is convenient as we've overwritten the register that had the 456 * address. :-) The tlbie above is mainly to make sure that this CPU comes 457 * and gets the new PTE from the hash table. 458 * 459 * We do however have to make sure that the PTE is never in an invalid 460 * state with the V bit set. 461 */ 462found_empty: 463found_slot: 464 CLR_V(r5,r0) /* clear V (valid) bit in PTE */ 465 STPTE r5,0(r4) 466 sync 467 TLBSYNC 468 STPTE r8,HPTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */ 469 sync 470 SET_V(r5) 471 STPTE r5,0(r4) /* finally set V bit in PTE */ 472#endif /* CONFIG_SMP */ 473 474 sync /* make sure pte updates get to memory */ 475 blr 476 477 .section .bss 478 .align 2 479next_slot: 480 .space 4 481primary_pteg_full: 482 .space 4 483htab_hash_searches: 484 .space 4 485 .previous 486 487/* 488 * Flush the entry for a particular page from the hash table. 489 * 490 * flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval, 491 * int count) 492 * 493 * We assume that there is a hash table in use (Hash != 0). 494 */ 495_GLOBAL(flush_hash_pages) 496 tophys(r7,0) 497 498 /* 499 * We disable interrupts here, even on UP, because we want 500 * the _PAGE_HASHPTE bit to be a reliable indication of 501 * whether the HPTE exists (or at least whether one did once). 502 * We also turn off the MMU for data accesses so that we 503 * we can't take a hash table miss (assuming the code is 504 * covered by a BAT). -- paulus 505 */ 506 mfmsr r10 507 SYNC 508 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ 509 rlwinm r0,r0,0,28,26 /* clear MSR_DR */ 510 mtmsr r0 511 SYNC_601 512 isync 513 514 /* First find a PTE in the range that has _PAGE_HASHPTE set */ 515#ifndef CONFIG_PTE_64BIT 516 rlwimi r5,r4,22,20,29 517#else 518 rlwimi r5,r4,23,20,28 519#endif 5201: lwz r0,PTE_FLAGS_OFFSET(r5) 521 cmpwi cr1,r6,1 522 andi. r0,r0,_PAGE_HASHPTE 523 bne 2f 524 ble cr1,19f 525 addi r4,r4,0x1000 526 addi r5,r5,PTE_SIZE 527 addi r6,r6,-1 528 b 1b 529 530 /* Convert context and va to VSID */ 5312: mulli r3,r3,897*16 /* multiply context by context skew */ 532 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ 533 mulli r0,r0,0x111 /* multiply by ESID skew */ 534 add r3,r3,r0 /* note code below trims to 24 bits */ 535 536 /* Construct the high word of the PPC-style PTE (r11) */ 537 rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ 538 rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */ 539 SET_V(r11) /* set V (valid) bit */ 540 541#ifdef CONFIG_SMP 542 addis r9,r7,mmu_hash_lock@ha 543 addi r9,r9,mmu_hash_lock@l 544 rlwinm r8,r1,0,0,(31-THREAD_SHIFT) 545 add r8,r8,r7 546 lwz r8,TI_CPU(r8) 547 oris r8,r8,9 54810: lwarx r0,0,r9 549 cmpi 0,r0,0 550 bne- 11f 551 stwcx. r8,0,r9 552 beq+ 12f 55311: lwz r0,0(r9) 554 cmpi 0,r0,0 555 beq 10b 556 b 11b 55712: isync 558#endif 559 560 /* 561 * Check the _PAGE_HASHPTE bit in the linux PTE. If it is 562 * already clear, we're done (for this pte). If not, 563 * clear it (atomically) and proceed. -- paulus. 564 */ 565#if (PTE_FLAGS_OFFSET != 0) 566 addi r5,r5,PTE_FLAGS_OFFSET 567#endif 56833: lwarx r8,0,r5 /* fetch the pte flags word */ 569 andi. r0,r8,_PAGE_HASHPTE 570 beq 8f /* done if HASHPTE is already clear */ 571 rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */ 572 stwcx. r8,0,r5 /* update the pte */ 573 bne- 33b 574 575 /* Get the address of the primary PTE group in the hash table (r3) */ 576_GLOBAL(flush_hash_patch_A) 577 addis r8,r7,Hash_base@h /* base address of hash table */ 578 rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ 579 rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ 580 xor r8,r0,r8 /* make primary hash */ 581 582 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ 583 li r0,8 /* PTEs/group */ 584 mtctr r0 585 addi r12,r8,-HPTE_SIZE 5861: LDPTEu r0,HPTE_SIZE(r12) /* get next PTE */ 587 CMPPTE 0,r0,r11 588 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ 589 beq+ 3f 590 591 /* Search the secondary PTEG for a matching PTE */ 592 ori r11,r11,PTE_H /* set H (secondary hash) bit */ 593 li r0,8 /* PTEs/group */ 594_GLOBAL(flush_hash_patch_B) 595 xoris r12,r8,Hash_msk>>16 /* compute secondary hash */ 596 xori r12,r12,(-PTEG_SIZE & 0xffff) 597 addi r12,r12,-HPTE_SIZE 598 mtctr r0 5992: LDPTEu r0,HPTE_SIZE(r12) 600 CMPPTE 0,r0,r11 601 bdnzf 2,2b 602 xori r11,r11,PTE_H /* clear H again */ 603 bne- 4f /* should rarely fail to find it */ 604 6053: li r0,0 606 STPTE r0,0(r12) /* invalidate entry */ 6074: sync 608 tlbie r4 /* in hw tlb too */ 609 sync 610 6118: ble cr1,9f /* if all ptes checked */ 61281: addi r6,r6,-1 613 addi r5,r5,PTE_SIZE 614 addi r4,r4,0x1000 615 lwz r0,0(r5) /* check next pte */ 616 cmpwi cr1,r6,1 617 andi. r0,r0,_PAGE_HASHPTE 618 bne 33b 619 bgt cr1,81b 620 6219: 622#ifdef CONFIG_SMP 623 TLBSYNC 624 li r0,0 625 stw r0,0(r9) /* clear mmu_hash_lock */ 626#endif 627 62819: mtmsr r10 629 SYNC_601 630 isync 631 blr 632 633/* 634 * Flush an entry from the TLB 635 */ 636_GLOBAL(_tlbie) 637#ifdef CONFIG_SMP 638 rlwinm r8,r1,0,0,(31-THREAD_SHIFT) 639 lwz r8,TI_CPU(r8) 640 oris r8,r8,11 641 mfmsr r10 642 SYNC 643 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ 644 rlwinm r0,r0,0,28,26 /* clear DR */ 645 mtmsr r0 646 SYNC_601 647 isync 648 lis r9,mmu_hash_lock@h 649 ori r9,r9,mmu_hash_lock@l 650 tophys(r9,r9) 65110: lwarx r7,0,r9 652 cmpwi 0,r7,0 653 bne- 10b 654 stwcx. r8,0,r9 655 bne- 10b 656 eieio 657 tlbie r3 658 sync 659 TLBSYNC 660 li r0,0 661 stw r0,0(r9) /* clear mmu_hash_lock */ 662 mtmsr r10 663 SYNC_601 664 isync 665#else /* CONFIG_SMP */ 666 tlbie r3 667 sync 668#endif /* CONFIG_SMP */ 669 blr 670 671/* 672 * Flush the entire TLB. 603/603e only 673 */ 674_GLOBAL(_tlbia) 675#if defined(CONFIG_SMP) 676 rlwinm r8,r1,0,0,(31-THREAD_SHIFT) 677 lwz r8,TI_CPU(r8) 678 oris r8,r8,10 679 mfmsr r10 680 SYNC 681 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ 682 rlwinm r0,r0,0,28,26 /* clear DR */ 683 mtmsr r0 684 SYNC_601 685 isync 686 lis r9,mmu_hash_lock@h 687 ori r9,r9,mmu_hash_lock@l 688 tophys(r9,r9) 68910: lwarx r7,0,r9 690 cmpwi 0,r7,0 691 bne- 10b 692 stwcx. r8,0,r9 693 bne- 10b 694 sync 695 tlbia 696 sync 697 TLBSYNC 698 li r0,0 699 stw r0,0(r9) /* clear mmu_hash_lock */ 700 mtmsr r10 701 SYNC_601 702 isync 703#else /* CONFIG_SMP */ 704 sync 705 tlbia 706 sync 707#endif /* CONFIG_SMP */ 708 blr 709