1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 6 * Low-level exception handlers and MMU support 7 * rewritten by Paul Mackerras. 8 * Copyright (C) 1996 Paul Mackerras. 9 * MPC8xx modifications by Dan Malek 10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 11 * 12 * This file contains low-level support and setup for PowerPC 8xx 13 * embedded processors, including trap and interrupt dispatch. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 */ 21 22#include <linux/init.h> 23#include <asm/processor.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/cache.h> 27#include <asm/pgtable.h> 28#include <asm/cputable.h> 29#include <asm/thread_info.h> 30#include <asm/ppc_asm.h> 31#include <asm/asm-offsets.h> 32 33/* Macro to make the code more readable. */ 34#ifdef CONFIG_8xx_CPU6 35#define DO_8xx_CPU6(val, reg) \ 36 li reg, val; \ 37 stw reg, 12(r0); \ 38 lwz reg, 12(r0); 39#else 40#define DO_8xx_CPU6(val, reg) 41#endif 42 __HEAD 43_ENTRY(_stext); 44_ENTRY(_start); 45 46/* MPC8xx 47 * This port was done on an MBX board with an 860. Right now I only 48 * support an ELF compressed (zImage) boot from EPPC-Bug because the 49 * code there loads up some registers before calling us: 50 * r3: ptr to board info data 51 * r4: initrd_start or if no initrd then 0 52 * r5: initrd_end - unused if r4 is 0 53 * r6: Start of command line string 54 * r7: End of command line string 55 * 56 * I decided to use conditional compilation instead of checking PVR and 57 * adding more processor specific branches around code I don't need. 58 * Since this is an embedded processor, I also appreciate any memory 59 * savings I can get. 60 * 61 * The MPC8xx does not have any BATs, but it supports large page sizes. 62 * We first initialize the MMU to support 8M byte pages, then load one 63 * entry into each of the instruction and data TLBs to map the first 64 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to 65 * the "internal" processor registers before MMU_init is called. 66 * 67 * The TLB code currently contains a major hack. Since I use the condition 68 * code register, I have to save and restore it. I am out of registers, so 69 * I just store it in memory location 0 (the TLB handlers are not reentrant). 70 * To avoid making any decisions, I need to use the "segment" valid bit 71 * in the first level table, but that would require many changes to the 72 * Linux page directory/table functions that I don't want to do right now. 73 * 74 * -- Dan 75 */ 76 .globl __start 77__start: 78 mr r31,r3 /* save parameters */ 79 mr r30,r4 80 mr r29,r5 81 mr r28,r6 82 mr r27,r7 83 84 /* We have to turn on the MMU right away so we get cache modes 85 * set correctly. 86 */ 87 bl initial_mmu 88 89/* We now have the lower 8 Meg mapped into TLB entries, and the caches 90 * ready to work. 91 */ 92 93turn_on_mmu: 94 mfmsr r0 95 ori r0,r0,MSR_DR|MSR_IR 96 mtspr SPRN_SRR1,r0 97 lis r0,start_here@h 98 ori r0,r0,start_here@l 99 mtspr SPRN_SRR0,r0 100 SYNC 101 rfi /* enables MMU */ 102 103/* 104 * Exception entry code. This code runs with address translation 105 * turned off, i.e. using physical addresses. 106 * We assume sprg3 has the physical address of the current 107 * task's thread_struct. 108 */ 109#define EXCEPTION_PROLOG \ 110 mtspr SPRN_SPRG_SCRATCH0,r10; \ 111 mtspr SPRN_SPRG_SCRATCH1,r11; \ 112 mfcr r10; \ 113 EXCEPTION_PROLOG_1; \ 114 EXCEPTION_PROLOG_2 115 116#define EXCEPTION_PROLOG_1 \ 117 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ 118 andi. r11,r11,MSR_PR; \ 119 tophys(r11,r1); /* use tophys(r1) if kernel */ \ 120 beq 1f; \ 121 mfspr r11,SPRN_SPRG_THREAD; \ 122 lwz r11,THREAD_INFO-THREAD(r11); \ 123 addi r11,r11,THREAD_SIZE; \ 124 tophys(r11,r11); \ 1251: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ 126 127 128#define EXCEPTION_PROLOG_2 \ 129 CLR_TOP32(r11); \ 130 stw r10,_CCR(r11); /* save registers */ \ 131 stw r12,GPR12(r11); \ 132 stw r9,GPR9(r11); \ 133 mfspr r10,SPRN_SPRG_SCRATCH0; \ 134 stw r10,GPR10(r11); \ 135 mfspr r12,SPRN_SPRG_SCRATCH1; \ 136 stw r12,GPR11(r11); \ 137 mflr r10; \ 138 stw r10,_LINK(r11); \ 139 mfspr r12,SPRN_SRR0; \ 140 mfspr r9,SPRN_SRR1; \ 141 stw r1,GPR1(r11); \ 142 stw r1,0(r11); \ 143 tovirt(r1,r11); /* set new kernel sp */ \ 144 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ 145 MTMSRD(r10); /* (except for mach check in rtas) */ \ 146 stw r0,GPR0(r11); \ 147 SAVE_4GPRS(3, r11); \ 148 SAVE_2GPRS(7, r11) 149 150/* 151 * Note: code which follows this uses cr0.eq (set if from kernel), 152 * r11, r12 (SRR0), and r9 (SRR1). 153 * 154 * Note2: once we have set r1 we are in a position to take exceptions 155 * again, and we could thus set MSR:RI at that point. 156 */ 157 158/* 159 * Exception vectors. 160 */ 161#define EXCEPTION(n, label, hdlr, xfer) \ 162 . = n; \ 163label: \ 164 EXCEPTION_PROLOG; \ 165 addi r3,r1,STACK_FRAME_OVERHEAD; \ 166 xfer(n, hdlr) 167 168#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ 169 li r10,trap; \ 170 stw r10,_TRAP(r11); \ 171 li r10,MSR_KERNEL; \ 172 copyee(r10, r9); \ 173 bl tfer; \ 174i##n: \ 175 .long hdlr; \ 176 .long ret 177 178#define COPY_EE(d, s) rlwimi d,s,0,16,16 179#define NOCOPY(d, s) 180 181#define EXC_XFER_STD(n, hdlr) \ 182 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ 183 ret_from_except_full) 184 185#define EXC_XFER_LITE(n, hdlr) \ 186 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ 187 ret_from_except) 188 189#define EXC_XFER_EE(n, hdlr) \ 190 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ 191 ret_from_except_full) 192 193#define EXC_XFER_EE_LITE(n, hdlr) \ 194 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ 195 ret_from_except) 196 197/* System reset */ 198 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD) 199 200/* Machine check */ 201 . = 0x200 202MachineCheck: 203 EXCEPTION_PROLOG 204 mfspr r4,SPRN_DAR 205 stw r4,_DAR(r11) 206 li r5,0x00f0 207 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 208 mfspr r5,SPRN_DSISR 209 stw r5,_DSISR(r11) 210 addi r3,r1,STACK_FRAME_OVERHEAD 211 EXC_XFER_STD(0x200, machine_check_exception) 212 213/* Data access exception. 214 * This is "never generated" by the MPC8xx. We jump to it for other 215 * translation errors. 216 */ 217 . = 0x300 218DataAccess: 219 EXCEPTION_PROLOG 220 mfspr r10,SPRN_DSISR 221 stw r10,_DSISR(r11) 222 mr r5,r10 223 mfspr r4,SPRN_DAR 224 li r10,0x00f0 225 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */ 226 EXC_XFER_EE_LITE(0x300, handle_page_fault) 227 228/* Instruction access exception. 229 * This is "never generated" by the MPC8xx. We jump to it for other 230 * translation errors. 231 */ 232 . = 0x400 233InstructionAccess: 234 EXCEPTION_PROLOG 235 mr r4,r12 236 mr r5,r9 237 EXC_XFER_EE_LITE(0x400, handle_page_fault) 238 239/* External interrupt */ 240 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) 241 242/* Alignment exception */ 243 . = 0x600 244Alignment: 245 EXCEPTION_PROLOG 246 mfspr r4,SPRN_DAR 247 stw r4,_DAR(r11) 248 li r5,0x00f0 249 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ 250 mfspr r5,SPRN_DSISR 251 stw r5,_DSISR(r11) 252 addi r3,r1,STACK_FRAME_OVERHEAD 253 EXC_XFER_EE(0x600, alignment_exception) 254 255/* Program check exception */ 256 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) 257 258/* No FPU on MPC8xx. This exception is not supposed to happen. 259*/ 260 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD) 261 262/* Decrementer */ 263 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) 264 265 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) 266 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) 267 268/* System call */ 269 . = 0xc00 270SystemCall: 271 EXCEPTION_PROLOG 272 EXC_XFER_EE_LITE(0xc00, DoSyscall) 273 274/* Single step - not used on 601 */ 275 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) 276 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) 277 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE) 278 279/* On the MPC8xx, this is a software emulation interrupt. It occurs 280 * for all unimplemented and illegal instructions. 281 */ 282 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD) 283 284 . = 0x1100 285/* 286 * For the MPC8xx, this is a software tablewalk to load the instruction 287 * TLB. It is modelled after the example in the Motorola manual. The task 288 * switch loads the M_TWB register with the pointer to the first level table. 289 * If we discover there is no second level table (value is zero) or if there 290 * is an invalid pte, we load that into the TLB, which causes another fault 291 * into the TLB Error interrupt where we can handle such problems. 292 * We have to use the MD_xxx registers for the tablewalk because the 293 * equivalent MI_xxx registers only perform the attribute functions. 294 */ 295InstructionTLBMiss: 296#ifdef CONFIG_8xx_CPU6 297 stw r3, 8(r0) 298#endif 299 DO_8xx_CPU6(0x3f80, r3) 300 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ 301 mfcr r10 302#ifdef CONFIG_8xx_CPU6 303 stw r10, 0(r0) 304 stw r11, 4(r0) 305#else 306 mtspr SPRN_DAR, r10 307 mtspr SPRN_SPRG2, r11 308#endif 309 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 310#ifdef CONFIG_8xx_CPU15 311 addi r11, r10, 0x1000 312 tlbie r11 313 addi r11, r10, -0x1000 314 tlbie r11 315#endif 316 DO_8xx_CPU6(0x3780, r3) 317 mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */ 318 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ 319 320 /* If we are faulting a kernel address, we have to use the 321 * kernel page tables. 322 */ 323#ifdef CONFIG_MODULES 324 /* Only modules will cause ITLB Misses as we always 325 * pin the first 8MB of kernel memory */ 326 andi. r11, r10, 0x0800 /* Address >= 0x80000000 */ 327 beq 3f 328 lis r11, swapper_pg_dir@h 329 ori r11, r11, swapper_pg_dir@l 330 rlwimi r10, r11, 0, 2, 19 3313: 332#endif 333 lwz r11, 0(r10) /* Get the level 1 entry */ 334 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ 335 beq 2f /* If zero, don't try to find a pte */ 336 337 /* We have a pte table, so load the MI_TWC with the attributes 338 * for this "segment." 339 */ 340 ori r11,r11,1 /* Set valid bit */ 341 DO_8xx_CPU6(0x2b80, r3) 342 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */ 343 DO_8xx_CPU6(0x3b80, r3) 344 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ 345 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ 346 lwz r10, 0(r11) /* Get the pte */ 347 348#ifdef CONFIG_SWAP 349 andi. r11, r10, _PAGE_ACCESSED | _PAGE_PRESENT 350 cmpwi cr0, r11, _PAGE_ACCESSED | _PAGE_PRESENT 351 bne- cr0, 2f 352#endif 353 /* The Linux PTE won't go exactly into the MMU TLB. 354 * Software indicator bits 21 and 28 must be clear. 355 * Software indicator bits 24, 25, 26, and 27 must be 356 * set. All other Linux PTE bits control the behavior 357 * of the MMU. 358 */ 359 li r11, 0x00f0 360 rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */ 361 DO_8xx_CPU6(0x2d80, r3) 362 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ 363 364 /* Restore registers */ 365#ifndef CONFIG_8xx_CPU6 366 mfspr r10, SPRN_DAR 367 mtcr r10 368 mtspr SPRN_DAR, r11 /* Tag DAR */ 369 mfspr r11, SPRN_SPRG2 370#else 371 lwz r11, 0(r0) 372 mtcr r11 373 lwz r11, 4(r0) 374 lwz r3, 8(r0) 375#endif 376 mfspr r10, SPRN_M_TW 377 rfi 3782: 379 mfspr r11, SPRN_SRR1 380 /* clear all error bits as TLB Miss 381 * sets a few unconditionally 382 */ 383 rlwinm r11, r11, 0, 0xffff 384 mtspr SPRN_SRR1, r11 385 386 /* Restore registers */ 387#ifndef CONFIG_8xx_CPU6 388 mfspr r10, SPRN_DAR 389 mtcr r10 390 li r11, 0x00f0 391 mtspr SPRN_DAR, r11 /* Tag DAR */ 392 mfspr r11, SPRN_SPRG2 393#else 394 lwz r11, 0(r0) 395 mtcr r11 396 lwz r11, 4(r0) 397 lwz r3, 8(r0) 398#endif 399 mfspr r10, SPRN_M_TW 400 b InstructionAccess 401 402 . = 0x1200 403DataStoreTLBMiss: 404#ifdef CONFIG_8xx_CPU6 405 stw r3, 8(r0) 406#endif 407 DO_8xx_CPU6(0x3f80, r3) 408 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ 409 mfcr r10 410#ifdef CONFIG_8xx_CPU6 411 stw r10, 0(r0) 412 stw r11, 4(r0) 413#else 414 mtspr SPRN_DAR, r10 415 mtspr SPRN_SPRG2, r11 416#endif 417 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ 418 419 /* If we are faulting a kernel address, we have to use the 420 * kernel page tables. 421 */ 422 andi. r11, r10, 0x0800 423 beq 3f 424 lis r11, swapper_pg_dir@h 425 ori r11, r11, swapper_pg_dir@l 426 rlwimi r10, r11, 0, 2, 19 4273: 428 lwz r11, 0(r10) /* Get the level 1 entry */ 429 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ 430 beq 2f /* If zero, don't try to find a pte */ 431 432 /* We have a pte table, so load fetch the pte from the table. 433 */ 434 ori r11, r11, 1 /* Set valid bit in physical L2 page */ 435 DO_8xx_CPU6(0x3b80, r3) 436 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ 437 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */ 438 lwz r10, 0(r10) /* Get the pte */ 439 440 /* Insert the Guarded flag into the TWC from the Linux PTE. 441 * It is bit 27 of both the Linux PTE and the TWC (at least 442 * I got that right :-). It will be better when we can put 443 * this into the Linux pgd/pmd and load it in the operation 444 * above. 445 */ 446 rlwimi r11, r10, 0, 27, 27 447 /* Insert the WriteThru flag into the TWC from the Linux PTE. 448 * It is bit 25 in the Linux PTE and bit 30 in the TWC 449 */ 450 rlwimi r11, r10, 32-5, 30, 30 451 DO_8xx_CPU6(0x3b80, r3) 452 mtspr SPRN_MD_TWC, r11 453 454 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set. 455 * We also need to know if the insn is a load/store, so: 456 * Clear _PAGE_PRESENT and load that which will 457 * trap into DTLB Error with store bit set accordinly. 458 */ 459 /* PRESENT=0x1, ACCESSED=0x20 460 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5)); 461 * r10 = (r10 & ~PRESENT) | r11; 462 */ 463#ifdef CONFIG_SWAP 464 rlwinm r11, r10, 32-5, _PAGE_PRESENT 465 and r11, r11, r10 466 rlwimi r10, r11, 0, _PAGE_PRESENT 467#endif 468 /* Honour kernel RO, User NA */ 469 /* 0x200 == Extended encoding, bit 22 */ 470 rlwimi r10, r10, 32-2, 0x200 /* Copy USER to bit 22, 0x200 */ 471 /* r11 = (r10 & _PAGE_RW) >> 1 */ 472 rlwinm r11, r10, 32-1, 0x200 473 or r10, r11, r10 474 /* invert RW and 0x200 bits */ 475 xori r10, r10, _PAGE_RW | 0x200 476 477 /* The Linux PTE won't go exactly into the MMU TLB. 478 * Software indicator bits 22 and 28 must be clear. 479 * Software indicator bits 24, 25, 26, and 27 must be 480 * set. All other Linux PTE bits control the behavior 481 * of the MMU. 482 */ 4832: li r11, 0x00f0 484 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ 485 DO_8xx_CPU6(0x3d80, r3) 486 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 487 488 /* Restore registers */ 489#ifndef CONFIG_8xx_CPU6 490 mfspr r10, SPRN_DAR 491 mtcr r10 492 mtspr SPRN_DAR, r11 /* Tag DAR */ 493 mfspr r11, SPRN_SPRG2 494#else 495 mtspr SPRN_DAR, r11 /* Tag DAR */ 496 lwz r11, 0(r0) 497 mtcr r11 498 lwz r11, 4(r0) 499 lwz r3, 8(r0) 500#endif 501 mfspr r10, SPRN_M_TW 502 rfi 503 504/* This is an instruction TLB error on the MPC8xx. This could be due 505 * to many reasons, such as executing guarded memory or illegal instruction 506 * addresses. There is nothing to do but handle a big time error fault. 507 */ 508 . = 0x1300 509InstructionTLBError: 510 b InstructionAccess 511 512/* This is the data TLB error on the MPC8xx. This could be due to 513 * many reasons, including a dirty update to a pte. We can catch that 514 * one here, but anything else is an error. First, we track down the 515 * Linux pte. If it is valid, write access is allowed, but the 516 * page dirty bit is not set, we will set it and reload the TLB. For 517 * any other case, we bail out to a higher level function that can 518 * handle it. 519 */ 520 . = 0x1400 521DataTLBError: 522#ifdef CONFIG_8xx_CPU6 523 stw r3, 8(r0) 524#endif 525 DO_8xx_CPU6(0x3f80, r3) 526 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ 527 mfcr r10 528 stw r10, 0(r0) 529 stw r11, 4(r0) 530 531 mfspr r10, SPRN_DAR 532 cmpwi cr0, r10, 0x00f0 533 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */ 534DARFixed: 535 mfspr r10, SPRN_M_TW /* Restore registers */ 536 lwz r11, 0(r0) 537 mtcr r11 538 lwz r11, 4(r0) 539#ifdef CONFIG_8xx_CPU6 540 lwz r3, 8(r0) 541#endif 542 b DataAccess 543 544 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) 545 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) 546 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) 547 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) 548 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) 549 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) 550 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) 551 552/* On the MPC8xx, these next four traps are used for development 553 * support of breakpoints and such. Someday I will get around to 554 * using them. 555 */ 556 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) 557 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) 558 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) 559 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) 560 561 . = 0x2000 562 563/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions 564 * by decoding the registers used by the dcbx instruction and adding them. 565 * DAR is set to the calculated address and r10 also holds the EA on exit. 566 */ 567 /* define if you don't want to use self modifying code */ 568#define NO_SELF_MODIFYING_CODE 569FixupDAR: 570 /* fetch instruction from memory. */ 571 mfspr r10, SPRN_SRR0 572 andis. r11, r10, 0x8000 /* Address >= 0x80000000 */ 573 DO_8xx_CPU6(0x3780, r3) 574 mtspr SPRN_MD_EPN, r10 575 mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */ 576 beq- 3f /* Branch if user space */ 577 lis r11, (swapper_pg_dir-PAGE_OFFSET)@h 578 ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l 579 rlwimi r11, r10, 32-20, 0xffc /* r11 = r11&~0xffc|(r10>>20)&0xffc */ 5803: lwz r11, 0(r11) /* Get the level 1 entry */ 581 DO_8xx_CPU6(0x3b80, r3) 582 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ 583 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ 584 lwz r11, 0(r11) /* Get the pte */ 585 /* concat physical page address(r11) and page offset(r10) */ 586 rlwimi r11, r10, 0, 20, 31 587 lwz r11,0(r11) 588/* Check if it really is a dcbx instruction. */ 589/* dcbt and dcbtst does not generate DTLB Misses/Errors, 590 * no need to include them here */ 591 srwi r10, r11, 26 /* check if major OP code is 31 */ 592 cmpwi cr0, r10, 31 593 bne- 141f 594 rlwinm r10, r11, 0, 21, 30 595 cmpwi cr0, r10, 2028 /* Is dcbz? */ 596 beq+ 142f 597 cmpwi cr0, r10, 940 /* Is dcbi? */ 598 beq+ 142f 599 cmpwi cr0, r10, 108 /* Is dcbst? */ 600 beq+ 144f /* Fix up store bit! */ 601 cmpwi cr0, r10, 172 /* Is dcbf? */ 602 beq+ 142f 603 cmpwi cr0, r10, 1964 /* Is icbi? */ 604 beq+ 142f 605141: mfspr r10, SPRN_DAR /* r10 must hold DAR at exit */ 606 b DARFixed /* Nope, go back to normal TLB processing */ 607 608144: mfspr r10, SPRN_DSISR 609 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ 610 mtspr SPRN_DSISR, r10 611142: /* continue, it was a dcbx, dcbi instruction. */ 612#ifdef CONFIG_8xx_CPU6 613 lwz r3, 8(r0) /* restore r3 from memory */ 614#endif 615#ifndef NO_SELF_MODIFYING_CODE 616 andis. r10,r11,0x1f /* test if reg RA is r0 */ 617 li r10,modified_instr@l 618 dcbtst r0,r10 /* touch for store */ 619 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */ 620 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */ 621 ori r11,r11,532 622 stw r11,0(r10) /* store add/and instruction */ 623 dcbf 0,r10 /* flush new instr. to memory. */ 624 icbi 0,r10 /* invalidate instr. cache line */ 625 lwz r11, 4(r0) /* restore r11 from memory */ 626 mfspr r10, SPRN_M_TW /* restore r10 from M_TW */ 627 isync /* Wait until new instr is loaded from memory */ 628modified_instr: 629 .space 4 /* this is where the add instr. is stored */ 630 bne+ 143f 631 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */ 632143: mtdar r10 /* store faulting EA in DAR */ 633 b DARFixed /* Go back to normal TLB handling */ 634#else 635 mfctr r10 636 mtdar r10 /* save ctr reg in DAR */ 637 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */ 638 addi r10, r10, 150f@l /* add start of table */ 639 mtctr r10 /* load ctr with jump address */ 640 xor r10, r10, r10 /* sum starts at zero */ 641 bctr /* jump into table */ 642150: 643 add r10, r10, r0 ;b 151f 644 add r10, r10, r1 ;b 151f 645 add r10, r10, r2 ;b 151f 646 add r10, r10, r3 ;b 151f 647 add r10, r10, r4 ;b 151f 648 add r10, r10, r5 ;b 151f 649 add r10, r10, r6 ;b 151f 650 add r10, r10, r7 ;b 151f 651 add r10, r10, r8 ;b 151f 652 add r10, r10, r9 ;b 151f 653 mtctr r11 ;b 154f /* r10 needs special handling */ 654 mtctr r11 ;b 153f /* r11 needs special handling */ 655 add r10, r10, r12 ;b 151f 656 add r10, r10, r13 ;b 151f 657 add r10, r10, r14 ;b 151f 658 add r10, r10, r15 ;b 151f 659 add r10, r10, r16 ;b 151f 660 add r10, r10, r17 ;b 151f 661 add r10, r10, r18 ;b 151f 662 add r10, r10, r19 ;b 151f 663 add r10, r10, r20 ;b 151f 664 add r10, r10, r21 ;b 151f 665 add r10, r10, r22 ;b 151f 666 add r10, r10, r23 ;b 151f 667 add r10, r10, r24 ;b 151f 668 add r10, r10, r25 ;b 151f 669 add r10, r10, r26 ;b 151f 670 add r10, r10, r27 ;b 151f 671 add r10, r10, r28 ;b 151f 672 add r10, r10, r29 ;b 151f 673 add r10, r10, r30 ;b 151f 674 add r10, r10, r31 675151: 676 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */ 677 beq 152f /* if reg RA is zero, don't add it */ 678 addi r11, r11, 150b@l /* add start of table */ 679 mtctr r11 /* load ctr with jump address */ 680 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */ 681 bctr /* jump into table */ 682152: 683 mfdar r11 684 mtctr r11 /* restore ctr reg from DAR */ 685 mtdar r10 /* save fault EA to DAR */ 686 b DARFixed /* Go back to normal TLB handling */ 687 688 /* special handling for r10,r11 since these are modified already */ 689153: lwz r11, 4(r0) /* load r11 from memory */ 690 b 155f 691154: mfspr r11, SPRN_M_TW /* load r10 from M_TW */ 692155: add r10, r10, r11 /* add it */ 693 mfctr r11 /* restore r11 */ 694 b 151b 695#endif 696 697 .globl giveup_fpu 698giveup_fpu: 699 blr 700 701/* 702 * This is where the main kernel code starts. 703 */ 704start_here: 705 /* ptr to current */ 706 lis r2,init_task@h 707 ori r2,r2,init_task@l 708 709 /* ptr to phys current thread */ 710 tophys(r4,r2) 711 addi r4,r4,THREAD /* init task's THREAD */ 712 mtspr SPRN_SPRG_THREAD,r4 713 714 /* stack */ 715 lis r1,init_thread_union@ha 716 addi r1,r1,init_thread_union@l 717 li r0,0 718 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 719 720 bl early_init /* We have to do this with MMU on */ 721 722/* 723 * Decide what sort of machine this is and initialize the MMU. 724 */ 725 mr r3,r31 726 mr r4,r30 727 mr r5,r29 728 mr r6,r28 729 mr r7,r27 730 bl machine_init 731 bl MMU_init 732 733/* 734 * Go back to running unmapped so we can load up new values 735 * and change to using our exception vectors. 736 * On the 8xx, all we have to do is invalidate the TLB to clear 737 * the old 8M byte TLB mappings and load the page table base register. 738 */ 739 /* The right way to do this would be to track it down through 740 * init's THREAD like the context switch code does, but this is 741 * easier......until someone changes init's static structures. 742 */ 743 lis r6, swapper_pg_dir@h 744 ori r6, r6, swapper_pg_dir@l 745 tophys(r6,r6) 746#ifdef CONFIG_8xx_CPU6 747 lis r4, cpu6_errata_word@h 748 ori r4, r4, cpu6_errata_word@l 749 li r3, 0x3980 750 stw r3, 12(r4) 751 lwz r3, 12(r4) 752#endif 753 mtspr SPRN_M_TWB, r6 754 lis r4,2f@h 755 ori r4,r4,2f@l 756 tophys(r4,r4) 757 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) 758 mtspr SPRN_SRR0,r4 759 mtspr SPRN_SRR1,r3 760 rfi 761/* Load up the kernel context */ 7622: 763 SYNC /* Force all PTE updates to finish */ 764 tlbia /* Clear all TLB entries */ 765 sync /* wait for tlbia/tlbie to finish */ 766 TLBSYNC /* ... on all CPUs */ 767 768 /* set up the PTE pointers for the Abatron bdiGDB. 769 */ 770 tovirt(r6,r6) 771 lis r5, abatron_pteptrs@h 772 ori r5, r5, abatron_pteptrs@l 773 stw r5, 0xf0(r0) /* Must match your Abatron config file */ 774 tophys(r5,r5) 775 stw r6, 0(r5) 776 777/* Now turn on the MMU for real! */ 778 li r4,MSR_KERNEL 779 lis r3,start_kernel@h 780 ori r3,r3,start_kernel@l 781 mtspr SPRN_SRR0,r3 782 mtspr SPRN_SRR1,r4 783 rfi /* enable MMU and jump to start_kernel */ 784 785/* Set up the initial MMU state so we can do the first level of 786 * kernel initialization. This maps the first 8 MBytes of memory 1:1 787 * virtual to physical. Also, set the cache mode since that is defined 788 * by TLB entries and perform any additional mapping (like of the IMMR). 789 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, 790 * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by 791 * these mappings is mapped by page tables. 792 */ 793initial_mmu: 794 tlbia /* Invalidate all TLB entries */ 795/* Always pin the first 8 MB ITLB to prevent ITLB 796 misses while mucking around with SRR0/SRR1 in asm 797*/ 798 lis r8, MI_RSV4I@h 799 ori r8, r8, 0x1c00 800 801 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ 802 803#ifdef CONFIG_PIN_TLB 804 lis r10, (MD_RSV4I | MD_RESETVAL)@h 805 ori r10, r10, 0x1c00 806 mr r8, r10 807#else 808 lis r10, MD_RESETVAL@h 809#endif 810#ifndef CONFIG_8xx_COPYBACK 811 oris r10, r10, MD_WTDEF@h 812#endif 813 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ 814 815 /* Now map the lower 8 Meg into the TLBs. For this quick hack, 816 * we can load the instruction and data TLB registers with the 817 * same values. 818 */ 819 lis r8, KERNELBASE@h /* Create vaddr for TLB */ 820 ori r8, r8, MI_EVALID /* Mark it valid */ 821 mtspr SPRN_MI_EPN, r8 822 mtspr SPRN_MD_EPN, r8 823 li r8, MI_PS8MEG /* Set 8M byte page */ 824 ori r8, r8, MI_SVALID /* Make it valid */ 825 mtspr SPRN_MI_TWC, r8 826 mtspr SPRN_MD_TWC, r8 827 li r8, MI_BOOTINIT /* Create RPN for address 0 */ 828 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ 829 mtspr SPRN_MD_RPN, r8 830 lis r8, MI_Kp@h /* Set the protection mode */ 831 mtspr SPRN_MI_AP, r8 832 mtspr SPRN_MD_AP, r8 833 834 /* Map another 8 MByte at the IMMR to get the processor 835 * internal registers (among other things). 836 */ 837#ifdef CONFIG_PIN_TLB 838 addi r10, r10, 0x0100 839 mtspr SPRN_MD_CTR, r10 840#endif 841 mfspr r9, 638 /* Get current IMMR */ 842 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ 843 844 mr r8, r9 /* Create vaddr for TLB */ 845 ori r8, r8, MD_EVALID /* Mark it valid */ 846 mtspr SPRN_MD_EPN, r8 847 li r8, MD_PS8MEG /* Set 8M byte page */ 848 ori r8, r8, MD_SVALID /* Make it valid */ 849 mtspr SPRN_MD_TWC, r8 850 mr r8, r9 /* Create paddr for TLB */ 851 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ 852 mtspr SPRN_MD_RPN, r8 853 854#ifdef CONFIG_PIN_TLB 855 /* Map two more 8M kernel data pages. 856 */ 857 addi r10, r10, 0x0100 858 mtspr SPRN_MD_CTR, r10 859 860 lis r8, KERNELBASE@h /* Create vaddr for TLB */ 861 addis r8, r8, 0x0080 /* Add 8M */ 862 ori r8, r8, MI_EVALID /* Mark it valid */ 863 mtspr SPRN_MD_EPN, r8 864 li r9, MI_PS8MEG /* Set 8M byte page */ 865 ori r9, r9, MI_SVALID /* Make it valid */ 866 mtspr SPRN_MD_TWC, r9 867 li r11, MI_BOOTINIT /* Create RPN for address 0 */ 868 addis r11, r11, 0x0080 /* Add 8M */ 869 mtspr SPRN_MD_RPN, r11 870 871 addis r8, r8, 0x0080 /* Add 8M */ 872 mtspr SPRN_MD_EPN, r8 873 mtspr SPRN_MD_TWC, r9 874 addis r11, r11, 0x0080 /* Add 8M */ 875 mtspr SPRN_MD_RPN, r11 876#endif 877 878 /* Since the cache is enabled according to the information we 879 * just loaded into the TLB, invalidate and enable the caches here. 880 * We should probably check/set other modes....later. 881 */ 882 lis r8, IDC_INVALL@h 883 mtspr SPRN_IC_CST, r8 884 mtspr SPRN_DC_CST, r8 885 lis r8, IDC_ENABLE@h 886 mtspr SPRN_IC_CST, r8 887#ifdef CONFIG_8xx_COPYBACK 888 mtspr SPRN_DC_CST, r8 889#else 890 /* For a debug option, I left this here to easily enable 891 * the write through cache mode 892 */ 893 lis r8, DC_SFWT@h 894 mtspr SPRN_DC_CST, r8 895 lis r8, IDC_ENABLE@h 896 mtspr SPRN_DC_CST, r8 897#endif 898 blr 899 900 901/* 902 * Set up to use a given MMU context. 903 * r3 is context number, r4 is PGD pointer. 904 * 905 * We place the physical address of the new task page directory loaded 906 * into the MMU base register, and set the ASID compare register with 907 * the new "context." 908 */ 909_GLOBAL(set_context) 910 911#ifdef CONFIG_BDI_SWITCH 912 /* Context switch the PTE pointer for the Abatron BDI2000. 913 * The PGDIR is passed as second argument. 914 */ 915 lis r5, KERNELBASE@h 916 lwz r5, 0xf0(r5) 917 stw r4, 0x4(r5) 918#endif 919 920#ifdef CONFIG_8xx_CPU6 921 lis r6, cpu6_errata_word@h 922 ori r6, r6, cpu6_errata_word@l 923 tophys (r4, r4) 924 li r7, 0x3980 925 stw r7, 12(r6) 926 lwz r7, 12(r6) 927 mtspr SPRN_M_TWB, r4 /* Update MMU base address */ 928 li r7, 0x3380 929 stw r7, 12(r6) 930 lwz r7, 12(r6) 931 mtspr SPRN_M_CASID, r3 /* Update context */ 932#else 933 mtspr SPRN_M_CASID,r3 /* Update context */ 934 tophys (r4, r4) 935 mtspr SPRN_M_TWB, r4 /* and pgd */ 936#endif 937 SYNC 938 blr 939 940#ifdef CONFIG_8xx_CPU6 941/* It's here because it is unique to the 8xx. 942 * It is important we get called with interrupts disabled. I used to 943 * do that, but it appears that all code that calls this already had 944 * interrupt disabled. 945 */ 946 .globl set_dec_cpu6 947set_dec_cpu6: 948 lis r7, cpu6_errata_word@h 949 ori r7, r7, cpu6_errata_word@l 950 li r4, 0x2c00 951 stw r4, 8(r7) 952 lwz r4, 8(r7) 953 mtspr 22, r3 /* Update Decrementer */ 954 SYNC 955 blr 956#endif 957 958/* 959 * We put a few things here that have to be page-aligned. 960 * This stuff goes at the beginning of the data segment, 961 * which is page-aligned. 962 */ 963 .data 964 .globl sdata 965sdata: 966 .globl empty_zero_page 967empty_zero_page: 968 .space 4096 969 970 .globl swapper_pg_dir 971swapper_pg_dir: 972 .space 4096 973 974/* Room for two PTE table poiners, usually the kernel and current user 975 * pointer to their respective root page table (pgdir). 976 */ 977abatron_pteptrs: 978 .space 8 979 980#ifdef CONFIG_8xx_CPU6 981 .globl cpu6_errata_word 982cpu6_errata_word: 983 .space 16 984#endif 985