1/* 2 * Copyright (C) 2001,2002,2003 Broadcom Corporation 3 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 18 */ 19 20/* 21 * BCM1250-specific PCI support 22 * 23 * This module provides the glue between Linux's PCI subsystem 24 * and the hardware. We basically provide glue for accessing 25 * configuration space, and set up the translation for I/O 26 * space accesses. 27 * 28 * To access configuration space, we use ioremap. In the 32-bit 29 * kernel, this consumes either 4 or 8 page table pages, and 16MB of 30 * kernel mapped memory. Hopefully neither of these should be a huge 31 * problem. 32 */ 33#include <linux/types.h> 34#include <linux/pci.h> 35#include <linux/kernel.h> 36#include <linux/init.h> 37#include <linux/mm.h> 38#include <linux/console.h> 39#include <linux/tty.h> 40#include <linux/vt.h> 41 42#include <asm/io.h> 43 44#include <asm/sibyte/sb1250_defs.h> 45#include <asm/sibyte/sb1250_regs.h> 46#include <asm/sibyte/sb1250_scd.h> 47#include <asm/sibyte/board.h> 48 49/* 50 * Macros for calculating offsets into config space given a device 51 * structure or dev/fun/reg 52 */ 53#define CFGOFFSET(bus, devfn, where) (((bus)<<16) + ((devfn)<<8) + (where)) 54#define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where) 55 56static void *cfg_space; 57 58#define PCI_BUS_ENABLED 1 59#define LDT_BUS_ENABLED 2 60#define PCI_DEVICE_MODE 4 61 62static int sb1250_bus_status; 63 64#define PCI_BRIDGE_DEVICE 0 65#define LDT_BRIDGE_DEVICE 1 66 67#ifdef CONFIG_SIBYTE_HAS_LDT 68/* 69 * HT's level-sensitive interrupts require EOI, which is generated 70 * through a 4MB memory-mapped region 71 */ 72unsigned long ldt_eoi_space; 73#endif 74 75/* 76 * Read/write 32-bit values in config space. 77 */ 78static inline u32 READCFG32(u32 addr) 79{ 80 return *(u32 *) (cfg_space + (addr & ~3)); 81} 82 83static inline void WRITECFG32(u32 addr, u32 data) 84{ 85 *(u32 *) (cfg_space + (addr & ~3)) = data; 86} 87 88int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 89{ 90 return dev->irq; 91} 92 93/* Do platform specific device initialization at pci_enable_device() time */ 94int pcibios_plat_dev_init(struct pci_dev *dev) 95{ 96 return 0; 97} 98 99/* 100 * Some checks before doing config cycles: 101 * In PCI Device Mode, hide everything on bus 0 except the LDT host 102 * bridge. Otherwise, access is controlled by bridge MasterEn bits. 103 */ 104static int sb1250_pci_can_access(struct pci_bus *bus, int devfn) 105{ 106 u32 devno; 107 108 if (!(sb1250_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE))) 109 return 0; 110 111 if (bus->number == 0) { 112 devno = PCI_SLOT(devfn); 113 if (devno == LDT_BRIDGE_DEVICE) 114 return (sb1250_bus_status & LDT_BUS_ENABLED) != 0; 115 else if (sb1250_bus_status & PCI_DEVICE_MODE) 116 return 0; 117 else 118 return 1; 119 } else 120 return 1; 121} 122 123/* 124 * Read/write access functions for various sizes of values 125 * in config space. Return all 1's for disallowed accesses 126 * for a kludgy but adequate simulation of master aborts. 127 */ 128 129static int sb1250_pcibios_read(struct pci_bus *bus, unsigned int devfn, 130 int where, int size, u32 * val) 131{ 132 u32 data = 0; 133 134 if ((size == 2) && (where & 1)) 135 return PCIBIOS_BAD_REGISTER_NUMBER; 136 else if ((size == 4) && (where & 3)) 137 return PCIBIOS_BAD_REGISTER_NUMBER; 138 139 if (sb1250_pci_can_access(bus, devfn)) 140 data = READCFG32(CFGADDR(bus, devfn, where)); 141 else 142 data = 0xFFFFFFFF; 143 144 if (size == 1) 145 *val = (data >> ((where & 3) << 3)) & 0xff; 146 else if (size == 2) 147 *val = (data >> ((where & 3) << 3)) & 0xffff; 148 else 149 *val = data; 150 151 return PCIBIOS_SUCCESSFUL; 152} 153 154static int sb1250_pcibios_write(struct pci_bus *bus, unsigned int devfn, 155 int where, int size, u32 val) 156{ 157 u32 cfgaddr = CFGADDR(bus, devfn, where); 158 u32 data = 0; 159 160 if ((size == 2) && (where & 1)) 161 return PCIBIOS_BAD_REGISTER_NUMBER; 162 else if ((size == 4) && (where & 3)) 163 return PCIBIOS_BAD_REGISTER_NUMBER; 164 165 if (!sb1250_pci_can_access(bus, devfn)) 166 return PCIBIOS_BAD_REGISTER_NUMBER; 167 168 data = READCFG32(cfgaddr); 169 170 if (size == 1) 171 data = (data & ~(0xff << ((where & 3) << 3))) | 172 (val << ((where & 3) << 3)); 173 else if (size == 2) 174 data = (data & ~(0xffff << ((where & 3) << 3))) | 175 (val << ((where & 3) << 3)); 176 else 177 data = val; 178 179 WRITECFG32(cfgaddr, data); 180 181 return PCIBIOS_SUCCESSFUL; 182} 183 184struct pci_ops sb1250_pci_ops = { 185 .read = sb1250_pcibios_read, 186 .write = sb1250_pcibios_write, 187}; 188 189static struct resource sb1250_mem_resource = { 190 .name = "SB1250 PCI MEM", 191 .start = 0x40000000UL, 192 .end = 0x5fffffffUL, 193 .flags = IORESOURCE_MEM, 194}; 195 196static struct resource sb1250_io_resource = { 197 .name = "SB1250 PCI I/O", 198 .start = 0x00000000UL, 199 .end = 0x01ffffffUL, 200 .flags = IORESOURCE_IO, 201}; 202 203struct pci_controller sb1250_controller = { 204 .pci_ops = &sb1250_pci_ops, 205 .mem_resource = &sb1250_mem_resource, 206 .io_resource = &sb1250_io_resource, 207}; 208 209static int __init sb1250_pcibios_init(void) 210{ 211 void __iomem *io_map_base; 212 uint32_t cmdreg; 213 uint64_t reg; 214 215 /* CFE will assign PCI resources */ 216 pci_probe_only = 1; 217 218 /* Avoid ISA compat ranges. */ 219 PCIBIOS_MIN_IO = 0x00008000UL; 220 PCIBIOS_MIN_MEM = 0x01000000UL; 221 222 /* Set I/O resource limits. */ 223 ioport_resource.end = 0x01ffffffUL; /* 32MB accessible by sb1250 */ 224 iomem_resource.end = 0xffffffffUL; /* no HT support yet */ 225 226 cfg_space = 227 ioremap(A_PHYS_LDTPCI_CFG_MATCH_BITS, 16 * 1024 * 1024); 228 229 /* 230 * See if the PCI bus has been configured by the firmware. 231 */ 232 reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG)); 233 if (!(reg & M_SYS_PCI_HOST)) { 234 sb1250_bus_status |= PCI_DEVICE_MODE; 235 } else { 236 cmdreg = 237 READCFG32(CFGOFFSET 238 (0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 239 PCI_COMMAND)); 240 if (!(cmdreg & PCI_COMMAND_MASTER)) { 241 printk 242 ("PCI: Skipping PCI probe. Bus is not initialized.\n"); 243 iounmap(cfg_space); 244 return 0; 245 } 246 sb1250_bus_status |= PCI_BUS_ENABLED; 247 } 248 249 io_map_base = ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 1024 * 1024); 250 sb1250_controller.io_map_base = (unsigned long)io_map_base; 251 set_io_port_base((unsigned long)io_map_base); 252 253#ifdef CONFIG_SIBYTE_HAS_LDT 254 /* 255 * Also check the LDT bridge's enable, just in case we didn't 256 * initialize that one. 257 */ 258 259 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(LDT_BRIDGE_DEVICE, 0), 260 PCI_COMMAND)); 261 if (cmdreg & PCI_COMMAND_MASTER) { 262 sb1250_bus_status |= LDT_BUS_ENABLED; 263 264 /* 265 * Need bits 23:16 to convey vector number. Note that 266 * this consumes 4MB of kernel-mapped memory 267 * (Kseg2/Kseg3) for 32-bit kernel. 268 */ 269 ldt_eoi_space = (unsigned long) 270 ioremap(A_PHYS_LDT_SPECIAL_MATCH_BYTES, 271 4 * 1024 * 1024); 272 } 273#endif 274 275 register_pci_controller(&sb1250_controller); 276 277#ifdef CONFIG_VGA_CONSOLE 278 take_over_console(&vga_con, 0, MAX_NR_CONSOLES - 1, 1); 279#endif 280 return 0; 281} 282arch_initcall(sb1250_pcibios_init); 283